21st week of 2012 patent applcation highlights part 17 |
Patent application number | Title | Published |
20120126312 | VERTICAL DMOS-FIELD EFFECT TRANSISTOR - A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), has a cell structure with a substrate; an epitaxial layer or well of the first conductivity type on the substrate; first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged within the first and second base region, respectively; a gate structure insulated from the epitaxial layer or well by an insulation layer and arranged above the region between the first and second base regions and covering at least partly the first and second base region, wherein the gate structure comprises first and second gates being spaced apart wherein each gate covers a respective portion of the base region. | 2012-05-24 |
20120126313 | ULTRA THIN DIE TO IMPROVE SERIES RESISTANCE OF A FET - A method for producing a power field effect transistor (FET) device having a low series resistance between the drain and source when switched on has the steps of: forming a vertical power FET in a semiconductor die; and back-grinding the semiconductor die to a thickness of less than or equal to about 100 μm (4 mils) or less. | 2012-05-24 |
20120126314 | VERTICAL DMOS-FIELD EFFECT TRANSISTOR - A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of the second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region is operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions, each gate region only covering the first and second channel, respectively within said first and second base region. | 2012-05-24 |
20120126315 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n | 2012-05-24 |
20120126316 | SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region. | 2012-05-24 |
20120126317 | ACCUFET WITH INTEGRATED CLAMPING CIRCUIT - The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates. | 2012-05-24 |
20120126318 | Integrated Circuit Including Field Effect Transistor - An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side. A conductive pathway extends through the semiconductor carrier from the first side to the second side, and is electrically insulated from the semiconductor carrier surrounding the conductive pathway. At least one of the first circuit elements is electrically coupled to a contact area at the first side via the conductive pathway. | 2012-05-24 |
20120126319 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE - A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes. | 2012-05-24 |
20120126320 | METHOD FOR MANUFACTURING A MOS-FIELD EFFECT TRANSISTOR - A method for manufacturing a Power Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has the steps of: implanting a base region of the Power MOSFET within an epitaxial layer of a semiconductor chip comprising an insulated gate structure, implanting a source link region on one side of the gate through a first mask, wherein the first mask is partially formed by an edge of the gate, the source link extending from a surface into the epitaxial layer and having a width defined by the first window, subsequently forming a spacer extending from the edge of the gate which defines the first window and forming a second mask which is partially formed by the spacer, and implanting a source region through the second mask. | 2012-05-24 |
20120126321 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A substrate having semiconductor material and a surface that supports a gate electrode and defines a surface normal direction is provided. The substrate can include a drift region including a first dopant type. A well region can be disposed adjacent to the drift region and proximal to the surface, and can include a second dopant type. A termination extension region can be disposed adjacent to the well region and extend away from the gate electrode, and can have an effective concentration of second dopant type that is generally less than that in the well region. An adjust region can be disposed between the surface and at least part of the termination extension region. An effective concentration of second dopant type may generally decrease when moving from the termination extension region into the adjust region along the surface normal direction. | 2012-05-24 |
20120126322 | LDMOS SEMICONDUCTOR DEVICE - A Lateral Double Diffused Metal-Oxide-Semiconductor (LDMOS) semiconductor device includes a substrate; a gate region, a source region, and a drain region on and/or over the substrate, a well region at one side of the drain region, and a guardring region disposed at one side of the well region and connected electrically to the well region. | 2012-05-24 |
20120126323 | SEMICONDUCTOR DEVICE HAVING A SPLIT GATE AND A SUPER-JUNCTION STRUCTURE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region. | 2012-05-24 |
20120126324 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N− type semiconductor layer. A source layer including an N− type layer is disposed in a surface portion of the body layer. An N− type drift layer is formed in a surface portion of the N− type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region. | 2012-05-24 |
20120126325 | METHOD FOR ADJUSTING FIN WIDTH IN INTEGRATED CIRCUITRY - A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins. | 2012-05-24 |
20120126326 | DEVICE AND METHOD FOR FORMING FINS IN INTEGRATED CIRCUITRY - A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures. | 2012-05-24 |
20120126327 | RESONATOR HAVING TERMINALS AND A METHOD FOR MANUFACTURING THE RESONATOR - A resonator and a method for manufacturing a resonator are provided. The method may include doping a wafer, and forming on the wafer a substrate, a drain electrode, a source electrode, a gate electrode, and at least one nanowire. | 2012-05-24 |
20120126328 | SEMICONDUCTOR DEVICE - A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripheral region, and has an arc portion, and a first strip portion and a second strip portion extended from two ends of the arc portion. The first strip portion points to an active device region, and the second strip portion is perpendicular to the first strip portion The second semiconductor layer is disposed in the epitaxial layer of the peripheral region between the active device region and the second strip portion, and the second semiconductor has a sidewall facing and parallel to the first semiconductor layer. | 2012-05-24 |
20120126329 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR - Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate. | 2012-05-24 |
20120126330 | Enhanced Thin Film Field Effect Transistor Integration into Back End of Line - A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip. | 2012-05-24 |
20120126331 | SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 2012-05-24 |
20120126332 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The invention provides a semiconductor device, including: a semiconductor base, on an insulation layer; source/drain regions abutting opposite first sides of the semiconductor base; and gates at opposite second sides of the semiconductor base, wherein the semiconductor base includes a cavity, and the insulation layer is exposed by the cavity. The invention also provides a method for forming a semiconductor device, including: forming a semiconductor bottom on an insulation layer; forming source/drain regions, the source/drain regions abutting opposite first sides of the semiconductor bottom; forming gates on opposite second sides of the semiconductor bottom; and removing a part of the semiconductor bottom to form a cavity in the semiconductor bottom, the cavity exposing the insulation layer. With the technical solutions provided by the invention, short-channel effects can be alleviated, and the resistance of the source/drain regions and parasitic capacitance can be reduced. | 2012-05-24 |
20120126333 | SELF-CONTAINED INTEGRATED CIRCUIT HAVING TRANSISTORS WITH SEPARATE THRESHOLD VOLTAGES - The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors ( | 2012-05-24 |
20120126334 | BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE - The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided. | 2012-05-24 |
20120126335 | METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY - A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature. | 2012-05-24 |
20120126336 | Isolation FET for Integrated Circuit - An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs. | 2012-05-24 |
20120126337 | SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME - A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions. | 2012-05-24 |
20120126338 | CROSS-HAIR CELL DEVICES AND METHODS FOR MANUFACTURING THE SAME - Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include forming gate trenches and gates on and parallel to row trenches in a substrate, wherein the gate trenches and gates are pitch-doubled such that four gate trenches are formed for every two row trenches. In another embodiment, a process may include forming gate trenches, gates, and grounded gates in a substrate, wherein the gate trenches and gates are formed such that three gate trenches are formed for every two row trenches. | 2012-05-24 |
20120126339 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 2012-05-24 |
20120126340 | CMOS Devices With Reduced Short Channel Effects - An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask. | 2012-05-24 |
20120126341 | USING LOW PRESSURE EPI TO ENABLE LOW RDSON FET - A method for forming an epitaxial layer on a substrate may have the steps of: forming a heavily doped silicon substrate; depositing an epitaxial layer at sub atmospheric pressure on the heavily doped silicon substrate; and implanting dopant into the epitaxial layer by ion implantation to form a lightly doped epitaxial layer. | 2012-05-24 |
20120126342 | FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME - Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation. | 2012-05-24 |
20120126343 | Self Aligned Silicided Contacts - Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material. | 2012-05-24 |
20120126344 | SENSOR DEVICE AND METHOD - A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element. | 2012-05-24 |
20120126345 | MEMS DEVICE WITH STRESS ISOLATION AND METHOD OF FABRICATION - A MEMS device ( | 2012-05-24 |
20120126346 | METHOD FOR CREATING A MICROMECHANICAL MEMBRANE STRUCTURE AND MEMS COMPONENT - In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity. | 2012-05-24 |
20120126347 | PACKAGES AND METHODS FOR PACKAGING - Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin. | 2012-05-24 |
20120126348 | SYSTEMS AND METHODS FOR A FOUR-LAYER CHIP-SCALE MEMS DEVICE - Systems and methods for a micro-electromechanical system (MEMS) apparatus are provided. In one embodiment, a system comprises a first double chip that includes a first base layer; a first device layer bonded to the first base layer, the first device layer comprising a first set of MEMS devices; and a first top layer bonded to the first device layer, wherein the first set of MEMS devices is hermetically isolated. The system also comprises a second double chip that includes a second base layer; a second device layer bonded to the second base layer, the second device layer comprising a second set of MEMS devices; and a second top layer bonded to the second device layer, wherein the second set of MEMS devices is hermetically isolated, wherein a first top surface of the first top layer is bonded to a second top surface of the second top layer. | 2012-05-24 |
20120126349 | SYSTEMS AND METHODS FOR A THREE-LAYER CHIP-SCALE MEMS DEVICE - Systems and methods for a micro-electromechanical system (MEMS) device are provided. In one embodiment, a system comprises a first outer layer and a first device layer comprising a first set of MEMS devices, wherein the first device layer is bonded to the first outer layer. The system also comprises a second outer layer and a second device layer comprising a second set of MEMS devices, wherein the second device layer is bonded to the second outer layer. Further, the system comprises a central layer having a first side and a second side opposite that of the first side, wherein the first side is bonded to the first device layer and the second side is bonded to the second device layer. | 2012-05-24 |
20120126350 | BATCH FABRICATED 3D INTERCONNECT - In an example, a method of fabricating one or more vertical interconnects is provided. The method includes patterning and stacking a plurality of wafers to form a wafer stack. A plurality of apertures can be formed in the wafer stack within one or more saw streets of the wafer stack, and conductive material can be deposited on sidewalls of the plurality of apertures. The wafer stack can be diced along the one or more saw streets and through the plurality of apertures such that the conductive material on the sidewalls is exposed on an edge portion of resulting stacked dies | 2012-05-24 |
20120126351 | Interconnection system on a plane adjacent to a solid-state device structure - A MEMS device is provided, which includes a silicon substrate with a face surface that has a pattern of recesses which define functional elements of the MEMS device, leaving sharp-edged, highly doped ridges, and a cover with a mating surface coupled to the face surface. The cover includes patterns of metal films that engage the ridges to form surface-to-surface electrical connections as well as hermetic surface-to-surface sealing and/or bonding between the silicon ridges of the face surface and the metal film on the mating surface, wherein the metal film on the mating surface comes into atomic contact with the silicon ridges. | 2012-05-24 |
20120126352 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS, MOUNTING METHOD AND SEMICONDUCTOR CHIP FOR VERTICAL MOUNTING ONTO CIRCUIT SUBSTRATES - A semiconductor chip having contact surfaces on an upper side parallel to the wafer plane has terminal pads on a terminal-pad side perpendicular to the upper side, each terminal pad being conductively connected to an assigned contact surface. This allows vertical mounting of the chip on a substrate and contacting with the aid of customary bonding techniques. A manufacturing method and two mounting methods are described. | 2012-05-24 |
20120126353 | Magnetic Memory Device - A magnetic memory device includes a magnetic tunnel junction (MTJ) structure and an electrode embedded in a dielectric structure. The MTJ structure includes a free layer. The electrode is formed of silicon-germanium and is electrically connected to the MTJ. The electrode heats the free layer to reduce the coercive force of the free layer to reduce a critical current density. | 2012-05-24 |
20120126354 | Down-Converting And Detecting Photons - In certain embodiments, an apparatus for down-converting and detecting photons includes a detector layer and a nanocrystal layer. The nanocrystal layer includes nanocrystals operable to absorb first photons of a higher energy and emit second photons of a lower energy in response to the absorption. The detector layer is configured to detect the second photons. In certain embodiments, a method for manufacturing an apparatus for down-converting and detecting photons includes preparing an outer surface of a substrate. Nanocrystals are disposed outwardly from the outer surface. The nanocrystals are operable to absorb first photons of a higher energy and emit second photons of a lower energy in response to the absorption. | 2012-05-24 |
20120126355 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - An oxide film capable of suppressing reflection of a lens is formed under a low temperature. A method of manufacturing a semiconductor device includes: (a) forming a lower layer oxide film on a lens formed on a substrate using a first processing source containing a first element, a second processing source containing a second element, an oxidizing source and a catalyst, the lower layer oxide film having a refractive index greater than that of air and less than that of the lens; and (b) forming an upper layer oxide film on the lower layer oxide film using the first processing source, the oxidizing source and the catalyst, the upper layer oxide film having a refractive index greater than that of the air and less than that of the lower layer oxide film. | 2012-05-24 |
20120126356 | PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device including a substrate, a photoelectric conversion element including a first electrode, a second electrode and an organic compound layer and a sealing member that are disposed in this order. When a cross section of the photoelectric conversion device in a thickness direction is observed with the sealing member being placed at an upper side, a bonding member seals the organic compound layer at an outside thereof. An output electrode on the sealing member has a protrusion. A side conductive portion is electrically connected with the protrusion in an up-and-down direction. A substrate conductive member electrically connected with the first electrode and the second electrode extends to an outside of the bonding member. An electrical connecting member electrically connects the side conductive portion to the substrate conductive member at a further outside of the bonding member. | 2012-05-24 |
20120126357 | LIGHT DETECTION DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are light detection devices and methods of manufacturing the same. The light detection device includes a first conductive pattern on a surface of a substrate, an insulating pattern on the substrate and having an opening exposing at least a portion of the first conductive pattern, a light absorbing layer filling the opening of the insulating pattern and having a top surface disposed at a level substantially higher than a top surface of the insulating pattern, a second conductive pattern on the light absorbing layer, and connecting terminals electrically connected to the first and second conductive patterns, respectively. | 2012-05-24 |
20120126358 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH - A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 2012-05-24 |
20120126359 | Structure to Reduce Etching Residue - A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too. | 2012-05-24 |
20120126360 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 2012-05-24 |
20120126361 | EPITAXIAL WAFER AND PRODUCTION METHOD THEREOF - A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer. | 2012-05-24 |
20120126362 | SOS SUBSTRATE HAVING LOW DEFECT DENSITY IN THE VICINITY OF INTERFACE - A bonded SOS substrate having a semiconductor film on or above a surface of a sapphire substrate is obtained by a method with the steps of implanting ions from a surface of a semiconductor substrate to form an ion-implanted layer; activating at least a surface from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to form a bonded body; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate for embrittling an interface of the ion-implanted layer, while keeping the bonded body at a temperature higher than the temperature at which the surfaces of the semiconductor substrate and the sapphire substrate were bonded. | 2012-05-24 |
20120126363 | STRUCTURE OF METAL E-FUSE - Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via. | 2012-05-24 |
20120126364 | MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK - An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. | 2012-05-24 |
20120126365 | Anti-Fuse Element - An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section. | 2012-05-24 |
20120126366 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 2012-05-24 |
20120126367 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 2012-05-24 |
20120126368 | Semiconductor Package - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer | 2012-05-24 |
20120126369 | Semiconductor Device and Method of Forming Passive Devices - A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump. | 2012-05-24 |
20120126370 | THIN FILM RESISTORS AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor. | 2012-05-24 |
20120126371 | CONDUCTIVE NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING THE SAME - A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 μm and arranged at a spacing of 250 to 10,000 μm; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 Ωcm≦r≦0.01 Ωcm, a thickness of 100 μm or more, and a radius of bow curvature U of 3.5 m≦U≦8 m. | 2012-05-24 |
20120126372 | RESIST PATTERN THICKENING MATERIAL AND PROCESS FOR FORMING RESIST PATTERN, AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A resist pattern thickening material is disclosed that can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. Also disclosed is a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized. | 2012-05-24 |
20120126373 | SEMICONDUCTOR DEVICE INCLUDING INNER INTERCONNECTION STRUCTURE - A semiconductor device includes a semiconductor chip and an inner interconnection structure. The semiconductor chip includes a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals. The inner interconnection structure includes horizontal buried conductive lines and vertical connection lines disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals. | 2012-05-24 |
20120126374 | Forming Three Dimensional Isolation Structures - A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches. | 2012-05-24 |
20120126375 | METHOD FOR FORMING METROLOGY STRUCTURES FROM FINS IN INTEGRATED CIRCUITRY - A method for forming a plurality of fins on a semiconductor substrate includes depositing a spacer layer to fill in gaps between the plurality of fins, the fins comprising a first material and the spacer layer comprising a second material. A first area is defined where the fins need to be broadened and a second area is defined where the fins do not need to be broadened. The method also includes patterning the spacer layer to remove spacers in the first area where the fins need to be broadened and applying an epitaxy process at a predetermined rate to grow a layer of the first material on fins in the first area. The spacer layer is removed in the second area where the fins do not need broadening. | 2012-05-24 |
20120126376 | SILICON DIOXIDE FILM AND PROCESS FOR PRODUCTION THEREOF, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE - To produce a silicon dioxide film having concentration of hydrogen atoms below or equal to 9.9×10 | 2012-05-24 |
20120126377 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions. | 2012-05-24 |
20120126378 | SEMICONDUCTOR DEVICE PACKAGE WITH ELECTROMAGNETIC SHIELDING - A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead. | 2012-05-24 |
20120126379 | DIE BOND FILM, DICING DIE BOND FILM, METHOD OF MANUFACTURING DIE BOND FILM, AND SEMICONDUCTOR DEVICE HAVING DIE BOND FILM - A semiconductor device having an electromagnetic wave shielding layer can be manufactured without decreasing productivity. The present invention provides a die bond film including an adhesive layer and an electromagnetic wave shielding layer made of a metal foil or a die bond film including an adhesive layer and an electromagnetic wave shielding layer formed by vapor deposition. | 2012-05-24 |
20120126380 | FILM FOR THE BACKSIDE OF FLIP-CHIP TYPE SEMICONDUCTOR, DICING TAPE-INTEGRATED FILM FOR THE BACKSIDE OF SEMICONDUCTOR, METHOD OF MANUFACTURING FILM FOR THE BACKSIDE OF FLIP-CHIP TYPE SEMICONDUCTOR, AND SEMICONDUCTOR DEVICE - An electromagnetic wave shielding layer can be provided on the backside of a semiconductor element that is flip-chip connected to an adherend, and a semiconductor device having the electromagnetic wave shielding layer can be manufactured without deteriorating productivity. The present invention provides a film for the backside of a flip-chip type semiconductor to be formed on the backside of a semiconductor element that is flip-chip connected to an adherend, having an adhesive layer and an electromagnetic wave shielding layer. | 2012-05-24 |
20120126381 | ADHESIVE FILM FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - An object of the present invention is to decrease the influence of an electromagnetic wave emitted from one semiconductor chip on other semiconductor chips in the same package, amounted substrate, adjacent devices, and the package. The present invention provides an adhesive film for a semiconductor device having an adhesive layer and an electromagnetic wave shielding layer, in which the attenuation of the electromagnetic wave that penetrates the adhesive film for a semiconductor device is 3 dB or more in at least a portion of the frequency range of 50 MHz to 20 GHz. | 2012-05-24 |
20120126382 | MAGNETIC SHIELDING FOR MULTI-CHIP MODULE PACKAGING - A system comprises a plurality of stacked integrated circuit dice, each integrated circuit die comprising at least one circuit, a package enclosing the plurality of dice, and at least two magnetic shields configured to magnetically shield the at least one circuit of each of the plurality of integrate circuit dice. At least one of the magnetic shields is within the package, and at least two of the plurality of stacked integrated circuit dice are positioned between the at least two magnetic shields. | 2012-05-24 |
20120126383 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different from the first metal on each surface. The first metal exposed at the sidewalls and at portions of the first surface of the pad. A semiconductor chip is assembled on the leadframe. Portions of the assembled chip and the leadframe are packaged in a polymeric encapsulation compound. | 2012-05-24 |
20120126384 | PACKAGE STRUCTURE - The present invention employs tie bar(s) of a lead frame as contact(s) so as to increase the number of contacts in a package structure. Therefore, a die can be packaged in a package structure with a smaller dimension to lower packaging cost of an integrated circuit. | 2012-05-24 |
20120126385 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad. | 2012-05-24 |
20120126386 | ELECTRONIC DEVICES - Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover. | 2012-05-24 |
20120126387 | ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends from the lateral portion to and contacts the substrate. An encapsulant covers the support member leaving the lateral and concaved portions exposed on outer sides thereof. In another aspect, a method of manufacturing an electronic device is also included. | 2012-05-24 |
20120126388 | STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/FLANGE HEAT SPREADER AND DUAL BUILD-UP CIRCUITRY - A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device. | 2012-05-24 |
20120126389 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND VIAS CONNECTED TO THE CENTRAL CONTACTS - The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface. | 2012-05-24 |
20120126390 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that may include an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, and a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate. The heat sink may include a housing that is made of a metal sheet and radiating fins that are fixed in the housing and made of aluminum. The metal sheet may have a coefficient of thermal expansion between those of the insulating substrate and the radiating fin. | 2012-05-24 |
20120126391 | Methods for Embedding Conducting Material and Devices Resulting from Said Methods - Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure. | 2012-05-24 |
20120126392 | Methods for Making Micro Needles and Applications Thereof - The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry. | 2012-05-24 |
20120126393 | RESIN COMPOSITION, MULTILAYER BODY CONTAINING THE SAME, SEMICONDUCTOR DEVICE, AND FILM - Disclosed is a resin composition which has high heat dissipation properties and high electrical insulation properties at the same time, while having low-temperature bondability to a conductor circuit or the like. The resin composition contains (A) a thermoplastic polyimide resin having a glass transition temperature of 160 DEG C or less and (B) an inorganic filler. The aspect ratio, that is the value of length/thickness, of the inorganic filler (B) is 9 or more, and the content of the inorganic filler (B) is 40-70 weight % relative to the total weight of the resin composition. The resin composition has a melt viscoelasticity of 10-300 MPa (inclusive) at 170 DEG C. | 2012-05-24 |
20120126394 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer. | 2012-05-24 |
20120126395 | Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die - A semiconductor device has an interposer frame having a die attach area. A uniform height insulating layer is formed over the interposer frame at corners of the die attach area. The insulating layer can be formed as rectangular or circular pillars at the corners of the die attach area. The insulating layer can also be formed in a central region of the die attach area. A semiconductor die has a plurality of bumps formed over an active surface of the semiconductor die. The bumps can have a non-fusible portion and fusible portion. The semiconductor die is mounted over the insulating layer which provides a uniform standoff distance between the semiconductor die and interposer frame. The bumps of the semiconductor die are bonded to the interposer frame. An encapsulant is deposited over the semiconductor die and interposer frame and between the semiconductor die and interposer frame. | 2012-05-24 |
20120126396 | DIE DOWN DEVICE WITH THERMAL CONNECTOR - Methods and apparatuses for a die down device with a thermal connector are provided. In an embodiment, an integrated circuit (IC) device includes an IC die having opposing first and second surfaces, a thermal connector coupled to the first surface of the IC die, and a substrate. The second surface of the IC die is coupled to the substrate. The thermal connector is configured to be coupled to a circuit board. | 2012-05-24 |
20120126397 | SEMICONDUCTOR SUBSTRATE AND METHOD THEREOF - A semiconductor substrate includes a substrate having plurality of electrical contact pads formed thereon, a first insulating protective layer formed on the substrate that exposes the electrical contact pads, a plurality of metal layers formed on the exposed electrical contact pads, a second insulating protective layer formed on the first insulating protective layer that exposes a portion of the metal layers, and a plurality of solder bumps formed on the exposed metal layers having copper. Through the second insulating protective layer covering a portion of the metal layers, the solder bumps are prevented from falling off or crack when the semiconductor substrate is under a temperature test. | 2012-05-24 |
20120126398 | INTEGRATED CIRCUIT PACKAGE AND PHYSICAL LAYER INTERFACE ARRANGEMENT - An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area. | 2012-05-24 |
20120126399 | THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND BUILD-UP CIRCUITRY - A semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device. | 2012-05-24 |
20120126400 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs. | 2012-05-24 |
20120126401 | STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND ELECTROMAGNETIC SHIELDING - A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a terminal, a plated through-hole and build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry provides signal routing for the semiconductor device. The plated through-hole provides signal routing between the build-up circuitry and the terminal. The heat spreader provides heat dissipation for the semiconductor device. | 2012-05-24 |
20120126402 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal. | 2012-05-24 |
20120126403 | SEMICONDUCTOR DEVICE - Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other. | 2012-05-24 |
20120126404 | SEMICONDUCTOR DEVICE - In a semiconductor device comprising a semiconductor chip, electrodes formed on the major surface of the semiconductor chip, and a wiring board for mounting the semiconductor chip, for example, wirings for electrically connecting the wirings of the wiring board to the electrodes are provided. As the wirings, those relaxing stress generated between the semiconductor chip and the wiring board are used. | 2012-05-24 |
20120126405 | SOLDER INTERCONNECT PADS WITH CURRENT SPREADING LAYERS - Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad. | 2012-05-24 |
20120126406 | USING BUMP BONDING TO DISTRIBUTE CURRENT FLOW ON A SEMICONDUCTOR POWER DEVICE - A semiconductor power chip may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; a plurality of ball bumps or a loaf bump disposed on each of the plurality of second elements and the plurality of third elements; and at least one ball bump or loaf on the at least one first contact element. | 2012-05-24 |
20120126407 | WAFER LEVEL CHIP PACKAGE AND A METHOD OF FABRICATING THEREOF - Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies. | 2012-05-24 |
20120126408 | INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT - The present invention discloses an integrated circuit (IC) comprising a bond pad ( | 2012-05-24 |
20120126409 | SEED LAYERS FOR METALLIC INTERCONNECTS AND PRODUCTS - A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method including: depositing a continuous seed layer over the sidewalls, using a first set of deposition parameters; and depositing another seed layer over the substrate, including inside the at least one opening and over a portion of said field, using a second set of deposition parameters, wherein: the second set of deposition parameters includes one deposition parameter which is different from any parameters in the first set, or whose value is different in the first and second sets; the continuous seed layer has a thickness in a range from about 20 Å to not more than 250 Å over the field; and the combined seed layers leave sufficient room for electroplating inside the opening. | 2012-05-24 |
20120126410 | Contact Array for Substrate Contacting - The present invention relates to a contact arrangement ( | 2012-05-24 |
20120126411 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of the present invention has a purpose to form a structure of preventing outflow of solder at low costs. A semiconductor element is bonded to a substrate through a solder layer. An outflow-preventing part is provided to surround the solder layer to prevent solder outflow during soldering. The outflow-preventing part is formed by a cold spray method and has a surface in an oxidized state. | 2012-05-24 |