21st week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120126212 | Light-Emitting Element, Light-Emitting Device, Lighting Device, and Electronic Devices - A light-emitting element which at least includes a monomolecular layer including a luminescent center material with a fluorescent light-emitting property, and a monomolecular layer including a host material with a carrier (electron or hole)-transport property and a band gap larger than a band gap (note that a band gap refers to the energy difference between a HOMO level and a LUMO level) of the luminescent center material, between a pair of electrodes, in which the monomolecular layer including the host material and the monomolecular layer including the luminescent center material share the same interface, is provided. | 2012-05-24 |
20120126213 | Semiconducting Component - The present invention relates to an organic semiconductor element that comprises multiple layers. One or more layers may include compounds that can function as light absorbers, charge transporting materials, and/or as a dopant. | 2012-05-24 |
20120126214 | METHODS AND INTERMEDIATES FOR THE SYNTHESIS OF DIPYRRIN-SUBSTITUTED PORPHYRINIC MACROCYCLES - The present invention provides dipyrrin substituted porphyrinic macrocycles, intermediates useful for making the same, and methods of making the same. Such compounds may be used for purposes including the making of molecular memory devices, solar cells and light harvesting arrays. | 2012-05-24 |
20120126215 | Anthracene Derivative, and Light-Emitting Element, Light-Emitting Device, Electronic Device Using Anthracene Derivative - An object is to provide a novel anthracene derivative. Another object is to provide a light-emitting element with high luminous efficiency. Yet another object is to provide a light-emitting element with a long lifetime. Still another object is to provide a light-emitting device and an electronic device having a long lifetime by using the light-emitting elements of the present invention. The anthracene derivative represented by General Formula (1) is provided. The ability of the anthracene derivative represented by General Formula (1) to exhibit high luminous efficiency allows the production of a light-emitting element with high luminous efficiency and a long lifetime. | 2012-05-24 |
20120126216 | LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID - The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform melt and thereafter, cooling the uniform melt to an ambient temperature under conditions sufficient to produce the melt-processed organic-inorganic hybrid material. | 2012-05-24 |
20120126217 | FLUORENE-CONTAINING AROMATIC COMPOUND, MATERIAL FOR ORGANIC ELECTROLUMINESCENT ELEMENT, AND ORGANIC ELECTROLUMINESCENT ELEMENT USING SAME - A fluorene-containing aromatic compound represented by a formula (1) below. | 2012-05-24 |
20120126218 | ORGANIC ELEMENT AND ORGANIC DEVICE INCLUDING THE SAME - An organic electric-field element includes an elongated support base member, a first electrode provided on the support base member, an organic layer provided to cover the first electrode, and a second electrode provided to cover the organic layer. At one end portion of the support base member, a two-layer structure region including the support base member and the first electrode is provided, and a three-layer structure region including the support base member, the first electrode, and the organic layer is provided, extending continuously from the other end of the two-layer structure region. At the other end portion of the support base member, a two-layer structure region including the support base member and the second electrode is provided, and a three-layer structure region including the support base member, the second electrode, and the organic layer is provided, extending continuously from one end of the two-layer structure region. | 2012-05-24 |
20120126219 | ORGANIC ELECTROLUMINESCENT ELEMENT AND METHOD FOR PRODUCING THE SAME - An organic electroluminescent element including: a first electrode; at least one organic deposition layer; and a second electrode, the first electrode, the organic deposition layer, and the second electrode being formed in this order, wherein the organic deposition layer satisfies the relationship 0.0932012-05-24 | |
20120126220 | COMPOUND HAVING SUBSTITUTED ANTHRACENE RING STRUCTURE AND PYRIDOINDOLE RING STRUCTURE, AND ORGANIC ELECTROLUMINESCENT DEVICE - There is provided an organic compound having excellent characteristics, including excellent electron-injecting/transporting performance, hole blocking ability, and high stability in the thin-film state, for use as material of an organic electroluminescent device having high efficiency and high durability. There is also provided a high-efficient and high-durable organic electroluminescent device using the compound. The compound is represented by general formula (1) having a substituted anthracene ring structure and a pyridoindole ring structure. The organic electroluminescent device includes a pair of electrodes, and one or more organic layers sandwiched between the pair of electrodes, and the compound is used as a constituent material of at least one organic layer. | 2012-05-24 |
20120126221 | CHARGE-TRANSPORTING MATERIAL AND ORGANIC ELECTROLUMINESCENCE DEVICE - A charge-transporting material contains a compound represented by the following formula (1) in an organic layer, in which the contents of specific halogen-containing compounds are 0.1% or less to the compound represented by formula (1). In formula (1), each of A | 2012-05-24 |
20120126222 | ORGANIC ELECTROLUMINESCENT ELEMENT - An organic electroluminescence device includes an anode, an emitting layer, an electron transporting zone and a cathode in sequential order. A blocking layer is provided in the electron transporting zone adjacently to the emitting layer. The blocking layer contains a fused hydrocarbon compound and at least one compound selected from an electron-donating dopant and an organic metal complex that contains an alkali metal. A triplet energy of the fused hydrocarbon compound is 2.0 eV or more. | 2012-05-24 |
20120126223 | TRANSISTORS, METHODS OF MANUFACTURING THE SAME AND ELECTRONIC DEVICES INCLUDING TRANSISTORS - An oxide transistor includes: a channel layer formed of an oxide semiconductor; a source electrode contacting a first end portion of the channel layer; a drain electrode contacting a second end portion of the channel layer; a gate corresponding to the channel layer; and a gate insulating layer disposed between the channel layer and the gate. The oxide semiconductor includes hafnium-indium-zinc-oxide (HfInZnO). An electrical conductivity of a back channel region of the channel layer is lower than an electrical conductivity of a front channel region of the channel layer. | 2012-05-24 |
20120126224 | SEMICONDUCTOR MEMORY DEVICE - An object is to provide a semiconductor memory device which can be miniaturized and also secures a sufficient margin for the refresh period. A memory cell includes a reading transistor, a writing transistor, and a capacitor. In the above structure, the capacitor controls a potential applied to a gate of the reading transistor. The writing transistor controls writing and erasing of data and, when the transistor is off, has small current so that loss of electric charges stored in the capacitor, which is due to leakage current of the writing transistor, can be prevented. A semiconductor layer included in the writing transistor is provided so as to extend from the gate electrode toward a source region of the reading transistor. The capacitor is provided to overlap with the gate electrode of the reading transistor. | 2012-05-24 |
20120126225 | SEMICONDUCTOR DEVICE - A semiconductor device according to an exemplary embodiment comprises a substrate, a middle layer comprising a first semiconductor layer disposed on the substrate and comprising Al | 2012-05-24 |
20120126226 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRIC DEVICE - It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diameter, the wiring in accordance with the shape of the contact hole is formed, and the wiring portion of the contact hole is likely to have a depression compared with other portions. A penetrating opening is formed by irradiating a light-transmitting insulating film with laser light having high intensity and a pulse high in repetition frequency. A plurality of openings having a minute contact area is provided instead of forming one penetrating opening having a large contact area to have an even thickness of a wiring by reducing a partial depression and also to ensure contact resistance. | 2012-05-24 |
20120126227 | INTERCONNECTION STRUCTURE AND DISPLAY DEVICE INCLUDING INTERCONNECTION STRUCTURE - A novel interconnection structure which is excellent in adhesion and is capable of realizing low resistance and low contact resistance is provided. An interconnection structure including an interconnection film and a semiconductor layer of a thin film transistor above a substrate in this order from the side of a substrate, wherein the semiconductor layer is composed of an oxide semiconductor, is provided. | 2012-05-24 |
20120126228 | Material Structure in Scribe Line and Method of Separating Chips - A method for manufacturing a chip is disclosed. The method comprises forming a material structure in a kerf adjacent the chip on a wafer. The method further comprises selectively removing the material structure in the kerf and dicing the wafer. | 2012-05-24 |
20120126229 | INTERCONNECTION STRUCTURES AND METHODS FOR TRANSFER-PRINTED INTEGRATED CIRCUIT ELEMENTS WITH IMPROVED INTERCONNECTION ALIGNMENT TOLERANCE - An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed. | 2012-05-24 |
20120126230 | METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP STACK DEVICE - A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array. | 2012-05-24 |
20120126231 | Electric Double Layer Capacitor, Lithium Ion Capacitor, and Charging Device - An electric double layer capacitor, a lithium ion capacitor, and a charging device including a solar cell and either of the capacitors are disclosed. The electric double layer capacitor includes a first and second light-transmitting substrates; a pair of current collectors provided perpendicular to the substrates; active material layers provided on facing planes of the current collectors; and an electrolyte in a region surrounded by the substrates and the facing active material layers. The lithium ion capacitor includes a first and second light-transmitting substrates; a positive and negative electrode active material layers provided perpendicular to the substrates; and an electrolyte in a region surrounded by the facing substrates and the positive and negative electrode active material layers. | 2012-05-24 |
20120126232 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured. | 2012-05-24 |
20120126233 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - Provided is a thin film transistor array panel. A thin film transistor array panel according to an exemplary embodiment includes a gate wire having a first region where the gate line is disposed, and a second region where the gate electrode is disposed, and a thickness of the gate wire formed in the first region is greater than the thickness of the gate wire that is formed in the second region. | 2012-05-24 |
20120126234 | Semiconductor Apparatus and Fabrication Method of the Same - It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic substrate. According to the present invention, devices formed on a glass substrate or a quartz substrate (a TFT, a light-emitting device having an organic compound, a liquid crystal device, a memory device, a thin-film diode, a pin-junction silicon photoelectric converter, a silicon resistance element, or the like) are separated from the substrate, and transferred to a plastic substrate having high thermal conductivity. | 2012-05-24 |
20120126235 | APPARATUS AND METHOD FOR REDUCING PHOTO LEAKAGE CURRENT FOR TFT LCD - In one aspect of the invention, the method of forming a TFT array panel includes forming a patterned first conductive layer on a substrate, forming a gate insulating layer on the patterned first conductive layer and the substrate, forming a patterned semiconductor layer on the gate insulating layer, forming a patterned second conductive layer, forming a patterned passivation layer on the patterned second conductive layer and the substrate, and forming a patterned transparent conductive layer on the patterned passivation layer. | 2012-05-24 |
20120126236 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present invention provides an array substrate, a method for manufacturing an array substrate, and a display device which are such that reflow failure of a resist mask does not occur readily at the time of manufacture of the array substrate, so the array substrate can be manufactured reliably. At the time of forming a TFT, third wiring | 2012-05-24 |
20120126237 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device is provided with a data line which are provided in a pixel region, a pixel electrode formed from a transparent conductive material which is upper layer than the data line, a storage capacitance electrode which is provided in a layer between the pixel electrode and the data line so as to face the pixel electrode via a capacitance insulation film, an additional capacitance which has a first capacitance electrode and a second capacitance electrode which is formed in the same layer as the pixel electrode and the storage capacitance electrode, respectively. The second capacitance electrode is electrically connected to the data line. | 2012-05-24 |
20120126238 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS USING THE SAME - A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high added value can be achieved. | 2012-05-24 |
20120126239 | LAYER STRUCTURES FOR CONTROLLING STRESS OF HETEROEPITAXIALLY GROWN III-NITRIDE LAYERS - A III-N layer structure is described that includes a III-N buffer layer on a foreign substrate, an additional III-N layer, a first III-N structure, and a second III-N layer structure. The first III-N structure atop the III-N buffer layer includes at least two III-N layers, each having an aluminum composition, and the III-N layer of the two III-N layers that is closer to the III-N buffer layer having the larger aluminum composition. The second III-N structure includes a III-N superlattice, the III-N superlattice including at least two III-N well layers interleaved with at least two III-N barrier layer. The first III-N structure and the second III-N structure are between the additional III-N layer and the foreign substrate. | 2012-05-24 |
20120126240 | Wafer level packaged GaN power device and the manufacturing method thereof - Disclosed are a GaN-based compound power semiconductor device and a manufacturing method thereof, in which on a GaN power semiconductor element, a contact pad is formed for flip-chip bonding, and a bonding pad of a module substrate to be mounted with the GaN power semiconductor element is formed with a bump so as to modularize an individual semiconductor element. In the disclosed GaN-based compound power semiconductor device, an AlGaN HEMT element is flip-chip bonded to the substrate, so that heat generated from the element can be efficiently radiated. | 2012-05-24 |
20120126241 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - A Group III nitride semiconductor light-emitting device includes a sapphire substrate having an embossment on a surface thereof; and an n-type layer, a light-emitting layer, and a p-type layer, which are sequentially stacked on the embossed surface of the sapphire substrate via a buffer layer, and each of which is formed of a Group HI nitride semiconductor. The embossment has a structure including a first stripe-pattern embossment which is formed on a surface of the sapphire substrate, and whose stripe direction corresponds to the x-axis direction; and a second stripe-pattern embossment which is formed atop the first stripe-pattern embossment, and whose stripe direction corresponds to the y-axis direction, the y-axis direction being orthogonal to the x-axis direction. | 2012-05-24 |
20120126242 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS - Provided are a light emitting device, a light emitting device package, and a lighting apparatus. The light emitting device includes: an n-type semiconductor layer including a first area and a second area in a plane; an n-type contact layer disposed on the n-type semiconductor layer and has a first thickness in the first area and a second thickness in the second area; an undoped semiconductor layer disposed on the n-type contact layer having the first thickness in the first area; an active layer disposed on the undoped semiconductor layer in the first area; a p-type semiconductor layer disposed on the active layer in the first area; a first electrode disposed on the n-type contact layer having the second thickness in the second area; and a second electrode disposed on the p-type semiconductor layer. | 2012-05-24 |
20120126243 | TRANSISTOR INCLUDING SHALLOW TRENCH AND ELECTRICALLY CONDUCTIVE SUBSTRATE FOR IMPROVED RF GROUNDING - Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 3 | 2012-05-24 |
20120126244 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device. | 2012-05-24 |
20120126245 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device. | 2012-05-24 |
20120126246 | PACKAGE AND HIGH FREQUENCY TERMINAL STRUCTURE FOR THE SAME - According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall. | 2012-05-24 |
20120126247 | SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion. | 2012-05-24 |
20120126248 | MEMBRANE HAVING MEANS FOR STATE MONITORING - The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 μm or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired. | 2012-05-24 |
20120126249 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer. | 2012-05-24 |
20120126250 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC. | 2012-05-24 |
20120126251 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate achieves reduced manufacturing cost. The method includes the steps of: preparing a base substrate and a SiC substrate; fabricating a stacked substrate by stacking the base substrate and the SiC substrate; fabricating a connected substrate by heating the stacked substrate; transferring a void, formed at a connection interface, in a thickness direction of the connected substrate by heating the connected substrate to cause the base substrate to have a temperature higher than that of the SiC substrate; and removing the void by removing a region including a main surface of the base substrate opposite to the SiC substrate. | 2012-05-24 |
20120126252 | PATTERNING THE EMISSION COLOUR IN TOP-EMISSIVE OLEDS - The invention relates to a top-emissive organic light-emitting diode (OLED) ( | 2012-05-24 |
20120126253 | PHOSPHOR BLEND FOR AN LED LIGHT SOURCE AND LED LIGHT SOURCE INCORPORATING SAME - There is provided a phosphor blend for an LED light source comprising from about 25 to about 35 weight percent of a cerium-activated yttrium aluminum garnet phosphor, from about 5 to about 10 weight percent of a europium-activated strontium calcium silicon nitride phosphor, and from about 50 to about 75 weight percent of a europium-activated calcium magnesium chlorosilicate phosphor. An LED light source in accordance with this invention has a B:G:R ratio for a 5500 K daylight balanced color film of X:Y:Z when directly exposed through a nominal photographic lens, wherein X, Y and Z each have a value from 0.90 to 1.10. | 2012-05-24 |
20120126254 | LED LAMP WITH IMPROVED DIE ARRANGEMENT - An LED lamp with improved die arrangement includes a main board equipped with a plurality of lines of light-emitting dies. The lines of the light-emitting dies are spaced by a distance equal to or greater than 0.38 mm. A number of the light-emitting dies in each of the lines may be added or reduced for fitting the main board. The light-emitting dies in one of the lines may be aligned with or offset from the light-emitting dies in the adjacent line. The LED lamp may have the light-emitting dies deployed in both of the aligned manner and the offset manner, so that the light-emitting dies fit a desired lighting pattern of the LED lamp and the LED lamp illuminates with enhanced uniformity and brightness. | 2012-05-24 |
20120126255 | LIGHT EMITTING DEVICES AND METHODS - Light emitting devices and methods are disclosed. In one embodiment a light emitting device can include a substrate, one or more light emitting diodes (LEDs) disposed over the substrate, and the LEDs can include electrical connectors for connecting to an electrical element. A light emitting device can further include a retention material disposed over the substrate and the retention material can be disposed over at least a portion of the electrical connectors. In one aspect, a method for making a light emitting device is disclosed. The method can include providing a substrate with one or more LEDs comprising electrical connectors. The method can further include providing a retention material on at least a portion of the substrate wherein the retention material is disposed over at least a portion of the electrical connectors. | 2012-05-24 |
20120126256 | LED PACKAGE - According to one embodiment, an LED package includes a first and a second lead frame separated from each other, an LED chip, a wire and a resin body. The LED chip is provided above the first and second lead frames, and has a pair of terminals provided on an upper surface of the LED chip. One of the terminals is connected to the first lead frame and one other terminal is connected to the second lead frame. The wire is drawn out from the one terminal horizontally to connect the one terminal to the first lead frame. The resin body covers the LED chip and the wire, an upper surface, a part of a lower surface and a part of an end surface of each of the first and second lead frames to expose a remaining part of the lower surface and a remaining part of the lower surface. | 2012-05-24 |
20120126257 | LIGHT EMITTING DEVICES AND METHODS - Light emitting devices and methods are disclosed. In one embodiment a light emitting device can include a substrate and a plurality of light emitting diodes (LEDs) disposed over the substrate in patterned arrays. The arrays can include one or more patterns of LEDs. A light emitting device can further include a retention material disposed about the array of LEDs. In one aspect, the retention material can be dispensed. | 2012-05-24 |
20120126258 | DISPLAY DEVICE, ORGANIC LIGHT EMITTING DIODE DISPLAY, AND MANUFACTURING METHOD OF SEALING SUBSTRATE - A display device includes a display unit, a sealing substrate, a first metal layer, a second metal layer, and a conductive wire member. The display unit is formed over a substrate. A sealing substrate is secured to the substrate by a bonding layer, and comprising a composite member and an insulating member. A first metal layer is formed over the inner surface of the sealing substrate facing the substrate, and a second metal layer is formed over the outer surface of the sealing substrate. A conductive wire member successively passes through at least two points of each of the first metal layer, the insulating member, and the second metal layer, and is secured to the sealing substrate to provide conduction of the first metal layer and the second metal layer. | 2012-05-24 |
20120126259 | LIGHT EMITTING DIODE - A light emitting diode, comprising: a transparent substrate; a wiring layer; and a semiconductor light emitting element structure part between the transparent substrate and the wiring layer, the semiconductor light emitting element structure part further comprising: a semiconductor light emitting layer; a transparent conductive layer provided on the wiring layer side of the semiconductor light emitting layer; a transparent insulating film; a metal reflection layer; and a first electrode part and a second electrode part provided on the wiring layer side of the transparent insulating film, to be electrically connected to the wiring layer, wherein the first electrode part is electrically connected to the first semiconductor layer via a first contact part which is provided to pass through the transparent insulating film, and the second electrode part is electrically connected to the second semiconductor layer by a second contact part provided to pass through the transparent insulating film, the transparent conductive layer, the first semiconductor layer, and the active layer. | 2012-05-24 |
20120126260 | HIGH EFFICACY SEMICONDUCTOR LIGHT EMITTING DEVICES EMPLOYING REMOTE PHOSPHOR CONFIGURATIONS - A semiconductor light emitting apparatus a semiconductor light emitting device configured to emit light inside a hollow shell including wavelength conversion material dispersed therein or thereon. A semiconductor light emitting apparatus according to some embodiments is capable of generating in excess of 230 lumens per watt. | 2012-05-24 |
20120126261 | LENS, LIGHT-EMITTING MODULE, LIGHT-EMITTING ELEMENT PACKAGE, ILLUMINATION DEVICE, DISPLAY DEVICE, AND TELEVISION RECEIVER | 2012-05-24 |
20120126262 | ETCHING GROWTH LAYERS OF LIGHT EMITTING DEVICES TO REDUCE LEAKAGE CURRENT - The present disclosure relates to methods for fabricating LEDs by patterning and etching an n-doped epitaxial layer to form regions of roughened surface of the n-doped layer and mesa structures adjacent to the roughened surface regions before depositing an active layer and the rest of the epitaxial layers on the mesa structures. The method includes growing epitaxial layers of an LED including an un-doped layer and an n-doped layer on a wafer of growth substrate. The method also includes patterning the n-doped layer to form a first region of the n-doped layer and a mesa region of the n-doped layer adjacent to the first region. The method further includes etching the first region of the n-doped layer to create a roughened surface. The method further includes growing additional epitaxial layers of the LED including an active layer and a p-doped layer on the mesa region of the n-doped layer. | 2012-05-24 |
20120126263 | ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic electroluminescence device and a method of manufacturing the same are provided. The organic electroluminescence device is suitable for being configured on a substrate. The organic electroluminescence device includes a first electrode, a first doped carrier transporting layer, a light-emitting layer, a second doped carrier transporting layer, and a second electrode. The first electrode is configured on the substrate. The first doped carrier transporting layer is configured on the first electrode. The light-emitting layer is configured on the first doped carrier transporting layer. The second doped carrier transporting layer is configured on the light-emitting layer and has a first surface in contact with the light-emitting layer and a second surface opposite to the first surface. The first surface is substantially a planar surface, and the second surface is a rough surface having a plurality of micro-protrusions. The second electrode is configured on the second surface. | 2012-05-24 |
20120126264 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An exemplary light emitting diode (LED) package includes a substrate having a first electrical portion and a second electrical portion formed thereon, two antioxidation layers formed on and electrically connected to the first electrical portion and the second electrical portion, respectively, and an LED chip disposed on the substrate and electrically connected to the two antioxidation layers. | 2012-05-24 |
20120126265 | LED PACKAGE - An exemplary LED package includes a substrate, an electric layer formed on the substrate, an LED chip mounted on the substrate and electrically connected with the electric layer, a first fluorescent layer and a second fluorescent layer. The first fluorescent encloses the LED chip and includes first phosphorous compounds. The second fluorescent covers the first fluorescent layer and includes second phosphorous compounds different from the first phosphorous compounds. The second fluorescent layer is detachably mounted at an outside of the first fluorescent layer. | 2012-05-24 |
20120126266 | ILLUMINATION APPARATUS - According to one embodiment, an illumination apparatus includes an LED (Light Emitting Diode) module, a light guide plate, and a support body. The support body supports the LED module and the light guide plate. A reflective surface of the support body is provided between a portion supporting the LED module and a portion supporting the light guide plate. The reflective surface is reflective with respect to the light emitted from the LED package. The LED module is tilted relative to the reflective surface with the LED package mounting surface being toward the reflective surface. An angle between the LED module and the reflective surface is less than 90°. | 2012-05-24 |
20120126267 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a light emitting diode (LED) package is provided. The method includes preparing a package body including a first lead frame formed with a cavity and inserted on one side of a bottom surface of the cavity and a second lead frame inserted on the other side, mounting an LED chip on the bottom surface and electrically connecting the LED chip with the first lead frame and the second lead frame, forming a molding portion by a molding resin in the cavity, connecting, to the package body, a first mold corresponding to the molding portion and including a through hole having an inner surface linearly or non-linearly inclined, connecting a second mold to an upper surface of the first mold, forming a lens portion on the molding portion by a transparent resin, and separating the first mold and the second mold from the package body. | 2012-05-24 |
20120126268 | LIGHTING DEVICE - A lighting device is provided with a structure body which has an inner surface including a region with a negative Fresnel lens shape and a high refractive index material layer which is closely in contact with the inner surface. The high refractive index material layer has a Fresnel lens shape in a region closely in contact with the inner surface, and a plane light-emitting body is provided over the structure body with the high refractive index material layer interposed therebetween. The high refractive index material layer is provided so as to fill at least the negative Fresnel lens shape of the structure body and thus has a surface including the region with the Fresnel lens shape at the interface with the structure body. | 2012-05-24 |
20120126269 | LIGHT EMITTING DEVICE, MANUFACTURING METHOD THEREOF, AND OPTICAL DEVICE - The present invention provides a light emitting device which is capable of enhancing the radiant intensity on a single direction. The light emitting device comprises a substrate, a lens bonded to the substrate, and an LED chip bonded to the substrate and exposed in a gap clipped between the substrate and the lens, wherein the lens has a light output surface which bulges in a direction that is defined from the substrate toward the LED chip and is contained in a thickness direction of the substrate to transmit the light emitted from the LED chip. | 2012-05-24 |
20120126270 | Organic Optical Device and Protective Component of Organic Optical Device - An organic optical device which can suppress deterioration due to moisture or an impurity is provided. An organic optical device includes a supporting body, a functional layer provided over the supporting body, and a light-emitting body containing an organic compound provided over the functional layer. The functional layer includes an insulating film containing gallium or aluminum, zinc, and oxygen. The supporting body and the functional layer each have a property of transmitting light with a wavelength of greater than or equal to 400 nm and less than or equal to 700 nm. By using the insulating film containing gallium or aluminum, zinc, and oxygen as a protective film, entry of moisture or an impurity into an organic compound or a metal material can be suppressed. | 2012-05-24 |
20120126271 | LIGHT-EMITTING DEVICE HAVING A GAIN REGION AND A REFLECTOR - A light-emitting device has a first cladding layer, an active layer formed above the first cladding layer, a second cladding layer formed above the active layer, a gain region, and a reflecting part. The active layer has first and second side surfaces parallel to each other. The gain region has a first end surface disposed on the first side surface. The gain region also has a second end surface disposed inside from the second side surface and angled relative to the second side surface. The second end surface, the gain region and the first end surface are provided in a first normal direction relative to the second end surface. The reflecting part is disposed next to the second end surface. | 2012-05-24 |
20120126272 | LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE USING SAME - A light-emitting element that has an improved light-extraction efficiency and an improved color purity of an emitted light. A light-emitting element includes a reflective electrode, a transparent electrode, a light-emitting layer, a functional layer, and a color filter. An optical film thickness of the functional layer is from approximately 218 nm to approximately 238 nm for a light emitting element that emits a blue light. An optical film thickness of the functional layer is from approximately 384 nm to approximately 400 nm for a light emitting element that emits a red light. | 2012-05-24 |
20120126273 | OLED SUBSTRATE CONSISTING OF TRANSPARENT CONDUCTIVE OXIDE (TCO) AND ANTI-IRIDESCENT UNDERCOAT - A light-emitting devices and methods for forming light-emitting devices are provided. The device comprises of a substrate having a first refractive index, a transparent electrode that is coupled to an organic layer, where the transparent electrode has a second refractive index different from the first refractive index. An undercoat layer is selected that has a third refractive index to substantially match the first refractive index to the second refractive index. The undercoat layer is selected such that it has a capacity to reduce root mean square roughness of the transparent electrode film deposited. The undercoat layer is selected to improve electrical properties of the transparent electrode layer. The undercoat layer is provided between the substrate and the transparent electrode. | 2012-05-24 |
20120126274 | OPTICAL COMPOSITION - The invention relates to a composition comprising a binder material and nanoparticles having an average particle size of 100 nm or less having a first refractive index of at least 1.65 in respect of light of a first wavelength, and a second refractive index in the range of 1.60-2.2 in respect of light of a second wavelength, wherein said first refractive index is higher than said second refractive index, and wherein the first and second refractive indices may be tuned by adjusting the volume ratio of the nanoparticles to the binder material. The composition may improve light extraction when used for bonding a ceramic member to an LED, and/or may reduce the amount of light that is directed back towards the LED. | 2012-05-24 |
20120126275 | LIGHT-EMITTING DIODE WITH COMPENSATING CONVERSION ELEMENT AND CORRESPONDING CONVERSION ELEMENT - A light-emitting diode includes a light-emitting diode chip which emits primary radiation in a spectral range of blue light during operation; a conversion element including a first phosphor and a second phosphor which absorbs part of the primary radiation and re-emits secondary radiation, wherein the first phosphor has, in an absorption wavelength range (Δλ | 2012-05-24 |
20120126276 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A light emitting element and a light emitting device for which light extraction efficiency is enhanced are provided. | 2012-05-24 |
20120126277 | Light-Emitting Element, Manufacturing Method Thereof, and Lighting Device - A light-emitting element includes a conductive layer functioning as a first electrode, an electroluminescent layer, and a conductive layer functioning as a second electrode, and further includes an insulating material filling a defect portion in the electroluminescent layer so that the defect portion is sealed. In the light-emitting element, the conductive layer functioning as a second electrode overlaps with the conductive layer functioning as a first electrode with the electroluminescent layer and the insulating material interposed therebetween and is in contact with a top surface of the electroluminescent layer. | 2012-05-24 |
20120126278 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a second electrode layer; a light emitting unit including a plurality of compound semiconductor layers under one portion of the second electrode layer; a first insulating layer under the other portion of the second electrode; an electrostatic protection unit including a plurality of compound semiconductor layer under the first insulating layer; a first electrode layer electrically connecting the light emitting unit to the electrostatic protection unit; and a wiring layer electrically connecting the electrostatic protection unit to the second electrode layer. | 2012-05-24 |
20120126279 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT - An optoelectronic semi-conductor component includes a first carrier having a top side and an underside laying opposite the top side of the first carrier, wherein the first carrier has a first and a second region; at least one optoelectronic semiconductor chip arranged at the top side on the first carrier; and at least one electronic component arranged in the second region at the underside of the first carrier, wherein the first region has a greater thickness in a vertical direction than the second region, wherein, at the underside, the first region projects beyond the second region in a vertical direction, and the at least one electronic component is electrically conductively connected to the at least one optoelectronic semi-conductor chip. | 2012-05-24 |
20120126280 | LIGHT EMITTING DEVICE AND LIGHT UNIT USING THE SAME - Disclosed are a light emitting device and a light unit using the same. The light emitting device includes a body, a light emitting diode installed in the body, a plurality of lead frames disposed in the body and electrically connected to the light emitting diode; and a heat dissipation member received in the body, thermally connected to the light emitting diode, and having a plurality of heat dissipation fins exposed from a lower surface of the body. | 2012-05-24 |
20120126281 | SYSTEM FOR FLASH-FREE OVERMOLDING OF LED ARRAY SUBSTRATES - System for flash-free overmolding of LED array substrates. In an aspect, a method is provided for molding encapsulations onto an LED array substrate. The method includes attaching a protective tape onto a substrate surface of the substrate so that openings in the protective tape align with LED devices of the substrate and applying molding material onto a molding surface of a molding tool and to portions of the substrate exposed through the openings in the protective tape. The method also includes pressing the molding surface and the substrate surface together at a selected pressure and a selected temperature so that encapsulations are formed on the portions of the substrate exposed through the openings in the protective tape, separating the molding surface from the substrate surface, and removing the protective tape so that molding material flash is removed from the substrate leaving a clean molded substrate. | 2012-05-24 |
20120126282 | SEALANT FOR OPTICAL SEMICONDUCTORS AND OPTICAL SEMICONDUCTOR DEVICE - The present invention provides a sealant for an optical semiconductor device which has high gas barrier property against corrosive gas, and is less likely to crack or is less likely to peel off even when used in harsh environments. | 2012-05-24 |
20120126283 | HIGH POWER, HIGH EFFICIENCY AND LOW EFFICIENCY DROOP III-NITRIDE LIGHT-EMITTING DIODES ON SEMIPOLAR SUBSTRATES - A III-nitride light emitting diode grown on a semipolar {20-2-1} plane of a substrate and characterized by high power, high efficiency and low efficiency droop. | 2012-05-24 |
20120126284 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 2012-05-24 |
20120126285 | Vertical NPNP Structure In a Triple Well CMOS Process - A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events. | 2012-05-24 |
20120126286 | MONOLITHIC THREE TERMINAL PHOTODETECTOR - Photodetectors operable to achieve multiplication of photogenerated carriers at ultralow voltages. Embodiments include a first p-i-n semiconductor junction combined with a second p-i-n semiconductor junction to form a monolithic photodetector having at least three terminals. The two p-i-n structures may share either the p-type region or the n-type region as a first terminal. Regions of the two p-i-n structures doped complementary to that of the shared terminal form second and third terminals so that the first and second p-i-n structures are operable in parallel. A multiplication region of the first p-i-n structure is to multiply charge carriers photogenerated within an absorption region of the second p-i-n structure with voltage drops between the shared first terminal and each of the second and third terminals being noncumulative. | 2012-05-24 |
20120126287 | COMPOUND SEMICONDUCTOR DEVICE HAVING INSULATION FILM WITH DIFFERENT FILM THICKNESSES BENEATH ELECTRODES - A compound semiconductor device includes a group-III nitride semiconductor layer; an insulation film located on the group-III nitride semiconductor layer; a drain electrode located in a position which is a first distance away from an upper surface of the group-III nitride semiconductor layer; a source electrode located in a position which is the first distance away from the upper surface of the group-III nitride semiconductor layer; a gate electrode located between the drain electrode and the source electrode; and a field plate electrode located between the drain electrode and the gate electrode at a position which is a second distance away from the upper surface of the group-III nitride semiconductor layer, the second distance is shorter than the first distance. | 2012-05-24 |
20120126288 | Semiconductor device and method of manufacturing the same - A semiconductor device having first and second stacks formed successively over a common substrate, in which the first stack that remains after removing the second stack comprises a field effect transistor, the second stack that is stacked over the first stack comprises a device different from the field effect transistor, and the first stack comprising the field effect transistor has an etching stopper layer that defines a stopping position of a recess formed in the first stack and comprises InGaP, a lower compound semiconductor layer that is disposed below a gate electrode disposed in the recess and comprises AlGaAs, and a spacer layer that is interposed between the etching stopper layer and the lower compound semiconductor layer for preventing phosphorus contained in the etching stopper layer from thermally diffusing as far as the lower compound semiconductor layer and chemically bonding with constituents elements of the lower compound semiconductor layer. | 2012-05-24 |
20120126289 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium. | 2012-05-24 |
20120126290 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region. | 2012-05-24 |
20120126291 | SEMICONDUCTOR DEVICE - A semiconductor device including at least a p-channel field-effect transistor region formed above a compound semiconductor substrate. The p-channel field-effect transistor region includes an undoped buffer layer; a p-type channel layer formed in contact with the buffer layer; a p-type source region and a p-type drain region formed in the channel layer, being separated with each other; and an n-type gate region formed above the channel layer and between the source region and the drain region. The buffer layer is formed having either a multilayer structure including a hole diffusion control layer with a band gap larger than the channel layer, or a single layer structure including only the hole diffusion control layer. | 2012-05-24 |
20120126292 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE - Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base. | 2012-05-24 |
20120126293 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - An epitaxial substrate, in which a group of group-III nitride layers is formed on a single-crystal silicon substrate so that a crystal plane is approximately parallel to a substrate surface, comprises: a first group-III nitride layer formed of AlN on the base substrate; a second group-III nitride layer formed of In | 2012-05-24 |
20120126294 | WAFER FILL PATTERNS AND USES - A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements. | 2012-05-24 |
20120126295 | BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION - A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided. | 2012-05-24 |
20120126296 | INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region | 2012-05-24 |
20120126297 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in which a metal silicide layer is formed by a salicide process is improved in reliability. By a salicide process according to a partial reaction method, metal silicide layers are formed over respective surfaces of gate electrodes, n | 2012-05-24 |
20120126298 | SELF-POWERED INTEGRATED CIRCUIT WITH PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the photovoltaic cell portion. | 2012-05-24 |
20120126299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a gate insulating film formed above the semiconductor substrate; a charge storage layer formed above the gate insulating film; a multilayered interelectrode insulating film formed in a first region above an upper surface portion of the element isolation insulating film, a second region above a sidewall portion of the charge storage layer and a third region above an upper surface portion of the charge storage layer, the interelectrode insulating film including a stack of an upper silicon oxide film, a middle silicon nitride film, and a lower silicon oxide film; a control gate electrode formed above the interelectrode insulating film; wherein the middle silicon nitride film is thinner in the third region than in the second region and the upper silicon oxide film is thicker in the third region than in the second region. | 2012-05-24 |
20120126300 | CAPACITORS, SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer. | 2012-05-24 |
20120126301 | MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS - One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed. | 2012-05-24 |
20120126302 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film. | 2012-05-24 |
20120126303 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode. | 2012-05-24 |
20120126304 | FLOATING GATE TYPE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A floating gate type semiconductor memory device includes a tunnel insulating layer, a floating gate formed on the tunnel insulating layer, a control gate electrode formed over the floating gates, a charge blocking layer formed between the floating gates and the control gate electrode, and a barrier layer formed in one or more areas of an area between the charge blocking layer and the control gate electrode and an area between the floating gate and the charge blocking layer and on an area corresponding to the sidewall of the floating gate. | 2012-05-24 |
20120126305 | Strained Semiconductor Device and Method of Making Same - In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress. | 2012-05-24 |
20120126306 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction. | 2012-05-24 |
20120126307 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. | 2012-05-24 |
20120126308 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region. | 2012-05-24 |
20120126309 | INTEGRATED NON-VOLATILE MEMORY (NVM) AND METHOD THEREFOR - A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack. | 2012-05-24 |
20120126310 | METHOD FOR FORMING CHANNEL MATERIAL - The present invention provides a method for forming a channel material, comprising: forming a substrate; forming an MOS device with a dummy gate stack on the substrate; removing the dummy gate stack; forming a channel trench at the channel located under the dummy gate stack; filling the channel trench with the channel material; and forming a gate stack. According to the embodiments of the present invention, the channel material is formed by a replacement gate process after the high temperature process, such as a high temperature annealing, thereby any negative influence on the formed channel material due to the high temperature process may be effectively avoided. | 2012-05-24 |
20120126311 | POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE - A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout. | 2012-05-24 |