21st week of 2013 patent applcation highlights part 23 |
Patent application number | Title | Published |
20130127484 | INSERT FOR SEMICONDUCTOR PACAKGE AND TESTING APPARATUS WITH THE SAME - An insert for a semiconductor package testing apparatus comprises a body having a pocket constructed and arranged to receive the semiconductor package, and a sliding tool slidingly positioned on the body. The sliding tool is constructed and arranged to open and close the pocket as a result of a sliding motion of the sliding tool relative to the body. | 2013-05-23 |
20130127485 | PRINTED CIRCUIT BOARD TESTING DEVICE - A printed circuit board testing device for performing electrical tests on a printed circuit board having test contacts includes a test platform. An installable and uninstallable positioning module is disposed on the test platform and adapted to receive the printed circuit board. The positioning module has through-holes corresponding in position to the test contacts. A dial module is disposed between the test platform and the positioning module, and has a needle corresponding in position to the through-holes, such that the distance between the dial module and the positioning module can be altered to cause the needle to penetrate a corresponding one the through-holes, insert into the positioning module, and come into contact with the test contacts to facilitate the electrical test. The printed circuit board testing device can perform electrical tests on any printed circuit boards having the test contacts, by changing the positioning module and the dial module. | 2013-05-23 |
20130127486 | Test Pad Structure, A Pad Structure For Inspecting A Semiconductor Chip And A Wiring Substrate For A Tape Package Having The Same - A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads and arranged in a first row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a second row next to the first row. | 2013-05-23 |
20130127487 | NON-CONTACT TESTING OF PRINTED ELECTRONICS - Apparatus and methods for non-contact testing of electronic components printed on a substrate ( | 2013-05-23 |
20130127488 | CONFIGURABLE TESTING PLATFORMS FOR CIRCUIT BOARDS WITH REMOVABLE TEST POINT PORTION - Circuit boards are provided that include a functional portion and at least one removable test point portion. The removable test point portion may include test points which are accessed to verify whether the functional portion is operating properly or whether installed electronic components are electrically coupled to the board. If multiple boards are manufactured together on a single panel (in which the individual boards are broken off), the test points can be placed on bridges (e.g., removable portions) that connect the individual boards together during manufacturing and testing. Configurable test boards are also provided that can be adjusted to accommodate circuit boards of different size and electrical testing requirements. Methods and systems for testing these circuit boards are also provided. | 2013-05-23 |
20130127489 | ELECTRONIC LOAD FOR TESTING DIMM SLOT - An exemplary electronic load includes a simulation load, a comparison circuit, a sample resistor, and a voltage control circuit. The comparison circuit includes a comparator. The sample resistor samples current flowing through the simulation load, and outputs the sampled current to a negative input of the comparator. An output of the comparator is connected to the simulation load. The voltage control circuit outputs an adjustable control voltage to a positive input of the comparator to control the simulation load to output an adjustable current. | 2013-05-23 |
20130127490 | SURGE TESTING METHOD AND SYSTEM FOR A BAR-WOUND STATOR - A method for surge testing a bar-wound stator includes electrically connecting a conductive lead of a test system to a corresponding welded hair pin in each of the layers mid-way through the stator windings. A calibrated voltage surge is applied via the conductive leads into the windings of the stator at the welded hair pins. The method includes measuring a voltage drop between turns of the windings after applying the calibrated voltage surge, recording the measured voltage drop in memory of the test system, and executing a control event with respect to the stator when the measured voltage drop is more than a calibrated threshold voltage drop. A system for surge testing the bar-wound stator includes a test device having a capacitor for storing the calibrated surge voltage and a pin set that is electrically connected to the test device. The pin set includes the conductive wires and leads. | 2013-05-23 |
20130127491 | Fault Tolerant Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 2013-05-23 |
20130127492 | TERMINATION FOR COMPLEMENTARY SIGNALS - Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described. | 2013-05-23 |
20130127493 | NEAREST NEIGHBOR SERIAL CONTENT ADDRESSABLE MEMORY - A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs. | 2013-05-23 |
20130127494 | MEMORY ELEMENTS WITH RELAY DEVICES - Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity. | 2013-05-23 |
20130127495 | HIGH-FREQUENCY SEMICONDUCTOR SWITCHING CIRCUIT - A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages. | 2013-05-23 |
20130127496 | DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF - Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. | 2013-05-23 |
20130127497 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped. | 2013-05-23 |
20130127498 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal. | 2013-05-23 |
20130127499 | FRACTIONAL-N SYNTHESIZER - One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output | 2013-05-23 |
20130127500 | POWER SEMICONDUCTOR DEVICE DRIVING CIRCUIT - A power semiconductor device driving circuit includes a gate control terminal, which is provided at a position separated from a drain terminal of a power semiconductor device by a predetermined distance so that electric discharge is generated between the drain terminal and the gate control terminal at the time of generation of surge. A surge voltage is applied to the gate control terminal due to this discharge, the gate of the power semiconductor device is charged to turn on and absorb the surge energy. Thus it becomes possible to suppress the surge voltage applied to the drain terminal and prevent breakdown of the power semiconductor device. | 2013-05-23 |
20130127501 | SPREAD SPECTRUM CLOCK GENERATORS - Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio. | 2013-05-23 |
20130127502 | LATCH CIRCUIT, FLIP-FLOP CIRCUIT AND FREQUENCY DIVIDER - The invention pertains to a latch circuit comprising a sensing arrangement with one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal. The latch circuit further comprises a storage arrangement with one or more storage transistors adapted to store the first signal and to provide a second signal based on the first signal, and a storage arrangement switching device connected or connectable to the first current source or a second current source, the storage arrangement switching device being adapted to switch on or off a current to the storage transistors based on a second clock signal, as well as a tuning arrangement connected or connectable to a temperature sensor, the tuning arrangement being adapted to bias a current of the sensing arrangement and/or the storage arrangement based on a temperature signal provided by the temperature sensor. The invention also pertains to a flip-flop circuit with two or more latch circuits and a frequency divider comprising at least one latch circuit as described. | 2013-05-23 |
20130127503 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal, a phase inversion control unit configured to generate a phase inversion control signal, and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases. | 2013-05-23 |
20130127504 | METHOD FOR RESETTING PHOTOELECTRIC CONVERSION DEVICE, AND PHOTOELECTRIC CONVERSION DEVICE - A reset method of an photoelectric conversion device at least including a phototransistor having a first collector, a first base, and a first emitter, and a first field-effect transistor having a first source, a first drain, and a first gate, includes: connecting the first base, and one of the first source and the first drain of the first field-effect transistor by having a common region, or a continuous region, without a base electrode; supplying a base reset potential to the other of the first source and the first drain; and overlapping a time in which a first emitter potential is supplied to the first emitter and a time in which a first ON-potential that turns on the first field-effect transistor is supplied to the first gate. | 2013-05-23 |
20130127505 | CLOCK GENERATOR, SEMICONDUCTOR DEVICE, AND CLOCK GENERATING METHOD - There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop. | 2013-05-23 |
20130127506 | SYSTEM AND METHOD FOR AN ACCURACY-ENHANCED DLL DURING A MEASURE INITIALIZATION MODE - A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals. | 2013-05-23 |
20130127507 | LOW-HYSTERESIS HIGH-SPEED DIFFERENTIAL SAMPLER - A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch. | 2013-05-23 |
20130127508 | SIGNAL DELAY CIRCUIT AND SIGNAL DELAY METHOD - A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled. | 2013-05-23 |
20130127509 | EMI SHIELDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An electromagnetic interference (EMI) shielding circuit and a semiconductor integrated circuit including the same are provided. The EMI shielding circuit includes a data level comparison unit, a control signal generation unit, and a driver for EMI cancellation. The data level comparison unit generates a data comparison signal by comparing a number of high-level data transmitted through a plurality of data lines and a number of low-level data transmitted through the plurality of data lines. The control signal generation unit generates a driving control signal in response to the data comparison signal. The driver for EMI cancellation outputs an EMI cancellation signal in response to the driving control signal. | 2013-05-23 |
20130127510 | ISOLATION INTERFACE CIRCUIT FOR POWER MANAGEMENT - An isolation interface circuit is disclosed. The isolation interface circuit comprising a transmitting circuit and a receiving circuit. The transmitting circuit configured to receive a first serial interface signal and a second serial interface signal for generating a differential polarity pulse signal. The receiving circuit configured to receive the differential polarity pulse signal for generating the first serial interface signal and the second serial interface signal. The differential polarity pulse signal are generated in response to the first serial interface signal and the second serial interface signal. The first serial interface signal and the second serial interface signal are generated in accordance with the differential polarity pulse signal. In a period, only one of the transmitting circuit and the receiving circuit can be enabled. | 2013-05-23 |
20130127511 | Method, Apparatus and System for Sensing a Signal With Automatic Adjustments for Changing Signal Levels - The present specification provides a method, apparatus and system for sensing a signal with automatic adjustments for changing signal levels. A novel fractional peak discriminator circuit is provided which can be incorporated into a system for measuring periodic signals from moving elements. The circuit can be used regardless of whether the periodic signals are detected using optics, magnetic detector or other methods. | 2013-05-23 |
20130127512 | MULTI-LEVEL CHIP INPUT - Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received. | 2013-05-23 |
20130127513 | TEMPERATURE COMPENSATION ATTENUATOR - In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change. | 2013-05-23 |
20130127514 | LEVEL TRANSLATOR - A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value. | 2013-05-23 |
20130127515 | VOLTAGE DIVIDING CIRCUIT - A voltage divider is disclosed that includes a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals. The voltage divider also includes a level shifter having a input terminal coupled to the reference voltage node and having a output terminal supplying an output reference voltage. | 2013-05-23 |
20130127516 | Offset Cancellation for Sampled-Data Circuits - A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period | 2013-05-23 |
20130127517 | DEBOUNCE APPARATUS AND METHOD THEREOF - A debounce apparatus and a method thereof are provided, which includes a debounce module, a register and a timer. The debounce module receives an input signal and eliminates a bounce phenomenon of the input signal within a transient-time of the state-changing of the input signal to produce a debounce signal. The register outputs an output signal according to the value stored in the register. When the input signal changes its state, the timer starts time-counting according to a counting-value of settling-time; when the debounce signal changes its state, the timer recounts time; and when time-counting is ended and when the value corresponding to the debounce signal is different from the register's value, the register's value is updated by the value corresponding to the debounce signal. In this way, the apparatus can eliminate the system misjudgement problem caused by occurred voltage level errors in the stable state. | 2013-05-23 |
20130127518 | CONTROL CIRCUIT AND ELECTRONIC DEVICE - A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element. | 2013-05-23 |
20130127519 | Auto Switch Mosfet - In one preferred form shown in | 2013-05-23 |
20130127520 | TRACKING CIRCUIT - A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage. | 2013-05-23 |
20130127521 | Semiconductor Device with Multiple Space-Charge Control Electrodes - A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal. | 2013-05-23 |
20130127522 | SYSTEM AND METHOD FOR GENERATING ABRITRARY VOLTAGE WAVEFORMS - An electrical system for generating arbitrary voltage waveform includes a power supply unit for providing a supply voltage to the electrical system. One or more charge pumps are in electrical communication with the power supply unit. Each charge pump generates a voltage. The electrical system also includes a plurality of switches, a first switch among the plurality of switches coupled between a ground and an output terminal, other switches among the plurality of switches coupled between the one or more charge pumps and the output terminal. A control circuit is in electrical communication with the power supply unit, the plurality of switches and the one or more charge pumps, and is operable to control the voltage generated by the each charge pump and the plurality of switches. Voltages from the one or more charge pumps additively result in a variable output voltage that generates an arbitrary voltage waveform. | 2013-05-23 |
20130127523 | DEVICE AND METHOD FOR PROVIDING POWER TO A MICROCONTROLLER - A charge pump device and method for providing power to a microcontroller where the voltage required to operate the microcontroller (VCCmin) is greater than the voltage of the power source, which may be a single galvanic cell. The invention utilizes a flying capacitor circuit having a flying capacitor, and a supply capacitor connected to the power supply terminal of the microcontroller. The invention utilizes firmware that runs on the microcontroller and which controls the flying capacitor circuit to repeatedly switch the flying capacitor from being connected in series with the power source to being connected in parallel with the power source so as to maintain the voltage provided to the microcontroller at a level of at least VCCmin. | 2013-05-23 |
20130127524 | HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE - A high-voltage integrated circuit device can include, in a surface layer of a p semiconductor substrate, an n region which is a high-side floating-potential region, an n | 2013-05-23 |
20130127525 | IC CIRCUIT - The present invention relates to an IC circuit. In an embodiment, an IC circuit includes: an RT terminal connected to an external; a current mirroring unit conducting a channel current between internal voltage power and the RT terminal and generating an internal reference current mirrored with the channel current; a negative feedback unit receiving the internal reference current, equalizing voltages of an RT terminal connection terminal and an internal reference current output terminal of the current mirroring unit to make the internal reference current constant, and providing the internal reference current inside the IC circuit; and an IC state indicating unit having a transistor, which operates complementarily with the current mirroring unit, connected between the RT terminal and a ground and providing the state of an IC or a system to the RT terminal by being linked with the complementary operation of the current mirroring unit. | 2013-05-23 |
20130127526 | LOW NOISE AUTO-ZERO CIRCUITS FOR AMPLIFIERS - An amplifier may include a low noise auto-zero circuit with auto-zero capacitors and switch-controlled auxiliary capacitors that function as switched-capacitor low-pass filters. In an acquisition phase of the auto-zero operation, the inputs of an amplifier may be shorted to a common voltage, and a representation of the offset voltage may be acquired by the auto-zero capacitors. In a hold phase of the auto-zero operation, the auto-zero capacitors may be connected to the auxiliary capacitors, and the resulting voltages may be applied to the circuit such that the original offset voltage is cancelled. Moreover, the switched-capacitor filters may reduce the effective sampling noise while maintaining high acquisition bandwidth. | 2013-05-23 |
20130127527 | CONTROL METHOD, APPARATUS OF PEAK AMPLIFIER AND DOHERTY POWER AMPLIFIER - A control method and apparatus of a peak amplifier of a Doherty power amplifier are disclosed, wherein, the control apparatus includes a Radio Frequency (RF) switching circuit in a peak amplification branch of the Doherty power amplifier, which is used to control the turn-on and turn-off of the peak amplifier in the peak amplification branch. The method and apparatus avoid a disadvantage that the peak branch in the Doherty power amplifier is turned on ahead of time, thus reducing the power consumption of the peak power amplifier, and enhancing the mass efficiency of the whole power amplifier; and largely reducing the product expense and production expense of the power amplifier compared to the scheme of some manufacturers improving on-time of the peak power amplifier using complex digital circuits. | 2013-05-23 |
20130127528 | POWER AMPLIFIER AND AMPLIFICATION METHOD THEREOF - Provided are a power amplifier and a method thereof. The power amplifier power amplifier includes: a main amplifying unit receiving power; an auxiliary amplifying unit connected in parallel to the main amplifying unit; and a balloon transformer combined with the main amplifying unit and the auxiliary amplifying unit. Respectively different bias voltages are applied to the main amplifying unit and the auxiliary amplifying unit. | 2013-05-23 |
20130127529 | AUTOMATIC GAIN CONTROL DEVICE - A first frequency converter generates an I-system baseband signal based on a high-frequency received signal and a first local signal with a predetermined frequency band. A second frequency converter generates a Q-system baseband signal based on a high-frequency received signal and a second local signal 90° out of phase with the first local signal. First and second AD converters convert respective amplified I-system and Q-system baseband signals to digital data. First and second over-range detecters detect the over-range of the first and the second CAD converters. An automatic gain controller selects the gain based on the detection information of the over-range and the respective I-system and Q-system baseband signals. An offset setter gives a predetermined offset to the selected gain, and sets a gain after the offset with respect to the first or the second variable amplifier. | 2013-05-23 |
20130127530 | MULTI-LEVEL BOOSTED CLASS D AMPLIFIER - Techniques to generate boosted multi-level switched output voltages from a boosted multi-level Class D amplifier. The amplifier may include a multi-level H-bridge, which may include pairs of transistor switches coupled to a first, second, and third supply potential. The second supply potential may be a boosted representation of the first supply potential. The amplifier may receive an input signal, and from the input signal may generate pulse-modulated control signals to control the switching for the transistor switches of the multi-level H-bridge. The amplifier may generate the boosted multi-level switched output voltages from output nodes of the multi-level H-bridge. | 2013-05-23 |
20130127531 | AMPLIFIER CIRCUIT WITH OFFSET CONTROL - Methods and apparatus for Class-D amplifier circuits with D.C. offset control/correction. A Class-D amplifier is described having an output stage, such as a full H-bridge or half bridge, with a plurality of switches operable to provide a plurality of output states comprising at least a positive output state and a negative output state. Control circuitry is configured to receive a first signal based on the input signal and produce a digital control signal, which is used to determine the switch state of the output stage. A digital integrator is configured to receive a feedback signal indicative of the output state of the output stage and to sample the feedback signal at a sample rate and produce an integrated output signal (INT, IVC) indicating the difference in number of instances of the positive output state and the negative output state. Correction circuitry subtracts the integrated output signal from the input signal to produce a D.C. offset corrected signal. | 2013-05-23 |
20130127532 | SWITCHED-MODE POWER SUPPLY APPARATUS AND METHOD - The present invention relates to a switched-mode power supply apparatus and a corresponding method. For an effective compensation of non-linearities caused by dead-time and voltage drops in the switching power amplifier of the apparatus, an apparatus is proposed comprising a switching power amplifier ( | 2013-05-23 |
20130127533 | OPERATIONAL AMPLIFIER HAVING LOW POWER CONSUMPTION - The present invention relates to an operational amplifier having low power consumption, which comprises a differential circuit, an output-stage circuit, and a floating bias generating circuit. The differential circuit receives an input signal and produces a control signal. The output-stage circuit is coupled to the differential circuit and produces an output signal according to the control signal. The floating bias generating circuit is coupled between the differential circuit and the output-stage circuit and generates a floating bias according to the control signal for controlling the rising or lowering of the voltage level of the output signal. Accordingly, the operational amplifier can charge and discharge rapidly, and thus extending the applications of the operational amplifier. Besides, the floating bias generating circuit can limit the output current while the operational amplifier is driving, and thus achieving the purpose of low power consumption. | 2013-05-23 |
20130127534 | VARIABLE PHASE AMPLIFIER CIRCUIT AND METHOD OF USE - A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair. | 2013-05-23 |
20130127535 | Method and System for Optoelectronic Receivers for Uncoded Data - A method and system for optoelectronic receivers for uncoded data are disclosed and may include amplifying received electrical signals in a signal amplifier comprising differential gain stages with signal detectors coupled to the outputs. First and second output voltages may be tracked and held utilizing the signal detectors. A difference between the tracked and held value may be amplified in a feedback path of the gain stage, which enables the dynamic configuration of a decision level. The received electrical signals may be generated from an optical signal by a PIN detector, an avalanche photodiode, or a phototransistor. The electrical signal may be received from a read channel. The feedback path may comprise digital circuitry, including an A/D converter, a state machine, and a D/A converter. The detectors may comprise envelope detectors utilized to detect maximum or minimum voltages. The signal amplifier may be integrated in a photonically-enabled CMOS chip. | 2013-05-23 |
20130127536 | FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER WITH COMMON-MODE FEEDBACK CIRCUIT - A fully differential operational amplifier includes a differential input stage, at least one output stage and a common-mode feedback circuit connected with the input stage. The differential input stage includes a differential pair of transistors and a bias circuit for the differential pair of transistors. A start-up circuit operates to detect an operating condition of the differential pair of transistors of the input stage and in response thereto turn on the bias circuit. | 2013-05-23 |
20130127537 | OUTPUT COMMON MODE VOLTAGE STABILIZER OVER LARGE COMMON MODE INPUT RANGE IN A HIGH SPEED DIFFERENTIAL AMPLIFIER - A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage. | 2013-05-23 |
20130127538 | CMOS INTEGRATED CIRCUIT AND AMPLIFYING CIRCUIT - There is provided a CMOS integrated circuit suppressing gate resistance and preventing increase in noise figure (NF), while an input transistor has a comb structure. The transistor includes: a gate electrode extended from a gate wiring to form a comb shape and receiving an input signal from an input terminal; a source electrode extended from a source wiring facing the gate wiring to form a comb shape and connected to a ground terminal, comb teeth thereof being interposed in every other space between comb teeth of the gate electrode; a drain electrode extended from a drain wiring facing the gate wiring to form a comb shape, comb teeth thereof being interposed in every other space between comb teeth of the gate electrode where the comb teeth of the source electrode are absent, wherein an overlapping region between the gate electrode and the source electrode or the drain electrode is absent. | 2013-05-23 |
20130127539 | CMOS INTEGRATED CIRCUIT AND AMPLIFYING CIRCUIT - There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit. | 2013-05-23 |
20130127540 | POWER AMPLIFIER - There is provided a power amplifier which may suppress fluctuations in a phase of an output signal in accordance with fluctuations in a level of an input signal by varying an impedance between a signal input terminal and an amplification unit in accordance with a power level of an input signal. The power amplifier includes a bias voltage generation unit generating a bias voltage set in accordance with a power level of an input signal, an amplification unit amplifying the power level of the input signal in accordance with the bias voltage, and an impedance variation unit varying an impedance of a signal transmission path through which the input signal is transmitted to the amplification unit in accordance with the bias voltage. | 2013-05-23 |
20130127541 | Analog Pre-distortion Linearizer - An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics. | 2013-05-23 |
20130127542 | ACTIVE ANTENNA ARRANGEMENT WITH DOHERTY AMPLIFIER - A Doherty amplifier ( | 2013-05-23 |
20130127543 | POWER AMPLIFIER - A power amplifier includes an input terminal into which an input signal is input; a first amplification element amplifying the input signal; a second amplification element amplifying an output signal of the first amplification element; an output terminal from which an output signal of the second amplification element is output; a first matching circuit connected between an output of the second amplification element and the output terminal; a first switch connected between an output of the first amplification element and an input of the second amplification element; a second switch having a first end connected to the output of the first amplification element, and a second end; and a second matching circuit having a first end connected to the second end of the second switch, and a second end directly connected to the output of the second amplification element. | 2013-05-23 |
20130127544 | AMPLIFIER CIRCUIT - According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage. | 2013-05-23 |
20130127545 | BIAS CURRENT MONITOR AND CONTROL MECHANISM FOR AMPLIFIERS - Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled. | 2013-05-23 |
20130127546 | BIAS CURRENT MONITOR AND CONTROL MECHANISM FOR AMPLIFIERS - Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled. | 2013-05-23 |
20130127547 | EFFICIENT SUPPLY VOLTAGE - There is disclosed an arrangement comprising: a driver stage connected to receive an input signal and generate a drive signal; a transformer comprising: a first winding of a first side of the transformer, across which winding a voltage signal is developed in dependence on the drive signal; and a second winding of the first side of the transformer, coupled to the first winding, which exhibits across it a voltage signal related to the voltage across the first winding, by swingback; and a first controller for comparing the voltage exhibited in the second winding to a first threshold voltage, and for selecting a first or a second supply voltage for the arrangement in dependence on the comparison. | 2013-05-23 |
20130127548 | APPARATUS AND METHODS FOR VOLTAGE CONVERTERS - Apparatus and methods for voltage converters are provided. In one embodiment, a voltage conversion system includes a bypass circuit and a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor. The bypass circuit includes a first p-type field effect transistor (PFET), a second PFET, a first n-type field effect transistor (NFET), and a second NFET. The first and second NFET transistors and the first and second PFET transistors are electrically connected between a first end and a second end of the inductor such that a source of the first PFET transistor and a drain of the first NFET transistor are electrically connected to the first end of the inductor and such that a drain of the second PFET transistor and a source of the second NFET transistor are electrically connected to the second end of the inductor. | 2013-05-23 |
20130127549 | CLOCK SIGNAL SYNCHRONIZATION AND DISTURBANCE DETECTOR - An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance. | 2013-05-23 |
20130127550 | FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION - A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers. | 2013-05-23 |
20130127551 | CRYSTAL REFERENCE OSCILLATOR FOR NAVIGATION APPLICATIONS - A resonator-controlled oscillator arrangement comprises a resonator-controlled oscillator of which the operating frequency is adjustable and a control circuit for setting the operating frequency of the oscillator. The control circuit is operative to set the operating frequency in dependence upon prevailing ambient conditions. The control circuit has a control input for initiating a set-up procedure during which the operating frequency of the oscillator is set to a value remote from any resonance frequency of a coupled mode that would cause an activity dip. | 2013-05-23 |
20130127552 | Ovenized System Containing Micro-Electromechanical Resonator - Disclosed an electronic device comprising an ovenized system containing a micro-electromechanical (MEM) resonator and a method for controlling such an MEM resonator. In one embodiment, the MEM resonator comprises a resonator body suspended above a substrate by means of at least a first and a second mechanical support forming a first and a second heating resistance, respectively, configured to heat the resonator body through Joules heating, biasing means configured to apply a bias voltage to the resonator body to enable vibration at a predetermined operating frequency, a temperature control system configured to control the temperature of the micro-electromechanical resonator, and an internal voltage monitoring system configured to monitor a voltage level of the resonator body. | 2013-05-23 |
20130127553 | PARAMETRIC OSCILLATOR AND METHOD FOR GENERATING ULTRA-SHORT PULSES - The invention relates to a parametric oscillator ( | 2013-05-23 |
20130127554 | SURFACE ACOUSTIC WAVE RESONATOR, SURFACE ACOUSTIC WAVE OSCILLATOR, AND SURFACE ACOUSTIC WAVE MODULE UNIT - It is possible to reduce the size of a surface acoustic wave (SAW) resonator by enhancing a Q value. In a SAW resonator in which an IDT having electrode fingers for exciting SAW is disposed on a crystal substrate, the IDT includes a first region disposed at the center of the IDT and a second region and a third region disposed on both sides of the first region. A frequency is fixed in the first region and a portion in which a frequency gradually decreases as it approaches an edge of the IDT is disposed in the second region and the third region. When the frequency of the first region is Fa, the frequency at an edge of the second region is Fb | 2013-05-23 |
20130127555 | Systems and Methods for Reducing Frequency Pulling in an Oscillator Circuit - Methods and systems are provided to calibrate an oscillator circuit to reduce frequency pulling as a result of a change in power to a portion of the oscillator circuit. In an embodiment, an oscillator is coupled to a clock buffer circuit and a tuning capacitor configured to tune a frequency of the oscillator to a baseline frequency required for cellular communications. A change in power to the clock buffer circuit initiates a change in an amount of capacitance seen by the oscillator, which negatively impacts the tuning of the oscillator. A register stores a frequency offset caused by the change in power, and the tuning capacitor is adjusted, using the frequency offset, in response to the change in power, such that the total amount of capacitance seen by the oscillator is not changed when the change in power occurs. | 2013-05-23 |
20130127556 | POWER SUPPLY MODULATOR AND METHOD FOR CONTROLLING SAME - A power amplifier amplifies a radio signal. Negative feedback is applied to a linear amplifier and the linear amplifier receives an envelope signal. A pulse current modulator is connected to a power supply terminal of a power amplifier and an output terminal of the linear amplifier via an inductor, and outputs a pulse current according to a control signal generated from the envelope signal. A diode has an anode connected to an output terminal of a direct current source and a cathode connected to an output terminal of the pulse current modulator. A switching element is disposed between the output terminal of the direct current source and a ground potential, and is controlled by the control signal. | 2013-05-23 |
20130127557 | SYSTEM AND METHOD OF MAINTAINING GAIN LINEARITY OF VARIABLE FREQUENCY MODULATOR - A variable frequency modulator including a compensation network, first and second pulse control networks and a linearity controller. The compensation network is configured to provide a compensation signal indicative of an output load condition. The first pulse control network is configured to initiate pulses on a pulse control signal and to adjust operating frequency based on changes of the compensation signal. The second pulse control network is configured to terminate the pulses on the pulse control signal based on a predetermined timing parameter. The linearity controller is configured to adjust timing of terminating the pulses based on a predetermined steady state operating frequency and an actual operating frequency to maintain modulator gain at a constant level. | 2013-05-23 |
20130127558 | Method for Providing a Modulation Scheme - A method for providing a first modulation scheme based on a second modulation scheme, the second modulation scheme including a first constellation point associated with a first bit pattern and a second constellation point associated with a second bit pattern. The method includes mapping the second bit pattern from the second constellation point to the first constellation point, wherein an energy associated with the second constellation point is greater than an energy associated with the first constellation point. | 2013-05-23 |
20130127559 | SUPPRESSION OF FAR-END CROSSTALK AND TIMING JITTER BY USING RECTANGULAR RESONATORS - Rectangular-shape resonators as guard traces formed in a region between the victim and aggressor lines are disclosed. No shorting-vias or resistors are required. The rectangular resonators are found to have functions of improving far-end crosstalk (FEXT) and timing jitter in both frequency domain and time domain if the parameters are appropriated selected. | 2013-05-23 |
20130127560 | HIGH-FREQUENCY SIGNAL TRANSMISSION LINE - Unwanted radiation is reduced in a high-frequency signal transmission line that includes a ground conductor provided with an opening that overlaps a signal line. A dielectric element assembly has a relative dielectric constant ∈ | 2013-05-23 |
20130127561 | Tunable Microwave Devices with Auto-Adjusting Matching Circuit - An embodiment of the present disclosure provides an impedance matching circuit including a matching network. The matching network includes a first port and a second port, and one or more variable reactance components. The one or more variable reactance components are operable to receive one or more variable voltage signals to cause the one or more variable reactance components to change an impedance of the matching network. At least one of the one or more variable reactance components includes a first conductor coupled to one of the first port or the second port of the matching network, a second conductor, and a tunable material positioned between the first conductor and the second conductor. Additionally, at least one of the first conductor and the second conductor are adapted to receive the one or more variable voltage signals to cause the change in the impedance of the matching network. Additional embodiments are disclosed. | 2013-05-23 |
20130127562 | SURFACE MOUNTABLE MICROWAVE SIGNAL TRANSITION BLOCK FOR MICROSTRIP TO PERPENDICULAR WAVEGUIDE TRANSITION - A surface mountable transition block for perpendicular transitions between a microstrip or stripline and a waveguide. The transition block configuration allows for a reduction in the overall cost of a microwave circuit assembly because the circuit board to which the transition block is attached can be an FR-4 type circuit board as opposed to more expensive microwave circuit board materials. | 2013-05-23 |
20130127563 | HIGH FREQUENCY, HIGH BANDWIDTH, LOW LOSS MICROSTRIP TO WAVEGUIDE TRANSITION - Embodiments of the invention are directed toward a novel printed antenna that provides a low-loss transition into waveguide. The antenna is integrated with a heat spreader and the interconnection between the antenna and the output device (such as a power amplifier) is a simple conductive connection, such as (but not limited to), a wirebond. Integrating the antenna with the heat spreader in accordance with the concepts, circuits, and techniques described herein drastically shortens the distance from the output device to the waveguide, thus reducing losses and increasing bandwidth. The transition and technique described herein may be easily scaled for both higher and lower frequencies. Embodiments of the present apparatus also eliminate the complexity of the prior art circuit boards and transitions and enable the use of a wider range of substrates while greatly simplifying assembly. | 2013-05-23 |
20130127564 | RECONFIGURABLE WILKINSON POWER DIVIDER AND DESIGN STRUCTURE THEREOF - A reconfigurable Wilkinson power divider, methods of manufacture and design structures are provided. The structure includes a first port, and a first arm and a second arm connected to the first port. The first arm and the second arm each include one or more tunable t-line circuits. The structure also includes a second port and a third port connected to the first port via the first arm and second arm, respectively. | 2013-05-23 |
20130127565 | DUPLEXER - A duplexer includes a transmission filter and a reception filter having different passbands, wherein: first resonators that are series resonators or parallel resonators included in the transmission and reception filters so as to form a skirt characteristic at a guard band side are a temperature compensated type piezoelectric thin film resonator or a surface acoustic wave resonator using Love waves, and second resonators that form a skirt characteristic at an opposite side to the guard band are one of a temperature non-compensated type piezoelectric thin film resonator, a surface acoustic wave resonator using a lithium tantalate substrate or a substrate made by bonding a lithium tantalate substrate on a sapphire substrate, and a surface acoustic wave resonator using Love waves. | 2013-05-23 |
20130127566 | FILTER AND DUPLEXER - A filter includes: first series resonators and first parallel resonators that are connected in a ladder shape between an input terminal and an output terminal; a first inductor that is connected in parallel to at least one first series resonator; one or more second parallel resonators that are provided separately from the first parallel resonators, are connected between the input terminal and the output terminal, and have a resonance frequency and an anti-resonance frequency at frequencies lower than a passband formed by the first series resonators and the first parallel resonators; wherein an attenuation region is formed by a first attenuation pole formed by the at least one first series resonator and the first inductor and a second attenuation pole formed by a resonant response of the one or more second parallel resonators. | 2013-05-23 |
20130127567 | CAPACITIVE FILTERED FEEDTHROUGH ARRAY FOR IMPLANTABLE MEDICAL DEVICE - In one example, a filtered feedthrough assembly for a medical device, such as, e.g., an implantable medical device, is described. The filtered feedthrough assembly may comprise a feedthrough comprising at least one feedthrough conductive pathway extending between a first feedthrough side and a second feedthrough side; a capacitive filter array comprising at least one filter array conductive pathway extending between a first filter array side and a second filter array side, and at least one capacitor filter substantially surrounding at least a portion the at least one filter array conductive pathway; and at least one electrically conductive member electrically coupling the at least one filter array conductive pathway to the at least one feedthrough conductive pathway. | 2013-05-23 |
20130127568 | DIELECTRIC CERAMIC AND DIELECTRIC FILTER UTILIZING SAME - A dielectric ceramic includes a main crystal phase containing Ba, Nd and Ti; and a remainder, part of Ti contained in the main crystal phase being substituted with Al, a content of the Al contained in the main crystal phase to a total content of Al in the main crystal phase and the remainder being greater than or equal to 10% on Al | 2013-05-23 |
20130127569 | Method for Manufacturing Resonant Tube, Resonant Tube and Cavity Filter - A method for manufacturing a resonant tube is provided in the present invention, which comprises: mechanically mixing 88-98 wt. % of iron-nickel alloy powder, 1-8 wt. % of carbonyl iron powder, and 1-8 wt. % of carbonyl nickel powder to form a uniform powder mixture; molding the uniform powder mixture to form a resonant tube blank; and continuously sintering and annealing the resonant tube blank. Also provided in the present invention are a resonant tube and a cavity filter. The method for manufacturing a resonant tube provided in the present invention significantly enhances production efficiency while greatly reducing consumption of raw materials. Moreover, the resonant tube provided in the present invention reduces, to the greatest extent, segregation of alloy components and coarse and uneven microstructures, thereby increasing the performance and stability of the corresponding products. | 2013-05-23 |
20130127570 | ELECTROMAGNETIC CONTACTOR - Provided is an electromagnetic contactor ( | 2013-05-23 |
20130127571 | CONTACT DEVICE AND ELECTROMAGNETIC SWITCH USING CONTACT DEVICE - A contact device includes a pair of fixed contactors fixed to one side of an insulation container with a predetermined space therebetween and having a columnar shape with a tip end contact surface protruding at lease inside the insulation container, and a movable contactor disposed to be capable of contacting with and separating from the pair of fixed contactors. Surfaces of the pair of fixed contactors facing the movable contactor are formed of annular peripheral walls having a concave part at a center thereof. An annular arc is formed between the annular peripheral wall and the movable contactor when the contact device is in an open state. | 2013-05-23 |
20130127572 | ACTUATION DEVICE - An electromagnetic actuation device with an actuation element, which can be adjusted relative to a stator on the basis of a magnetic actuation force which can be generated by the stator, wherein the stator has a coil winding, the winding wire of which is guided to a contact element bent at a bending region and is fixedly and electrically conductively connected to the same, wherein the contact element ( | 2013-05-23 |
20130127573 | COMMUNICATION TERMINAL APPARATUS AND ANTENNA DEVICE - An antenna device which includes a coil conductor and a booster conductor. The coil conductor is defined by wound loop-shaped conductors and includes a first opening at a winding center and two ends connected to a feeding circuit. The booster conductor includes a coupling conductor portion and a frame-shaped radiation conductor portion. The coupling conductor portion includes a second opening overlapped at least partially by the first opening, is split in a portion thereof by a slit, and is electromagnetically coupled to the coil conductor. The frame-shaped radiation conductor portion includes a third opening and is connected to the coupling conductor portion. | 2013-05-23 |
20130127574 | OUTER CORE MANUFACTURING METHOD, OUTER CORE, AND REACTOR - When an outer core that is to be mounted on a reactor is seen in plan, the outer core is a compact that has a plan-view shape in which a side of the outer core that is opposite to a facing side of the outer core, which faces the inner cores, has a smaller dimension in a width direction, which is parallel to a facing surface, than the facing side of the outer core. A method of manufacturing such an outer core includes a preparing step and a compacting step. In the preparing step, coated soft magnetic powder including multiple coated soft magnetic particles formed by coating soft magnetic particles with insulating coated films is prepared as raw-material powder of the outer core. In the compacting step, a compacting space | 2013-05-23 |
20130127575 | TRANSFORMER AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a transformer and a method of manufacturing the same. The transformer includes: a primary side winding having a loop shape; a secondary side winding formed on the same plane as that of the primary side winding in a remaining section except for at least a section at which it intersects with the primary side winding and having the same loop shape as that of the primary side winding so as to be electromagnetically coupled to the primary side winding; and an intersecting section formed so that the primary side and secondary side windings having the sum of the turn numbers of 3 or more intersect with each other in a two-layer structure, wherein the intersecting section includes at least one point of intermediate node having one side connected in a first layer and the other side connected in a second layer. | 2013-05-23 |
20130127576 | LAMINATED INDUCTOR - A laminated inductor offers higher magnetic permeability, high inductance, low resistance and high rated current, while also supporting downsizing of device, by using a soft magnetic alloy as the magnetic material. Provided is a laminated inductor, comprising: an internal conductor forming area and a top cover area and a bottom cover area formed in a manner sandwiching the internal conductor forming area from above and below, wherein the internal conductor forming area has a magnetic material part formed by soft magnetic alloy particles, and internal conductors buried in the magnetic material part, and at least one of the top cover area and bottom cover area is formed by soft magnetic alloy particles exhibiting a two-peak particle size distribution curve (based on count). | 2013-05-23 |
20130127577 | Micromagnetic Device and Method of Forming the Same - A micromagnetic device includes a first insulating layer formed above a substrate, a first seed layer formed above the first insulating layer, a first conductive winding layer selectively formed above the first seed layer, and a second insulating layer formed above the first conductive winding layer. The micromagnetic device also includes a first magnetic core layer formed above the second insulating layer, a third insulating layer formed above the first magnetic core layer, and a second magnetic core layer formed above the third insulating layer. The micromagnetic device still further includes a fourth insulating layer formed above the second magnetic core layer, a second seed layer formed above the fourth insulating layer, and a second conductive winding layer formed above the second seed layer and in vias to the first conductive winding layer. The first and second conductive winding layers form a winding for the micromagnetic device. | 2013-05-23 |
20130127578 | METHOD FOR FABRICATING A THREE-DIMENSIONAL INDUCTOR CARRIER WITH METAL CORE AND STRUCTURE THEREOF - A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures. | 2013-05-23 |
20130127579 | REACTOR AND MANUFACTURING METHOD THEREOF - A reactor comprises a reactor core in which two U-shaped core members are connected in a ring shape with gap sections including adhesive layers therebetween, a primary insert-molded resin part which is provided covering leg parts of the core member and which includes joint sections formed around end surfaces of the leg parts a coil placed around the gap sections and the leg parts of the core members, and a secondary insert-molded resin part which is made of a thermoplastic resin and which is insert-molded around the coil to fix the coil on the reactor core and fix the leg parts of the two core members in a connected state, wherein the joint sections of the primary insert-molded resin parts are fitted to each other in a state where the core members are placed connected in a ring shape, to form a peripheral wall surrounding the gap section. | 2013-05-23 |
20130127580 | SHIELDED POWER COUPLING DEVICE - Axisymmetric solid of revolution derivable from section at FIG. | 2013-05-23 |
20130127581 | CURRENT TRANSFORMER - Exemplary embodiments are directed to a current transformer having a toroidal magnetic core around which an even number of shielding coils is wound. The shielding coils are operatively associated two by two to form corresponding couples. The shielding coils of each couple are wound on parts of the toroidal magnetic core opposite to each other and are connected in parallel to each other for obtaining a magnetic flux in them. The magnetic flux in a first shielding coil of a couple of shielding coils has an opposite direction with respect to a magnetic flux in a second shielding coil of the couple. The couples of shielding coils are connected in series. | 2013-05-23 |
20130127582 | SINGLE- OR MULTI-PHASE DRY-TYPE TRANSFORMER HAVING AT LEAST TWO COILS - A single- or multi-phase dry-type transformer includes at least two coils. A barrier between phases made of an electrically insulating material is arranged in the intermediate space between the individual coils. | 2013-05-23 |
20130127583 | DEVICE FOR PROTECTING AN ELECTRICAL CIRCUIT FED BY AN ALTERNATING CURRENT WHICH CAN BE INTEGRATED INTO A CONTACTOR - Device for protecting an electrical circuit fed by an alternating current, comprising a housing and a fuse element disposed in the housing. The housing comprises a first portion and a second portion which are mobile in relation to one another, and elastic means suitable for causing the first portion to bear against the second portion and causing the housing to be set in a closed state. | 2013-05-23 |