21st week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130126883 | Wiring Material, Semiconductor Device Provided with a Wiring Using the Wiring Material and Method of Manufacturing Thereof - A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from −1×10 | 2013-05-23 |
20130126884 | ALUMINUM GALLIUM NITRIDE ETCH STOP LAYER FOR GALLIUM NITRIDE BASES DEVICES - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. | 2013-05-23 |
20130126885 | METHOD AND SYSTEM FOR FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS - A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer. | 2013-05-23 |
20130126886 | GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer. | 2013-05-23 |
20130126887 | LIGHT EMITTING DIODE - An LED includes a seat and an LED chip. The seat includes a main body, a first electrode protruding upwardly from the main body, and a second electrode formed on the main body. The LED chip includes a substrate, a first semiconductor layer disposed on the substrate, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, and a third electrode fixed on the second semiconductor layer. The first electrode extends through the substrate and electrically connects with the first semiconductor layer, and the third electrode electrically connects with the second electrode via a wire. | 2013-05-23 |
20130126888 | Edge Termination by Ion Implantation in GaN - An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure. | 2013-05-23 |
20130126889 | Manufacturable Enhancement-Mode Group III-N HEMT with a Reverse Polarization Cap - An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer. | 2013-05-23 |
20130126890 | INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES - A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array. | 2013-05-23 |
20130126891 | MICRO LIGHT EMITTING DIODE - A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate. | 2013-05-23 |
20130126892 | P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors - A new composition of matter is described, amorphous GaN | 2013-05-23 |
20130126893 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region). | 2013-05-23 |
20130126894 | LOW VOLTAGE DIODE WITH REDUCED PARASITIC RESISTANCE AND METHOD FOR FABRICATING - A method of making a diode begins by depositing an Al | 2013-05-23 |
20130126895 | Gallium Nitride Devices with Vias - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 2013-05-23 |
20130126896 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 2013-05-23 |
20130126897 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An electrode ( | 2013-05-23 |
20130126898 | GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT SOURCE PROVIDED WITH SAID LIGHT EMITTING ELEMENT - In a gallium nitride based compound semiconductor light-emitting element including an active layer, the active layer includes a well layer | 2013-05-23 |
20130126899 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor light emitting device includes: a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a first electrode on the first conductive type semiconductor layer, wherein the light emitting structure includes an outer groove formed at an outer area of the light emitting structure, wherein a thickness of an outmost area of the light emitting structure is smaller than a thickness of an center area of the light emitting structure, and wherein the first conductive type semiconductor layer includes AlGaN layer and the second conductive type semiconductor layer includes AlGaN layer. | 2013-05-23 |
20130126900 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Around a nitride-based semiconductor light-emitting element which has a polarization characteristic, a transparent encapsulating member which has a cylindrical shape is provided such that the symmetry plane of the cylindrical shape forms an angle of 25° to 65° with respect to the polarization direction of the nitride-based semiconductor light-emitting element. | 2013-05-23 |
20130126901 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer | 2013-05-23 |
20130126902 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer | 2013-05-23 |
20130126903 | DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer. | 2013-05-23 |
20130126904 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide layer includes a first region having a first conductivity type, a second region provided on the first region and having a second conductivity type, and a third region provided on the second region and having the first conductivity type. A trench having an inner surface is formed in the silicon carbide layer. The trench penetrates the second and third regions. The inner surface of the trench has a first side wall and a second side wall located deeper than the first side wall and having a portion made of the second region. Inclination of the first side wall is smaller than inclination of the second side wall. | 2013-05-23 |
20130126905 | SEMICONDUCTOR DEVICE WITH LOW-CONDUCTING BURIED AND/OR SURFACE LAYERS - A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency. | 2013-05-23 |
20130126906 | SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR, SILICON CARBIDE BULK SUBSTRATE FOR EPITAXIAL GROWTH AND MANUFACTURING METHOD THEREFOR AND HEAT TREATMENT APPARATUS - A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T | 2013-05-23 |
20130126907 | GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - [Problem] To provide a group III nitride semiconductor device and a method for manufacturing the same in which dislocation density in a semiconductor layer can be precisely reduced. | 2013-05-23 |
20130126908 | Memory Cells, And Methods Of Forming Memory Cells - Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells. | 2013-05-23 |
20130126909 | ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. | 2013-05-23 |
20130126910 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact. | 2013-05-23 |
20130126911 | STRESS ENHANCED JUNCTION ENGINEERING FOR LATCHUP SCR - A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR. | 2013-05-23 |
20130126912 | Light Emitting Device and Method of Driving the Light Emitting Device - A light emitting device that achieves long life, and which is capable of performing high duty ‘drive,’ by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method. | 2013-05-23 |
20130126913 | THIN MULTI-LAYER LED ARRAY ENGINE - A thin multi-layer LED array engine is provided, which includes a substrate having a phosphor layer and a silica gel protection layer formed thereon. The phosphor layer is disposed on LED dices and makes direct contact with the substrate, and the silica gel protection layer is disposed on the phosphor layer. The LED dices are covered with the phosphor layer, and thereby the phosphor particles in the phosphor layer can be uniformly dispersed around the LED dices, so that the narrow color temperature distribution can be achieved. Furthermore, the phosphor layer makes direct contacts with the substrate, and thereby heat generated in the phosphor layer can be effectively dissipated through the substrate, and thereby the reliability of the optical components can be increased. | 2013-05-23 |
20130126914 | HIGH-VOLTAGE AC LIGHT-EMITTING DIODE STRUCTURE - A high-voltage alternating current (AC) light-emitting diode (LED) structure is provided. The high-voltage AC LED structure includes a circuit substrate and a plurality of high-voltage LED (HV LED) chips. Each one of the HV LED chips includes a first substrate, an adhering layer, first ohmic contact layers, epi-layers, a first insulating layer, at least two first electrically conducting plates, at least two second electrically conducting plates, and a second substrate. The HV LED chips manufactured by a wafer-level process are coupled to the low-cost circuit substrate to produce the downsized high-voltage AC LED structure. | 2013-05-23 |
20130126915 | FLEXIBLE ACTIVE DEVICE ARRAY SUBSTRATE AND ORGANIC ELECTROLUMINESCENT DEVICE HAVING THE SAME - A flexible active device array substrate including a flexible substrate, an active device array layer, a barrier layer, and a plurality of pixel electrodes is provided. The active device array layer is disposed on the flexible substrate. The barrier layer covers the active device array layer. The barrier layer includes a plurality of organic material layers and a plurality of inorganic material layers. The organic material layers and the inorganic material layers are alternately stacked on the active device array layer. The pixel electrodes are disposed on the barrier layer, and each of the pixel electrodes is electrically connected to the active device array layer. | 2013-05-23 |
20130126916 | PACKAGE FOR MOUNTING ELECTRONIC COMPONENTS, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING THE PACKAGE - A package includes: a leadframe made of conductive material and on which the plurality of electronic components are to be mounted, the leadframe including a first surface and a second surface opposite to the first surface and including a plurality of elongate portions arranged in parallel to each other with a gap interposed between the adjacent elongate portions; a heat sink including a first surface and a second surface opposite to the first surface, wherein the leadframe is disposed above the heat sink such that the second surface of the leadframe faces the first surface of the heat sink; and a resin portion, wherein the leadframe and the heat sink are embedded in the resin portion such that the first surface of the leadframe and the second surface of the heat sink are exposed from the resin portion, respectively. | 2013-05-23 |
20130126917 | LIGHT EMITTING DIODES AND SUBSTRATES - A thin layer substrate has a plurality of micron sized electrically conductive whisker components which are arranged in parallel and extending from one surface of the substrate to another surface to provide electrically conductive paths though the substrate. Such a substrate may be usable for micron sized LEDs. | 2013-05-23 |
20130126918 | LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF - A light emitting device and a fabricating method thereof are described, wherein the light emitting device includes a substrate, a wall, a first LED chip and a light conversion filling. The first LED chip is disposed on a surface of the substrate. The wall is disposed on the surface of the substrate, and surrounds the first LED chip. A first angle between a central axis of the wall and an inner surface of the wall is 0 degree or is acute, a second angle between the central axis of the wall and an outer surface of the wall is 0 degree or is acute, and the outer surface of the wall and the substrate has a space therebetween. The light conversion filling is surrounded by the light conversion wall, and is disposed on the first LED chip. | 2013-05-23 |
20130126919 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to an embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a dielectric film and an electrode. The first semiconductor layer is capable of emitting light. The second semiconductor layer has a first major surface in contact with the first semiconductor layer and a second major surface opposite to the first major surface, the second major surface including a first region having convex structures and a second region not having the convex structures. The dielectric film is provided at least at a tip portion of the convex structures, and the electrode is provided above the second region. | 2013-05-23 |
20130126920 | Light-Emitting Diode Chip with Current Spreading Layer - A light-emitting diode chip includes a semiconductor layer sequence having a phosphide compound semiconductor material. The semiconductor layer sequence contains a p-type semiconductor region, an n-type semiconductor region, and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region. The active region serves to emit electromagnetic radiation. The n-type semiconductor region faces a radiation exit area of the light-emitting diode chip, and the p-type semiconductor region faces a carrier of the light-emitting diode chip. A current spreading layer having a thickness of less than 500 nm is arranged between the carrier and the p-type semiconductor region. The current spreading layer has one or a plurality of p-doped Al | 2013-05-23 |
20130126921 | INVERTED OPTICAL DEVICE - Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices. | 2013-05-23 |
20130126922 | LIGHT EMITTING DIODE INCORPORATING LIGHT CONVERTING MATERIAL - An LED includes an LED chip, an encapsulant for encapsulating the LED chip, and a lens attached to the encapsulant. The lens includes a main body, and a light converting unit with a light converting material distributed therein. The main body defines a receiving space facing the LED chip. The light converting unit is received in the main body. Light emitted by the LED chip passes through the light converting unit and then enters into the main body of the lens. The light converting material of the light converting unit changes a wavelength of the light of the LED chip when the light passes through the light converting unit. | 2013-05-23 |
20130126923 | SUBMOUNT FOR LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate. | 2013-05-23 |
20130126924 | LIGHT-EMITTING DIODE ELEMENT, METHOD FOR MANUFACTURING LIGHT GUIDE STRUCTURE THEREOF AND EQUIPMENT FOR FORMING THE SAME - A light-emitting diode (LED) element is provided. The LED element includes a substrate, a diode structure layer and several light-guide structures. The light-guide structures are formed on at least one of the substrate and the diode structure layer. Each light-guide structure has an inner sidewall, and several spiral slits formed on the inner side wall. | 2013-05-23 |
20130126925 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device, and a method for manufacturing the semiconductor light-emitting device, in which light propagating through a light-emitting layer and reaching an edge surface of a semiconductor film can be extracted to the exterior in an efficient manner. The semiconductor light-emitting device comprises a semiconductor film including a light-emitting layer made from a group III nitride semiconductor. The semiconductor film has a tapered edge surface inclined diagonally with respect to a light extraction surface. The light extraction surface has a relief structure comprising a plurality of protrusions having a shape originating from the crystal structure of the semiconductor film. The average size of the protrusions in a first region in the vicinity of an edge section of the light extraction surface is smaller than the average size of the protrusions in a second region. | 2013-05-23 |
20130126926 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor light emitting device which has a wavelength converting part on a semiconductor film and can eliminate unevenness in emission color without a reduction in light output. The semiconductor film includes a light emitting layer. The support substrate is bonded to the semiconductor film via a light-reflecting layer and has a support surface supporting the semiconductor film and edges located further out than the side surfaces of the semiconductor film. The light-shielding part covers the side surfaces of the semiconductor film and part of the support surface around the semiconductor film in plan view. The wavelength converting part contains a fluorescent substance and is provided over the support substrate to bury the semiconductor film and the light-shielding part therein. The wavelength converting part has a curved surface shape in which its thickness increases when going from the edges toward the center of the semiconductor film. | 2013-05-23 |
20130126927 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface. | 2013-05-23 |
20130126928 | LIGHT EMITTING DIODE CHIP, AND METHODS FOR MANUFACTURING AND PACKAGING THE SAME - A light emitting diode chip includes a substrate, an epitaxial layer, two inclined plane units, and two electrode units. The substrate has top and bottom surfaces. The epitaxial layer is disposed on the top surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer toward the bottom surface of the substrate, and includes an inclined sidewall formed on the epitaxial layer, and a substrate inclined wall formed on the substrate. Each of the electrode units includes an electrode disposed on the epitaxial layer, and a conductive portion extending from the electrode to the substrate inclined wall along corresponding one of the inclined plane units. | 2013-05-23 |
20130126929 | METHOD FOR MANUFACTURING NANO-IMPRINT MOULD, METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE USING THE NANO IMPRINT MOULD MANUFACTURED THEREBY, AND LIGHT-EMITTING DIODE MANUFACTURED THEREBY - A method of manufacturing a light emitting diode, includes a process of forming an n-type nitride semiconductor layer, a light emitting layer, and a p-type nitride semiconductor layer on a temporary substrate, a process of forming a p-type electrode on the p-type nitride semiconductor layer, a process of forming a conductive substrate on the p-type electrode, a process of removing the temporary substrate to expose the n-type nitride semiconductor layer, a process of forming a nanoimprint resist layer on the n-type nitride semiconductor layer, a process of pressing the nanoimprint mold on the nanoimprint resist layer to transfer the nano-pattern onto the nanoimprint resist layer, and a process of separating the nanoimprint mold from the nanoimprint resist layer having the nano-pattern and etching a portion of the nanoimprint resist layer having the nano-pattern to form an n-type electrode. | 2013-05-23 |
20130126930 | LIGHT SOURCE DEVICE - Disclosed herein is a light source device for converting excited light into long-wavelength light having a longer wavelength than the excited light. The light source includes: an excited light source emitting excited light; a wavelength conversion member including a light transmission plate and a wavelength conversion layer formed on the light transmission plate and receiving the excited light from the excited light source and emitting long-wavelength light having a longer wavelength than the excited light, the excited light emitted from the excited light source being incident upon one side of the wavelength conversion layer; a light reflection member provided at one side of the wavelength conversion member and including an excited light transmission window transmitting the excited light; and a filter member provided at the other side of the wavelength conversion member and reflecting the excited light and transmitting the long-wavelength light. | 2013-05-23 |
20130126931 | LIGHT EMITTING DIODE WITHOUT LEADS - An LED (light emitting diode) includes a seat and an LED chip. The seat includes a main body, and a first electrode and a second electrode formed on the main body. The LED chip includes a first semiconductor layer, an annular light-emitting layer encircling the first semiconductor layer, and an annular second semiconductor layer encircling the light-emitting layer. The first electrode electrically connects with the first semiconductor layer, and the second electrode electrically connects with the second semiconductor layer. | 2013-05-23 |
20130126932 | PACKAGE OF ENVIRONMENTAL SENSITIVE ELECTRONIC ELEMENT - A package of an environmental sensitive electronic element including a first substrate, a second substrate, an environmental sensitive electronic element, a flexible structure layer and a filler layer is provided. The environmental sensitive electronic element is disposed on the first substrate and located between the first substrate and the second substrate. The environmental sensitive electronic element includes an anode layer, a hole injecting layer, a hole transporting layer, an organic light emitting layer, a cathode layer and an electron injection layer. The flexible structure layer is disposed on the environmental sensitive electronic element and includes a soft layer, a trapping layer and a protective layer. The material of the trapping layer is the same as the material of the electron injection layer. The filler layer is disposed between the first substrate and the second substrate and encapsulates the environmental sensitive electronic element and the flexible structure layer. | 2013-05-23 |
20130126933 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic device contact structures are disclosed. | 2013-05-23 |
20130126934 | BONDING WIRE FOR SEMICONDUCTOR DEVICES - A bonding wire for semiconductor devices and a method of manufacturing the wire are provided. The bonding wire contains at least one element selected from zinc, tin, and nickel in an amount of 5 ppm to 10 wt %, the remainder containing silver and inevitable impurities. The method involves pouring a silver alloy according to the invention into a mold and melting the silver alloy, continuously casting the melted silver alloy, and drawing the continuously casted silver alloy. | 2013-05-23 |
20130126935 | Surface-Mountable Optoelectronic Component and Method for Producing a Surface-Mountable Optoelectronic Component - A surface-mountable optoelectronic component has a radiation passage face, an optoelectronic semiconductor chip and a chip carrier. A cavity is formed in the chip carrier and the semiconductor chip is arranged in the cavity. A molding surrounds the chip carrier at least in places. The chip carrier extends completely through the molding in a vertical direction perpendicular to the radiation passage face. | 2013-05-23 |
20130126936 | Light-Emitting Element and Display Device - When a light-emitting element having an intermediate conductive layer between a plurality of light-emitting layers is formed, the intermediate conductive layer can have transparency; and thus, materials are largely limited and the manufacturing process of an element becomes complicated by a conventional method. A light-emitting element according to the present invention is formed by sequentially stacking a pixel electrode, a first light-emitting layer, an intermediate conductive layer (including an electron injecting layer and a hole-injecting layer, one of which is island-like), a second light-emitting layer and an opposite electrode. Therefore, the present invention can provide a light-emitting element typified by an organic EL element in which a range of choice of materials that can be used as the intermediate conductive layer is broadened extremely, and which can realize a high light-emitting efficiency, a low power consumption and a high reliability, and further a display device using the light-emitting element. | 2013-05-23 |
20130126937 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed between the n-type semiconductor layer and the p-type semiconductor layer, and emitting light. The device further includes a p-electrode contacting to the p-type semiconductor layer, and including a first conductive oxide layer having an oxygen content lower than 40 atomic % and a second conductive oxide layer contacting to the first conductive oxide layer and having a higher oxygen content than the oxygen content of the first conductive oxide layer. The device also includes an n-electrode connecting electrically to the n-type semiconductor layer. | 2013-05-23 |
20130126938 | Optoelectronic Semiconductor Element and Associated Method of Production by Direct Welding of Glass Housing Components by Means of Ultra Short Pulsed Laser without Glass Solder - An optoelectronic semiconductor element having a light source, a housing and electrical terminals, wherein the optoelectronic semiconductor element comprises components, which are produced from glass, and wherein at least two components touch at boundary surfaces adjusted to one another and are welded to one another directly there. | 2013-05-23 |
20130126939 | SEALING FILM FORMING METHOD, SEALING FILM FORMING DEVICE, AND LIGHT-EMITTING DEVICE - A sealing film forming method is capable of forming a sealing film having high moisture permeability resistance in a shorter time and at lower cost. The sealing film forming method for forming a sealing film | 2013-05-23 |
20130126940 | LIGHT EMITTING DIODE ASSEMBLY AND THERMAL CONTROL BLANKET AND METHODS RELATING THERETO - The present disclosure relates generally to a light emitting diode assembly and a thermal control blanket. The light emitting diode assembly and the thermal control blanket have advantageous reflective and thermal properties. | 2013-05-23 |
20130126941 | SEMICONDUCTOR OPTICAL DEVICE - A semiconductor optical device includes a first clad layer, a second clad layer and an optical waveguide layer sandwiched between the first clad layer and the second clad layer, wherein the optical waveguide layer includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer and extending in one direction, and a third semiconductor layer covering a top surface of the second semiconductor layer, and wherein the first semiconductor layer includes an n-type region disposed on one side of the second semiconductor layer, a p-type region disposed on the other side of the second semiconductor layer, and an i-type region disposed between the n-type region and the p-type region, and wherein the second semiconductor layer has a band gap narrower than band gaps of the first semiconductor layer and the third semiconductor layer. | 2013-05-23 |
20130126942 | SEMICONDUCTOR DEVICE - A low-loss GaN-based semiconductor device is provided. | 2013-05-23 |
20130126943 | FIELD-EFFECT TRANSISTOR - An insulator is formed on the upper surface of a first semiconductor layer on at least a part of a portion above which a second semiconductor layer is not formed due to an opening. In the opening, a source electrode is formed to cover an insulator. The source electrode is formed to be in contact with an interface between the first semiconductor layer and the second semiconductor layer. | 2013-05-23 |
20130126944 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH EPITAXIAL EMITTER STACK TO IMPROVE VERTICAL SCALING - A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p | 2013-05-23 |
20130126945 | ULTRA HIGH VOLTAGE SIGE HBT AND MANUFACTURING METHOD THEREOF - An ultra high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which, a collector region is formed between two isolation structures; a pseudo buried layer is formed under each isolation structure and each side of the collector region is connected with a corresponding pseudo buried layer; a SiGe field plate is formed on each of the isolation structures; each pseudo buried layer is picked up by a first contact hole electrode and each SiGe field plate is picked up by a second contact hole electrode; and each first contact hole electrode is connected to its adjacent second contact hole electrode and the two contact hole electrodes jointly serve as an emitter. A manufacturing method of the ultra high voltage SiGe HBT is also disclosed. | 2013-05-23 |
20130126946 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask. | 2013-05-23 |
20130126947 | SEMICONDUCTOR GAS SENSOR - A semiconductor gas sensor is provided that includes a semiconductor body with a passivation layer formed on a surface of thereof. A gas-sensitive control electrode is separated from a channel region by a gap or a control electrode is arranged as a first plate of a capacitor with a gap and a second plate of the capacitor is connected to a gate of the field effect transistor implemented as a Capacitively Controlled Field Effect Transistor. The control electrode has is connected to a reference voltage. A support area is provided with a first support structure and a second support structure. A contact area is provided on the surface of the semiconductor body. A first contact region has a frictional connection and an electrical connection with the control electrode and the second contact region has at least a frictional connection with the control electrode. | 2013-05-23 |
20130126948 | METHOD FOR PRODUCING A MICROELECTROMECHANICAL DEVICE AND MICROELECTROMECHANICAL DEVICE - In a method for producing a micro-electromechanical device in a material substrate, component element defining the position of an electronic component and/or required for the function of the electronic component is selectively formed on the material substrate from an etching stop material acting as an etching stop in case of etching of the material substrate and/or in case of etching of a material layer disposed on the material substrate. When the component element of the electronic component is implemented, a bounding region is also formed on the material substrate along at least a partial section of an edge of the surface structure, wherein the bounding region bounds the partial section. The material substrate thus implemented is selectively etched for forming the surface structure, in that the edge of the bounding region defines the position of the surface structure to be implemented on the material substrate. | 2013-05-23 |
20130126949 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers. | 2013-05-23 |
20130126950 | Semiconductor Device and Method of Formation - A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region. | 2013-05-23 |
20130126951 | Method of Fabricating FinFET Device and Structure Thereof - The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions. | 2013-05-23 |
20130126952 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid-state imaging device includes: a semiconductor substrate; and a plurality of pixels arrayed two-dimensionally in the semiconductor substrate, each of the pixels having a photoelectric conversion element that performs photoelectric conversion, the photoelectric conversion element having a first impurity region, formed in the semiconductor substrate, containing an impurity of a first conductivity type; a second impurity region formed in the semiconductor substrate so as to be in contact with the first impurity region, containing an impurity of a second conductivity type different from the first conductivity type; and a PN junction portion in which the first impurity region and the second impurity region are in contact with each other, formed in a protruding shape projecting toward a surface side of the semiconductor substrate. | 2013-05-23 |
20130126953 | Methods and Apparatus for MOS Capacitors in Replacement Gate Process - Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed. | 2013-05-23 |
20130126954 | Dynamic Random Access Memory Array and Method of Making - The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array. | 2013-05-23 |
20130126955 | Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process - Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed. | 2013-05-23 |
20130126956 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor to disposed over the upper portion of the active region and the word line, | 2013-05-23 |
20130126957 | 3D Non-Volatile Memory With Metal Silicide Interconnect - A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays. | 2013-05-23 |
20130126958 | Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates - An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate. | 2013-05-23 |
20130126959 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern. | 2013-05-23 |
20130126960 | Semiconductor Device and Method of Manufacturing the Same - Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d | 2013-05-23 |
20130126961 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells. | 2013-05-23 |
20130126962 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. After spacers are formed on sidewalls of a pillar pattern and a photoresist pattern exposing an OSC formation region is formed on a semiconductor substrate including the pillar pattern and the spacer, processes for removing a spacer corresponding to the OSC formation region to form an OSC, removing the photoresist pattern, forming a bit line between the pillar patterns, an epitaxial layer on the pillar pattern, and forming a vertical gate and a storage node contact, are performed so that the OSC formation process can be simplified. In addition, the OSC formation process is performed in a state that the pillar pattern has a low height so that a failure such as a not-open failure caused in the OSC formation process can be prevented. | 2013-05-23 |
20130126963 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device. | 2013-05-23 |
20130126964 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for forming the same are disclosed, which can greatly reduce a cell area as compared to a conventional layout of 8F2 and 6F2, and need not form a bit line contact, a storage node contact, or a land plug, such that the number of fabrication steps is reduced and a contact region between the bit line and the active region is increased in size. The semiconductor device including a vertical transistor includes an active region formed over a semiconductor substrate, a first recess formed to have a predetermined depth at both sides of the active region, and a bit line buried in the first recess. | 2013-05-23 |
20130126965 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset. | 2013-05-23 |
20130126966 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 2013-05-23 |
20130126967 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n | 2013-05-23 |
20130126968 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region. | 2013-05-23 |
20130126969 | LATERAL DOUBLE DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film and lower an ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same. More specifically, when an n-drift region is formed on a P-type substrate, a p-body is formed on the n-drift region through an epitaxial process, and then the p-body region is partially etched to form a plurality of p-epitaxial layers, so that when the device executes an action for blocking a reverse voltage, depletion layers are formed between the junction surfaces of the p-epitaxial layers and the n-drift region including the junction surfaces between the n-drift region and the p-body. | 2013-05-23 |
20130126970 | CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE USING EMPTY AND FILLED WELLS - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs ( | 2013-05-23 |
20130126971 | SILICON-CARBIDE MOSFET CELL STRUCTURE AND METHOD FOR FORMING SAME - In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process. | 2013-05-23 |
20130126972 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions. | 2013-05-23 |
20130126973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress. | 2013-05-23 |
20130126974 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit is used in an integrated circuit with a first sub-circuit working with a first working voltage source and a second sub-circuit working with a second working voltage source lower than the first working voltage source. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor transistor of a first conductive type, having a drain thereof electrically connected to a pad of the integrated circuit, and gate, source and bulk thereof electrically connected to a bulk voltage; and a guard ring of the first conductive type, surrounding the first metal-oxide-semiconductor transistor of the first conductive type and coupled to the second working voltage source. | 2013-05-23 |
20130126975 | THIN FILM TRANSISTOR ARRAY AND CIRCUIT STRUCTURE THEREOF - A thin film transistor array and a circuit structure thereof are provided. The circuit structure includes a patterned metal layer, a transparent conductive layer and a dielectric layer. The transparent conductive layer is formed on and contacts a top surface of the patterned metal layer. The dielectric layer overlies and contacts the patterned metal layer and the transparent conductive layer. In addition, the dielectric layer has a contact window to expose a portion of the transparent conductive layer. The transparent conductive layer on the top surface of the patterned metal layer can protect the surface layer metal against damage during fabrication of the contact window. | 2013-05-23 |
20130126976 | SELECTIVE PARTIAL GATE STACK FOR IMPROVED DEVICE ISOLATION - A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure. | 2013-05-23 |
20130126977 | N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates. | 2013-05-23 |
20130126978 | CIRCUITS WITH LINEAR FINFET STRUCTURES - A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. | 2013-05-23 |
20130126979 | INTEGRATED CIRCUITS WITH ELECTRICAL FUSES AND METHODS OF FORMING THE SAME - A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer. | 2013-05-23 |
20130126980 | SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES HAVING CONDUCTIVE CONTACTS POSITIONED THEREBETWEEN - Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures. | 2013-05-23 |
20130126981 | MULTI-GATE SEMICONDUCTOR DEVICES - A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion. | 2013-05-23 |
20130126982 | EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICES - A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. | 2013-05-23 |