20th week of 2016 patent applcation highlights part 61 |
Patent application number | Title | Published |
20160141374 | ASPECT RATIO TRAPPING AND LATTICE ENGINEERING FOR III/V SEMICONDUCTORS - A method of forming a semiconductor structure. The method may include; forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate; relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor; forming barrier layers in the first trenches; forming a second trench between adjacent barrier layers; and growing a second semiconductor layer on the strained semiconductor having relaxed edges. | 2016-05-19 |
20160141375 | Field Plates on Two Opposed Surfaces of Double-Base Bidirectional Bipolar Transistor: Devices, Methods, and Systems - Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage. | 2016-05-19 |
20160141376 | Vertical Semiconductor Device and Method for Manufacturing Therefor - A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above. | 2016-05-19 |
20160141377 | LOW TEMPERATURE SPACER FOR ADVANCED SEMICONDUCTOR DEVICES - Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure. | 2016-05-19 |
20160141378 | THIN FILM TRANSISTOR SUBSTRATE - A thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and drain electrodes include a metal oxide having a crystal size in a c-axis direction Lc(002) that ranges from 67 Å or more to 144 Å or less. | 2016-05-19 |
20160141379 | INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region. | 2016-05-19 |
20160141380 | Method for Manufacturing a Semiconductor Device, and Semiconductor Device - A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode. | 2016-05-19 |
20160141381 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers. | 2016-05-19 |
20160141382 | Fabrication of Nanoscale Vacuum Grid and Electrode Structure With High Aspect Ratio Dielectric Spacers Between the Grid and Electrode - Some embodiments of vacuum electronics call for a grid that is fabricated in close proximity to an electrode, where, for example, the grid and electrode are separated by nanometers or microns. Methods and apparatus for fabricating a nanoscale vacuum grid and electrode structure are described herein. | 2016-05-19 |
20160141383 | INTERLAYER DIELECTRIC LAYER WITH TWO TENSILE DIELECTRIC LAYERS - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer. | 2016-05-19 |
20160141384 | MASK-LESS DUAL SILICIDE PROCESS - A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions. | 2016-05-19 |
20160141385 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° C. for 8 to 240 hours on the transistor; and after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C. | 2016-05-19 |
20160141386 | METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH LOW SEALING LOSS - A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer. | 2016-05-19 |
20160141387 | FIN SHAPED STRUCTURE AND METHOD OF FORMING THE SAME - A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure. | 2016-05-19 |
20160141388 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING MASKS HAVING VARYING WIDTHS - In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction. | 2016-05-19 |
20160141389 | Radiation Hardened MOS Devices and Methods of Fabrication - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 2016-05-19 |
20160141390 | METHOD FOR MANUFACTURING DISPLAY PANEL - A method for manufacturing display panel is disclosed, which comprises: (A) providing a substrate, an oxide semiconductor layer disposed on the substrate, and a gate electrode disposed on the substrate and corresponding to the oxide semiconductor layer; (B) forming a metal layer on the oxide semiconductor layer; (C) forming a photoresist on the metal layer, and etching the metal layer to form a source electrode and a drain electrode; (D) heating the photoresist and the photoresist covers at least partial of side walls of the source electrode and the drain electrode; (E) applying an alkaline solution on the substrate; and (F) removing the photoresist to expose the source electrode and the drain electrode. | 2016-05-19 |
20160141391 | Method for Reducing Contact Resistance in MOS - A method for growing a III-V semiconductor structure on a Si | 2016-05-19 |
20160141392 | METHODS OF MANUFACTURING FINFET SEMICONDUCTOR DEVICES USING SACRIFICIAL GATE PATTERNS AND SELECTIVE OXIDIZATION OF A FIN - A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate. | 2016-05-19 |
20160141393 | MEANDER RESISTOR - A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins. A mask is formed above the conductive layer. The conductive layer is etched using the mask to define trenches in the conductive layer. A first insulating layer is formed above the conductive layer and in the trenches. First and second contacts are formed connected to respective ends of the conductive layer. | 2016-05-19 |
20160141394 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING - A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided. | 2016-05-19 |
20160141395 | SiGe and Si FinFET Structures and Methods for Making the Same - FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. | 2016-05-19 |
20160141396 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy. | 2016-05-19 |
20160141397 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing Ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment. | 2016-05-19 |
20160141398 | TUNNEL FIELD-EFFECT TRANSISTOR (TFET) WITH SUPERSTEEP SUB-THRESHOLD SWING - Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (V | 2016-05-19 |
20160141399 | Method for Forming a Semiconductor Device and a Semiconductor Device - A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate. | 2016-05-19 |
20160141400 | SEMICONDUCTOR DEVICE - A semiconductor device is configured such that the distance between the trench gate in the IGBT and the trench gate in the diode is reduced or a p-well layer is provided between the trench gate in the IGBT and the trench gate in the diode. | 2016-05-19 |
20160141401 | SEMICONDUCTOR DEVICE - A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region. | 2016-05-19 |
20160141402 | SEMICONDUCTOR DEVICE - A semiconductor substrate is provided with a first cell region, the first cell region including: an n-type emitter region; a p-type first top body region; an n-type first barrier region; an n-type first pillar region; and a p-type first bottom body region, the semiconductor substrate may further comprise: an n-type drift region; a p-type collector region; an n-type cathode region, the n-type first barrier region may include a first peak position where a peak of the n-type impurity density is present within a part linked to the n-type first pillar region, and a second peak position where a peak of the n-type impurity density is present within a part in contact with the gate insulating layer, and a depth of the first peak position from a front surface of the semiconductor substrate is different from a depth of the second peak position from the front surface of the semiconductor substrate. | 2016-05-19 |
20160141403 | Semiconductor Device and Insulated Gate Bipolar Transistor with Transistor Cells and Sensor Cell - A transistor cell region of a semiconductor device includes transistor cells that are electrically connected to a first load electrode. An idle region includes a gate wiring structure that is electrically connected to gate electrodes of the transistor cells. A transition region, which is disposed between the transistor cell region and the idle region, includes at least one sensor cell that is electrically connected to a sense electrode. The at least one sensor cell is configured to convey a unipolar current during an on state of the transistor cells. | 2016-05-19 |
20160141404 | STRUCTURE FOR A GALLIUM NITRIDE (GaN) HIGH ELECTRON MOBILITY TRANSISTOR - A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided. | 2016-05-19 |
20160141405 | Semiconductor Field Plate for Compound Semiconductor Devices - A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein. | 2016-05-19 |
20160141406 | Semiconductor to Metal Transition - A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region. | 2016-05-19 |
20160141407 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided, the method including forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching. | 2016-05-19 |
20160141408 | SUPER JUNCTION FIELD EFFECT TRANSISTOR WITH INTERNAL FLOATING RING - A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped P− type columns, a floating ring-shaped P− type column that surrounds the set of strip-shaped P− type columns, and a set of ring-shaped P− type columns that surrounds the floating ring-shaped P− type column. A source metal is disposed above portions of the charge compensation region. The source metal contacts each of the strip-shaped P− type columns and each of the ring-shaped P− type columns. An oxide is disposed between the floating P− type column and the source metal such that the floating P− type column is electrically isolated from the source metal. The device exhibits a breakdown voltage that is 0.2% greater than if the floating P− type column were to contact the source metal. | 2016-05-19 |
20160141409 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench. | 2016-05-19 |
20160141410 | SEMICONDUCTOR COMPONENT WITH DYNAMIC BEHAVIOR - One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches. | 2016-05-19 |
20160141411 | HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2016-05-19 |
20160141412 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage. | 2016-05-19 |
20160141413 | SEMICONDUCTOR DEVICES - Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region. | 2016-05-19 |
20160141414 | METHOD AND APPARATUS FOR POWER DEVICE WITH DEPLETION STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region. | 2016-05-19 |
20160141415 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region. | 2016-05-19 |
20160141416 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS - Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described. | 2016-05-19 |
20160141417 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction. | 2016-05-19 |
20160141418 | Embedded JFETs for High Voltage Applications - A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. | 2016-05-19 |
20160141419 | THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF - A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate. | 2016-05-19 |
20160141420 | HIGH-VOLTAGE FINFET DEVICE HAVING LDMOS STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region. | 2016-05-19 |
20160141421 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 2016-05-19 |
20160141422 | SEMICONDUCTOR DEVICE - A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is T | 2016-05-19 |
20160141423 | Contacts For Highly Scaled Transistors - A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium. | 2016-05-19 |
20160141424 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE, MANUFACTURING METHOD AND DISPLAY DEVICE - A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain layer disposed on the substrate. The source layer and the drain layer are disposed in different layers and the drain layer and the gate layer are disposed in same and one layer. | 2016-05-19 |
20160141425 | THIN FILM TRANSISTOR ASSEMBLY, ARRAY SUBSTRATE METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure discloses a thin film transistor assembly, an array substrate and a method of manufacturing the same, and a display device including the array substrate. The array substrate includes a substrate; a plurality of thin film transistors formed on the substrate; and a plurality of light shielding layers, each of the light shielding layers being arranged between a source electrode and a drain electrode of the thin film transistor and configured to block light from the exterior from illuminating an active layer of the thin film transistor. The light shielding layer and the source electrode and the drain electrode of the thin film transistor are formed in the same layer on the substrate. As the light shielding layer, the source electrode and the drain electrode of the thin film transistor and a data line may be formed on the substrate by using the same material layer through a single patterning process, times of performing patterning processes and the number of masks used may be reduced and thus manufacturing process and cost of the array substrate may be decreased. | 2016-05-19 |
20160141426 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL HAVING THE THIN FILM TRANSISTOR SUBSTRATE - A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed. | 2016-05-19 |
20160141427 | Multi-Channel Field Effect Transistors Using 2D-Material - A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric. | 2016-05-19 |
20160141428 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING AN EMPTY TRENCH STRUCTURE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY - The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench. | 2016-05-19 |
20160141429 | ELECTROSTATIC DISCHARGE DEVICE AND METHOD OF FABRICATING THE SAME - Provided are an electrostatic discharge (ESD) device and method of fabricating the same where the ESD device is configured to prevent electrostatic discharge which can be a cause to product failure. More particularly, the ESD device provided includes a Zener diode and a plurality of PN diodes by improving the architecture of an area wherein a Zener diode is configured compared to alternatives, to provide improved functionality when protecting against ESD events. | 2016-05-19 |
20160141430 | AVALANCHE PHOTODIODE RECEIVER - A method of operating an avalanche photodiode includes providing an avalanche photodiode having a multiplication region capable of amplifying an electric current when subject to an electric field. The multiplication region, in operation, has a first ionization rate for electrons and a second, different, ionization rate for holes. The method also includes applying the electric field to the multiplication region, receiving a current output from the multiplication region, and varying the electric field in time, whereby a portion of the current output is suppressed. | 2016-05-19 |
20160141431 | INTEGRATED SOLAR COLLECTORS USING EPITAXIAL LIFT OFF AND COLD WELD BONDED SEMICONDUCTOR SOLAR CELLS - There is disclosed ultrahigh-efficiency single- and multi-junction thin-film solar cells. This disclosure is also directed to a substrate-damage-free epitaxial lift-off (“ELO”) process that employs adhesive-free, reliable and lightweight cold-weld bonding to a substrate, such as bonding to plastic or metal foils shaped into compound parabolic metal foil concentrators. By combining low-cost solar cell production and ultrahigh-efficiency of solar intensity-concentrated thin-film solar cells on foil substrates shaped into an integrated collector, as described herein, both lower cost of the module as well as significant cost reductions in the infrastructure is achieved. | 2016-05-19 |
20160141432 | SOLAR CELL MODULE AND METHOD FOR PRODUCING SOLAR CELL MODULE - A solar cell module with an anti-glare property, capable of exhibiting a high antifouling property. A surface of a plate body made of glass in the module is roughened, and an antireflection film is laminated thereon. A change point at which the slope of the contour line of the surface changes steeply exists on a cross-section cutting through the plate body in the thickness direction. With the change point as a boundary, straight lines obtained by pseudo-leveling of the contour lines existing within 0.7 micrometer on one side and 0.7 micrometer on another side, are a one-side pseudo-straight line and an other-side pseudo-straight line, respectively, a steep slope portion in which an angle formed by the pseudo-straight lines is 135 degrees or less, and a total number of less than 5 large cracks having an opening width of 0.2 micrometer or more are distributed per 58-micrometer compartment range. | 2016-05-19 |
20160141433 | COMPOSITION FOR SOLAR CELL ELECTRODE AND ELECTRODE PREPARED USING THE SAME - A composition for solar cell electrodes, the composition including silver (Ag) powder; a glass frit; an organic binder; and a solvent, the organic binder including a compound containing a repeat unit represented by Formula 1: | 2016-05-19 |
20160141434 | Hybrid Vapor Phase-Solution Phase Growth Techniques for Improved CZT(S,Se) Photovoltaic Device Performance - A hybrid vapor phase-solution phase CZT(S,Se) growth technique is provided. In one aspect, a method of forming a kesterite absorber material on a substrate includes the steps of: depositing a layer of a first kesterite material on the substrate using a vapor phase deposition process, wherein the first kesterite material includes Cu, Zn, Sn, and at least one of S and Se; annealing the first kesterite material to crystallize the first kesterite material; and depositing a layer of a second kesterite material on a side of the first kesterite material opposite the substrate using a solution phase deposition process, wherein the second kesterite material includes Cu, Zn, Sn, and at least one of S and Se, wherein the first kesterite material and the second kesterite material form a multi-layer stack of the absorber material on the substrate. A photovoltaic device and method of formation thereof are also provided. | 2016-05-19 |
20160141435 | SOLAR CELL ASSEMBLY - A solar cell assembly ( | 2016-05-19 |
20160141436 | POLYOLEFIN ADHESIVE MATERIAL FOR USE IN SOLAR MODULES - This disclosure generally relates to films capable of use in electronic device modules and to electronic device modules including such films. The disclosure also generally relates to materials for use in such films. | 2016-05-19 |
20160141437 | PHOTOVOLTAIC SYSTEM, MODULE HOLDER SYSTEM AND REFLECTOR - A photovoltaic system has at least two bifacial solar modules, which are respectively held in a module holder, and a reflector. The module holders are configured to hold two bifacial solar modules vertically positioned and parallel to each other, wherein the module holders are interconnected via the reflector. | 2016-05-19 |
20160141438 | SUBSTRATE FOR SOLAR CELL, AND SOLAR CELL - Provided is a substrate for a solar cell, wherein a flat chamfered portion is formed on one corner of a silicon substrate having a square shape in a planar view, or a notch is formed on the corner or close to the corner. This invention makes it possible to easily check the position of the substrate and determine the direction of the substrate in a solar cell manufacturing step, and suppresses failures generated due to the direction of the substrate. | 2016-05-19 |
20160141439 | LIGHT DETECTION DEVICE - A semiconductor light detection element includes a plurality of avalanche photodiodes operating in Geiger mode and formed in a semiconductor substrate, quenching resistors connected in series to the respective avalanche photodiodes and arranged on a first principal surface side of the semiconductor substrate, and a plurality of through-hole electrodes electrically connected to the quenching resistors and formed so as to penetrate the semiconductor substrate from the first principal surface side to a second principal surface side. A mounting substrate includes a plurality of electrodes arranged corresponding to the respective through-hole electrodes on a third principal surface side. The through-hole electrodes and the electrodes are electrically connected through bump electrodes, and a side surface of the semiconductor substrate and a side surface of a glass substrate are flush with each other. | 2016-05-19 |
20160141440 | OPTICAL SENSOR MODULE - An optical sensor module is disclosed. The optical sensor module can include a housing comprising an air cavity. An optical emitter die can be disposed in the air cavity of the housing. A top surface of the optical emitter die can face a first side of the housing, the optical emitter die configured to emit light towards the first side of the housing. An optical sensor die can be disposed in the air cavity of the housing adjacent the optical emitter die. The optical sensor die can be spaced from the optical emitter die by a lateral distance. A top surface of the optical sensor die can face the first side of the housing. There may be no septum between the optical sensor die and the optical emitter die that optically separates the optical sensor die and the optical emitter die. | 2016-05-19 |
20160141441 | CONTROL OF COMPOSITION PROFILES IN ANNEALED CIGS ABSORBERS - Particular embodiments of the present disclosure relate to the use of sputtering, and more particularly magnetron sputtering, in forming absorber structures, and particular multilayer absorber structures, that are subsequently annealed to obtain desired composition profiles across the absorber structures for use in photovoltaic devices. | 2016-05-19 |
20160141442 | USE OF SILICON NITRIDE AS A SUBSTRATE AND A COATING MATERIAL FOR THE RAPID SOLIDIFICATION OF SILICON - Silicon nitride particles are used as a coating or substrate material for kerfless wafer making technologies. | 2016-05-19 |
20160141443 | RESTORATION METHOD OF SILICON-BASED PHOTOVOLTAIC SOLAR CELLS - The treatment method of a photovoltaic element comprises at least the following steps:
| 2016-05-19 |
20160141444 | METHOD AND APPARATUS FORMING COPPER (Cu) OR ANTIMONY (Sb) DOPED ZINC TELLURIDE AND CADMIUM ZINC TELLURIDE LAYERS IN A PHOTOVOLTAIC DEVICE - A method and apparatus for an amount of Cu or Sb dopant incorporated into a zinc-based layer as the layer is being formed. The layer is formed over a coated substrate using an electrochemical deposition (ECD) process. In the ECD process, the bias voltage and plating solution composition may be systematically changed during the electrochemical deposition process to change the amount of Cu or Sb dopant incorporated into the plated layer. | 2016-05-19 |
20160141445 | METHOD AND DEVICE FOR PRODUCING A PHOTOVOLTAIC ELEMENT WITH STABILISED EFFICIENCY - According to an example, in a method for producing a photovoltaic element with stabilised efficiency, a silicon substrate may be provided with an emitter layer and electrical contacts, which may be subjected to a stabilisation treatment step. Hydrogen from a hydrogenated silicon nitride layer may be introduced into the silicon substrate, for example, within a zone of maximum temperature. The silicon substrate may then be cooled rapidly in a zone in order to avoid hydrogen effusion. The silicon substrate may then be maintained, for example in a zone within a temperature range of from 230° C. to 450° C. for a period of, for example, at least 10 seconds. The previously introduced hydrogen may thereby assume an advantageous bond state. At the same time or subsequently, a regeneration may be carried out by generating excess minority charge carriers in the substrate at a temperature of at least 90° C., preferably at least 230° C. | 2016-05-19 |
20160141446 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device is provided. Step (a): A semiconductor wafer having a substrate and at least one epitaxial structure is provided. Step (b): An electrode connection layer is formed on the epitaxial structure, wherein the electrode connection layer includes connection pads, first electrodes and second electrodes. Step (c): A package substrate having the similar size as that of the semiconductor wafer and having conductive through holes is provided. Step (d): The semiconductor wafer and the package substrate are bonded by aligning the connection pads with the conductive through holes, so that the conductive through holes are electrically connected to a first type semiconductor layer or a second type semiconductor layer of the epitaxial structure. Step (e): The substrate is removed so as to expose a surface of the epitaxial structure and form a light emitting device. | 2016-05-19 |
20160141447 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of In | 2016-05-19 |
20160141448 | MONOLITHIC NANO-CAVITY LIGHT SOURCE ON LATTICE MISMATCHED SEMICONDUCTOR SUBSTRATE - An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities. The optoelectronic light emission device is free of defects | 2016-05-19 |
20160141449 | LIGHT EMITTING DIODE WITH DOPED QUANTUM WELLS AND ASSOCIATED MANUFACTURING METHOD - A light emitting diode based on GaN including an active zone located between an n-doped layer and a p-doped layer that together form a p-n junction, wherein the active zone includes at least one n-doped emissive layer. | 2016-05-19 |
20160141450 | Nanowire Sized Opto-Electronic Structure and Method for Modifying Selected Portions of Same - A method for treating a LED structure with a substance, the LED structure includes an array of nanowires on a planar support. The method includes producing the substance at a source and causing it to move to the array along a line. The angle between the line followed by the substance and the plane of the support is less than 90° when measured from the center of the support. The substance is capable of rendering a portion of the nanowires nonconductive or less conductive compared to before being treated by the substance. | 2016-05-19 |
20160141451 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR COMPONENT COMPRISING SUCH A SEMICONDUCTOR STRUCTURE - A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the silicon carbide layer, the structure including at least one part, as a contact part, in contact with the surface of the silicon carbide layer, which includes gallium. | 2016-05-19 |
20160141452 | LIGHTING EMITTING DEVICE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - The present invention discloses a light emitting device, a manufacturing method thereof and a display device. The light emitting device comprises a substrate. An anode layer, a functional layer and a cathode layer are provided above the substrate, and the functional layer is provided between the anode layer and the cathode layer. A transmission enhanced layer is further provided on the substrate. The transmission enhanced layer comprises a plurality of photonic crystal microstructures, so that light is refracted while transmitting through the transmission enhanced layer, so as to form light in different directions and thus to reduce an incident angle of light incident to the substrate. Therefore, the total reflection generated when light transmits through an interface between the substrate and the air is reduced, thereby improving luminous efficiency and reducing power loss. | 2016-05-19 |
20160141453 | LATTICE-MATCHED LIGHT EMITTING ELEMENT - A light emitting element and its manufacturing method are disclosed. A larger end face of a gallium nitride pyramid contacts with a mounting face of a gallium nitride layer disposed on a substrate, with c-axes of the gallium nitride layer and the gallium nitride pyramid coaxial to each other, and with M-planes of the gallium nitride layer and the gallium nitride pyramid parallel to each other. Broken bonds at contact faces of the gallium nitride pyramid and of the gallium nitride layer weld with each other after heating and cooling. A portion of an insulating layer coated on the gallium nitride pyramid and is removed to form an electrically conductive portion on which a first electrode is disposed. A portion of the insulating layer coated on the gallium nitride layer is removed to form another electrically conductive portion on which a second electrode is disposed. | 2016-05-19 |
20160141454 | LIGHT-EMITTING DIODE DEVICE - A light-emitting element, includes a substrate; a first light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, and wherein the triangular upper surface has three sides and three vertexes; a first electrode formed on the first light-emitting stack and located near a first side of the three sides of the triangular upper surface; and a second electrode formed on the first light-emitting stack; including a second electrode pad near a first vertex of the three vertexes; and a second electrode extending part extending from the second electrode pad in two directions, disposed along other two sides of the three sides to surround the first electrode and stopping at the first side to form an opening. | 2016-05-19 |
20160141455 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a plurality of V-pits. The light-emitting device further includes a layer-quality improvement layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a plurality of V-pits with substantially same size and shape as the plurality of V-pits of the active layer, wherein layer-quality improvement layer is a group III-V semiconductor layer including Al or In. Due to the improved layer quality, the luminescent quality of the light-emitting device is improved. | 2016-05-19 |
20160141456 | ELECTRODE STRUCTURE OF LIGHT EMITTING DEVICE - An electrode structure of a light emitting device includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes electrically contact with the light emitting device and are separated from one other. The second electrodes electrically contact with the light emitting device and are located at the same side with the first electrodes. The second electrodes are separated from one other, and the second electrodes have at least two different profiles when viewing from atop. | 2016-05-19 |
20160141457 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a substrate; a light-emitting structure including first and second nitride-based semiconductor layers on the substrate and an active layer between the first and second nitride-based semiconductor layers; an insulating layer on a top surface of the light-emitting structure; a protrusion on the insulating layer, a top surface of the protrusion being larger than a bottom surface thereof, the protrusion having a trapezoidal cross-section; a transparent conductive layer covering a top surface of the light-emitting structure, a top surface of the insulating layer, and the top surface of the protrusion and having a constant thickness along the top surface of the light-emitting structure, the top surface of the insulating layer, and the top surface of the protrusion; and an electrode covering at least one of inclined surfaces of the protrusion on the transparent conductive layer. | 2016-05-19 |
20160141458 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a light-emitting stack comprising a first surface and a second surface opposite to the first surface; a first electrode formed on the second surface of the light-emitting stack; a current blocking layer formed on the first surface of the light-emitting stack and corresponding to a location of the first electrode; and a second electrode covering the current blocking layer and comprising a plurality of first metal layers and a plurality of second metal layers alternating with the plurality of first metal layers, wherein the plurality of first metal layers is discontinuous. | 2016-05-19 |
20160141459 | LIGHT-EMITTING DEVICE - A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer; an electrode structure on the light-emitting stack and comprising a first electrode and an extension electrode protruding from the first electrode toward an edge of the light-emitting device in a first extending direction; a transparent insulating layer between the light-emitting stack and the electrode structure, wherein the transparent insulating layer comprises a first part and an extension part protruding from the first part toward the edge of the light-emitting device in a second extending direction; wherein a surface area of a surface of the first electrode distal from the transparent insulating layer is smaller than a surface area of a surface of the transparent insulating layer distal from the light-emitting stack, the first electrode is right above the first part, and a part of the extension electrode is right above the extension part. | 2016-05-19 |
20160141460 | ILLUMINATION METHOD AND LIGHT-EMITTING DEVICE - To provide an illumination method and a light-emitting device which are capable of achieving, under an indoor illumination environment where illuminance is around 5000 lx or lower when performing detailed work and generally around 1500 lx or lower, a color appearance or an object appearance as perceived by a person, will be as natural, vivid, highly visible, and comfortable as though perceived outdoors in a high-illuminance environment, regardless of scores of various color rendition metric. Light emitted from the light-emitting device illuminates an object such that light measured at a position of the object satisfies specific requirements. A feature of the light-emitting device is that light emitted by the light-emitting device in a main radiant direction satisfies specific requirements. | 2016-05-19 |
20160141461 | LED LIGHTING ARRANGEMENT INCLUDING LIGHT EMITTING PHOSPHOR - A method of manufacturing an LED lighting arrangement, comprises: receiving an optical component having a diffusing material that is light diffusive and at least one photoluminescent material that is excitable by light of a first wavelength range and which emits light of a second wavelength range; receiving an LED assembly that is operable to generate the light of the first wavelength range and mounting the optical component to the LED assembly to form the LED lighting arrangement. The optical component having the diffusing and photoluminescent materials is mass produced separately from the LED assembly and can be selected such that light generated by the optical component combined with the light generated by the LED assembly corresponds to light of a selected color. Also disclosed are LED lighting arrangements, components for LED lighting arrangements and methods of fabricating an optical component. | 2016-05-19 |
20160141462 | MOLDED SUBSTRATE, PACKAGE STRUCTURE, AND METHOD OF MANUFACTURE THE SAME - A molded substrate is provided, including: a release film; and a plurality of phosphor particles formed on the release film, wherein the phosphor particles have gaps therebetween. A method of manufacturing a package structure is also provided, including: disposing at least one light emitting element on a carrier; forming a transparent adhesive layer on a surface of the light emitting element; disposing the molded substrate on the transparent adhesive layer with the phosphor particles disposed between the transparent adhesive layer and the release film; filling the transparent adhesive layer into the gaps of the phosphor particles to form a phosphor layer; and removing the release film, so as to obtain an even phosphor layer. | 2016-05-19 |
20160141463 | COMPOSITE HAVING SEMICONDUCTOR STRUCTURES EMBEDDED IN A MATRIX - Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core. | 2016-05-19 |
20160141464 | LIGHT-EMITTING DEVICE - In order to provide a light-emitting device having improved color rendering properties, a light-emitting device which uses a SiC fluorescent material comprises a first SiC fluorescent portion in which a donor impurity and an acceptor impurity are added and which is formed of a SiC crystal; a second SiC fluorescent portion which is formed of a SiC crystal in which the same donor impurity as the first SiC fluorescent portion and the same acceptor impurity as the first SiC fluorescent portion are added, and in which a concentration of the acceptor impurity is higher than the concentration of the acceptor impurity in the first SiC fluorescent portion and an emission wavelength is longer than that of the first SiC fluorescent portion; and a light-emitting portion that emits excitation light that excites the first SiC fluorescent portion and the second SiC fluorescent portion. The color rendering property of the SiC fluorescent material is improved and it becomes easy to adjust the color temperature and the color rendering index of the light-emitting device which uses the SiC fluorescent material. | 2016-05-19 |
20160141465 | LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF - A light-emitting device includes a light-emitting element for emitting primary light, and a wavelength conversion unit for absorbing part of the primary light and emitting secondary light having a wavelength longer than that of the primary light, wherein the wavelength conversion unit includes plural kinds of phosphors having light absorption characteristics different from each other, and then at least one kind of phosphor among the plural kinds of phosphors has an absorption characteristic that can absorb the secondary light emitted from at least another kind of phosphor among the plural kinds of phosphors. | 2016-05-19 |
20160141466 | THIN FILM LIGHT EMITTING DIODE - Light emitting devices comprise a substrate having a surface and a side surface; a semiconductor structure on the surface of the substrate, the semiconductor structure having a first surface, a second surface and a side surface, wherein the second surface is opposite the first surface, wherein the first surface, relative to the second surface, is proximate to the substrate, and wherein the semiconductor structure comprises a first-type layer, a light emitting layer and a second-type layer; a first and a second electrodes; and a wavelength converting element arranged on the side surface of the semiconductor structure, wherein the wavelength converting element has an open space, and wherein the open space is a portion not covered by the wavelength converting element. | 2016-05-19 |
20160141467 | LIGHT EMITTING DEVICE - A light emitting device includes an epitaxial structure and a sheet-shaped wavelength converting layer. The sheet-shaped wavelength converting layer is disposed on the epitaxial structure and at least includes a first wavelength converting unit layer and a second wavelength converting unit layer. The first wavelength converting unit layer is disposed between the second wavelength converting unit layer and the epitaxial structure. An emission peak wavelength of the first wavelength converting unit layer is greater than an emission peak wavelength of the second wavelength converting unit layer. A full width half magnitude of the second wavelength converting unit layer is greater than a full width half magnitude of the first wavelength converting unit layer. | 2016-05-19 |
20160141468 | WAVELENGTH CONVERTING FILM AND MANUFACTURING METHOD THEREOF - A method for manufacturing a wavelength converting film is provided. A release film is provided. At a least one coating process is performed to form at least one wavelength converting layer on the release film, wherein a first contact surface of the at least one wavelength converting layer and the release film has a first roughness. An adhesive layer is formed on a surface of the wavelength converting layer farthest from the release film, wherein a second contact surface of the adhesive layer and the wavelength converting layer has a second roughness. The second roughness is greater than the first roughness. | 2016-05-19 |
20160141469 | OPTOELECTRONIC DEVICE WITH LIGHT-EMITTING DIODES - An optoelectronic device including an array of light-emitting diodes and photoluminescent blocks opposite at least part of the light-emitting diodes, each light-emitting diode having a lateral dimension smaller than 30 μm, each photoluminescent block including semiconductor crystals having an average size smaller than 1 μm, dispersed in a binding matrix. | 2016-05-19 |
20160141470 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, an electrode connection layer, an epitaxial structure and a plurality of pads. The substrate has an upper surface, a lower surface and a plurality of conductive through holes. The electrode connection layer is disposed on the upper surface of the substrate, and connects with the conductive through holes. An edge of the electrode connection layer is aligned with an edge of the substrate. The epitaxial structure is disposed on the electrode connection layer and electrically connected to the electrode connection layer. The pads are disposed on the lower surface of the substrate and connect with the conductive through holes. | 2016-05-19 |
20160141471 | PROCESS FOR FORMING ULTRA-MICRO LEDS - A flexible light sheet includes a bottom conductor layer overlying a flexible substrate. An array of vertical light emitting diodes (VLEDs) is printed as an ink over the bottom conductor layer so that bottom electrodes of the VLEDs electrically contact the bottom conductor layer. A top electrode of the VLEDs is formed of a first transparent conductor layer, and a temporary hydrophobic layer is formed over the first transparent conductor layer. A dielectric material is deposited between the VLEDs but is automatically de-wetted off the hydrophobic layer. The hydrophobic layer is then removed, and a second transparent conductor layer is deposited to electrically contact the top electrode of the VLEDs. The VLEDs can be made less than 10 microns in diameter since no top metal bump electrode is used. The VLEDs are illuminated by a voltage differential between the bottom conductor layer and the second transparent conductor layer. | 2016-05-19 |
20160141472 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING APPARATUS INCLUDING THE SAME - A light emitting device package includes a package body, first and second lead frames located on the package body, a light source mounted on at least one of the first or second lead frames, a lens located on the package body, and a wavelength conversion unit partially located on the package body between the package body and the lens. | 2016-05-19 |
20160141473 | LIGHT EMITTING DIODE DEVICE - A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light. | 2016-05-19 |