20th week of 2009 patent applcation highlights part 20 |
Patent application number | Title | Published |
20090121726 | TEST APPARATUS AND MEASUREMENT APPARATUS - There is provided a test apparatus for testing a device under test, which includes a voltage supplying section that supplies a voltage to the device under test through a wire, a first capacitor that is arranged between the wire and a common potential in series, a current detecting section that detects a current flowing through the wire at a location closer to the device under test than the first capacitor is, an integrating section that outputs an integration value obtained by integrating a difference between the current detected by the current detecting section and a predetermined reference current, and a judging section that judges whether the device under test is a pass or a failure based on the integration value. | 2009-05-14 |
20090121727 | ELECTRICAL IMPEDANCE TOMOGRAPHY OF NANOENGINEERED THIN FILMS - The present teachings relate to the application of electrical impedance tomography (EIT) to demonstrate the multifunctionality of carbon nanocomposite thin films under various types of environmental stimuli. Carbon nanotube (CNT) thin films are fabricated by a layer-by-layer (LbL) technique or other techniques and mounted with electrodes along their boundaries. The response of the thin films to various stimuli determined by relying on electric current excitation and corresponding boundary potential measurements. The spatial conductivity variations are reconstructed based on a mathematical model for the EIT technique. Here, the ability of the EIT method to provide two-dimensional mapping of the conductivity of CNT thin films is validated by (1) electrically imaging intentional structural defects in the thin films and (2) mapping the film's response to various pH environments. | 2009-05-14 |
20090121728 | Resin Impregnated Amount Measuring Method and Resin Impregnated Amount Measuring Device in Filament Winding Molding - A resin impregnated amount measuring method and device for accurately and successively measuring an amount of resin impregnated in a fiber in a filament winding molding. An electrostatic capacitance of a fiber impregnated with resin is measured, and an amount of resin impregnated in the fiber is measured based on the measurement result. The fiber impregnated with resin is traveled in a non-contacting manner between two parallel flat plates of an electrostatic capacitance sensor and a change in electrostatic capacitance is measured. The amount of resin impregnated in the fiber may also be measured by irradiating light on the impregnated fiber to determine the image area of, reflectivity of, or distance of the light source from, the fiber. | 2009-05-14 |
20090121729 | System and Method for Current Measurement - Load current of a circuit is determined across a component of the circuit by calibrating the resistance of the component with a reference current having a distinguishable characteristic. For example, a reference current with swept frequency modulation is applied to the component so that the resistance of the component is determined from voltage drop associated with the reference current across the component. The component resistance is applied to a voltage drop associated with the load current to determine the load current. For example, a filter matched to the reference current frequency modulation isolates the reference current voltage drop so that a ratio of the reference current voltage drop and the load current voltage drop provides a ratio of the reference current and load current. | 2009-05-14 |
20090121730 | CONNECTOR FOR MEASURING ELECTRICAL RESISTANCE, AND APPARATUS AND METHOD FOR MEASURING ELECTRICAL RESISTANCE OF CIRCUIT BOARD - Disclosed are a connector for measurement of electric resistance, by which necessary electrical connection is surely achieved even when a circuit board to be inspected is large in area and has a great number of small-sized electrodes to be inspected, and measurement is surely performed with high precision, and which can be produced at a low cost, and an electric resistance-measuring apparatus and an electric resistance-measuring method for circuit boards, which make use of this connector. The connector for measurement of electric resistance has a first electrode sheet, an anisotropically conductive elastomer sheet arranged on a back surface of the first electrode sheet and having through-holes formed corresponding to the electrodes to be inspected, and a second electrode sheet arranged on a back surface of the anisotropically conductive elastomer sheet. The first electrode sheet has an insulating sheet having through-holes formed corresponding to the electrodes to be inspected, a plurality of ring-like electrodes each formed on a front surface of the insulating sheet so as to surround the through-hole, and junction electrodes formed on a back surface of the insulating sheet, and the second electrode sheet has a plurality of core electrodes for inspection arranged corresponding to the electrodes to be inspected, and a plurality of core electrodes for connection arranged corresponding to the junction electrodes. | 2009-05-14 |
20090121731 | DIAGNOSTIC JUMPER - A jumper including a control module and a plurality of conduits connected to the control module is provided. A connector is connected to each of the conduits. The control module controls the flow of a communications medium through the conduits and the control module. | 2009-05-14 |
20090121732 | TEMPORARY PLANAR ELECTRICAL CONTACT DEVICE AND METHOD USING VERTICALLY-COMPRESSIBLE NANOTUBE CONTACT STRUCTURES - A wafer-scale probe card for temporary electrical contact to a sample wafer or other device, for burn-in and test. The card includes a plurality of directly metallized single-walled or multi-walled nanotubes contacting a pre-arranged electrical contact pattern on the probe card substrate. The nanotubes are arranged into bundles for forming electrical contacts between areas of the device under test and the probe card. The bundles are compressible along their length to allow a compressive force to be used for contacting the probe card substrate to the device under test. A strengthening material may be disposed around and/or infiltrate the bundles. The nanotubes forming the bundles may be patterned to provide a pre-determined bundle profile. Tips of the bundles may be metallized with a conductive material to form a conformal coating on the bundles; or metallized with a conductive material to form a continuous, single contact surface. | 2009-05-14 |
20090121733 | TEST CIRCUIT FOR USE IN A SEMICONDUCTOR APPARATUS - A test circuit that senses a misaligned probe during a test includes a first power control section that senses voltage levels of a plurality of sensing lines and controls power supplied to a lower circuit section provided below a part of a pad group, and a second power control section that selectively provides an internal voltage in response to a sensing result of the first power control section. | 2009-05-14 |
20090121734 | Integrated compound nano probe card and method of making same - An integrated compound nano probe card is disclosed to include a substrate layer having a front side and a back side, and compound probe pins arranged in the substrate layer. Each compound probe pin has a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to the bundle of aligned parallel nanotubes/nanorods and filled in gaps in the nanotubes/nanorods. Each compound probe pin has a base end exposed on the back side of the substrate layer and a distal end spaced above the front side of the substrate layer. | 2009-05-14 |
20090121735 | METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR PACKAGE - A method and system for testing a semiconductor package. At least some of the illustrative embodiments are methods comprising testing a semiconductor package unit ( | 2009-05-14 |
20090121736 | DISPOSABLE BUILT-IN SELF-TEST DEVICES, SYSTEMS AND METHODS FOR TESTING THREE DIMENSIONAL INTEGRATED CIRCUITS - A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit. | 2009-05-14 |
20090121737 | CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY - An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified. | 2009-05-14 |
20090121738 | SEMICONDUCTOR TEST DEVICE - A semiconductor test device of the present invention for conducting a test on a device under test, includes: a plurality of comparison units which compare a signal obtained from the device under test with a predetermined reference voltage and output a comparison result; a plurality of measuring units which are provided in correspondence with the plurality of comparison units, and measure a time from when a measurement start signal is input thereto to when the comparison result from a corresponding comparison unit is input thereto, and output a measuring result; a start signal output unit which outputs the measurement start signal at a same timing to each of the plurality of measuring units; and a computation unit which computes time differences between a plurality of signals obtained from the device under test based on the measuring results of the plurality of measuring units. | 2009-05-14 |
20090121739 | AC DETECTING APPARATUS FOR DETECTING OPERATING STATES OF AC POWER SUPPLY - An exemplary AC detecting apparatus for detecting operating states of an AC power supply includes a detecting circuit connected to an AC power supply, the detecting circuit comprising a photocoupler having a luminous element with the anode connected to a live line of the AC power supply and the cathode connected to a neutral line of the AC power supply, and an optical receiving block with the cathode grounded and the anode connected to a first power source via a resistor; and a processor comprising an interrupt terminal connected to the anode of the optical receiving block, and an output terminal, wherein the detecting circuit detects the AC power supply to send a trigger signal to the processor for triggering a detecting program preinstalled in the processor to real-time analyze the operating states of the AC power supply, and outputs a result of the program via the output terminal. | 2009-05-14 |
20090121740 | Audio/Video Router - Technique for Routing digital audio and digital video signals commences by routing a digital video signal, devoid of embedded digital audio, to at least one output, typically by way of a video cross-point switch. At least one digital audio signal undergoes buffering to obtain a prescribed amount of data prior re-timing of the digital audio signal to a prescribed timing format. Following buffering and re-timing, the digital audio signal undergoes routing to at least one output, typically by way of an audio cross-point switch. When routed to outputs associated with each other, the digital audio signal undergoes embedding in the digital video. | 2009-05-14 |
20090121741 | SEMICONDUCTOR APPARATUS, ON-DIE TERMINATION CIRCUIT, AND CONTROL METHOD OF THE SAME - An on-die termination circuit of a semiconductor apparatus can include: a code converting unit configured to change a code value of a termination code in response to a termination control signal; and a plurality of on-die termination blocks configured to commonly receive the termination code, and perform a termination operation. | 2009-05-14 |
20090121742 | APPARATUS AND METHOD OF CALIBRATING ON-DIE TERMINATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a current comparison result signal and a previous comparison result signal, among comparison result signals obtained by sequential comparison operations by the comparing unit, to determine whether or not the levels thereof are the same, and outputs an external code update signal according to the comparison result, and a counter that increases or decreases the internal code according to the comparison result signal and outputs the internal code as an external code according to the external code update signal | 2009-05-14 |
20090121743 | Digital Method and Device for Transmission with Reduced Crosstalk - The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit(s) input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk. | 2009-05-14 |
20090121744 | Glitch Free 2-Way Clock Switch - The present invention switches between a first clock signal (CLK | 2009-05-14 |
20090121745 | DFLOP CIRCUIT FOR AN EXTERNALLY ASYNCHRONOUS-INTERNALLY CLOCKED SYSTEM - A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal, and a precharge unit that is activated in response to the internal clock signal to precharge an output node of the signal transmission controller. | 2009-05-14 |
20090121746 | FRACTIONAL-N FREQUENCY SYNTHESIZER - A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value. | 2009-05-14 |
20090121747 | Maintaining Circuit Delay Characteristics During Power Management Mode - A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time. | 2009-05-14 |
20090121748 | WAVEFORM GENERATOR AND PLASMA DISPLAY DEVICE USING THE SAME - A waveform generator capable of generating a square wave and a ramp wave using one switching element is provided. A waveform generator includes a first transistor having a drain electrode, a gate electrode, and a source electrode. A first resistor and a first diode are coupled at a common node between a first input terminal and the gate electrode. A second resistor is coupled between the gate electrode and a second input terminal. A first capacitor is coupled between the drain electrode and the common node between the first resistor and the first diode. | 2009-05-14 |
20090121749 | Generation of an Analog Gaussian Noise Signal Having Predetermined Characteristics - The present invention relates to a method and system for providing an analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. A band-limited digital noise signal indicative of a Gaussian noise signal having a predetermined Gaussian probability distribution function is ΣΔ modulated generating a pulse-density modulated 1-bit sequence representing a Gaussian noise signal having a predetermined probability distribution function, bandwidth and center frequency. Using an analog low-pass filter the pulse-density modulated 1-bit sequence is then converted into a respective analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. The method and system are successfully employed in numerous applications such as in histogram testing and probabilistic digitization. | 2009-05-14 |
20090121750 | Constant Current Drive Device - An object of the present invention is to eliminate fluctuation in the value of the constant current I even if there is characteristic fluctuation in field effect transistors and at the same time, to improve the power consumption. There are provided with a plurality of current mirror circuits consisting of those on the reference side and on the mirror side; current holding capacitors | 2009-05-14 |
20090121751 | Write Driver Circuit - A write driver circuit comprising a first transistor comprising a first source/drain terminal coupled to a first output, a second source/drain terminal coupled with a first reference potential, and a gate terminal; a second transistor comprising a first source/drain terminal coupled to a second output, a second source/drain terminal coupled with the first reference potential, and a gate terminal; and a gate voltage generator coupled to the gate terminals of the first and second transistors. | 2009-05-14 |
20090121752 | SOURCE FOLLOWER - A source follower includes first through third switches, first and second transistors, and a first capacitor. The first switch is used to determine whether or not to couple the source of the first transistor with an input signal. The second switch is used to determine whether or not to couple a gate and a drain of the first transistor with a first voltage. A first end of the first capacitor is coupled with a first control signal, and a second end of the first capacitor is coupled to the drain of the first transistor and a gate of the second transistor. The third switch is used to determine whether to or not couple a drain of the second transistor with the first voltage, and a source of the second transistor serves as an output of the source follower. | 2009-05-14 |
20090121753 | PROTECTIVE CIRCUIT FOR MICROPROCESSOR - A protective circuit for microprocessor comprises an input terminal, a bias circuit, a reset circuit, and an output terminal, wherein the bias circuit coupled to the input terminal is configured to receive an input signal and generate a bias signal. The reset circuit coupled to the bias circuit is configured to receive a bias signal and generate a reset signal. The output terminal outputs the reset signal to a reset pin of the microprocessor so that the microprocessor is reset and protected from getting failure. | 2009-05-14 |
20090121754 | Power-On Reset Circuit - An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage. | 2009-05-14 |
20090121755 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data. | 2009-05-14 |
20090121756 | PSEUDO-SYNCHRONOUS SMALL REGISTER DESIGNS WITH VERY LOW POWER CONSUMPTION AND METHODS TO IMPLEMENT - Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains. Various embodiments of the present invention replace conventional continuous clocking schemes with a strobe signal that is only generated when a data transfer operation with the one or more pseudo-synchronous registers is to take place. The strobe signal is generated so as to have a duration of one full cycle of the clock signal which defines the clock domain in which the at least one pseudo-synchronous register resides. | 2009-05-14 |
20090121757 | DATA CENTER TRACKING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal. | 2009-05-14 |
20090121758 | CHIPSETS AND CLOCK GENERATION METHODS THEREOF - Chipsets capable of preventing malfunction caused by feedback clock distortion are provided, in which a phase frequency detector generates a control voltage according to a first reference clock and a first feedback clock, a voltage-controlled oscillator generates an output clock according to the control voltage, a frequency divider performs a frequency-division on a second feedback clock to obtain the first feedback clock, and a frequency filter estimates swings and frequency of a third feedback clock from an external unit and selectively outputs one of the third feedback clock or the output clock to serve as the second clock. | 2009-05-14 |
20090121759 | FAST-SWITCHING LOW-NOISE CHARGE PUMP - In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump. | 2009-05-14 |
20090121760 | Charge pump for PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 2009-05-14 |
20090121761 | INTRA-PAIR DIFFERENTIAL SKEW COMPENSATION METHOD AND APPARATUS FOR HIGH-SPEED CABLE DATA TRANSMISSION SYSTEMS - A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew. | 2009-05-14 |
20090121762 | TIMEBASE VARIATION COMPENSATION IN A MEASUREMENT INSTRUMENT - Timebase variation compensation in a measurement instrument is achieved by simultaneously acquiring both a signal under test and a reference signal. The reference signal is derived from a source that has very stable timing with respect to the timebase. Timing variations are measured from the acquired signals. Timing variations detected in the reference signal are deemed to reflect variations in the timebase of the test and measurement instrument. The timing variations in the reference signal are used to detect, and compensate for, timebase variation in the signal under test to produce a corrected signal under test that reflects the actual timing variations present in the signal under test. | 2009-05-14 |
20090121763 | ADJUSTABLE DUTY CYCLE CIRCUIT - Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transitors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband. | 2009-05-14 |
20090121764 | SEMICONDUCTOR DEVICE - A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line. | 2009-05-14 |
20090121765 | LATCH CIRCUIT AND FLIP-FLOP CIRCUIT - A latch circuit includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits is connected with at least two of the three or more second nodes, and controls the voltage of the first node based on the voltages of the at least two second modes. Each of the second node voltage control circuits is connected with at least two of the three or more first nodes and controls the voltage of the second node based on the voltages of the at least two first nodes. | 2009-05-14 |
20090121766 | EXTERNALLY ASYNCHRONOUS INTERNALLY CLOCKED SYSTEM - An Externally Asynchronous-Internally Clocked (EAIC) system that generates an internal clock signal includes a clock signal control block. The clock signal control block includes a pull-up unit that is activated in response to an input signal used to generate an internal clock signal; a pull-down unit that is activated in response to the input signal used to generate an internal clock signal, and a bypass unit that is provided between the pull-up unit and the pull-down unit, and selectively provides a signal path to the pull-down unit if the pull-down unit is activated and a signal path from the pull-up unit if the pull-up unit is activated. | 2009-05-14 |
20090121767 | SIGNAL PROCESSING APPARATUS - The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f | 2009-05-14 |
20090121768 | Semiconductor device and operation method thereof - Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock signal corresponding to a falling edge of the external clock, a drive control signal generator configured to restrict an activation period of the first clock signal within a deactivation period of the second clock signal to generate a first drive control signal, and restrict an activation period of the second clock signal within a deactivation period of the first clock signal to generate a second drive control signal and an output driver configured to receive a drive data in response to the first and second drive control signal to drive an output terminal in response to the drive data. | 2009-05-14 |
20090121769 | OFFSET COMPENSATION CIRCUIT AND YAW RATE SENSOR EQUIPPED THEREWITH - An offset compensation circuit for a yaw rate sensor, having a subtracter, which is provided for subtracting a correction value from an input signal, the correction value being obtainable by dividing each of n measurements of the input signal by the constant n and subsequently integrating a number of n quotients into an integrator. Furthermore, a yaw rate sensor having such an offset compensation circuit. | 2009-05-14 |
20090121770 | METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND - A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio. | 2009-05-14 |
20090121771 | LEVEL SHIFT CIRCUIT AND METHOD THEREOF - A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal. | 2009-05-14 |
20090121772 | Multiplier circuit - Disclosed is a multiplier circuit including first and second squaring circuits comprising first and second differential MOS transistors respectively connected in cascode to first and second diode-connected MOS transistors. The first squaring circuit receives a differential sum voltage of a first input voltage and a second input voltage. The second squaring circuit receives a differential subtraction voltage of the first input voltage and the second input voltage. Outputs of the first and second squaring circuits are first and second terminal voltages of the first and second diode-connected MOS transistors. A differential voltage between the first and second terminal voltages corresponds to the product of the first and second input voltages. | 2009-05-14 |
20090121773 | SAMPLING CIRCUIT - The sampling circuit of the present invention includes a latch circuit | 2009-05-14 |
20090121774 | MONOLITHIC INTEGRATED CIRCUIT AND USE OF A SEMICONDUCTOR SWITCH - A monolithic integrated circuit is provided that includes a semiconductor switch, a constant current source, a capacitor, and a load circuit, which has a load capacitance. An output of the semiconductor switch is connected to the load circuit to turn on and off a supply voltage of the load circuit. The capacitor is connected to the output of the semiconductor switch and to a control input of the semiconductor switch. The constant current source can be or is connected to the control input of the semiconductor switch. Also, a use of a semiconductor switch is provided to reduce the leakage current of a load circuit of a monolithic integrated circuit. | 2009-05-14 |
20090121775 | TRANSISTOR AND METHOD FOR OPERATING THE SAME - In a transistor, an AlN buffer layer | 2009-05-14 |
20090121776 | Bus switch and electronic switch - A bus switch for connecting and disconnecting a bus connection provided by a pair of buses includes a first switching element and a second switching element. The first switching element is coupled between an input terminal and an output terminal of a high-potential side bus of the pair of buses. The second switching element is coupled between an input terminal and an output terminal of a low-potential side bus of the pair of buses. The bus connection is connected when the first switching element and the second switching element are activated, and the bus connection is disconnected when the first switching element and the second switching element are deactivated. | 2009-05-14 |
20090121777 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, POWER CONTROL DEVICE, AND ELECTRONIC EQUIPMENT AND MODULE - A semiconductor device of the invention for miniaturizing and cost reduction includes: a solid-state relay | 2009-05-14 |
20090121778 | Anti-Shock Methods for Processing Capacitive Sensor Signals - A low impedance coupling to bias voltage dissipates abnormal charge levels within a microphone in response to a shock event such as dropping or bumping. High impedance coupling to bias voltage is thereafter restored. | 2009-05-14 |
20090121779 | METHOD AND APPARATUS FOR CONTROLLING A CIRCUIT WITH A HIGH VOLTAGE SENSE DEVICE - A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage. | 2009-05-14 |
20090121780 | MULTIPLE-STAGE CHARGE PUMP WITH CHARGE RECYCLE CIRCUIT - A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit and the second pump capacitor, the second transfer circuit, and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval. | 2009-05-14 |
20090121781 | CONTROL CIRCUIT AND CONTROL METHOD FOR CHARGE PUMP CIRCUIT - A charge pump circuit includes a first switch to a fourth switch, a flying capacitor, and an output capacitor. A driver turns on the first switch and the fourth switch during a predetermined precharge period from the start of activation of the charge pump circuit to charge the output capacitor. Thereafter, on the basis of a pulse signal, the driver alternately turns on and off a first pair and a second pair. | 2009-05-14 |
20090121782 | CONTROL CIRCUIT AND CONTROL METHOD FOR CHARGE PUMP CIRCUIT - A pulse frequency modulator generates a pulse signal having a fixed duty ratio and a frequency which is adjusted such that a feedback voltage corresponding to the output voltage of a charge pump circuit is coincident with a predetermined first reference voltage. A driver, on receiving the pulse signal, turns on a first or second group of switches during the time periods corresponding to the high time periods of the pulse signal and turns on the other ones of the first and second group of switches during the time periods corresponding to the low time periods of the pulse signal. | 2009-05-14 |
20090121783 | VOLTAGE LEVEL GENERATING DEVICE - The present invention discloses a voltage level generating device. The voltage level generating device includes: a reference voltage generating module, a first circuit module, a second circuit module, and a switch module. The voltage level generating device disclosed in the present invention only requires a buffer, a voltage regulator, and a arithmetic logic unit (ALU) to attain the same function of the conventional common voltage level generating device, and thus the circuit layout area can be reduced so as to decrease the cost of the integrated circuit (IC). In addition, the voltage level generating device disclosed in the present invention also can select different output of voltage level in order to reduce the power consumption of a display device. | 2009-05-14 |
20090121784 | POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME - A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal. | 2009-05-14 |
20090121785 | DEVICE AND METHOD FOR REDUCING INPUT NOISE - A device and a method for reducing input noise providing at least a microcontroller. The microcontroller comprises: at least a noise reduction device, at least an analog switch and at least a signal output unit. The noise reduction device connected to the ground or a voltage is turned on to charge or discharge a stray capacitor existing on a turned off analog switch so that the amount of charge stored in the stray capacitor is zero or a specific value. Thereby, the noise in a touch switch is reduced and the cost of layout on the PCB is saved. | 2009-05-14 |
20090121786 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit. | 2009-05-14 |
20090121787 | Harmonic quadrature demodulation apparatus and method thereof - Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal, and a harmonic detection unit for detecting a second-order harmonic component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extractor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal. The Hilbert transformer Hilbert-transforms a signal transmitted from the quadrature component extractor. The adder receives an output signal of the in-phase component extractor and an output signal of the Hilbert transformer, and adds the two received signals to each other. The harmonic detection unit outputs the second-order harmonic component of the input focused signal. The present invention can extract the harmonic components of an input signal through a single transmission/reception procedure without limiting the bandwidth of a transmission signal. | 2009-05-14 |
20090121788 | SYSTEM AND METHOD FOR SELF-CANCELLATION OF NTH-ORDER INTERMODULATION PRODUCTS - A method for reducing distortion in a nonlinear device whereby n | 2009-05-14 |
20090121789 | DEVICE COMPRISING A FEEDBACK-LESS GAIN CONTROLLED AMPLIFIER | 2009-05-14 |
20090121790 | System and method for signal level detection - An electronic signal level detection system and method are provided. The method receives an analog input signal having a variable voltage and compares the input signal voltage to a threshold. A detection signal is generated for input signal voltages exceeding the threshold in a periodic first time frame. In a second periodic time frame (following the first time frame), a count is updated in response to the generated detection signals. The count is used to create a metric representative of the difference between the input signal voltage and the threshold. The count is incremented in response to the generating a detection signal (“1”) in the first time frame, and decremented in response to not generating a detection signal (“0”) in the first time frame. | 2009-05-14 |
20090121791 | WIDEBAND LOW NOISE AMPLIFIERS - A wideband low noise amplifier. The wideband low noise amplifier comprises an amplifier, an output device, and an inductor. The amplifier amplifies an input signal received from an input node, and outputs the amplified signal to an output node. The output device is coupled to a first voltage and the output node. The peaking inductor is coupled between the amplifier and the output device. | 2009-05-14 |
20090121792 | METHOD OF ESTABLISHING AN OSCILLATOR CLOCK SIGNAL - A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate. | 2009-05-14 |
20090121793 | Phase locked loop including a frequency change module - A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur. | 2009-05-14 |
20090121794 | Phase lock control system for a voltage controlled oscillator - A phase lock control system is presented for controlling a voltage controlled oscillator. The system includes a voltage controlled oscillator that produces a frequency signal exhibiting an output frequency that varies dependent upon the value of a control voltage applied thereto. A frequency deviation determining system employs a counter intermittently triggered ON for a fixed time by successive timing pulses received from a reference source and a comparator that determines any frequency deviation of the output frequency relative to a preset frequency. An error filter monitors the comparator for any frequency deviation for a plurality of samples of the frequency deviation determinations. A controller varies the control voltage to vary the output frequency in a direction to eliminate any frequency deviation. | 2009-05-14 |
20090121795 | SYNTHESIZER - A synthesizer that has a phase detector | 2009-05-14 |
20090121796 | POLYPHASE NUMERICALLY CONTROLLED OSCILLATOR - A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases. | 2009-05-14 |
20090121797 | High Frequency Digital Oscillator-on-Demand with Synchronization - A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f | 2009-05-14 |
20090121798 | HIGH POWER MICROWAVE WASTE MANAGEMENT - A variable capacitor power supply for a high-power, industrial magnetron is powered directly from a conventional, public-service, 4,160 volt and higher power line. The magnetron's output is removably attached to a tractor trailers or train boxcar fabricated as a microwave work chambers. Microwave work chambers are configured to dry waste, burn dried waste, enhance chemical processes, fix free nitrogen, burn waste metal, reclaim component metals from mixed waste metal, and for gasification, pyrolysis, and plasma waste disposal. Alternately, the microwave power supply is removably connected to an underground cave, configured as a microwave oven chamber, to microwave waste therein. The microwave power supply is located in the basement of a high rise building designed to convert the high rise building waste into heat and electricity. | 2009-05-14 |
20090121799 | PIEZOELECTRIC OSCILLATOR - A piezoelectric oscillator includes: a piezoelectric resonator; an oscillation circuit including a variable resistance circuit and a transistor for oscillation; a constant current circuit, the constant current circuit including a first current mirror circuit, and a current control circuit having an output terminal and controlling a current flowing in the first current circuit so as to enable an output current of the constant current circuit to be adjusted, the output terminal of the first current mirror circuit being coupled to at least one of a collector and a base of the transistor for oscillation with the variable resistance circuit; and a control circuit coupled to the current control circuit and the variable resistance circuit, the control circuit controlling the current control circuit and a resistance value of the variable resistance circuit. | 2009-05-14 |
20090121800 | Apparatus for Low Phase Noise Oscillators - The present invention relates to an oscillator circuit. In the oscillator circuit, the level of the output signal is monitored and compared to a desired reference level. An error signal is then generated and used to modify the feedback so that the negative resistance of the active device presented to the resonator exactly equals the magnitude of the positive resistance of the resonator without having to rely upon saturation in the active device and for very linear operation of the device such that over the full swing of the output, the negative impedance presented to the resonator remain extremely constant—thus reducing the sensitivity of the oscillator to any noise present. | 2009-05-14 |
20090121801 | PULSE WIDTH MODULATION DRIVING DEVICE - A pulse width modulation (PWM) driving device for generating a driving signal to a load is provided. A driving unit provides the driving signal according to a PWM signal and a control signal. A pulse generating unit generates the PWM signal according to a feedback signal from the load. A control unit generates the control signal according to an enable signal and the feedback signal. The control unit generates the control signal to control the driving unit to stop outputting the driving signal when the enable signal is at a first logic level and the feedback signal is smaller than a first predetermined voltage during a first time interval. The control unit generates a reset signal to reset the driving unit and the pulse generating unit when the enable signal is at a second logic level during a second time interval. | 2009-05-14 |
20090121802 | Systems and Methods for Tuning Filters - Methods, systems and apparatus for filter design, analysis and adjustment are provided. Various embodiments may include, for example, methods, systems and apparatus for electric signal filter tuning. Embodiments may also include design techniques for planar electric signal (e.g., RF signals) filter tuning. In at least an embodiment of the present invention a technique for filter tuning is provided which may include parameter extraction, optimization and tuning recipes techniques that may require only a single permanent filter tuning. In at least another embodiment a system and method of filter design, analysis and adjustment according to the present invention includes use of tuning that may be set using a mechanical scribing tool or a laser trimming device. In at least one other embodiment, a filter tuning technique may be provided and include providing trimming tabs on a resonator edge that may be disconnected or trimmed for filter tuning. | 2009-05-14 |
20090121803 | DUPLEXER AND TRANSCEIVER - A duplexer according to the present invention includes a first port, a second port and a third port for external input/output, a first path formed between the first port and the third port, a second path formed between the second port and the third port, a phase shifting part provided for each path, and a resonating part provided for each path. At least any of the resonating parts has a ring conductor having a length equal to one wavelength at a resonant frequency or an integral multiple thereof, a plurality of passive circuits, and a plurality of switches each of which is connected to a different part of the ring conductor at one end and to any of the passive circuits at the other end. A switch may simply be connected to a ground conductor instead of being connected to the passive circuit. | 2009-05-14 |
20090121804 | MONOLITHIC SEMICONDUCTOR MICROWAVE SWITCH ARRAY - A microwave switch array includes a plurality of microwave slotlines, each of which is controlled by a semiconductor switch including a first PIN junction formed by a primary P-type electrode and a primary N-type electrode separated by the slotline. The switches inject a plasma into the slotline in response to a potential applied across the first PIN junction. Each of the switches includes a second PIN junction between the primary P-type electrode and a secondary N-type electrode, and a third PIN junction between the primary N-type electrode and a secondary P-type electrode. Metal contacts connect the primary P-type electrode and the secondary N-type electrode across second PIN junction, and the primary N-type electrode and the secondary P-type electrode across the third PIN junction. The secondary electrodes extract plasma that diffuses away from the first PIN junction, thereby minimizing the performance degrading effects of plasma diffusion. | 2009-05-14 |
20090121805 | LOW-LEAKAGE EMC FILTER - EMC filter, connectable between a supply network and an electric operated appliance to reduce conduction noise between said supply network and said appliance, comprising one voltage regulator having an output terminal whose potential is kept close to the earth potential, in order to reduce the voltage drop, at mains frequency, across a “Y” capacitor or an active shunt module. In this way the leakage current to earth is sensibly reduced. The device of the invention is especially useful in corner-earthed three-phase lines or in conjunction with RCD devices. | 2009-05-14 |
20090121806 | NOISE FILTER ARRAY - A noise filter array includes filter elements including an LC parallel resonant circuit and an LC series resonant circuit each of which includes a coil and a capacitor provided in proximity in an array and integrally provided with one another. The LC series resonant circuits include ground capacitors having signal-side electrodes. Inductance adjustment conductors are connected to signal-side electrodes of the capacitors defining the respective filter elements, and a ground electrode of the capacitors is commonly arranged so as to oppose the signal-side electrodes. | 2009-05-14 |
20090121807 | Electronic component - An electronic component includes a layered substrate including a plurality of dielectric layers stacked, and three resonators provided within the layered substrate. One of the three resonators includes resonator-forming conductor layers of a first type and a second type that each have a short-circuited end and an open-circuited end, relative positions of the short-circuited end and the open-circuited end being reversed between the first and second types. The resonator-forming conductor layers of the first type and the second type are arranged to be adjacent to each other in a direction in which the plurality of dielectric layers are stacked. | 2009-05-14 |
20090121808 | MEMS RESONATOR, A METHOD OF MANUFACTURING THEREOF, AND A MEMS OSCILLATOR - The invention relates to a MEMS resonator comprising a first electrode, a movable element ( | 2009-05-14 |
20090121809 | Thin Film Elastic Wave Resonator - An upper electrode ( | 2009-05-14 |
20090121810 | ACOUSTIC WAVE FILTER - A longitudinally coupled resonator acoustic wave filter device that utilizes an inter-IDT resonance mode with a reduced insertion loss has a structure in which apodization weights are assigned in first to third IDTs having narrow pitch electrode finger portions in portions other than the narrow pitch electrode finger portions, such that the electrode finger overlap width sequentially varies in an acoustic wave propagating direction in which an acoustic wave propagates, and portions of the IDTs located at ends adjacent to the narrow pitch electrode finger portions have a maximum electrode finger overlap width. | 2009-05-14 |
20090121811 | MULTILAYERED COPLANAR WAVEGUIDE FILTER UNIT AND METHOD OF MANUFACTURING THE SAME - A multilayered coplanar waveguide (CPW) filter unit and a method of manufacturing the same are provided. A plate having a capacitance element is formed on or below a CPW layer including a signal line for transmitting a signal and a ground plane. As the filter unit has a multilayered structure, characteristic impedance may be reduced without increasing the width of the signal line. Where an inductor line is inserted between the signal line and the plate, a clear frequency response curve may be obtained without performing an additional process or increasing the area of the filter unit. | 2009-05-14 |
20090121812 | LOW-PASS FILTER - A low-pass filter ( | 2009-05-14 |
20090121813 | Electronic component - An electronic component includes first and second resonators provided within a layered substrate including stacked dielectric layers. The first resonator includes resonator-forming conductor layers of a first type and a second type. The resonator-forming conductor layers of the first type and the second type are reversed in relative positions of the short-circuited end and the open-circuited end, and are alternately arranged in the stacking direction of the dielectric layers. An input terminal is connected to all of the resonator-forming conductor layers of the first type. The second resonator includes resonator-forming conductor layers of a third type and a fourth type. The resonator-forming conductor layers of the third type and the fourth type are reversed in relative positions of the short-circuited end and the open-circuited end, and are alternately arranged in the stacking direction of the dielectric layers. An output terminal is connected to all of the resonator-forming conductor layers of the third type. | 2009-05-14 |
20090121814 | DEVICE FOR COUPLING LOW-FREQUENCY HIGH-POWER ULTRASOUND RESONATORS BY A TOLERANCE-COMPENSATING FORCE-TRANSMITTING CONNECTION - The invention relates to a device for coupling low-frequency high-power ultrasound resonators by a tolerance-compensating force-transmitting connection having at least one contact surface between the at least two resonators on or proximate to the oscillation maximum of the oscillation to be transmitted by the coupling for the purpose of transmitting low-frequency ultrasound power between the resonators coupled in this manner. | 2009-05-14 |
20090121815 | RELAY - A relay includes a movable iron piece, a plate spring fixed to the one surface of the movable iron piece, a shaft hole formed by the one surface of the movable iron piece and the plate spring, and a supporting shaft inserted through the shaft hole. The movable iron piece is rotated around the supporting shaft based on excitation and nonexcitation of a magnetic unit. Both end portions of the plate spring alternately drive a contact point unit. The shaft hole is formed by a flat portion of the one surface of the movable iron piece and a bearing portion formed by subjecting the plate spring to bending work. The movable iron piece is supported so as to be rotatable. | 2009-05-14 |
20090121816 | SWITCH AND SWITCH DEVICE USING SAME - Regarding a switch used for various controls of a motor vehicle in particular and a switch device using the switch, it becomes possible to simplify the configuration and to perform reliable detection of trouble. A first detector is disposed on a surface opposing to a magnet fitted to an actuator, and a second detector is disposed thereunder. A controller detects magnetism of the magnet by using the first detector and the second detector. In case one of the detectors is out of order, it can also be detected from ON/OFF signal from the first detector and the second detector. | 2009-05-14 |
20090121817 | LINEAR SOLENOID - An assist spring is provided between a plunger and a bottom wall of a yoke in order to bias the plunger forward. The assist spring has nonlinear characteristic to compensate a decrease in magnetic attracting force. In a range where the magnetic attracting force is weakened, the assist spring strongly biases the plunger forward and the plunger receives both of the magnetic attracting force and a biasing force of the assist spring. Therefore, a decrease in driving force of the plunger can be avoided. | 2009-05-14 |
20090121818 | AIR CORE INDUCTOR INCLUDING A FLUX INHIBITING MEMBER - An air core inductor includes an inductor member formed in a plurality of coils. The inductor member includes a first end portion, a second end portion and a hollow core portion. The air core inductor also includes at least one stray flux inhibiting member provided on one of the first and second end portions of the inductor member. The stray flux inhibiting member blocks stray magnetic flux emanating from the air core inductor. | 2009-05-14 |
20090121819 | Magnetic coupler - A magnetic coupler having higher response is provided. The magnetic coupler includes a thin film coil wound in a first layer; a first MR element being disposed in a second layer, and detecting an induced magnetic field generated by a signal current flowing through the thin film coil; and yokes being disposed close to the first MR element, and including a soft magnetic material. The first MR element is disposed in a position corresponding to a linear region of the thin film coil in a stacking direction. The yokes are disposed at both of an inner turn side and an outer turn side of the thin film coil in a manner of interposing the first MR element in the second layer. Thus, reduction in intensity of the induced magnetic field is suppressed, and intensity distribution of the induced magnetic field becomes flatter. | 2009-05-14 |
20090121820 | Core and method for producing core - Disclosed is a highly heat-resistant core which has a dust core as a base body. A dust core obtained by press-molding magnetic powder particles particles each of which are covered with an insulating film is used as the base body. An inorganic heat-resistant insulating film is formed on at least a part of a surface of the dust core which faces a winding wire. | 2009-05-14 |
20090121821 | SAFETY SWITCH - A switch includes a body with a switch member on a top thereof, an extension extends from an underside of the switch member, and a substantially inverted L-shaped slot is defined through the extension. Two terminals extend through a bottom of the body, in which one of the terminals is fixed with a contact plate. The contact plate has a tongue with a free end, which contacts the other terminal when the circuit is ON, and is separated from the other terminal when the circuit is OFF. An operation member has a first end movably engaged with the slot and a second end connected with the contact plate. Under the current overload condition, the contact plate deforms, the first end of the operation member move downward along the vertical space of the slot, and the switch member is pivoted by a torsion spring to the OFF position. | 2009-05-14 |
20090121822 | Disc Varistor and Method of Manufacturing the Same - Disclosed herein are a disc varistor having a capability to absorb a double amount of surge and a method of manufacturing the varistor. The varistor includes a disc-shaped first ceramic body having first and second electrodes on opposite surfaces thereof, and a disc-shaped second ceramic body having third and fourth electrodes on opposite surfaces thereof. A first lead wire is in interposed between the second and third electrodes and electrically connected to the second and third electrodes. The varistor also includes a second lead wire. The second lead wire has a body portion electrically connected to the first electrode of the first ceramic body, a first extension extending from the body portion to the second ceramic body, and a second extension extending from the first extension to the fourth electrode. | 2009-05-14 |
20090121823 | VARIABLE-RESISTANCE ELEMENT - The invention provides a variable-resistance element having a multilayer structure. The variable-resistance element includes, for example, a first electrode, a second electrode, and an oxygen ion migration layer disposed between the first electrode and the second electrode. In the oxygen ion migration layer, oxygen vacancy can be produced owing to oxygen ion migration, thereby forming a low resistance path. The variable-resistance element also includes an oxygen ion generation promoting layer disposed between the oxygen ion migration layer and the first electrode and held in contact with the oxygen ion migration layer. | 2009-05-14 |
20090121824 | Device having at least one PTC resistor - The present invention relates to a device having at least one PCT resistor and having at least one AC voltage source connected to the PTC resistor, with the PTC resistor being dimensioned such that the voltage drop over the PTC resistor does not exceed the value of 40 V/mm. | 2009-05-14 |
20090121825 | Method Of An Device For Performing Bi-Directional Transmission Using A Single-Wire - A communication system transfers a signal over a single signal wire (SW) between a first system (S | 2009-05-14 |