19th week of 2010 patent applcation highlights part 46 |
Patent application number | Title | Published |
20100120183 | Method of fabricating light-emitting apparatus with improved light extraction efficiency and light-emitting apparatus fabricated using the method - Provided are a method of fabricating a light-emitting apparatus with improved light extraction efficiency and a light-emitting apparatus fabricated using the method. The method includes: preparing a monocrystalline substrate; forming an intermediate structure on the substrate, the intermediate structure comprising a light-emitting structure which comprises a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type stacked sequentially, a first electrode which is electrically connected to the first conductive pattern, and a second electrode which is electrically connected to the second conductive pattern; forming a polycrystalline region, which extends in a horizontal direction, by irradiating a laser beam to the substrate in the horizontal direction such that the laser beam is focused on a beam-focusing point within the substrate; and cutting the substrate in the horizontal direction along the polycrystalline region. | 2010-05-13 |
20100120184 | OPTOELECTRONIC DEVICE STRUCTURE - The application is related to an optoelectronic device structure including a stress-balancing layer. The optoelectronic device structure comprises a high thermal conductive substrate, a stress-balancing layer on the high thermal conductive substrate, a reflective layer on the stress-balancing layer and an epitaxial structure on the reflective layer. | 2010-05-13 |
20100120185 | METHOD OF MANUFACTURING ORGANIC EL ELEMENT, ORGANIC EL ELEMENT, AND ORGANIC EL DISPLAY DEVICE - A method of manufacturing an organic EL element according to the present invention comprises the steps of forming pixel electrodes ( | 2010-05-13 |
20100120186 | LIQUID CRYSTAL DISPLAY DEVICE - An object of the present invention is to provide a transflective liquid crystal display device having an excellent visibility obtained by optimizing the arrangement of a color filter, which would become a problem in the process of fabricating transparent and reflective liquid crystal display devices, for the transflective liquid crystal display device. In the present invention, the arrangement of a color filter is optimized for improving the visibility of the transflective liquid crystal display device. In addition, the structure, which allows the formation of color filters without increasing the capacitance that affects on a display, is fabricated. Furthermore, in the process of fabricating the transflective liquid crystal display device, an uneven structure is additionally formed without particularly increasing an additional patterning step for the formation of such an uneven structure. | 2010-05-13 |
20100120187 | PRODUCTION OF A HEXAGONAL BORON NITRIDE CRYSTAL BODY CAPABLE OF EMITTING OUT ULTRAVIOLET RADIATION - The invention has for its object to provide a process of synthesizing high-purity hBN crystal bodies on a robust substrate even under normal pressure. | 2010-05-13 |
20100120188 | METHOD FOR MANUFACTURING PHOTOVOLTAIC DEVICE - Provided is a method for manufacturing a photovoltaic device which is capable of easily forming a texture having an aspect ratio larger than 0.5. The method for manufacturing a photovoltaic device include the steps of: forming an etching-resistant film on a silicon substrate; forming a plurality of fine holes in the etching-resistant film with an irradiated laser beam which has a focal depth adjusted to 10 μm or more to expose a surface of the silicon substrate which is a base layer; and etching the exposed surface of the silicon substrate, in which the step of exposing the surface of the silicon substrate includes forming a fine recess at a concentric position to each of the fine holes in the surface of the silicon substrate which lies under the etching-resistant film. | 2010-05-13 |
20100120189 | METHOD FOR MANUFACTURING IMAGE SENSOR - A method for manufacturing an image sensor includes forming circuitry including a metal line over a semiconductor substrate, forming a photodiode over the metal line, and forming a contact plug in the photodiode such that the contact plug is connected to the metal line. The forming of the contact plug includes performing a first etch process to etch a portion of the photodiode, and performing a second etch process to expose a portion of the metal line by using a byproduct generated in etching, to form a via hole for the contact plug in the photodiode. | 2010-05-13 |
20100120190 | IMAGE SENSOR AND METHOD FOR FORMING THE SAME - A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A transistor directly connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern. Since the ion-implantation interrupting pattern is located on an upper portion of the gate electrode pattern of the transistor in the vicinity of the photo-detective device, a threshold voltage of the gate electrode pattern of the transistor in the vicinity of the photo-detective device is adjusted to a desired value. | 2010-05-13 |
20100120191 | Method of forming front contacts to a silicon solar cell wiithout patterning - A method for forming front contacts on a silicon solar cell which includes texture etching the front surface of the solar cell, forming an antireflective layer over the face, diffusing a doping material into the face to form a heavily doped region in valleys formed during the texture-etching of the face, depositing an electrically conductive material on the heavily doped regions in the valleys and annealing the solar cell. | 2010-05-13 |
20100120192 | SYNTHESIS OF I-III-VI2 NANOPARTICLES AND FABRICATION OF POLYCRYSTALLINE ABSORBER LAYERS - A method for preparing III-VI | 2010-05-13 |
20100120193 | IMAGE SENSOR AND FABRICATION METHOD THEREOF - An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer. | 2010-05-13 |
20100120194 | METHOD OF MANUFACTURING IMAGE SENSOR - A method of manufacturing an image sensor includes forming an interlayer dielectric including a metal line on a semiconductor substrate, forming an image sensing part, over which a first doped layer and a second doped layer are stacked, over the interlayer dielectric, forming a via hole exposing the metal line, the via hole passing through the image sensing part and the interlayer dielectric, forming a first barrier layer and a second barrier layer over surfaces defining the via hole, forming a contact plug inside the via hole to have a first height equal to that of the first doped layer, thereby exposing the second barrier layer over the second doped layer inside the via hole, performing a wet etch process on the exposed second barrier layer to form a second barrier pattern having the same height as that of the contact plug, and performing a wet etch process on the first barrier layer to expose the second doped layer within the via hole, thereby forming a first barrier pattern. | 2010-05-13 |
20100120195 | METHOD FOR MANUFACTURING IMAGE SENSOR - In a method for forming an image sensor, an interlayer dielectric may be formed over a semiconductor substrate. The interlayer dielectric may include an interconnection. A via hole may be formed through the interlayer dielectric by performing an etching process on the semiconductor substrate. The via hole exposes the interconnection. A first cleaning process and a second cleaning process may be performed on the semiconductor substrate including the via hole. The contact plug may be formed by filing a metal material in the via hole. The image sensing unit, with a first doping layer and a second doping layer stacked therein may be formed over the interlayer dielectric including the interconnection and the contact plug. Here, the first and second cleaning processes include removing residues formed over a sidewall of the via hole through the etching process. | 2010-05-13 |
20100120196 | NANO-ARRAY AND FABRICATION METHOD THEREOF - The invention provides a method for fabricating a nano-array comprising the following steps. A template with a plurality of nano-holes is provided. A polymer is embossed by the template to integrally form a plurality of nano-protrusions thereon, and demolding to reveal the nano-protrusions. The nano-protrusion has a concave or convex top surface. | 2010-05-13 |
20100120197 | METHODS OF MAKING THIN FILM TRANSISTORS COMPRISING ZINC-OXIDE-BASED SEMICONDUCTOR MATERIALS - A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. during fabrication. | 2010-05-13 |
20100120198 | METHOD AND ARTICLE OF MANUFACTURE FOR WIRE BONDING WITH STAGGERED DIFFERENTIAL WIRE BOND PAIRS - A method and article of manufacture for performing wire-bonding operations in an integrated circuit. In one aspect, the operations include the steps of bonding a wire to a first bond site in the integrated circuit and terminating the wire at a second bond site. The bonding and terminating steps are repeated for at least two differential wire bond pairs, and proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles. | 2010-05-13 |
20100120199 | Stacked package-on-package semiconductor device and methods of fabricating thereof - Methods for fabricating a semiconductor package are provided, by coupling a plurality of first interconnects and a semiconductor die to a first surface of a substrate, and depositing a mold material on the first surface by compression molding to fully encapsulate the die and to partially encapsulate the first interconnects. | 2010-05-13 |
20100120200 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a thin but robust stack of electrically connected thin film semiconductor elements includes the steps of forming a first element to be stacked: forming a separation layer and a semiconductor element layer over a substrate, forming a wiring connected to the semiconductor element layer, forming a protective material over the semiconductor layer and the wiring, forming a conductive region electrically connected to the wiring in the protective layer, and separating the semiconductor element layer from the substrate along the separation layer. A second element is formed according to the aforementioned process, and the first element is stacked thereon, before separating the second element from its substrate. The first element is bonded to the protective layer of the second element so that the semiconductor element layers of the first and the second element are electrically connected to each other through the protective layer, without damaging the protective layer. | 2010-05-13 |
20100120201 | METHOD OF FABRICATING QUAD FLAT NON-LEADED PACKAGE - A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed. | 2010-05-13 |
20100120202 | Method for Reducing Chip Warpage - A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material. | 2010-05-13 |
20100120203 | SEMICONDUCTOR DEVICE AND MEMORY CARD USING THE SAME - A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks. | 2010-05-13 |
20100120204 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A chip is bonded onto a flat face of a first support through a first bonding layer with a terminal surface of the chip turned toward the flat face of the first support. A second support is bonded onto the chip through a second bonding layer. The first support is peeled from the chip to expose the terminal surface of the chip. An insulating layer from which the terminal surface of the chip is exposed is formed on the second support. | 2010-05-13 |
20100120205 | MANUFACTURING METHOD OF WIRING BOARD AND SEMICONDUCTOR DEVICE - A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method of a semiconductor device using the wiring board are proposed. A pattern of a conductive material is formed over a first substrate, a conductive film is formed over the pattern by an electrolytic plating process, the pattern and the conductive film are separated, an IC chip including at least one thin film transistor is formed over a second substrate, and the conductive film is electrically connected to the IC chip. | 2010-05-13 |
20100120206 | INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR DISSIPATING HEAT IN AN INTEGRATED CIRCUIT PACKAGE - An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”. | 2010-05-13 |
20100120207 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip has a rectangular main surface with first and second vertices on a diagonal line and first and second sides connecting the first and second vertices. A wire is formed between an electrode and a pad of the semiconductor chip. The wire is enclosed in a cavity of a mold. A liquid resin is poured into the cavity to flow from the first vertex toward the second vertex along the first and second sides. The liquid resin is cured to form a resin portion. The wire is formed such that the wire extends on the side relatively further from the first vertex with respect to a straight line connecting the pad and electrode as seen in plan view. Wires are thus prevented from contacting each other in the process of pouring the liquid resin and accordingly electrical short circuit between the wires can be prevented. | 2010-05-13 |
20100120208 | INTEGRATED CIRCUIT ARRANGEMENT WITH SHOCKLEY DIODE OR THYRISTOR AND METHOD FOR PRODUCTION AND USE OF A THYRISTOR - An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element. | 2010-05-13 |
20100120209 | ETCHANT COMPOSITION, AND METHOD OF FABRICATING METAL PATTERN AND THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - An etchant composition is provided. The etchant composition includes about 40 to about 65 wt % of phosphoric acid, about 2 to about 5 wt % of nitric acid, about 2 to about 20 wt % of acetic acid, about 0.1 to about 2 wt % of a compound containing phosphate, about 0.1 to about 2 wt % of a compound simultaneously containing an amino group and a carboxyl group, and a remaining weight percent of water for the total weight of the composition. | 2010-05-13 |
20100120210 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 2010-05-13 |
20100120211 | Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures - A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed. | 2010-05-13 |
20100120212 | Method of forming capacitor of semiconductor memory device - A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures. | 2010-05-13 |
20100120213 | Embedded DRAM with multiple gate oxide thicknesses - A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells. | 2010-05-13 |
20100120214 | Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method - A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions. | 2010-05-13 |
20100120215 | Nitrogen Based Implants for Defect Reduction in Strained Silicon - A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer. | 2010-05-13 |
20100120216 | TRANSISTOR FABRICATION METHOD - A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed. | 2010-05-13 |
20100120217 | Methods of Forming SRAM Devices having Buried Layer Patterns - An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed. | 2010-05-13 |
20100120218 | METHOD FOR FABRICATING PARTIAL SOI SUBSTRATE - A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches. | 2010-05-13 |
20100120219 | Method for Fabricating Semiconductor Device - A method for fabricating a semiconductor device is disclosed. The method includes forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate in succession, etching the second oxide film and the nitride film to form a second oxide film pattern and a nitride film pattern, exposing a portion of the first oxide film, performing at least one nitrogen implantation into the semiconductor substrate to form a nitrogen injection region under the exposed portion of the first oxide film, forming a third oxide film over the second oxide film pattern, the nitride film pattern, and the semiconductor substrate, forming a trench that is deeper than the nitrogen ion injection region by etching the semiconductor substrate using the second oxide film pattern as a mask, and filling the trench with an oxide film to form a device isolating film. | 2010-05-13 |
20100120220 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL GATE - A method for fabricating a semiconductor device includes: forming a stack structure including pillar regions whose upper portion has a wider width than a lower portion over a substrate, the lower portion including at least a conductive layer; forming a gate insulation layer on sidewalls of the pillar regions; forming active pillars to gap-fill the pillar regions; and forming vertical gates that serve as both gate electrode and word lines by selectively etching the conductive layer. | 2010-05-13 |
20100120221 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR - A method for fabricating a semiconductor device includes forming a plurality of pillar structures over a substrate, forming gate electrodes over sidewalls of the pillar structures, forming a sacrificial layer buried between the pillar structures, etching the sacrificial layer and the substrate to form trenches in the substrate, forming first inter-layer insulation patterns buried over the trenches and removing the remaining sacrificial layer at substantially the same time, and forming second inter-layer insulation patterns over the first inter-layer insulation patterns and buried between the pillar structures. | 2010-05-13 |
20100120222 | Methods and apparatus for bonding wafers - In a method of and apparatus for bonding wafers, the method includes heating a first wafer having a first coefficient of thermal expansion (CTE) until the first wafer reaches a first temperature, heating a second wafer having a second CTE that is different from the first CTE until the second wafer reaches a second temperature that is different from the second temperature, and bonding the first wafer and the second wafer to each other. | 2010-05-13 |
20100120223 | METHOD FOR MANUFACTURING BONDED WAFER - The present invention is a method for manufacturing a bonded wafer by an ion implantation delamination method including at least the steps of, bonding a bond wafer having a micro bubble layer formed by gas ion implantation with a base wafer to be a supporting substrate, delaminating the bond wafer along the micro bubble layer as a boundary to form a thin film on the base wafer, the method comprising, cleaning the bonded wafer after delaminating the bond wafer using ozone water; performing rapid thermal anneal process under a hydrogen containing atmosphere; forming a thermal oxide film on a surface layer of the bonded wafer by subjecting to heat treatment under an oxidizing gas atmosphere and removing the thermal oxide film; subjecting to heat treatment under a non-oxidizing gas atmosphere. As a result, the method for manufacturing a bonded wafer, which can remove the damage caused by the ion implantation and can suppress a occurrence of the concave defects without deterioration of surface roughness on the surface of the thin film of the bonded wafer after delamination is provided. | 2010-05-13 |
20100120224 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing an SOI substrate including a single crystal silicon film whose plane orientation is (100) and a single crystal silicon film whose plane orientation is (110) with high yield. A first single crystal silicon substrate whose plane orientation is (100) is doped with first ions to form a first embrittlement layer. A second single crystal silicon substrate whose plane orientation is (110) is doped with second ions to selectively form a second embrittlement layer. Only part of the first single crystal silicon substrate is separated along the first embrittlement layer by first heat treatment, thereby forming a first single crystal silicon film. A region of the second single crystal silicon substrate, in which the second embrittlement layer is not formed, is removed. Part of the second single crystal silicon substrate is separated along the second embrittlement layer by second heat treatment, thereby forming a second single crystal silicon film. | 2010-05-13 |
20100120225 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the number of steps can be suppressed. A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween. | 2010-05-13 |
20100120226 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified. | 2010-05-13 |
20100120227 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 2010-05-13 |
20100120228 | SEMICONDUTOR MANUFACTURING METHOD - A manufacturing method for semiconductor devices having a metal support is provided. The method in one aspect includes growing a semiconductor film on a growth substrate; forming a metal support on a surface of said semiconductor film opposite to the growth substrate; thereafter removing said growth substrate from said semiconductor film; forming a street groove reaching said metal support in the said semiconductor film; radiating a first laser beam onto said metal support to form a first dividing groove having a substantially flat bottom in said metal support; and radiating a second laser beam onto said metal support to form a second dividing groove that penetrates though a portion of said metal support that remains where the first divining groove is formed. | 2010-05-13 |
20100120229 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, ADHESIVE FILM FOR SEMICONDUCTOR, AND COMPOSITE SHEET USING THE FILM - There is provided a method that allows semiconductor chips to be obtained from a semiconductor wafer at high yield, while sufficiently inhibiting generation of chip cracks and burrs. The method for manufacturing a semiconductor chip comprises a step of preparing a laminated body having a semiconductor wafer, an adhesive film for a semiconductor and dicing tape laminated in that order, the semiconductor wafer being partitioned into multiple semiconductor chips and notches being formed from the semiconductor wafer side so that at least a portion of the adhesive film for a semiconductor remains uncut in its thickness direction, and a step of stretching out the dicing tape in a direction so that the multiple semiconductor chips are separated apart, to separate the adhesive film for a semiconductor along the notches. The adhesive film for a semiconductor has a tensile breaking elongation of less than 5% and the tensile breaking elongation of less than 110% of the elongation at maximum load. | 2010-05-13 |
20100120230 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 2010-05-13 |
20100120231 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the present invention includes the following step: a step (S | 2010-05-13 |
20100120232 | METHOD OF FABRICATING THIN FILM DEVICE - Provided is a method of fabricating a thin film device. A sacrifice layer is formed on a first substrate. A thin film laminated body is formed on the sacrifice layer. A separation groove exposing the sacrifice layer is formed to divide the thin film laminated body into at least one thin film device. The sacrifice layer is partially removed using a dry etching process. After the partial removal of the sacrifice layer, a remaining sacrifice layer region maintains the thin film device on the first substrate. A supporting structure is temporarily joined to the thin film device. The thin film device joined to the supporting structure is separated from the first substrate. Then, the remaining sacrifice layer is removed. The thin film device joined to the supporting structure is joined to a second substrate. Finally, the supporting structure is separated from the thin film device. | 2010-05-13 |
20100120233 | Continuous Feed Chemical Vapor Deposition - Embodiments of the invention generally relate to a method for forming a multi-layered material during a continuous chemical vapor deposition (CVD) process. In one embodiment, a method for forming a multi-layered material during a continuous CVD process is provided which includes continuously advancing a plurality of wafers through a deposition system having at least four deposition zones. Multiple layers of materials are deposited on each wafer, such that one layer is deposited at each deposition zone. The methods provide advancing each wafer through each deposition zone while depositing a first layer from the first deposition zone, a second layer from the second deposition zone, a third layer from the third deposition zone, and a fourth layer from the fourth deposition zone. Embodiments described herein may be utilized to form an assortment of materials on wafers or substrates, especially for forming Group III/V materials on GaAs wafers. | 2010-05-13 |
20100120234 | METHOD FOR GROWTH OF GaN SINGLE CRYSTAL, METHOD FOR PREPARATION OF GaN SUBSTRATE, PROCESS FOR PRODUCING GaN-BASED ELEMENT, AND GaN-BASED ELEMENT - A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer ( | 2010-05-13 |
20100120235 | METHODS FOR FORMING SILICON GERMANIUM LAYERS - Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method includes depositing a silicon germanium seed layer atop the substrate using a first precursor comprising silicon and chlorine; and depositing a silicon germanium bulk layer atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H | 2010-05-13 |
20100120236 | FABRICATION OF ULTRA LONG NECKLACE OF NANOPARTICLES - The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. A variety of combinations of nanoparticles, such as Au and CdS nanoparticles, may be used to form a necklace. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V. The present invention also provides methods for constructing such a device. | 2010-05-13 |
20100120237 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A growth substrate is removed from a semiconductor film, and a surface of the semiconductor film exposed by removing the growth substrate is flattened. The semiconductor film along device division lines are partially etched by dry etching to form grooves in a lattice that form streets, not reaching the metal support in the semiconductor film. The surface of the semiconductor film at the bottom of the grooves is flattened. The semiconductor film along the device division lines at the bottom of the grooves are further etched by wet etching to expose the metal support at the bottom of the grooves to finish the streets. | 2010-05-13 |
20100120238 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD - A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber | 2010-05-13 |
20100120239 | MEMORY DEVICE ETCH METHODS - A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF | 2010-05-13 |
20100120240 | METHOD FOR FABRICATING PMOS TRANSISTOR AND METHOD FOR FORMING DUAL GATE USING THE SAME - Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber. | 2010-05-13 |
20100120241 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including an integrated circuit having a plurality of semiconductor elements which are formed on a semiconductor substrate and electrically connected through a line, the method including: forming a conducting path to be connected to the semiconductor elements in a similar manner as the line is to be connected thereto; etching the semiconductor elements in a state where the semiconductor elements are electrically connected via the conducting path; and forming the line to be connected to the semiconductor elements in a similar manner as the conducting path is connected thereto. | 2010-05-13 |
20100120242 | METHOD TO PREVENT LOCALIZED ELECTRICAL OPEN CU LEADS IN VLSI CU INTERCONNECTS - One embodiment of the present invention relates a method for preventing the formation of electrical opens due to localized copper dissolution during fabrication of metal interconnect wires. More particularly, a semiconductor body comprising one or more exposed copper metal levels is coated with a benzotriazole (BTA) solution. The semiconductor body is then dried, resulting in a protective layer of BTA coating the copper metal levels. The protective layer of BTA passivates the exposed copper surface by forming a protective BTA layer that prevents the copper metal level from coming into direct contact with deionized water thereby preventing copper metal dissolution and providing improved integrated chip yields and reliability. | 2010-05-13 |
20100120243 | FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS - The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element. | 2010-05-13 |
20100120244 | INTEGRATED CIRCUIT SHIELD STRUCTURE AND METHOD OF FABRICATION THEREOF - A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion. | 2010-05-13 |
20100120245 | PLASMA AND THERMAL ANNEAL TREATMENT TO IMPROVE OXIDATION RESISTANCE OF METAL-CONTAINING FILMS - Method and apparatus are provided for treatment of a deposited material layer. In one embodiment, a method is provided for processing a substrate including depositing a metal-containing layer using an atomic layer deposition technique, exposing the metal-containing layer to a plasma treatment process at a temperature of less than about 200° C., and exposing the metal-containing layer to a thermal anneal process at a temperature of about 600° C. or greater. The plasma treatment process and/or the thermal anneal process may use a nitrating gas, which may form a passivating surface or layer with the metal-containing layer. | 2010-05-13 |
20100120246 | Methods Of Forming Electrically Insulative Materials, Methods Of Forming Low k Dielectric Regions, And Methods Of Forming Semiconductor Constructions - Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material. | 2010-05-13 |
20100120247 | METHOD OF FORMING FINE PATTERNS USING MULTIPLE SPACER PATTERNS - Fine patterns are formed by forming an etch-target layer on a substrate; forming support patterns on the etch-target layer; forming first spacer patterns on sidewalls of the support patterns; forming second spacer patterns coming in contact with the first spacer patterns; removing the support patterns; and etching the etch-target layer by using the first spacer patterns and the second spacer patterns as an etch mask. | 2010-05-13 |
20100120248 | ETCHING SOLUTION AND ETCHING METHOD - An etching solution contains water, nitric acid, hydrofluoric acid, and sulphuric acid. More specifically it contains 15 to 40% by weight of nitric acid, 10 to 41% by weight of sulphuric acid and 0.8 to 2.0% by weight of hydrofluoric acid. The etching solution is used for etching silicon and to etching methods for silicon wafers. | 2010-05-13 |
20100120249 | PROCESS FOR PRODUCING POLYURETHANE FOAM - A method for manufacturing a polishing pad containing substantially spherical cells and having high thickness accuracy includes preparing a cell-dispersed urethane composition by a mechanical foaming method; continuously discharging the cell-dispersed urethane composition from a single discharge port to a substantially central portion in the width direction of a face material A, while feeding the face material A; laminating a face material B on the cell-dispersed urethane composition; then uniformly adjusting the thickness of the cell-dispersed urethane composition by thickness adjusting means; curing the cell-dispersed urethane composition with the thickness adjusted in the preceding step without applying any additional load to the composition so that a polishing sheet including a polyurethane foam is formed; and cutting the polishing sheet. | 2010-05-13 |
20100120250 | METAL POLISHING SLURRY AND POLISHING METHOD - The present invention relates to a metal polishing slurry containing abrasive grains, a metal-oxide-dissolving agent, and water, wherein the abrasive grains contain two or more abrasive grain species different from each other in average secondary particle diameter. Using the metal polishing slurry of the present invention, a metal polishing slurry can be obtained which gives a large polishing rate of an interlayer dielectric layer, and is high in the flatness of the polished surface. This metal polishing slurry can provide suitable method for a semiconductor device which is excellent in being made finer and thinner and in dimension precision and in electric characteristics, is high in reliability, and can attain a decrease in costs. | 2010-05-13 |
20100120251 | Large Area Patterning of Nano-Sized Shapes - Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process. | 2010-05-13 |
20100120252 | Method of Positioning Patterns from Block Copolymer Self-Assembly - A method of controlling both alignment and registration (lateral position) of lamellae formed from self-assembly of block copolymers, the method comprising the steps of obtaining a substrate having an energetically neutral surface layer comprising a first topographic “phase pinning” pattern and a second topographic “guiding” pattern; obtaining a self-assembling di-block copolymer; coating the self-assembling di-block copolymer on the energetically neutral surface to obtain a coated substrate; and annealing the coated substrate to obtain micro-domains of the di-block copolymer. | 2010-05-13 |
20100120253 | Post Etch Dielectric Film Re-Capping Layer - Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased. | 2010-05-13 |
20100120254 | Passivation Layer for a Circuit Device and Method of Manufacture - According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter | 2010-05-13 |
20100120255 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mask material onto the foundation film so as to cover the core pattern, the mask material being crosslinkable upon supply acid from the core pattern; etching back the mask material to expose an upper surface of the core pattern and remove a portion of the mask material formed on the end portion of the core pattern, thereby leaving a mask material side wall portion formed on a side wall of the core pattern; and removing the core pattern and processing the foundation film by using the mask material sidewall portion left on the foundation film as a mask. | 2010-05-13 |
20100120256 | METHOD FOR REMOVING ETCHING RESIDUES FROM SEMICONDUCTOR COMPONENTS - A method for cleaning structured surfaces of semiconductor components to remove photoresist and etching residues after the etching of the surface, comprising: a) removal of the photoresist, b) treatment of the surface with an acidic aqueous solution comprising one or more acids and one or more oxidizing agents, c) treatment of the surface with an alkaline aqueous solution and d) washing of the surface with demineralized water, the steps a), b) and c) being effected before step d). | 2010-05-13 |
20100120257 | METHOD FOR MAKING MICRO-ELECTRO-MECHANICAL SYSTEM DEVICE - The present invention discloses a method for making a MEMS device, comprising: providing a zero-layer substrate; forming a MEMS device region on the substrate, wherein the MEMS device region is provided with a first sacrificial region to separate a suspension structure of the MEMS device from another part of the MEMS device; removing the first sacrificial region by etching; and micromachining the zero-layer substrate. | 2010-05-13 |
20100120258 | METHOD FOR FORMING MICRO-PATTERN IN SEMICONDUCTOR DEVICE - A method for forming a micro-pattern in a semiconductor device includes forming a hard mask layer and a sacrificial layer over an etch target layer, forming a plurality of openings having a hole shape in the sacrificial layer, forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings, etching the sacrificial layer outside of the sidewalls of the openings using the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns, wherein the first area is smaller than the second area, and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns. | 2010-05-13 |
20100120259 | METHOD AND APPARATUS TO ENHANCE PROCESS GAS TEMPERATURE IN A CVD REACTOR - Methods and apparatus for controlling temperature and flow characteristics of process gases in a process chamber have been provided herein. In some embodiments, an apparatus for controlling temperature and flow characteristics of a process gas in a process chamber may include a gas pre-heat ring configured to be disposed about a substrate and having a labyrinthine conduit disposed therein, wherein the labyrinthine conduit has an inlet and outlet to facilitate the flow of the process gas therethrough. | 2010-05-13 |
20100120260 | Multi-Step Process for Forming High-Aspect-Ratio Holes for MEMS Devices - A method of forming an integrated circuit structure includes forming an opening in a substrate, with the opening extending from a top surface of the substrate into the substrate. The opening is filled with a filling material until a top surface of the filling material is substantially level with the top surface of the substrate. A device is formed over the top surface of the substrate, wherein the device includes a storage opening adjoining the filling material. A backside of the substrate is grinded until the filling material is exposed. The filling material is removed from the channel until the storage opening of the device is exposed. | 2010-05-13 |
20100120261 | Method of Nonstoichiometric CVD Dielectric Film Surface Passivation for Film Roughness Control - A method is provided for reducing film surface roughness in Chemical Vapor Deposition (CVD) of dielectric films. The method may include removing dangling bonds from a film surface of a CVD dielectric film by a reactant. For reducing a surface roughness of a dielectric film, a further method may passivate a nonstoichiometric film surface of the dielectric film, or of a previous dielectric film, or of the dielectric film and of a previous dielectric film, by a reactant gas in the vapor environment. The dielectric film may include at least one out of the following group: ultraviolet light transparent Silicon Nitride (UVSIN), Silicon Rich Oxide (SRO), Silicon Dioxide (SiO | 2010-05-13 |
20100120262 | Amino Vinylsilane Precursors for Stressed SiN Films - The present invention is a method to increase the intrinsic compressive stress in plasma enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) and silicon carbonitride (SiCN) thin films, comprising depositing the film from an amino vinylsilane-based precursor. More specifically the present invention uses the amino vinylsilane-based precursor selected from the formula: [RR | 2010-05-13 |
20100120263 | MICROWAVE ACTIVATION ANNEALING PROCESS - The present invention relates a microwave activation annealing process, which includes: the providing of a semiconductor process to form a semiconductor device on a substrate; activation: using a microwave device to perform microwave activation on the semiconductor device with frequency in the range of 2.45 GHz and 24.15 GHz and temperature in the range of 100° C. and 600° C.; annealing: using the microwave device to perform microwave annealing on the semiconductor device with frequency in the range 2.45 GHz to 24.15 GHz and temperature in the range 100° C. to 600° C.; by doing so, the present invention can, in the premise without the destruction of material property and structural interface and be able to shorten process time and enhance heating homogeneity, achieve the objective of activation annealing, hence, it can solve the defects caused by the heat treatment technique of prior art high temperature activation annealing. | 2010-05-13 |
20100120264 | Intelligent Patching System - An intelligent network patch field management system is provided that includes active electronic hardware, firmware, mechanical assemblies, cables, and software that guide, monitor, and report on the process of connecting and disconnecting patch cords plugs in an interconnect or cross-connect patching environment. The system is also capable of monitoring patch cord connections to detect insertions or removals of patch cords or plugs. In addition, the system can map embodiments of patch fields. | 2010-05-13 |
20100120265 | ELECTRICAL CONNECTING DEVICE - An electrical connecting device for electrically connecting between two contacted articles, comprising a push member, a lock member, which holds one of the contacted articles in a predetermined mount position through the push member, a base member, to which the two contacted articles are mounted, an elastic member held on the base member, and a plurality of contacts held on the elastic member, and wherein the base member includes an upper base member and a lower base member, each including an accommodating recess, which accommodates the elastic member, the elastic member includes slits, respectively, holding the plurality of contacts, the plurality of contacts, respectively, include at least an upper contact arm having an upper contact portion and a lower contact arm having a lower contact portion, and the upper and lower contact portions of each of the plurality of contacts are structured to enable abutting against the elastic member. | 2010-05-13 |
20100120266 | Backplane To Mate Boards With Different Widths - The invention provides a backplane ( | 2010-05-13 |
20100120267 | WAFER LEVEL INTERPOSER - Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements. | 2010-05-13 |
20100120268 | SOCKET WITH IMPROVED LOAD PLATE - A socket for electrically connecting an IC package to a printed circuit board, comprises an insulative housing, a stiffener surrounding the housing and having a front wall defining a hole; and a load plate pivotably mounted to the front wall of the stiffener. The load plate has a pivotal portion with a hook, the hook has a latching finger engaging with the latching hole of the stiffener, a protruding finger and a gap defined between the latching finger and the protruding finger. The protruding finger resists the stiffener when the load plate deflects on a top-to-bottom direction relative to the stiffener. The protruding finger also can engage with the stiffener to guide the load plate to rotate in a correct direction. | 2010-05-13 |
20100120269 | SOCKET FOR TESTING SEMICONDUCTOR PACKAGE - A socket adapted for electrically connecting a semiconductor package to a printed circuit board, includes a main body defining a number of contact passageways and a plurality of contacts received in the contact passageways of the main body. Each contact has a base portion, a first contacting portion and a second contacting portion upwardly extending from the base portion, and a spring arm bent from a bottom edge of the base portion. The spring arm extends substantially in a horizontal direction and is bent downwardly at a free end thereof to form a tail. The spring arm can deform to provide an elastic force for the tail to press against the printed circuit board. | 2010-05-13 |
20100120270 | TEST SOCKET ASSEMBLY HAVING STACKED INSULATIVE BOARDS - A socket assembly, for electrically connecting IC package and a printed circuit board, has a base with a cavity, a module received in the cavity of the base, a plurality of helical contacts received in the module and a cover mounted on the base. The module has a positioning board, a retaining board and a plurality of stacked insulative boards disposed between the positioning board and the retaining board. Each insulative board defines a plurality of through holes, which cooperatively define a plurality of separate helical channels to receive the contacts. | 2010-05-13 |
20100120271 | IC SOCKET HAVING IMPROVED CONTACT - An IC socket, adapted for electrically connecting an IC package to a printed circuit board, comprises a main body defining a plurality of passageways and a plurality of contacts received in the passageways of the main body. Each contact has a base portion, a first contacting portion and a second contacting portion extending upwardly from the base portion. The first contacting portion and the second contacting portion each is formed with a contacting end to cooperatively clamp a guiding trace of the IC package. The contacting end of the second contacting portion defines a recess to receive the contacting end of the first contacting portion when the IC package is disassembled to the main body. | 2010-05-13 |
20100120272 | SEMICONDUCTOR DEVICE SOCKET - A pressing member has a pressing section capable of pressing semiconductor devices with different shapes having an external shape within a predetermined range. The pressing section is held, via a coupling pin, by paired arm members coupled to paired lever members rotationally movably supported by a socket main body section. When the pressing member is in a pressing state, the opposite ends of the coupling pin are held by a circular arc surface portion of holding walls. When the pressing member is in a standby state, the opposite ends of the coupling pin are disengaged from the circular arc surface portion of the holding walls. | 2010-05-13 |
20100120273 | STRUCTURAL RING INTERCONNECT PRINTED CIRCUIT BOARD ASSEMBLY FOR A DUCTED FAN UNMANNED AERIAL VEHICLE - A structural ring interconnect printed circuit board assembly for a ducted fan unmanned aerial vehicle that comprises a printed circuit board attached to a core vehicle body, wherein the printed circuit board conforms to the shape of the core vehicle body's airframe skirt, and wherein the printed circuit board provides structural integrity to the core vehicle body. | 2010-05-13 |
20100120274 | MODULAR WIRING SYSTEM WITH LOCKING ELEMENTS - A wiring system includes a wiring module and a functional module. The wiring module in at least one embodiment includes elongated holes or openings which are configured to engage or lock with prongs on a functional module to create a lockable connection. The wiring module and the functional module form both a physical and an electrical connection. In another embodiment, there is an adapter which is configured to connect the wiring module and the functional module or unit together. | 2010-05-13 |
20100120275 | SAFETY ELECTRIC SOCKET - An electric socket includes a main member having two apertures. A first block member and a second block member have a first block portion and a second block portion respectively. The first block member and a second block member are received in the main member. An elastic member urging the first block member and the second block member to have the first block portion of the first block member and the second block portion of the second block member under one aperture and the first block portion of the second block member and the second block portion of the first block member under the other aperture. The first block member and the second block member are moved independently that when an improper stuff is inserted into one of the aperture, only one block portion is moved away, and the other block portion will stand still to serve protection function. | 2010-05-13 |
20100120276 | Self Retained Electrical Device Having Positive Locking Mechanism - A self retained cover assembly for holding an electrical device in an electrical outlet. The cover includes a retaining body with a front face for covering the outlet and a rear face with two retainer prongs having moveable barbs for holding the cover to the outlet. The cover retains an electrical cord or an electronic device with electrically conductive prongs to the outlet. A tab is provided to move the barbs so the cover may be removed from the outlet. | 2010-05-13 |
20100120277 | ELECTRICAL CARD CONNECTOR - An electrical card connector comprises an insulative housing, a shield covering the insulative housing, a plurality of terminals received within the insulative housing, and an ejection mechanism. The insulative housing and the shield define a receiving space for receiving an electrical card. The ejection mechanism disposed on one side of the receiving space comprises a base and a movable push rod mounted within the base. A reinforced rib protruding from a surface of the rear portion of the push rod, and a corresponding receiving groove is defined on the base for receiving said the reinforced rib movable therein. A guide groove is defined on the bottom wall of the push rod, and a guide rib protrudes from the base, which is received within said guide groove and movable therein. Therefore, the push rod will have improved mechanical strength and is not easily broken. The engagement between the reinforced rib and the receiving groove and the engagement between the guide groove and the guide rib together confine the push rod in a lateral and vertical direction and prevent the push rod from shifting. | 2010-05-13 |
20100120278 | MULTI-ANGULAR POWER ADAPTER - This invention discloses a multi-angular power adapter particularly used for electrically charging a small electric appliance and having a multi-angular function. The multi-angular power adapter includes a casing, a circuit section, an output power cord, and a connector section connected to an external power supply, characterized in that the connector section includes a fixed base, a movable connector base corresponding to the fixed base, and a limit section for restricting the movements of the movable connector base. The fixed base installed on the casing includes at least two fixed contact points electrically connected to the circuit section, and the movable connector base operates in coordination with the fixed base to change an angle in a plane, and the movable connector base includes two movable contact points respectively in contact with the two fixed contact point and electrically connected with the two insert pins of the movable connector base. | 2010-05-13 |
20100120279 | LAMP HOLDER - A bipin fluorescent-lamp holder has a housing formed with an outwardly open housing mouth and a rotor rotatable in the housing adjacent the mouth about an axis and having a diametrally throughgoing rotor slot. The rotor is rotatable between an installation position with the rotor slot aligned with the slot and an angularly offset contact position with the slot not aligned with the mouth. The rotor and housing are so dimensioned as to receive the pins extending parallel to the axis and to move the pins in a circular orbit centered on the axis on rotation of the rotor in the housing, and contacts in the housing diametrally flanking the axis each having a main part lying outside the orbit and a contact part engageable into the orbit. The contacts pins are aligned with the slot and project into ends of the slot and into engagement with the pins only in the contact position of the rotor. | 2010-05-13 |
20100120280 | CONNECTOR HAVING THREE-WAY INTERCONNECTION - An electrical connector ( | 2010-05-13 |
20100120281 | Card connector capable of detecting card insertion - A card connector capable of detecting card insertion includes a base frame, a cover member, and a plurality of terminals. The base frame is made of an insulated material. The cover member is made of electrically conductive material and is mounted onto the base frame, whereby a card chamber is formed between the cover member and the base frame. The terminals are mounted onto the base frame, extending into the card chamber. Among the terminals, a detectable terminal is insert-molded in the base frame and located at one side of the base frame. The detectable terminal includes a contact portion exposed outside. The cover member includes a tongue extending toward the detectable terminal therefrom. The tongue has a working portion extending into the card chamber and a touch portion corresponding to the contact portion. Therefore, the card connector is of convenient assembly to lessen the assembly time and the labor cost. | 2010-05-13 |
20100120282 | PUSH-PULL CONNECTOR - A connector assembly configured to engage a mating connector. The connector assembly includes a plug body that has loading and mating ends and a central axis extending therebetween. The mating end is configured to be inserted into a cavity of the mating connector to establish at least one of communicative and power connections. The plug body has an outer surface that surrounds and faces away from the central axis. The connector assembly also includes a ring that is slidably mounted over the plug body. The ring is configured to slide along the outer surface of the plug body in an axial direction between withdrawn and locked positions. The connector assembly also includes a sleeve member that is slidably mounted over the plug body and the ring. The sleeve member includes a plurality of fingers that extend toward the mating end and are biased toward the outer surface of the plug body. The ring is configured to engage the fingers thereby causing the fingers to flex outward away from the outer surface and engage the mating connector. | 2010-05-13 |