18th week of 2010 patent applcation highlights part 78 |
Patent application number | Title | Published |
20100115128 | TARGET ROUTING BY INITIATOR - An illustrative embodiment provides a computer-implemented method for target routing by initiator, using Internet small computer system interface. The computer-implemented method obtains a logical unit number configuration, containing a set of logical unit numbers, determines whether an initiator Internet protocol address, associated with a requester, has a mapping to a logical unit number in the set of logical unit numbers. The computer implemented method further sets a path for an input output/request from the requester to a backing file, according to the mapping, and returns success to the requester. | 2010-05-06 |
20100115129 | CONDITIONAL PROCESSING METHOD AND APPARATUS - A conditional processing method and apparatus for efficient memory management are provided. A conditional processing method includes generating a parse tree by loading a plurality of nodes of data structured based on a declarative description language in a memory in series; evaluating, when a parsing switch node having an attribute describing a condition for conditional processing exists among the nodes, child nodes of the parsing switch node according to the attribute; loading only the child nodes fulfilling the attribute in the memory; and outputting the child nodes retained on the memory. | 2010-05-06 |
20100115130 | TIME SLOT ALLOCATION METHOD FOR REDUCING CONSUMPTION OF ENERGY IN WIRELESS SENSOR NETWORK - Disclosed is a time slot allocation method for reducing consumption of energy in a wireless sensor network, including transmitting and receiving, by an upper node, a report request and a response to and from at least one lower node in order to identify whether there is data to be transmitted between the upper node and the at least one lower node, transmitting, by the upper node, information required for data transmission to the at least one lower node based on the report request and response, and transmitting and receiving, by the upper node, data to and from the at least one lower node based on the information required for data transmission. | 2010-05-06 |
20100115131 | Maintaining Storage Area Network ('SAN') Access Rights During Migration Of Operating Systems - Maintaining SAN access rights during migration of operating systems including assigning, to a virtual SAN interface adapter of a source virtualization intermediary (SVI′) on the source server, at least two world wide port names (WWPN), identifying devices coupled for data communications to the SVI through the primary WWPN; selecting a target physical SAN interface adapter on a target server available to a target virtualization intermediary (‘TVI’) having a target virtual SAN interface adapter; assigning to the target virtual SAN interface adapter the secondary WWPN; identifying devices coupled for data communications to the TVI through the secondary WWPN; determining whether the devices coupled to the SVI through the primary WWPN are also coupled to TVI through the secondary WWPN; migrating the operating system from the source server to the target server if the devices coupled to the SVI through the primary WWPN are also coupled to TVI through the secondary WWPN. | 2010-05-06 |
20100115132 | ADDRESS IDENTIFIER SCALING IN CONVERGED NETWORKS - Embodiments of the present invention allow for address scaling of existing addresses in a FC, FCoE, CEE or other type of network. More specifically, subaddresses can be used in conjunction with existing addresses, so that a combination of a subaddress and existing address can identify an addressable entity. Thus, multiple entities can be share a single existing address and be distinguished among each other by way of their respective subaddresses. Some embodiments of the invention allow for use of the inventive subaddressing scheme in conjunction with devices or network elements (e.g., gateways, switches, etc.) that may not be subaddressing aware. Further embodiments allow for the multiple distinct devices to communicate with a single Fibre Channel switching element through a single port by using N_Port_ID Virtualization. | 2010-05-06 |
20100115133 | CONFIGURABLE GEOGRAPHIC PREFIXES FOR GLOBAL SERVER LOAD BALANCING - In a load balancing system, user-configurable geographic prefixes are provided. IP address prefix allocations provided by the Internet Assigned Numbers Authority (IANA) and associated geographic locations are stored in a first, static database in a load balancing switch, along with other possible default geographic location settings. A second, non-static database stores user-configured geographic settings. In particular, the second database stores Internet Protocol (IP) address prefixes and user-specified geographic regions for those prefixes. The specified geographic region can be continent, country, state, city, or other user-defined region. The geographic settings in the second database can override the information in the first database. These geographic entries help determine the geographic location of a client and host IP addresses, and aid in directing the client to a host server that is geographically the closest to that client. | 2010-05-06 |
20100115134 | All Hazards Information Distribution Method and System, and Method of Maintaining Privacy of Distributed All-Hazards Information - An information distribution method includes: gathering all-hazards information into an information exchange from a first information source; gathering all-hazards information into the information exchange from a second information source; distributing the all-hazards information from the information exchange to a first independently-controlled alert network; distributing the all-hazards information from the information exchange to a second independently-controlled alert network. | 2010-05-06 |
20100115135 | AGGREGATE CONTROL FOR APPLICATION-LEVEL COMPRESSION - The claimed subject matter relates to an architecture that can actively regulate associated gateways in connection with lossless application-level compression. In particular, the architecture can monitor a flow of messages that enter and/or traverse a gateway in order to determine a bandwidth utilization of an associated network due to the messages. The architecture can also monitor the aggregate messages load for the associated network due to all gateways. In particular, the architecture can regulate lossless application-level compression at that gateway or all of the gateways in the set as a function of the bandwidth utilization and/or the aggregate message load. Accordingly, compression features can be activated or deactivated based upon a utilization threshold parameter, and gateways can be regulated uniformly or independently from one another. | 2010-05-06 |
20100115136 | METHOD FOR THE DELIVERY OF AUDIO AND VIDEO DATA SEQUENCES BY A SERVER - The invention relates to a method for the delivery of audio and video data by a server device. A network can interconnect various media components in the same home. Such a network comprises a server, generally a computer, and clients, for example a decoder. This configuration offers the possibility of creating a desktop managed by the server but remotely controlled by the client via the network. Such a network must transmit data and process them rapidly. Currently, the trend is to compress the data traveling through the network as much as possible. However, the more these data are compressed, the longer they take to process. The invention does not provide for facilitating the transfer of the data but for reducing the time required to process the data flowing through the network. | 2010-05-06 |
20100115137 | Data compression method and data communication system utilizing the same - A data compression method and data communication system utilizing the same includes: a sender apparatus that compares, in response to input of data to be sent, the input data with the previously sent data in storage. The sender apparatus produces, when a data item repeated in the input data and previously sent data is found, delta data by excluding the repeated data item from the input data. The sender apparatus represents the delta data in a transport format, and transmits the delta data. The system includes a receiver apparatus that receives the data in a transport format. The receiver apparatus adds, when delta data is present in the received data, a repeated data item to the delta data, and recovers the original data. The sender apparatus sends and receives data to and from the receiver apparatus through a text-based protocol. | 2010-05-06 |
20100115138 | Method and Apparatus for Using a Network - In accordance with an example embodiment of the present invention, an apparatus comprising a processor configured to connect to a network, determine a property associated with the network, and generate an event based at least in part on the determined property and the connection to the network is disclosed. | 2010-05-06 |
20100115139 | COMPUTER NETWORK ARCHITECTURE AND METHOD OF PROVIDING DISPLAY DATA - Systems and methods are provided having a plurality of ultra-thin client devices coupled to at least one display device and a data processing device coupled to the ultra-thin client devices over a general purpose data network, the data processing device being operable to transmit image data directly representing at least a portion of the image displayed on one or more of the display devices over the general purpose data network. | 2010-05-06 |
20100115140 | ENCODED ADDRESSING WITHIN CONTROL CODE FOR BUS COMMUNICATION - Electronic devices and methods facilitate encoding target device identification in data packets transmitted on a communications bus. For example, unique tokens are generated and encoded with unique identification information to identify target devices coupled to a communications bus. Unique tokens and encoded device identification information may be selected such that the tokens will not appear as part of other data appearing on the communications bus. | 2010-05-06 |
20100115141 | Processor and method for controlling memory - A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate. | 2010-05-06 |
20100115142 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group. | 2010-05-06 |
20100115143 | STORAGE CONTROL SYSTEM, CONTROL METHOD FOR STORAGE CONTROL SYSTEM, PORT SELECTOR, AND CONTROLLER - An object of the present invention is to provide a means for detecting a logical command error, and a storage system and its control method that can properly perform error handling, and detection and blockage of a malfunctioning section. A storage control system includes controller units | 2010-05-06 |
20100115144 | Wireless Switch State Using Controller Powered with System in Various Low-Powered States - A computer system detects a power state change and determines that the power state change puts the computer system in a low power state. In turn, the computer system informs an external slot device to enable an external wireless device included in the external slot device. | 2010-05-06 |
20100115145 | PLUG-AND-PLAY DEVICE AND METHOD OF USING THE SAME - A plug-and-play device comprises a first plug-and-play interface for establishing a connection with a first computing device and a second plug-and-play interface for establishing a connection with a second computing device. Storage stores code that is automatically executed by the second computing device when the plug-and-play device is connected to the second computing device via the second plug-and-play interface. The code when executed by the second computing device initiates a screen display data exchange between the first and second computing devices through the plug-and-play device. A controller controls the first plug-and-play interface, the second plug-and-play interface and the storage. | 2010-05-06 |
20100115146 | Pairing Service Technologies - Pairing service technologies is described. In embodiment(s), peripheral devices can be discovered, such as by a computer device, and a peripheral device can be configured with multiple services that each correspond to one or more data communication protocols. The multiple services of the peripheral device can be determined, and a pairing sequence can be prioritized for the multiple services. The data communication protocol(s) can then be paired according to the pairing sequence to configure the multiple services of the peripheral device. | 2010-05-06 |
20100115147 | APPARATUS AND METHOD FOR CONTROLLING USB SWITCHING CIRCUIT IN PORTABLE TERMINAL - An apparatus and method for automatically switching the operation mode of a Universal Serial Bus (USB) switching circuit in a portable terminal are provided. The automatic switching is performed according to a detected signal transmitted between the portable terminal and the external device, thereby reducing consumption of electrical current. If an external device is connected to a USB interface unit, a signal is detected from the USB interface unit. The type of external device is identified by the detected signal. If the identified external device is a USB communication device, a communication mode is activated and a signal path is established between an internal module and the USB communication device during the communication mode. A determination is made as to whether an internal event occurs in the portable terminal and an external event occurs in the USB communication device, during the communication mode. The mode of the USB switching circuit is switched to a sleep mode if the internal and external events have not occurred. | 2010-05-06 |
20100115148 | INFORMATION PROCESS SYSTEM, INFORMATION PROCESS APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - An information process system that makes it possible to easily a create process definition ticket according to a template created by checking common capabilities of devices. Devices that have a potential for being used to execute a process based on the process definition ticket defining the process comprised of a plurality of processes on a network are selected, and information on capabilities of the selected devices is obtained. Process items included in the template are designated. Functions common or uncommon to the devices are displayed in an identifiable manner based on the information on the capabilities of the devices in the designated process items. A process definition ticket template including common capabilities of the selected devices is generated with respect to the designated process items based on checking of a display. A process definition ticket that is to be executed using the devices is created based on the generated template. | 2010-05-06 |
20100115149 | System and method for digital signaling of computer headset connection status - A system and method for automatic detection and signaling of the connection status of a headset used with telephony or other multimedia application software running on processor-based hosts using digital signaling are disclosed. The signaling system includes a signaling module for communicating with the host and a headset selectively in communication with the signaling module for use with the application software. The signaling module monitors the headset connection status, generates a status signal, and transmits the status signal to the host for determining the state of host and/or the application software. The signaling module may include a connection status detector and a status signal generating processor. A signal indicating that the headset is disconnected may pause or terminate an executing application or prevent the application from being executed. A signal indicating that the headset is connected may resume a paused application or allow the application to be executed. | 2010-05-06 |
20100115150 | INFORMATION PROCESSOR - According to one embodiment, an information processor includes a power supply module, an interface, an electronic device detector, a notification module, and a power supply controller. The power supply module supplies power. The interface has a power supply function for supplying power from the power supply module to an electronic device even when an operating system is idle. The electronic device detector detects whether the electronic device is connected to the interface. The notification module notifies information indicating that the power supply module supplies power to the electronic device when the electronic device detector has detected that the electronic device is connected to the interface. The power supply controller controls the power supply module to supply power to the electronic device when the electronic device detector has detected that the electronic device is connected to the interface. | 2010-05-06 |
20100115151 | WIRELESS HUMAN INTERFACE DEVICE (HID) COORDINATION - A method relating to wireless human interface device (HID) coordination is disclosed. A first human interface device (HID) is wirelessly coupled to two or more computing devices, wherein the first HID is configured to toggle between interactions with each of the two or more computing devices. An inquiry or paging message is broadcast to one or more HIDs, including a second HID wirelessly coupled to the two or more computing devices, wherein the second HID is configured to receive and provide a response to the inquiry or paging message. The second HID is located based on the response to the inquiry or paging message. A wireless link is established between the first HID and the second HID based on tshe identifying, wherein the first HID is configured to coordinate, via the wireless link, interactions with the two or more computing devices by both the first HID and the second HID based on the toggle. | 2010-05-06 |
20100115152 | Sending large command descriptor block (CDB)Structures in serial attached SCSI(SAS) controller - A system for sending large Command Descriptor Block (CDB) structures in a serial attached SCSI (SAS) controller includes a CDB Transmit Block, a CDB Memory, a Context Memory, a Direct Memory Access (DMA) Queue, a Transmit DMA Engine, and a SAS Interface. The CDB Transmit Block receives one or more Message Frames. If the CDB is small (32 bytes or less), the CDB Transmit Block reads data from the Message Frame and transmits a SAS Command Frame over the SAS interface. If the CDB is large (33 bytes or more), the CDB Transmit Block places a large CDB entry into the DMA Queue. The Transmit DMA Engine receives the large CDB entry from the DMA queue, utilizes an address pointer from the Message Frame to the CDB Memory to fetch large CDB information into a DMA buffer, and transmits a SAS Command Frame over the SAS interface. | 2010-05-06 |
20100115153 | ADAPTIVE MULTI-CHANNEL CONTROLLER AND METHOD FOR STORAGE DEVICE - An adaptive multi-channel controller and its method for a storage device are provided for data transmission between a host and the storage device. The storage device is configured to have multiple channels. A channel use amount is determined based on a data access amount of the host. Then, activated channels are selected among the channels according to the channel use amount. The data transmission is then carried out through the selected channels. | 2010-05-06 |
20100115154 | INFORMATION PROCESSING SYSTEM AND METHOD OF ALLOCATING I/O TO PATHS IN SAME - Provided is an information processing system that communicates with a storage apparatus through a plurality of paths P | 2010-05-06 |
20100115155 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND PERIPHERAL - In a system in which an information processing apparatus and a peripheral are connected to each other. Initially, the information processing apparatus transmits, to the peripheral, a request to use a service provided by the peripheral. The peripheral determines whether to grant use permission to the received request, and notifies the information processing apparatus which has transmitted the request of the determination result. The peripheral stores information associated with the information processing apparatus to which use permission is granted in response to the request. The information processing apparatus then receives, from the peripheral, a response to the request. | 2010-05-06 |
20100115156 | Electronic device capable of matching a multimedia playback device - An electronic device capable of matching a multimedia playback device is disclosed. The electronic device comprises a slot, a connecting port, a sliding cover, a positioning device, and an identification device. The slot is used to accommodate the multimedia playback device. The connecting port is used to electrically connect the multimedia playback device. The sliding cover matches with the slot. The sliding cover has a support structure to support the multimedia playback device. The positioning device is used to fix the sliding cover at a specific position. The identification device is used to identify the type of the multimedia playback device. When the multimedia playback device is accommodated in the slot, the sliding cover fixes in a specific position to match and support the multimedia playback device. | 2010-05-06 |
20100115157 | MODULAR DATA COLLECTION MODULE WITH STANDARD COMMUNICATION INTERFACE - A modular data collection module is provided. The module includes a data collection module configured to condition and sample signals from one or more of a plurality of measuring devices that operably detect the condition of a machine, the data collection module includes a Universal Serial Bus (USB) interface configured to interchangeably connect the data collection module to at least one of a plurality of host platforms forming an integrated data collection unit. | 2010-05-06 |
20100115158 | Methods and Systems to Accomplish Variable Width Data Input - Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes. | 2010-05-06 |
20100115159 | KEYBOARD SHORTCUT SOFTWARE UTILITY - A method and system for accessing one or more functions corresponding to one or more applications is provided. An active application is determined. Subsequently, a set of functions corresponding to the active application is identified. A set of keys corresponding to the set of functions is displayed on a display panel. One or more inputs are received, based on activation of at least one key. At least one function corresponding to the at least one key is determined and performed. | 2010-05-06 |
20100115160 | SYSTEM FOR TRANSFERRING A FILE BETWEEN ASSOCIATED COMPUTERS - A system for transferring a file between associated computers is provided. The system comprises a micro control unit; a first USB interface coupled between the micro control unit and a set of keyboard, monitor and mouse; a second USB interface coupled between the micro control unit and a plurality computers; and a switching mechanism for switching the set of keyboard, monitor and mouse coupled to on of the computers to another; wherein the micro control unit including a buffer for registering a file from one of the computers and then transferred to other one of the computers. | 2010-05-06 |
20100115161 | Restoring Data to a Point in a Continuum of Input/Output Operations - To restore data, substantially continuous recording of input/output (I/O) operations in a storage system is performed to provide an I/O continuum of I/O operations. Based on analyzing activity associated with the storage system, points in the I/O continuum associated with valid data are identified. Data in the storage system is restored to one of the identified points. | 2010-05-06 |
20100115162 | Redundant Storage Virtualization Computer System - A redundant storage virtualization computer system is provided. The redundant storage virtualization computer system comprises a host entity for issuing an IO request, a redundant storage virtualization controller set coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage space to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller set. The redundant storage virtualization controller set comprises a first and a second storage virtualization controller both coupled to the host entity, the storage virtualization controllers communicate therebetween via a PCI-Express interconnect. In the redundant storage virtualization controller set, a storage virtualization controller will take over the functionality originally performed by the alternate storage virtualization controller when the alternate storage virtualization controller is not on line. | 2010-05-06 |
20100115163 | METHOD, APPARATUS AND SYSTEM FOR SERIAL ATTACHED SCSI (SAS) ZONING MANAGEMENT OF A DOMAIN USING CONNECTOR GROUPING - Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than one zone group. The connector grouping application removes all phys common to more than one zone group from the respective zone groups and moves the common phys to a new zone group. The zone groups are processed in this manner until no zone groups have common phys. Once all zone groups have been processed accordingly, information associated with the resulting zone groups and their respective permissions are transferred to the zone manager. | 2010-05-06 |
20100115164 | Mobile Device Combining Business Card with Chip - A mobile device combining a business card with at least one chip comprises: a chip sensing device; a data transforming device connected to the chip sensing device; a microprocessor connected to the data transforming device; a display interface connected to the microprocessor for showing the data of the chip; an operation interface able to change the property of the data of the chip and connected to the microprocessor; a memory for the microprocessor storing the data of the chip; and a power supply system for the mobile device; wherein the chip sensing device is disposed in the mobile device and has two modes for receiving data, to keep a certain distance between the business card with the chip and the mobile device is to let the mobile device sense the data of the chip of the business card through the chip sensing device. | 2010-05-06 |
20100115165 | Data Communications Among Electronic Devices Within A Computer - Data communications among electronic devices within a computer, including transmitting, from a transmitting device to a first translation device, data communications encoded according to an unreliable wireline data communications protocol; translating, by the first translation device, the data communications from the encoding of the unreliable wireline data communications protocol to an encoding of a reliable wireless data communications protocol; transmitting, by the first translation device to a second translation device, the data communications according to the reliable wireless data communications protocol; translating, by the second translation device, the data communications from the encoding of the reliable wireless data communications protocol to the encoding of the unreliable wireline data communications protocol; and transmitting, by the second translation device to a receiving device, the data communications according to the unreliable wireline data communications protocol. | 2010-05-06 |
20100115166 | CONTROL OF AN ACTUATOR-SENSOR-INTERFACE COMPATIBLE DEVICE USING A REMOTE INTELLIGENCE DEVICE - A communication network that includes a master device, an actuator-sensor-interface (AS-I) communication bus, a device configured to be monitored and controlled, and a slave device in communication with the master device via the AS-I communication bus. The device that is configured to be monitored and controlled, is operatively connectable to the slave device, and the slave device is configured to receive commands from the master device via the AS-I communication bus, and to execute the commands to control the device. | 2010-05-06 |
20100115167 | Shared Resource Arbitration - Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a corresponding bandwidth threshold. The request is arbitrated if the usage of the shared bus by the master is below the bandwidth threshold, and the request to use the shared bus is granted to the master based on the arbitration. | 2010-05-06 |
20100115168 | MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS - A plurality of data processing tasks with processing elements ( | 2010-05-06 |
20100115169 | Processor and interrupt handling method - Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs. | 2010-05-06 |
20100115170 | CHIP COMBINED WITH PROCESSOR CORES AND DATA PROCESSING METHOD THEREOF - A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal. | 2010-05-06 |
20100115171 | MULTI-CHIP PROCESSOR - Provided is a multiprocessor configured by stacking a plurality of unit chips each having, at least, a processor core and a memory, and the unit chip has a configuration including: a plurality of processor cores; a plurality of memories; a construction controlling unit setting connection relations between the processor core and the memory and between the processor core and the outside of the chip; and a chip connecting unit transmitting transaction between the processor, the memory, or the construction controlling unit and another stacked unit chip to be connected. The chip connecting units are arranged so as to be rotationally symmetric to each other on side portions of the unit chip, so that any of the unit chips configured by stacking is rotationally connected. | 2010-05-06 |
20100115172 | BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has a virtual page buffer corresponding to each discrete memory device for storing read data from the discrete memory device, or write data from an external device. The virtual page buffer is configurable to have a size up to the maximum physical size of the page buffer of a discrete memory device. The page buffer is then logically divided into page segments, where each page segment corresponds in size to the configured virtual page buffer size. By storing read or write data in the virtual page buffer, both the discrete memory device and the external device can operate to provide or receive data at different data rates to maximize the performance of both devices. | 2010-05-06 |
20100115173 | Bus Translator - Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus. | 2010-05-06 |
20100115174 | PCI Express Load Sharing Network Interface Controller Cluster - Embodiments provide load balancing in a virtual computing environment comprising a plurality of PCI-Express switches (the PCIe switching cloud) coupled to a plurality of network interface devices (NICs). An NIC cluster is added between the PCIe switching cloud and the NICs. The NIC cluster is configured to hide NICs from system images and allow the system images to access functions across multiple NICs. The NIC cluster of an embodiment dynamically load balances network resources by performing a hashing function on a header field of received packets. The NIC cluster of an embodiment performs load balancing and state management in association with driver software, which is embedded in the system image. The driver software adds a tag for flow identification to downstream data packets. The NIC cluster distributes data packets based on information in the tag. | 2010-05-06 |
20100115175 | Method of managing a large array of non-volatile memories - The present invention provides a non-volatile flash memory management system and method that provides the ability to efficiently manage a large array of flash devices and allocate flash memory use in a way that improves reliability and longevity, while maintaining excellent performance. The invention mainly comprises of a processor, an array of flash memories that are modularly organized, an array of module flash controllers and DRAM caching. The processor manages the above mention large array of flash devices with caching memory through mainly two tables: Virtual Zone Table and Physical Zone Table, a number of queues: Cache Line Queue, Evict Queue, Erase Queue, Free Block Queue, and a number of lists: Spare Block List and Bad Block List. | 2010-05-06 |
20100115176 | DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE - Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example. | 2010-05-06 |
20100115177 | DATA STORAGE DEVICES - A data storage device includes a non-volatile memory array, a user input device, and a host interface adapted to connect the data storage device to a host device and convey data to the host device. In response to a first operation of the user input device, application configuration data is communicated from the data storage device to the host device. The application configuration data is configured to trigger execution by the host device of a configuration application that includes a listing of a plurality of applications for display by the host device allowing a user to identify a selected application. In response to selection of an application, application designation data is generated and stored in the non-volatile memory array. In response to a second operation of the user input device, the application designation data is communicated to the host device to trigger automatic execution by the host device of the selected application. | 2010-05-06 |
20100115178 | System and Method for Hierarchical Wear Leveling in Storage Devices - Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module. | 2010-05-06 |
20100115179 | MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE - Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module. | 2010-05-06 |
20100115180 | MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION - A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions. | 2010-05-06 |
20100115181 | MEMORY DEVICE AND METHOD - A memory device may include a volatile memory and a non-volatile memory which are arranged to be accessed via a common bus. The memory device may include a controller that is arranged as an interface between the common bus and the volatile and non-volatile computer memories, the controller to transmit read/write commands from the common bus to either the volatile memory or the non-volatile memory. | 2010-05-06 |
20100115182 | FLASH MEMORY OPERATION - An embodiment is a technique to improve operations of flash memory devices. A plurality of logical block numbers is mapped to a plurality of physical block numbers using a mapper. The physical block numbers are associated with blocks in a flash memory device. A plurality of block statuses of the plurality of free physical block numbers is stored in a replacement table. Each of the block statuses is one of a ready, dirty, and broken status. A destination block in the blocks is written to. The destination block has the ready status. The mapper and the replacement table are updated. | 2010-05-06 |
20100115183 | Storage Apparatus and Method of Managing Data Storage Area - Disclosed is a storage apparatus that extends endurance and reduces bit cost. A storage apparatus includes a controller and a semiconductor storage media that has a plurality of storage devices. The plurality of storage devices include a first storage device and a second storage device having an upper limit of an erase count of data smaller than that of the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address. | 2010-05-06 |
20100115184 | FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA PROTECTION METHOD THEREOF - A flash memory storage system including a controller and a flash memory chip is provided, wherein the controller is disposed with a rewritable non-volatile memory. When the controller writes a security data into the flash memory chip, the controller randomly generates a data token and generates a message digest according to the security data and the data token by using a one-way hash function, wherein the data token and the message digest are respectively stored in the rewritable non-volatile memory and the flash memory chip. Subsequently, when the controller reads the security data from the flash memory chip, the controller determinates whether the security data is falsified according to the data token and the message digest respectively stored in the rewritable non-volatile memory and the flash memory chip. Thereby, the security data in the flash memory chip can be effectively protected. | 2010-05-06 |
20100115185 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - Without corresponding to different address spaces between an access device ( | 2010-05-06 |
20100115186 | FLASH MEMORY DEVICE WITH WEAR-LEVELING MECHANISM AND CONTROLLING METHOD THEREOF - A flash memory device with a wear-levelining mechanism includes at least one flash memory, a hot list, a bitmap, a source pointer, and a controller. The controller obtains a physical memory block with high erase count through the hot list, an erase count of the physical memory block, and an overall average erase count of the flash memory device. The controller further finds out a physical memory block which stores static data through managing the bitmap and the source pointer. The controller moves the static data to the physical memory block with high erase count, and releases the physical memory block which stores the static data to avoid the physical memory block with high erase count being worn down increasingly more seriously. | 2010-05-06 |
20100115187 | NON-VOLATILE DATA STORAGE SYSTEM AND METHOD THEREOF - A non-volatile data storage system including a first non-volatile storage medium, a second non-volatile storage medium, and a microprocessor is provided. The first non-volatile storage medium includes a popular data address recording area for recording logic addresses of popular data in the first non-volatile storage medium. The microprocessor is coupled to the first non-volatile storage medium and the second non-volatile storage medium. When the non-volatile data storage system boots up, the microprocessor copies the popular data from the first non-volatile storage medium to the second non-volatile storage medium according to the popular data address recording area. The popular data is accessed in the second non-volatile storage medium instead of the first non-volatile storage medium. | 2010-05-06 |
20100115188 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block; and determining whether to erase a portion of the blocks according to the usage information. For example, the usage information includes a valid page count table for recording valid page counts of the blocks, respectively; and the ranking of a field of the valid page count table represents a physical block address, and the content of the field represents an associated valid page count. In another example, the usage information includes an invalid page count table for recording invalid page counts of the blocks, respectively; and the ranking of a field of the invalid page count table represents a physical block address, and the content of the field represents an associated invalid page count. | 2010-05-06 |
20100115189 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. | 2010-05-06 |
20100115190 | SYSTEM AND METHOD FOR PROCESSING READ REQUEST - A system for processing a read request for maximizing host read performance in a flash memory-based storage device is provided. The system for processing the read request solves a bottleneck phenomenon caused by a processor by adding an independent automatic read request processor, different from a conventional system in which a processor of a storage device processes the read request. Also, when processing the read request, a storage device using a write buffer may control a process of merging data of the write buffer and a flash memory and transmitting the data to a host based on a descriptor array, thereby minimizing processor overhead. | 2010-05-06 |
20100115191 | System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices - A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy. | 2010-05-06 |
20100115192 | WEAR LEVELING METHOD FOR NON-VOLATILE MEMORY DEVICE HAVING SINGLE AND MULTI LEVEL MEMORY CELL BLOCKS - A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation. | 2010-05-06 |
20100115193 | SYSTEM AND METHOD FOR IMPROVING DATA INTEGRITY AND MEMORY PERFORMANCE USING NON-VOLATILE MEDIA - A system and computer system for improving data integrity and memory performance using non-volatile media. A system includes a non-volatile mass storage unit, e.g., a flash memory device and/or a hard drive unit for instance. A memory device is used as a high speed data buffer and/or cache for the non-volatile storage unit. The memory device may be non-volatile, e.g., magnetic random access memory (MRAM) or volatile memory, e.g., static dynamic random access memory (SDRAM). By buffering and/or caching the write data, fewer accesses are required to the mass storage device thereby increasing system performance. Additionally, mechanical and electrical degradation of the mass storage device is reduced. Certain trigger events can be programmed to cause data from the memory device to be written to the mass storage device. In one embodiment, the write buffer contents are preserved across reset or power loss events. In one embodiment, the mass storage unit may be a data transport layer, e.g., Ethernet, USB, Bluetooth, etc. | 2010-05-06 |
20100115194 | SEMICONDUCTOR MEMORY INFORMATION STORAGE APPARATUS AND METHOD OF CONTROLLING WRITING - A semiconductor memory information storage apparatus includes a storage unit using a nonvolatile memory, a write number manager counting each of numbers of times of writing of all blocks, a list manager classifying the blocks in the nonvolatile memory by in-use/unused, managing in an in-use list a block of the in-use, managing in a first unused list a block with the number of times of writing equal to a maximum value, and managing in a second unused list a block with the number of times of writing less than the maximum value, and a controller writing and erasing information data to and from the storage unit. | 2010-05-06 |
20100115195 | HARDWARE MEMORY LOCKS - Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a SOC unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM). | 2010-05-06 |
20100115196 | SHARED STORAGE FOR MULTI-THREADED ORDERED QUEUES IN AN INTERCONNECT - In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed. | 2010-05-06 |
20100115197 | METHODS AND STRUCTURE FOR LIMITING STORAGE DEVICE WRITE CACHING - Methods and structures for limiting the write portion of a local cache memory in one or more disk drives of a storage system such that a storage controller coupled to each may mirror the content and structure of the write portion of each disk drive. The size of the write portion of the local cache memory in a disk drive controller may be controlled by the storage controller or other host device. The size of the write portion may be controlled by switch settings to select among a plurality of predefined sizes or may be programmed by the storage controller or other host device. Programming such a size value may be by setting parameter values in a configuration page of a SCSI disk drive's local memory or may be by a vendor unique command sent by a host device to the disk drive. | 2010-05-06 |
20100115198 | System and method for loose coupling between raid volumes and drive groups - The present disclosure describes a system and method for allocating volume pieces across a redundant array of inexpensive discs (RAID). | 2010-05-06 |
20100115199 | DISK ARRAY APPARATUS AND CONTROL METHOD FOR DISK ARRAY APPARATUS - A disk array apparatus capable of effecting saving and operation of data through a simple construction. When a host computer sets “write inhibit” or “read/write inhibit” for an LDEV which is set on a first storage device, this setting is registered in an access attribute management table and is also reflected onto a migration management table. A migration control program moves the LDEV for which access limitation has been set to a lower-speed (lower-performance) second storage device or to an external storage device. When the access limitation is released, the moved LDEV is restored to the first storage device from the storage device to which the LDEV has been moved. By performing migration control in interlocking relation to control of access attributes, it is possible to obtain a simple data saving function and data management function. | 2010-05-06 |
20100115200 | METHOD FOR COMMUNICATION WITH A MULTI-FUNCTION MEMORY CARD - In the method for communication with a multi-function memory comprising a card controller and a functional module carrying out at least one data processing function which is different from the data storage function of a memory card, it is provided that, for initiating the at least one data processing function of the functional module, for communication with the functional module and for retrieval of data processed by the functional module corresponding to this data processing function, use is made of standardized write and read commands of the type used for addressing the data memory of a memory card. | 2010-05-06 |
20100115201 | AUTHENTICABLE USB STORAGE DEVICE AND METHOD THEREOF - An external storage device accessible to a host is proposed. The external storage device includes a memory device and a processing unit. The memory device includes a protected area for storing an authentication application, a public area for storing an unlock application, and a reserved area for storing authentication information. The processing unit is used for performing an identification request from the authentication application. When the authentication information is confirmed, the host is allowed to access the protected area of the external storage device, accordingly. | 2010-05-06 |
20100115202 | METHODS AND SYSTEMS FOR MICROCODE PATCHING - Methods and systems for performing microcode patching are presented. In one embodiment, a data processing system comprises a cache memory and a processor. The cache memory comprises a plurality of cache sections. The processor sequesters one or more cache sections of the cache memory and stores processor microcode therein. In one embodiment, the processor executes the microcode in the one or more cache sections. | 2010-05-06 |
20100115203 | MUTABLE OBJECT CACHING - In one embodiment, a method for caching mutable objects comprises adding to a cache a first cache entry that includes a first object and a first key. Assigning a unique identification to the first object. Adding an entry to an instance map for the first object. The entry includes the unique identification and the first object. Creating a data structure that represents the first object. The data structure includes information relevant to the current state of the first object. A second cache entry is then added to the cache. The second cache entry includes the data structure and the unique identification. Updating the first cache entry to replace the first object with the unique identification. | 2010-05-06 |
20100115204 | NON-UNIFORM CACHE ARCHITECTURE (NUCA) - In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory. | 2010-05-06 |
20100115205 | SYSTEM, METHOD, AND COMPUTER-READABLE MEDIUM FOR SPOOL CACHE MANAGEMENT - A system, method, and computer-readable medium that facilitate efficient use of cache memory in a massively parallel processing system are provided. A residency time of a data block to be stored in cache memory or a disk drive is estimated. A metric is calculated for the data block as a function of the residency time. The metric may further be calculated as a function of the data block size. One or more data blocks stored in cache memory are evaluated by comparing a respective metric of the one or more data blocks with the metric of the data block to be stored. A determination is then made to either store the data block on the disk drive or flush the one or more data blocks from the cache memory and store the data block in the cache memory. In this manner, the cache memory may be more efficiently utilized by storing smaller data blocks with lesser residency times by flushing larger data blocks with significant residency times from the cache memory. The disclosed cache management mechanisms are effective for many workloads and are adaptable to various database usage scenarios without requiring detailed studies of the particular data demographics and workload. | 2010-05-06 |
20100115206 | STORAGE DEVICE PREFETCH SYSTEM USING DIRECTED GRAPH CLUSTERS - A system analyzes access patterns in a storage system. Logic circuitry in the system identifies different address regions of contiguously accessed memory locations. A statistical record identifies a number of storage accesses to the different address regions and a historical record identifies previous address regions accessed prior to the address regions currently being accessed. The logic circuitry is then used to prefetch data from the different address regions according to the statistical record and the historical record. | 2010-05-06 |
20100115207 | METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS - An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data. | 2010-05-06 |
20100115208 | CONTROL I/O OFFLOAD IN A SPLIT-PATH STORAGE VIRTUALIZATION SYSTEM - Various embodiments of systems, methods, computer systems and computer software are disclosed for implementing a control I/O offload feature in a split-path storage virtualization system. One embodiment is a method for providing split-path storage services to a plurality of hosts via a storage area network. | 2010-05-06 |
20100115209 | METHODS AND APPARATUS FOR DETECTING A SYNCMARK IN A HARD DISK DRIVE - Methods and apparatus are provided for detecting a syncMark in a read channel, such as a hard disk drive. A syncMark is detected in a sector in an iterative read channel by obtaining a sector signal from a storage media, the sector signal comprising a first syncMark, data and a second syncMark substantially at an end of the sector; determining whether the first syncMark is detected in the sector signal; searching for the second syncMark if the first syncMark is not detected in the sector signal; and detecting and decoding the sector signal based on a detection of the second syncMark. The second syncMark may be positioned, for example, following data in the sector signal. The second syncMark can be searched for in a window within the signal sector that is based on an estimated location of the first syncMark. | 2010-05-06 |
20100115210 | METHOD AND APPARATUS FOR EXPANDING A VIRTUAL STORAGE DEVICE - The present invention provides for the expansion of a virtual storage device. Expansion of the virtual storage device includes adding one or more additional storage device units to an existing virtual storage device. Blocks or strips included in an added storage device unit are assigned addresses, to allow the added storage capacity to be accessed immediately. In order to reestablish a pattern of data storage addresses from the original storage device units of the pre-expanded virtual storage device across all of the storage device units of the post-expanded virtual storage device, temporary storage is provided. In particular, as a strip of data is relocated to its proper post-expand location, the data occupying that location is placed in a temporary storage buffer. Data in the temporary storage buffer is then written to the proper post-expand location for that data, with displaced data being written to a second temporary storage buffer. | 2010-05-06 |
20100115211 | BEHAVIORAL MONITORING OF STORAGE ACCESS PATTERNS - A storage control system monitors storage operations directed to storage blocks in a storage device. The storage control system uses arrays of counters to track a number of the storage operations, sizes of the storage operations, types of transitions between the storage operations, and time durations between different types of successive storage operations. The storage blocks are classified into different behavioral groups based on the access pattern history of the individual blocks. The behavioral group classifications are then used by the storage control system to determine when to access the storage blocks from the storage device, when to load the storage blocks into a tiering media, or when to time out the storage blocks from the tiering media. | 2010-05-06 |
20100115212 | MEMORY ACCESS APPARATUS - A memory access apparatus is provided with a processor, an I/F circuit, and a memory control circuit. The processor is provided with an access-request generating circuit which issues a memory access request. The I/F circuit is provided with an F/F circuit which holds the memory access request outputted from the processor in response to a clock signal. The memory control circuit is provided with an access processing circuit which executes an access process that complies with the memory access request held by the F/F circuit. | 2010-05-06 |
20100115213 | MEMORY APPARATUS AND MEMORY MANAGEMENT METHOD OF THE SAME - A method of memory management for an apparatus having a non-volatile memory and a volatile memory includes the steps of forming a tree structure of entries in the volatile memory, in which the tree structure has a left branch and a right branch, and a difference of heights of the left branch and the right branch is equal to or less than one; and accessing an entry in the volatile memory through the tree structure. | 2010-05-06 |
20100115214 | BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks. | 2010-05-06 |
20100115215 | Recovering From a Backup Copy of Data in a Multi-Site Storage System - To make available a backup copy of source data in a multi-site storage system, the source data is provided at a first storage site and an operational copy of the source data is provided at a second storage site. In response to a request to create a backup copy of the source data, the backup copy of the source data is produced at each of the first and second storage sites. In response to failure that causes the first storage site to be unavailable, recovery of a version of the source data is enabled based on accessing the backup copy of the source data at the second storage site, and accessing the operational copy of the source data at the second storage site. | 2010-05-06 |
20100115216 | DATA ALLOCATION AND REPLICATION ACROSS DISTRIBUTED STORAGE SYSTEM - In a distributed storage system such as those in a data center or web based service, user characteristics and characteristics of the hardware such as storage size and storage throughput impact the capacity and performance of the system. In such systems, an allocation is a mapping from the user to the physical storage devices where data/information pertaining to the user will be stored. Policies regarding quality of service and reliability including replication of user data/information may be provided by the entity managing the system. A policy may define an objective function which quantifies the value of a given allocation. Maximizing the value of the allocation will optimize the objective function. This optimization may include the dynamics in terms of changes in patterns of user characteristics and the cost of moving data/information between the physical devices to satisfy a particular allocation. | 2010-05-06 |
20100115217 | DATA MIRRORING IN SERIAL-CONNECTED MEMORY SYSTEM - A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems. | 2010-05-06 |
20100115218 | MAINTAINING STORAGE DEVICE BACKUP CONSISTENCY - A method, system, and computer program product are provided for maintaining a storage device backup consistency group. The method comprises receiving a first I/O command for a first storage device, receiving a second I/O command for a second storage device, identifying a transaction comprising both the first I/O command and the second I/O command, accessing a storage device backup consistency group for the first storage device, determining whether a backup for the second storage device is a member of the storage device backup consistency group, and performing a predefined corrective action if a backup for the second storage device is not a member of the storage device backup consistency group. The predefined corrective action may comprise detecting or creating a backup for the second storage device and then adding the detected or created backup to the storage device backup consistency group, invalidating the second I/O command, and/or issuing a warning. | 2010-05-06 |
20100115219 | STORAGE SECTION CONTROLLING APPARATUS, STORAGE SECTION CONTROLLING SYSTEM AND COMPUTER-READABLE RECORDING MEDIUM ON OR IN WHICH STORAGE SECTION CONTROLLING PROGRAM IS RECORDED - A storage section controlling apparatus includes a queuing section adapted to retain a processing order of write requests and readout requests from a data processing apparatus to plural storage sections to, and a processing order controlling section adapted to change, where a readout request for a target region of a duplexing process of a second storage section of the plural storage sections by a duplexing controlling section is issued from the data processing apparatus and a write request for a target region of at least one first storage section of the plural storage sections of a copying source corresponding to the target region of the readout request exists later than a processing turn of the readout request in a processing order in the queuing section, the processing turn of the readout request in the processing order so as to be later than the writing request in the processing order. | 2010-05-06 |
20100115220 | COMPUTING SYSTEM INCLUDING MEMORY AND PROCESSOR - A computing system includes; a memory having first and second storage areas, and a processor sending a memory control signal to the memory to define a data access period during which data is accessed, and a read source control signal indicating whether the first storage area or the second storage area is to be accessed during the data access period. The memory activates a wait signal in response to the memory access signal and the read source control signal, and the processor is further configured to adjust the duration of the data access period in response to the wait signal. | 2010-05-06 |
20100115221 | SYSTEM AND METHOD FOR PROCESSOR WITH PREDICTIVE MEMORY RETRIEVAL ASSIST - A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance. | 2010-05-06 |
20100115222 | HIERARCHICAL STORAGE SYSTEM - Pools of a plurality of types of storage devices are configured and are included in different layers. Based on at least one storage device of the same type, the pools of types corresponding to the type are configured. The controller in the storage system carries out storage location change processing in which the storage location of targeted data that has been stored into the targeted first real page allocated to a virtual page in a virtual volume is changed to the second real page that has not been allocated in a pool of the second type different from a pool of the first type including the targeted first real page in the case in which the controller conforms to the prescribed storage location change conditions. A size of a real page is different depending on a type of a pool. | 2010-05-06 |
20100115223 | Storage Area Allocation Method and a Management Server - An object is to allocate a storage area to a business application by taking a security evaluation of the storage area and a security evaluation value of the business application into consideration. A management server includes a business management table to store a calculated security evaluation value of a business application to be executed in a host in association with information concerning the business application, and a management table to store a calculated encryption level of a virtual pool in a storage device in association with information concerning the virtual pool. The management server retrieves a virtual pool having an encryption level which is the same in value as the evaluation value, and allocates the retrieved virtual pool to the business application. | 2010-05-06 |
20100115224 | MEMORY APPARATUSES WITH LOW SUPPLY VOLTAGES - Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation. | 2010-05-06 |
20100115225 | Memory Device and Memory System Including the Same - Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed. | 2010-05-06 |
20100115226 | Memory Management System - This memory management system has: (a) a logical partition management unit that manages allocation and release of a virtual memory used by an application in a logical address space; (b) a physical partition management unit that manages allocation and release of small size parts into which a physical memory is divided in a physical address space; and (c) a converter unit that converts an address between the logical address space and the physical address space. | 2010-05-06 |
20100115227 | PARALLEL PRUNED BIT-REVERSAL INTERLEAVER - A parallel lookahead pruned bit-reversal interleaver algorithm and architecture have been proposed. The algorithm interleaves a packet of length N in at most log(N)−1 steps compared to N steps using existing sequential algorithms, and has a simple architecture amenable for high-speed applications. The proposed algorithm is valuable for emerging wireless standards especially those that employ PBRI channel (de-)interleavers on long packets in reducing interleaving latency on the transmitter side and deinterleaving latency on the receiver side. | 2010-05-06 |