18th week of 2011 patent applcation highlights part 74 |
Patent application number | Title | Published |
20110106992 | APPARATUS AND METHOD FOR SCALING DYNAMIC BUS CLOCK - An apparatus and a method for scaling a dynamic bus clock are provided. The apparatus for scaling the dynamic bus clock includes at least one master module, at least one slave module, a bus for delivering data transmitted and received by the at least one master module and the at least one slave module, a bus frequency controller for determining a bus clock frequency by considering activity information of the at least one master module, and a clock generator for generating the frequency as determined by the bus frequency controller and providing the generated frequency to the at least one master module, the at least one slave module, and the bus. | 2011-05-05 |
20110106993 | VIRTUAL MACHINE CONTROL DEVICE, VIRTUAL MACHINE CONTROL PROGRAM, AND VIRTUAL MACHINE CONTROL CIRCUIT - The interrupt level storing unit ( | 2011-05-05 |
20110106994 | METHOD AND APPARATUS FOR QUALIFYING COLLECTION OF PERFORMANCE MONITORING EVENTS BY TYPES OF INTERRUPT WHEN INTERRUPT OCCURS - A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit. | 2011-05-05 |
20110106995 | DATA PROCESSING SYSTEM AND METHOD OF INTERRUPT HANDLING - A data processing system is provided which comprises at least two processing units ( | 2011-05-05 |
20110106996 | COMMUNICATIONS CONTROL BUS AND APPARATUS FOR CONTROLLING MULTIPLE ELECTRONIC HARDWARE DEVICES - Disclosed is a communications control bus. The bus comprises an IMB slave CPU, at least two registers, and a three bit data connector, which connects the two registers. The connector permits transmission of a three bit data signal between the two registers. A network interconnects the two registers and the IMB slave CPU. | 2011-05-05 |
20110106997 | METHODS AND APPARATUS FOR INTERCONNECTING SAS/SATA DEVICES USING EITHER ELECTRICAL OR OPTICAL TRANSCEIVERS - Methods and apparatus for interconnecting Serial Attached SCSI (SAS) or Serial Advanced Technology Attachment (SATA) devices using either an electrical communication medium or an optical communication medium. Each device includes an out of band (OOB) encoder/decoder (endec) logic component to translate between standard OOB signals used by the devices and digitally encoded OOB signals exchanged over the communication medium. Thus the devices may be coupled using either optical or electrical cabling. The digitally encoded OOB signals may also be scrambled to reduce electromagnetic interference (EMI) generated during OOB communications using the digitally encoded OOB signals. The scrambled digitally encoded OOB signals may comprise information regarding capabilities of the device that generated the underlying OOB signal. Such information may indicate to the other high speed device certain capabilities of the transmitting device—the information to be used in establishing logical connections between devices. | 2011-05-05 |
20110106998 | Storage Router and Method for Providing Virtual Local Storage - A storage router and method for providing virtual local storage on remote storage devices to devices are provided. A plurality of devices, such as workstations, are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and receives and processes native low level block protocol requests from the devices connected to the first transport medium to access allocated storage. | 2011-05-05 |
20110106999 | ON-CHIP BUS - This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus. | 2011-05-05 |
20110107000 | VOLTAGE INDICATOR SIGNAL GENERATION SYSTEM AND METHOD - The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal. | 2011-05-05 |
20110107001 | Performing data operations using non-volatile third dimension memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 2011-05-05 |
20110107002 | SAS Expander-Based SAS/SATA Bridging - Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process. | 2011-05-05 |
20110107003 | REMOTE USB SYSTEM FOR SUPPORTING MULTIPLE VIRTUAL MACHINES OF MULTIPLE HOST AND METHOD THEREOF - There is a master server according to an embodiment of the present invention that includes: a remote USB information manager receiving information on a USB device connected to a remote USB bridge from the remote USB bridge and managing the received information; a virtual machine information manager receiving information of a user's virtual machine from a virtual machine host server and managing the received information; a user request processor, in accordance with a request of a user who wants to access a predetermined USB device on the remote USB bridge, extracting information on the corresponding USB device from the remote USB information manager and extracting the information on the user's virtual machine from the virtual machine information manager; and a remote USB connection controller connecting the user's virtual machine to the predetermined USB device by using the information extracted by the user request processor. | 2011-05-05 |
20110107004 | Network Switch - A system and method for electronically transferring data between servers in a Local Area Network (LAN) requires a Network switch. Essentially, the Network switch incorporates a PCI Express switch that is run by a Central Processing Unit (CPU). A plurality of connectors (i.e. one for each server in the system) is provided to directly connect the PCI Express capability of the respective server to the PCI Express switch. With these connections, the CPU is used to implement an Internet Protocol (IP) routing function in compliance with IP addresses provided by respective servers to route data through the system from one server to another. | 2011-05-05 |
20110107005 | SEMICONDUCTOR DEVICE - A renewal of an internal address generated by an internal address generator that is used for a refresh operation of information in a memory unit including a plurality of memory cells is preformed during a refresh operation before an activated word line connected to the memory cell corresponding to the internal address is inactivated in the refresh operation. | 2011-05-05 |
20110107006 | Multiprocessor system and method thereof - A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port. | 2011-05-05 |
20110107007 | ASYNCHRONOUS PAGE FAULTS FOR VIRTUAL MACHINES - A method and system to handle an asynchronous page fault in a virtual machine system. A computer hosts a virtual machine that includes a virtual central processing unit (CPU). The virtual CPU requests access to a page that is not resident in memory. The host operating system of the computer receives an indication of a page fault, and informs the virtual CPU of the page fault. The host operating system provides an identifier associated with the page fault. The host operating system performs page swapping operating in parallel with a new task rescheduled by the virtual CPU, and sends a wake-up signal to the virtual CPU when the page has been brought back into the memory. | 2011-05-05 |
20110107008 | MEMORY MANAGEMENT IN A NESTED VIRTUALIZATION ENVIROMENT - A method for managing memory in a nested virtualization environment is provided. The method comprises implementing a first virtual machine (VM) for a first software such that a first guest memory is allocated to the first software; maintaining a first data structure to translate one or more memory addresses in the first guest memory to corresponding memory addresses in a physical memory; maintaining a second data structure to translate one or more memory addresses in the second guest memory to corresponding memory addresses in the physical memory. The first software implements a second VM for a second software such that a second guest memory is allocated to the second software and maintains a third data structure to translate one or more memory addresses in the second guest memory to corresponding memory addresses in the first guest memory. | 2011-05-05 |
20110107009 | NON-VOLATILE MEMORY CONTROLLER DEVICE AND METHOD THEREFOR - A method of storing information at a non-volatile memory includes storing a status bit prior to storing data at the memory. A second status bit is stored after storing of the data. Because the storage of data is interleaved with the storage of the status bits, a brownout or other corrupting event during storage of the data will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly stored at the non-volatile memory. | 2011-05-05 |
20110107010 | ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF - A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location. | 2011-05-05 |
20110107011 | DATA DEFRAGMENTATION OF SOLID-STATE MEMORY - A method and apparatus for improving the performance of a computer system having a solid-state (flash) memory device as the main system memory. After weeks or months of frequent use, solid-state memories can become badly fragmented, and although every memory cell has basically the same access time to retrieve or to write data from or into that cell, vendors have found that self-defragging utilities within the memory device often improves overall performance. Yet if such defragging utilities are automatically run when other applications are running simultaneously, the drain on system performance can be very detrimental. To avoid the occurrence of unwanted self-defragging of these solid-state memory devices, we inhibit under some circumstances such functionality until it is deemed safe to do so. | 2011-05-05 |
20110107012 | NON-VOLATILE SEMICONDUCTOR MEMORY COMPRISING POWER FAIL CIRCUITRY FOR FLUSHING WRITE DATA IN RESPONSE TO A POWER FAIL SIGNAL - A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment. | 2011-05-05 |
20110107013 | High Throughput Flash Memory System - There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area. | 2011-05-05 |
20110107014 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 2011-05-05 |
20110107015 | DATA WRITING METHOD FOR A FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip having a plurality of physical blocks is provided. The method includes configuring a plurality of logical access addresses and recording address centers and address radiuses for the physical blocks. The method also includes receiving data to be written in logical access addresses, determining opened physical blocks among the physical blocks, and writing the data into the flash memory chip based on the logical access addresses, and the address centers and the address radiuses of the opened physical blocks. Accordingly, the method can effectively reduce the degree of data dispersion of each of the physical blocks, reduce the time for organizing valid data, and increase the speed for writing data. | 2011-05-05 |
20110107016 | SOLID STATE STORAGE SYSTEMS AND METHODS FOR FLEXIBLY CONTROLLING WEAR LEVELING - Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements. | 2011-05-05 |
20110107017 | Storage Apparatus and Data Access Method Thereof - A storage apparatus includes a first data section, a second data section, and a common data section. The first data section stores first data, the second data section stores second data, and the common data section stores common data. The storage apparatus stores a single copy of the common data. The common data and the first data correspond to a first memory bank. The common data and the second data correspond to a second memory bank. | 2011-05-05 |
20110107018 | PLURAL-PARTITIONED TYPE NONVOLATILE STORAGE DEVICE AND SYSTEM - A plural-partitioned type nonvolatile storage device which solves the problem that a memory card composed of a flash memory and a controller, when a storage area is divided into a plurality of partitions, cannot be correctly used with a conventional host apparatus incapable of recognizing plural partitions. The memory card includes, as its storage areas, a device characteristic data storage area, a division table storage area, and a device storage area, where the device storage area is partitioned into plural partitions. The memory card can have different, modes for adapting different accesses from the external host, and allows the external host to access partitions corresponding to the mode. Division information as to a dividing method for the plural partitions, and access information as to the host-accessible partitions corresponding to each individual mode are stored in the division table storage area. Plural types of device characteristic data corresponding to mode, respectively, are stored in the device characteristic data storage area. | 2011-05-05 |
20110107019 | APP (A PRIORI PROBABILITY) STORAGE DESIGN FOR LTE TURBO DECODER WITH QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER - Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention. | 2011-05-05 |
20110107020 | HIBERNATION SOLUTION FOR EMBEDDED DEVICES AND SYSTEMS - An embedded device is hibernated by storing state data of the embedded device to a non-volatile data storage medium, and powering off the embedded device. The embedded device is later woken up in response to the detection of a wakeup event from a wakeup source. The state data stored in the RAM of the embedded device comprises data in one or more registers of a Central Processing Unit (CPU) of the embedded device, one or more registers of a system-on-chip (SOC) of the embedded device, and the system and applications code and data. Waking the embedded device comprises loading, from the non-volatile data storage medium, initial memory sections that are used to run a kernel of the embedded device. State data that is stored in the RAM of a system may be compressed by dividing the RAM into a plurality of sections and independently choosing, for each section in the plurality of sections, a corresponding compression arithmetic. | 2011-05-05 |
20110107021 | Column Oriented In-Memory Page Caching - A one-dimensional array is allocated in an in-memory cache for each column in a set of tabular data. The data type of each one-dimensional array is set to be the same as the data type of the corresponding column in the tabular data. Once the one-dimensional arrays have been allocated in memory, a portion of the data from each column in the tabular data is stored in a corresponding one-dimensional array. The tabular data stored in the one-dimensional arrays in the cache may then be utilized to generate an on-screen display of a portion of the tabular data. | 2011-05-05 |
20110107022 | REDUCING POWER CONSUMPTION FOR DYNAMIC MEMORIES USING DISTRIBUTED REFRESH CONTROL - A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory. | 2011-05-05 |
20110107023 | Automatically Linking Partitions on a Tape Media Device - A system and method for automatically linking partitions on storage media for use within a storage management system is provided to minimize wasted space on the storage media, the time and expense traditionally spent reclaiming partitions containing invalid data, and the computer processing capability required to write data to and read data from the storage media. The storage management system includes a partitioned storage tape, a host application running on a server, and an archive device. The host application is operative to track location information for each host file or data object written to the storage tape. Using the location information, the host application is able to identify one or more “free” or writable partitions that are created on the storage tape as host files expire. Moreover, when writing host files to the storage tape, the archive device is operative to automatically link the writable partitions to form logical volumes such that when reading host files from the storage tape, the archive device can automatically navigate through the logical volumes. | 2011-05-05 |
20110107024 | EXTENDED LOGICAL WORM DATA INTEGRITY PROTECTION - A data storage system stores logical data object(s), each identified by a logical identifier. A control is configured to assign a unique WORM (Write Once Read Many) identifier to the logical data object, and stores the unique WORM identifier as associated with the logical identifier, in a database maintained by the control so as to be persistent. Data storage is configured to write the logical data object with a header with the unique WORM identifier. The control, in order to allow the logical data object to be accessed externally to the control, requires matching the unique WORM identifier in the header of a logical data object to the unique WORM identifier of the persistent database for the logical object. The unique WORM identifier is formed of a checksum hash value related to nonce fields comprising at least the logical identifier of the logical data object, an incrementing token, and a time stamp. | 2011-05-05 |
20110107025 | SYNCHRONIZING SNAPSHOT VOLUMES ACROSS HOSTS - Prior to overwriting a block of data in a first volume of data on a primary host, the block of data is written to a first snapshot of the first volume. Subsequently, the first snapshot can be synchronized with a snapshot of a second volume of data on a secondary host, where the second volume is a replica of the first volume. To synchronize the snapshots, only a portion of the first snapshot (e.g., the block of data that was written to the first snapshot) is sent to the secondary host. | 2011-05-05 |
20110107026 | CONCURRENT SET STORAGE IN DISTRIBUTED STORAGE NETWORK - For each original data segment, a distributed storage processing unit generates encoded slices designed to prevent the original data segment from being reconstructed using fewer than a threshold number of encoded slices. Multiple encoded slices are generated for each of two different data segments, and the slices associated with the first and second data segment are stored substantially concurrently in different storage sets employing different distributed storage units. Encoded slices for even and odd data segments can be stored in different storage sets, or longer sequences of data segments can be stored in alternating storage sets. Storage sets can also be determined by the vault generation of a particular data segment. | 2011-05-05 |
20110107027 | INDIRECT STORAGE OF DATA IN A DISPERSED STORAGE SYSTEM - A method begins by a dispersed storage processing module obtaining data for storage. The method continues with the dispersed storage processing module encoding the data in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the dispersed storage processing module determining a proxy unit. The method continues with the dispersed storage processing module transmitting the plurality of sets of encoded data slices to the proxy unit, wherein the proxy unit disperses the plurality of sets of encoded data slices to a plurality of dispersed storage units. | 2011-05-05 |
20110107028 | Dynamically Expanding Storage Capacity of a Storage Volume - A storage system includes at least one storage device on which are provided data storage volumes and an extended storage volume. The data storage volumes include a first data storage volume that is implemented with a data protection mechanism, and a second data storage volume that is implemented without the data protection mechanism. Also, an extended storage volume is provided that is initially un-allocated to any of the data storage volumes. A controller dynamically allocates at least one portion of the extended storage volume to the particular data storage volume to dynamically expand storage capacity of the particular data storage volume. | 2011-05-05 |
20110107029 | STORAGE SUBSYSTEM THAT CONNECTS FIBRE CHANNEL AND SUPPORTS ONLINE BACKUP - The storage system includes first and second disk arrays. The first disk array has a first port coupled to a second port of the second disk array, a port controller controlling the first port, a plurality of disk devices to store data, and a controller managing a plurality of logical units on the plurality of disk drives. The first port controller controls the first port so as to execute, in a time-sharing manner, data transfer corresponding to a initiator task and data transfer corresponding to a target task. The initiator task is generated to execute the data transfer from a first logical unit on the plurality of disk drives of the first disk array to a second logical unit on a plurality of disk drives of the second disk array. The target task is generated to execute the data transfer to receive data from the second disk array. | 2011-05-05 |
20110107030 | SELF-ORGANIZING METHODOLOGY FOR CACHE COOPERATION IN VIDEO DISTRIBUTION NETWORKS - A content distribution network (CDN) comprising content storage nodes (CSNs) or caches having storage space that preferentially stores more popular content objects. | 2011-05-05 |
20110107031 | Extended Cache Capacity - A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores. | 2011-05-05 |
20110107032 | CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT - A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc. | 2011-05-05 |
20110107033 | METHOD AND APPARATUS FOR PROVIDING AN APPLICATION-LEVEL CACHE - An approach is provided for providing an application-level cache. A caching application configures at least one memory of a mobile terminal into an application-level cache with a locked region and a floating region. The caching application then causes, at least in part, actions that result in caching, into each of the locked region and the floating region, of data items that are anticipated to be requested via an application of the mobile terminal. | 2011-05-05 |
20110107034 | CACHE DEVICE - A cache device comprises: data memory that includes a plurality of ways for storing a part of data of a main memory; tag memory that includes a plurality of ways, each of which is for storing tag contained in address of data recorded in each way of the data memory; comparison circuit that decides whether tag contained in address to be accessed agrees with the tag recorded in the tag memory or not; next address generation circuit that calculates address to be accessed next time as second address by referring to first address to be accessed at present time; and tag reading control circuit that pre-reads tag corresponding to index of the second address from the tag memory and ceases to read tags hereafter from the tag memory in a case where the tag contained in the second address agrees with the pre-read tag. | 2011-05-05 |
20110107035 | CROSS-LOGICAL ENTITY ACCELERATORS - A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time. | 2011-05-05 |
20110107036 | DISTRIBUTED STORAGE REVISION ROLLBACKS - Multiple revisions of an encoded data slice can be stored in a distributed storage unit. Before writing a new revision of an encoded data slice to storage, the distributed storage unit can invoke a write lock for all encoded data slices having the same slice name as the slice being currently written. The slice being currently written can be stored in temporary storage, and a rollback timer started. If a commit command is received before expiration of the rollback timer, the currently written slice can be permanently stored and made accessible for read requests. If the rollback timer expires prior to the storage unit receiving a commit command, however, a previously stored revision will be used. | 2011-05-05 |
20110107037 | Information Processing Apparatus and Memory Control Method - According to one embodiment, an information processing apparatus includes memory modules, a measuring module, a determination module, and a controller. The measuring module initializes the memory modules when the apparatus has been booted and an operating system of the information processing apparatus has not yet been started, measures a temperature of the memory modules at a time of the initialization, and measures a maximum temperature of each of the memory modules when the operating system is running. The determination module determines a first memory module, which has the least difference between the temperature at the time of the initialization and the maximum temperature at the time when the operating system is running, and a second memory module which has the lowest temperature at the time of the initialization. The controller maps memory addresses allocated to the first memory module in the second memory module, based on the temperatures. | 2011-05-05 |
20110107038 | MEMORY MANAGEMENT PROGRAM AND APPARATUS - A memory management apparatus includes: a memory space including a memory area serving as a heap area and a non-heap-area memory area; and memory management unit which add a header for an object to a memory area other than heap-area to treat the non-heap-area memory area as a mock object in order to treat a plurality of heap areas divided by the non-heap-area memory area as a single continuous heap area. | 2011-05-05 |
20110107039 | METHODS FOR IMPLEMENTATION OF DATA FORMATS ON A REMOVABLE DISK DRIVE STORAGE SYSTEM - An archiving system including one or more removable disk drives embedded in removable disk cartridges, referred to simply as removable disk drives. The removable disk drives allow for expandability and replacement such that the archiving system need not be duplicated to add new or more storage capacity. In embodiments, the removable disk drives store metadata that contain information about the data stored on the removable disk drive. The metadata allows the system to retrieve the correct data from the random access memory and establishes controls on the data stored on the removable disk drive. In embodiments, the metadata is stored in two locations, such that, if the metadata in one location is corrupted, the second copy of the metadata may be retrieved. | 2011-05-05 |
20110107040 | Adaptable External Drive - In one embodiment a network attached storage device comprises a detection module to detect, in the network attached storage device, the connection of an external storage media to the network attached storage device, a format module to initiate, in the network attached storage device, a format utility, and configure the external storage media with at least a primary partition and a secondary partition. | 2011-05-05 |
20110107041 | METHOD FOR EXECUTING DATA UPDATES IN AN IC CARD - A method is for executing n data updates in an IC Card which has memory pages supporting m erase operations per page, with m2011-05-05 | |
20110107042 | FORMATTING DATA STORAGE ACCORDING TO DATA CLASSIFICATION - A set of data can be classified into a data level of multiple possible data levels. Additionally, an indicator of the data level for the set of data can be transmitted to a storage device. In response to receiving the indicator, a storage area in the device can be formatted to store data at a storage quality level. The set of data can be stored in the storage area at the storage quality level. | 2011-05-05 |
20110107043 | SELF LEARNING BACKUP AND RECOVERY MANAGEMENT SYSTEM - A system and method provide for a reception of data at a computer processor. The data relates to a dataset in a computer system. The computer processor calculates a weight for the dataset as a function of the data, and the processor executes an action on the dataset as a function of the weight. In an embodiment, the action is a backup of data on the computer system, and through recalculation of the weight over a period of time, the backup schedule, backup media, and other parameters are altered based on the changing weight for a dataset. | 2011-05-05 |
20110107044 | MEMORY MIGRATION - A source system comprises memory and a processor executing code to cause at least some of the memory to be migrated over a network to a target system. The processor causes the memory to be migrated by migrating some of the memory while a guest continues to write the memory, halts execution of the guest, and completes a remainder of the memory migration. | 2011-05-05 |
20110107045 | HYBRID STORAGE DATA MIGRATION BY SELECTIVE DATA REMOVAL - A hybrid data storage system is one which has data storage clusters of different types. In a hybrid data storage system, at least one first data storage cluster is configured to store data and has high data storage capacity; and at least one second data storage cluster is configured to store data and has lower data storage capacity than the first cluster. The data is initially replicated and stored by at least one first and at least one second data storage cluster. The method identifies a portion of the stored initially replicated data of at least one second data storage cluster as “pinned”; continues to store the pinned initially replicated data; and selectively removes non-pinned initially replicated data from the second data storage cluster(s) to account for the capacity difference. | 2011-05-05 |
20110107046 | BINARY-LEVEL UPDATE OF COMPRESSED READ-ONLY FILE SYSTEMS - A method and computer-readable memory device that enable processing of a first memory image comprising a plurality of compressed sub-blocks and uncompressed sub-blocks to produce a second memory image comprising contents of the first memory image arranged as a plurality of memory blocks. The memory blocks of the second memory image may be independently decompressible, to enable more efficient updating of an electronic device. | 2011-05-05 |
20110107047 | Enforcing a File Protection Policy by a Storage Device - A file attribute, which is called herein “enforcement bit”, is used for each file that is stored in a storage device. If the protection particulars associated with a stored file are allowed to be changed, the enforcement bit is set to a first value, and if the protection particulars or properties are not to be changed, the enforcement bit is set to a second value. When the storage device is connected to a host device, the storage device provides to the host device protection particulars and an enforcement bit, which collectively form a “file protection policy”, for each stored file in response to a file system read command that the host device issues, in order to notify the host device of files in the storage device whose protection particulars are allowed to be changed freely, and of files whose protection particulars are not allowed to be changed by unauthorized users or devices. | 2011-05-05 |
20110107048 | Importing Media Content Items - Systems and techniques are disclosed for allowing a user to view and edit media content items while those media content items are being transferred from one location to another. For example, a method can include receiving a request to transfer a media content from a source memory location where the media content item resides to a destination memory location; reading from the source memory location a sufficient amount of data to create in a database associated with the application a first record corresponding to the media content item to be transferred, the first record including a pointer to the source memory location of the media content item; initiating a transfer of the media content item to the destination memory location, and making the media content item available for manipulation prior to completion of the transfer of the first media content item. | 2011-05-05 |
20110107049 | METHOD AND APPARATUS ADAPTED TO PREVENT CODE DATA FROM BEING LOST IN SOLDER REFLOW - A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted. | 2011-05-05 |
20110107050 | ADAPTIVE TRIGGERING OF GARBAGE COLLECTION - Methods and apparatus are provided for adaptively triggering garbage collection. During relatively steady or decreasing rates of allocation of free memory, a threshold for triggering garbage collection is dynamically and adaptively determined on the basis of memory drops (i.e., decreases in free memory) during garbage collection. If a significant increase in the rate of allocation of memory is observed (e.g., two consecutive measurements that exceed a mean rate plus two standard deviations), the threshold is modified based on a memory drop previously observed in conjunction with the current memory allocation rate, or a memory drop estimated to be possible for the current allocation rate. | 2011-05-05 |
20110107051 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND METHOD OF CONTROLLING THE SAME - Various embodiments of a semiconductor system, a semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory is selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory. | 2011-05-05 |
20110107052 | Virtual Disk Mapping - A storage area network can include a storage virtualization entity—intelligent storage application resource (iSAR)—either as a separate device in the fabric, or as an integrated module in one or more switches within the fabric. All I/O operations can be re-directed to iSAR for processing. iSAR can segment virtual storage and physical storage into units, where each unit of the virtual storage is mapped to a single unit in physical storage. Data associated with incoming I/O operation can be compressed before being stored in physical storage. iSAR includes overflow reserve storage at the block, sub-page and page level to accommodate changes in compressed data size on subsequent I/O operations. These measures can improve I/O performance and reduce fragmentation. iSAR can also employ deduplication of incoming data stored on physical storage to improve storage efficiency. | 2011-05-05 |
20110107053 | Allocating Storage Memory Based on Future Use Estimates - A method for allocating storage memory space is provided. The method involves receiving a request for storage memory allocation for a file of a current size; estimating a future size of the file, different than the current size of the file, based at least on a particular attribute associated with the file; and causing allocation of storage memory space for storage of the file based on the future size of the file. | 2011-05-05 |
20110107054 | EXPANDING MEMORY SIZE - A method, system, and computer usable program product for expanding memory size are provided in the illustrative embodiments. A desired size of an expanded memory and a first information about a workload in the data processing system are received. A size of a compressed memory pool to use with the memory to make the desired size of the expanded memory available is computed. A representation of the memory is configured, the representation of the memory appearing to be of a size larger than the size of the memory, the representation of the memory being the expanded memory, and the size of the representation being the size of the expanded memory. The expanded memory is made available such that the memory in the data processing system is usable by addressing the expanded memory. | 2011-05-05 |
20110107055 | Diagonally accessed memory array circuit - A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether. | 2011-05-05 |
20110107056 | METHOD FOR DETERMINING DATA CORRELATION AND A DATA PROCESSING METHOD FOR A MEMORY - A method for determining data correlation and a data processing method for a memory are disclosed. The data with correlation is collected and stored in the same block. Also the data with correlation is determined based on a specific function to be executed by the user. In other words, if the user needs to access some data in order to perform the specific function, those data has correlation. | 2011-05-05 |
20110107057 | ADDRESS TRANSLATION UNIT WITH MULTIPLE VIRTUAL QUEUES - An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier. | 2011-05-05 |
20110107058 | PROCESSOR MEMORY SYSTEM - A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory. | 2011-05-05 |
20110107059 | MULTILAYER PARALLEL PROCESSING APPARATUS AND METHOD - A multilayer parallel processing apparatus. The multilayer parallel processing apparatus includes two or more hierarchical parallel processing units, each configured to process flow data corresponding to a hierarchy that is allocated thereto in response to inputting pieces of flow data configured with two or more hierarchies, and a common database configured to be accessed by the two or more hierarchical parallel processing units and store processing results of each of the hierarchical parallel processing units. | 2011-05-05 |
20110107060 | TRANSPOSING ARRAY DATA ON SIMD MULTI-CORE PROCESSOR ARCHITECTURES - Systems, methods and articles of manufacture are disclosed for transposing array data on a SIMD multi-core processor architecture. A matrix in a SIMD format may be received. The matrix may comprise a SIMD conversion of a matrix M in a conventional data format. A mapping may be defined from each element of the matrix to an element of a SIMD conversion of a transpose of matrix M. A SIMD-transposed matrix T may be generated based on matrix M and the defined mapping. A row-wise algorithm may be applied to T, without modification, to operate on columns of matrix M. | 2011-05-05 |
20110107061 | Performance of first and second macros while data is moving through hardware pipeline - A hardware pipeline has a number of rows including a first row, a last row, and an intermediate row between the first row and the last row. Each row stores a number of bytes of data as the data moves through the pipeline on a row-by-row basis from the first row towards the last row. A mechanism performs a first macro on the data beginning at the first row. The mechanism performs a second macro different than the first macro on the data beginning at the intermediate row where the first macro has been completely performed when the data has reached the intermediate row. The first and second macros each include a number of modifications of the data as the data moves through the pipeline to effect a complete transformation of the data. The complete transformation of the first macro is different than the complete transformation of the second data. | 2011-05-05 |
20110107062 | Interrupt Handling - Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another. | 2011-05-05 |
20110107063 | VECTOR PROCESSING APPARATUS AND METHOD - There is provided a vector processing apparatus and method allowing for the parallel processing of a plurality of different instructions while maintaining vector processing architecture. The vector processing apparatus includes an instruction memory storing a multiple instruction group including one or more instructions; an instruction fetch unit reading the multiple instruction group from the instruction memory; and a plurality of instruction processing units each receiving the multiple instruction group through the instruction fetch unit, selecting a single instruction from the multiple instruction group according to a previous arithmetic result, and performing a arithmetic operation. | 2011-05-05 |
20110107064 | DATA PROCESSOR - The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code. | 2011-05-05 |
20110107065 | INTERCONNECT CONTROLLER FOR A DATA PROCESSING DEVICE AND METHOD THEREFOR - A data processing device includes an interconnect controller operable to manage the communication of information between modules of the data processing device via an interconnect. In response to a transaction request the interconnect controller selects a tag value from a set of available tag values, assigns the tag to the transaction and reserves the tag value so that it is unavailable for assignment to other transactions. If an expected response to the transaction request is not received within a designated amount of time, the transaction enters a timed-out state and the interconnect controller locks the tag value, so that it remains unavailable for assignment to other transactions until an unlock event, such as a request from software. | 2011-05-05 |
20110107066 | CASCADED ACCELERATOR FUNCTIONS - Accelerator functions are cascaded, such that a result of one accelerator function is directly forwarded to another accelerator function, bypassing the processor requesting the functions to be performed. The cascading may be provided during compilation of a program specifying the functions to be performed, but can be dynamically reversed during runtime of the program. | 2011-05-05 |
20110107067 | SINGLE-CHIP MULTIPROCESSOR WITH CLOCK CYCLE-PRECISE PROGRAM SCHEDULING OF PARALLEL EXECUTION - A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm. | 2011-05-05 |
20110107068 | ELIMINATING REDUNDANT OPERATIONS FOR COMMON PROPERTIES USING SHARED REAL REGISTERS - One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The method may assign the first virtual register to use a real register. The method may further identify a second virtual register storing a second value also having the common property. The method may assign the second virtual register to use the same real register after the first value is no longer live. As a result of assigning the second virtual register to the first real register, the method may eliminate an operation configured to establish the common property for the second virtual register since this operation is redundant and is no longer needed. | 2011-05-05 |
20110107069 | Processor Architecture for Executing Wide Transform Slice Instructions - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2011-05-05 |
20110107070 | PATCHING OF A READ-ONLY MEMORY - An information processing device comprises a memory carrying a program, and a processor capable of executing the program. The program instructs the processor to determine whether a selected identifier is contained in a set of identifiers, and, if the processor has determined that the identifier is contained in the set of identifiers, to execute a patch instruction identified by the identifier, and, if the processor has determined that the identifier is not contained in the set of identifiers, to execute an original instruction identified by the identifier. The memory may comprise a read-only memory (ROM) and a random access memory (RAM), the ROM carrying the original instruction and the RAM carrying the patch instruction and the set of identifiers. A method of executing a program on an information processing device and a method of modifying a program on an information processing device are also disclosed. | 2011-05-05 |
20110107071 | SYSTEM AND METHOD FOR USING A BRANCH MIS-PREDICTION BUFFER - A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction. | 2011-05-05 |
20110107072 | METHOD FOR SELF-DIAGNOSING SYSTEM MANAGEMENT INTERRUPT HANDLER - A method for self-diagnosing a system management interrupt (SMI) handler is provided. A first time value is obtained from an advanced configuration and power interface (ACPI) timer at a time of executing the SMI handler. And a source path of a SMI is obtained. Then, a second time value is obtained from the ACPI timer at a time of finishing the SMI handler. An execution time is obtained according to the first time and the second time. If the execution time is greater than or equal to a time-out value, related information of the SMI is recorded. | 2011-05-05 |
20110107073 | BOOTING A COMPUTER DEVICE - A method of booting a computing device includes, responsive to said computing device powering on, loading a first lightweight operating system on said computing device and executing an instant-on application through said lightweight operating system. The method further includes, during execution of said instant-on application, loading a hypervisor on said computing device and migrating said instant-on application to a first virtual machine executing a second lightweight operating system implemented by said hypervisor. The method further includes loading a full-feature operating system on a second virtual machine implemented by said hypervisor. | 2011-05-05 |
20110107074 | Electronic Device Capable of Automatically Setting up Operating Systems and Related Method and System - To reduce human resource cost, a method of automatically, consecutively setting up multiple operating systems, for an electronic device operating in an operating system, includes clearing a partition sector of the electronic device during operation of the operating system to generate an emptied boot record status, and setting up a target operating system according to the emptied boot record status and a setup procedure associated with the target operating system when the electronic device reboots. | 2011-05-05 |
20110107075 | NETWORK DEVICE AND NETWORK CONTROL DEVICE IN WIRELESS BODY AREA NETWORK, AND SECURE WAKE-UP METHOD AND WAKE-UP AUTHENTICATION CODE GENERATION METHOD OF NETWORK DEVICE AND NETWORK CONTROL DEVICE - A network device and a network control device in a Wireless Body Area Network (WBAN), and a secure wake-up method and a wake-up authentication code (WAC) generation method of the network device and the network control device are provided. The network device includes a wake-up circuit to receive a wake-up radio signal from a network control device using a Radio-Frequency Identification (RFID) receiver, to compare a WAC contained in the received wake-up radio signal with a WAC stored in advance, and to determine whether to wake up a main circuit unit, the network control device being contained in the WBAN; and the main circuit unit to be woken up in response to an interrupt signal from the wake-up circuit. | 2011-05-05 |
20110107076 | SYSTEM COMPRISING ELECTRONIC DEVICE AND EXTERNAL DEVICE STORING BOOT CODE FOR BOOTING SYSTEM - An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code. | 2011-05-05 |
20110107077 | OBSCURING FORM DATA THROUGH OBFUSCATION - Obscuring form data to be passed in forms that are sent in messages over a communications network. The form data to be obscured is removed from a form and inserted as a portion of a Uniform Resource Location (“URL”) string. The obscured form data may comprise hidden fields and/or links. An obfuscation is then applied to the portion of the URL string, thereby obscuring the information for sending on an outbound message. The original information is recovered from an inbound message which contains the obscured information by reversing the processing used for the obscuring. In one aspect, the obfuscation comprises encryption. In another aspect, the obfuscation comprises creating a tiny URL that replaces the portion of the URL string. | 2011-05-05 |
20110107078 | ENCODED DATA SLICE CACHING IN A DISTRIBUTED STORAGE NETWORK - A distributed storage processing unit encodes data objects into multiple encoded data slices to prevent reconstruction of the original data object using a single encoded data slice, but to allow reconstruction using at least a threshold number of encoded data slices. The distributed storage processing unit can decide to whether and where to cache frequently requested data slices. When retrieving data slices related to a particular data object, a check can be made to determine if the data slices are cached in a temporary memory associated with the distributed storage processing unit, or elsewhere in the distributed storage network. This check can be facilitated by storing data slices and a hash table identifying the location of stored data slices in the same temporary memory. | 2011-05-05 |
20110107079 | TARGET DEVICE, METHOD AND SYSTEM FOR MANAGING DEVICE, AND EXTERNAL DEVICE - A device management system is configured with a target device including at least one unit that includes a tamper-resistant chip, a management apparatus that manages or uses the target device, and an authentication apparatus including a database for authentication, connected via a network in a communicable manner. In the target device, each unit is equipped with the tamper-resistant chip that collects device information specific to a unit, stores collected device information, and stores a confidential-key. | 2011-05-05 |
20110107080 | Data broadcasting system, server and program storage medium - A data broadcasting system includes a user device and a data broadcasting server. The device includes: a transmission requesting section transmitting the own model information and a request to transmit a content; and a content reproduction section reproducing the requested encoded content by decoding the content using key information for decoding the content. The server includes: a qualification storage section storing correspondence information where model information and reproduction qualification information are associated with each other; a reproduction qualification determination section referring to the correspondence information upon receiving the model information and the request from the user device, obtaining the reproduction qualification information corresponding to the model information, and determining whether the user device is qualified to reproduce the content; and a content transmission section transmitting, to the user device, the content and the key information when the user device is determined as being qualified by the reproduction qualification determination section. | 2011-05-05 |
20110107081 | METHOD AND APPARATUS FOR PROCESSING OF BROADCAST DATA - A plurality of conditional access (CA) clients are needed to receive services from a plurality of service, where the CA clients respectively correspond to the service providers. Thus, the CA clients should be installed into a broadcast receiver, and in this case, a method of managing the CA clients is needed. Provided are a method and apparatus for processing broadcast data by using a security client. The method includes determining a first security client based on a security client list, where the first security client is used to decrypt encrypted broadcast data and the security client list comprises information regarding each of security clients available which provide information necessary to decrypt the encrypted broadcast data; and decrypting the encrypted broadcast data by using the first security client. Accordingly, it is possible to allow a user to receive various services. | 2011-05-05 |
20110107082 | Storing and Forwarding Media Data - A method apparatus for storing and forwarding media data in a communication network. An intermediate node disposed between a media data source node and a client node receives encrypted media data packets from the media data source node. The intermediate node stores the received media data packets in a memory for later sending to the client node, and adjusts fields in the original header of each stored media data packet to create modified media data packets having a modified header, and sends adjustment information to the client node. The adjustment information allows the client node to recreate the original headers from the modified headesr, before decrypting the encrypted media packets with keying materials already sent between the media data source node and the client node. The modified media data packets are then sent to the client node for decryption. This allows the intermediate node to “store and forward” SRTP data without being able to access the encrypted data content. | 2011-05-05 |
20110107083 | CONTENT TRANSMISSION DEVICE AND CONTENT TRANSMISSION METHOD - Provided is a content transmission device | 2011-05-05 |
20110107084 | SYSTEM FOR AND METHOD FOR RELAYING MESSAGES - A system for and method of relaying messages is presented. In an exemplary embodiment, the system and method may include receiving a request from a user to transmit a message to an intended recipient, processing the message for transmission, wherein processing the message comprises assigning metadata to the message, and transmitting the message with the metadata to the intended recipient, where transmitting the message with metadata comprises searching for at least one proximate ad hoc relay device in the event that a communication link cannot be established with a communication network. | 2011-05-05 |
20110107085 | Authenticator relocation method for wimax system - A method is provided for Authenticator Relocation in a communication system applying an Extensible Authentication Protocol, or the like, which provides replay protection and mitigates the rogue ASN-GW problem during relocation of the Anchor Authentication, and without conducting re-authentication of the MS. The method of the invention optionally allows secure refresh of the MSK. | 2011-05-05 |
20110107086 | SECURE AUTHENTICATION AND PRIVACY OF DATA COMMUNICATION LINKS VIA DYNAMIC KEY SYNCHRONIZATION - A dynamic computer system security method and system using dynamic encryption and full synchronization between system nodes. A data record from a data stream created by a source user is encrypted with an initial dynamic session key. A new dynamic session key is generated based upon a data record and a previous dynamic session key. The new dynamic session key is then used to encrypt the next data record. A central authority is used to synchronize and authenticate both source and destination users with dynamic authentication keys. The central authority and users constantly regenerate new dynamic authentication keys. A child process is forked to ensure synchronization and authentication of dynamic authentication keys of each node upon a request for a secure communication establishment from a user. The central authority generates the initial dynamic session key with the current dynamic authentication key to begin a secure communication session. | 2011-05-05 |
20110107087 | APPARATUS AND METHOD FOR REFRESHING MASTER SESSION KEY IN WIRELESS COMMUNICATION SYSTEM - A Master Session Key (MSK) refresh in a wireless communication system is provided. A MSK refreshing method MSK includes when receiving a first Media Access Control (MAC) message including MSK refresh indication information from a Base Station (BS), generating, at a Mobile Station (MS), an Extended Master Session Key (EMSK)_Hash by applying a hash function to an EMSK and sending a second MAC message including the EMSK_Hash, sending, at the BS, a context request message including the EMSK_Hash to an Access Service Network GateWay (ASN-GW), sending, at the ASN-GW, an authentication request message including the EMSK_Hash to an authentication server, when receiving the authentication request message including the EMSK_Hash, confirming, at the authentication server, the same EMSK as the MS based on the EMSK_Hash, determining an MSK | 2011-05-05 |
20110107088 | SYSTEM AND METHOD FOR VIRTUAL TEAM COLLABORATION IN A SECURE ENVIRONMENT - A computing platform for facilitating dynamic connection and collaboration of users to transact services in a secure computing environment. The users include service providers and service requesters. The platform includes a registration module for registering users including service requesters and service providers, a connection module for connect users to form groups based on users' selective invitations to other users, and a collaboration module for creating a virtual secure data room for collaboration and sharing of encrypted data by the connected users in a user-friendly and transparent manner. The platform further comprises a transaction module for settling payments between the service requesters and the service providers based on completion of previously agreed project milestones. | 2011-05-05 |
20110107089 | METHODS AND SYSTEMS FOR IMPLEMENTING POLICY BASED TRUST MANAGEMENT - This disclosure describes, generally, methods and systems for implementing policy based trust management. The method includes receiving, at an host server, a trust request from a partner, and identifying, at the host server via a trust policy enforcer, parameters and attributes associated with the partner. The method further includes identifying, at the host server via the trust policy enforcer, parameters and attributes associated with the requested resource, and accessing, by the trust policy enforcer, a policy database. Furthermore, the method includes retrieving, by the trust policy enforcer, one or more trust policies associated with the requested resource, and based on the attributes and parameters of the partner, applying, by the trust policy enforcer, the one or more associated trust policies to the request. Further, the method includes based on conformity with the one or more trust policies, providing the partner with access to the requested resource. | 2011-05-05 |
20110107090 | System and Method for Flying Squad Re Authentication of Enterprise Users - Enterprise users access several applications and services routinely to carry out their work-related activities on a day-to-day basis. These applications and services could be hosted within an enterprise or on a third-party data center. The enterprise users login into the applications and services so as to gain access to the applications and services. In the case of single sign-on, it is expected that the users authenticate once to a specific application/service/system and obtain access to any other application/service/system. In such a scenario, it is important to ensure that during the course of this authenticated access grant, the right users are provided access to right information. This is achieved by a re-authentication system that demands minimum re-authentication effort from “right” users and maximum re-authentication effort from “non-right” users. A system and method of on the fly re-authentication involves a novel challenge-response mechanism. | 2011-05-05 |
20110107091 | Secure communication between client device and server device - A user is enabled to select one or more client devices from a number of client devices and to select one or more server devices from a number of server devices. Secure communication is to occur between each selected client device and each selected server device. For each unique pair of a selected client device and a selected server device, a validation of a security configuration of the selected client device and a security configuration of the selected server device is performed, to determine whether secure communication can occur between the selected client device and the selected server device. Where the validation has failed, reconfiguration of one or more of the selected client device and the selected server device is performed so that secure communication can occur between the selected client device and the selected server device. | 2011-05-05 |