18th week of 2015 patent applcation highlights part 74 |
Patent application number | Title | Published |
20150121000 | INDEPENDENTLY SELECTIVE TILE GROUP ACCESS WITH DATA STRUCTURING - Embodiments of the present disclosure include data structuring techniques and configurations for memory access. In one embodiment, an apparatus includes a plurality of tiles, a plurality of blocks, wherein individual tiles of the plurality of tiles and individual blocks of the plurality of blocks each include a plurality of tile blocks having memory elements and wherein the plurality of tile blocks are accessible for read or write according to a tile address to identify a tile of the plurality of tiles and a block address to identify a block of the plurality of blocks and a data restructuring module configured to modify, based on the tile address, an order of data to be read from or written to the tile blocks. Other embodiments may be described and/or claimed. | 2015-04-30 |
20150121001 | STORAGE CONTROL DEVICE AND STORAGE CONTROL METHOD - A storage control device that is any of a plurality of storage control devices configured to control access to a plurality of storages included in a storage system, includes: a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: executing, depending on a first bias for accessing a plurality of storage regions included in the plurality of storages, a first configuration change which corrects the first bias based on configuration information identifying a configuration of the storage system; and executing, depending on a second bias for accessing the plurality of storages, a second configuration change which corrects the second bias based on the configuration information after changing the first configuration, or executing, depending on a third bias for loading the plurality of storage control devices, a third configuration change which corrects the third bias. | 2015-04-30 |
20150121002 | RAID CONFIGURATION MANAGEMENT DEVICE AND RAID CONFIGURATION MANAGEMENT METHOD | 2015-04-30 |
20150121003 | Storage controllers - A storage array controller provides a method and system for autonomously issuing trim commands to one or more solid-state storage devices in a storage array. The storage array controller is separate from any operating system running on a host system and separate from any controller in the solid-state storage device(s). The trim commands allow the solid-state storage device to operate more efficiently. | 2015-04-30 |
20150121004 | COMPUTER REALIZING HIGH-SPEED ACCESS AND DATA PROTECTION OF STORAGE DEVICE, COMPUTER SYSTEM, AND I/O REQUEST PROCESSING METHOD - In a computer, a logical partition for calculation in which an OS and an application operate and a logical partition for storage for providing a storage function are constructed. In the logical partition for calculation, a device corresponding to a storage device is provided, while the logical partition for storage provides a volume. A memory space that can be shared by the both logical partitions is prepared, and management information describing a sorting destination or a sorting method of an I/O request issued by an application is provided in the memory. If the logical partition for calculation receives an I/O request from the application, the partition refers to the management information and sorts the I/O request to the storage device or the logical partition for storage. The logical partition for storage processes the received I/O request by the storage function and transmits the result to the storage device. | 2015-04-30 |
20150121005 | MANAGEMENT METHOD OF VIRTUAL STORAGE SYSTEM AND REMOTE COPY SYSTEM - Exemplary embodiments provide techniques of managing storage systems including remote copy systems and improving the manageability by automating complicated operations. In one embodiment, a computer comprises a memory and a controller. The controller is operable to: manage a virtual volume to be provided for a server; manage a plurality of logical volumes provided from a plurality of storage systems; manage a condition to be required of the virtual volume, the condition relating to a location in which data to be sent to the virtual volume is stored; manage location information of each of the plurality of logical volumes, the location information of a logical volume being defined based on a location of the logical volume; and control to map the virtual volume to a logical volume of the plurality of logical volumes, based on the condition of the virtual volume and the location information of the logical volumes. | 2015-04-30 |
20150121006 | SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE - A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command. | 2015-04-30 |
20150121007 | ADJUSTMENT OF THE NUMBER OF TASK CONTROL BLOCKS ALLOCATED FOR DISCARD SCANS - A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress. | 2015-04-30 |
20150121008 | Write Cache Destaging - Disclosed is a system for controlling write actions to a plurality of data storage devices, the system comprising a plurality of write caches, wherein each cache is associated with a set of said data storage devices; and a controller adapted to issue write permissions to said data storage devices, said write permissions including a permission to perform a data destage operation from a cache to a data storage device; wherein each cache has a first performance score expressed as the difference between the number of data destage operations said cache has in flight and the maximum number of data destage actions said cache is permitted to issue in parallel; and wherein the controller is adapted to offer a data destage operation permission to the cache in said plurality of caches associated with the highest first performance score. | 2015-04-30 |
20150121009 | METHOD AND APPARATUS FOR REFORMATTING PAGE TABLE ENTRIES FOR CACHE STORAGE - A device for and method of storing page table entries in a first cache. A first page table entry is received having a fragment field that contains address information for a requested first page and at least a second page logically adjacent to the first page. A second page table entry is generated from the first page table entry to be stored with the first page table entry. The second page table entry provides address information for the second page. The second page table entry has a configuration that is compatible with the first cache. | 2015-04-30 |
20150121010 | UNIFIED STORE QUEUE - Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction. | 2015-04-30 |
20150121011 | STORAGE SYSTEM HAVING TAG STORAGE DEVICE WITH MULTIPLE TAG ENTRIES ASSOCIATED WITH SAME DATA STORAGE LINE FOR DATA RECYCLING AND RELATED TAG STORAGE DEVICE - A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated. | 2015-04-30 |
20150121012 | METHOD AND APPARATUS FOR PROVIDING DEDICATED ENTRIES IN A CONTENT ADDRESSABLE MEMORY TO FACILITATE REAL-TIME CLIENTS - A device and method for partitioning a cache that is expected to operate with at least two classes of clients (such as real-time clients and non-real-time clients). A first portion of the cache is dedicated to real-time clients such that non-real-time clients are prevented from utilizing said first portion. | 2015-04-30 |
20150121013 | CACHE LONGEVITY DETECTION AND REFRESH - A web server cache performs verification of cached computational results by storing a computed function result as a cached value in a cache, and upon receiving a subsequent invocation of the function, examining a duration of the value in the cache. The web server compares, if the duration exceeds a staleness detection threshold, a result of a subsequent execution of the function to the cached value in response to the subsequent invocation by recomputing, a result from execution of the function for validating the cached value, and flags an error if the duration exceeds the staleness detection threshold and the result differs from the cached value. Alternatively, the method returns, if the duration of the cache value is within the staleness detection threshold, the cache value as the result of the subsequent invocation. | 2015-04-30 |
20150121014 | DATA PROCESSING METHOD AND APPARATUS FOR PREFETCHING - A data processing device includes processing circuitry | 2015-04-30 |
20150121015 | DEVICE AND METHOD FOR PROCESSING MESSAGE - Embodiments provide a device and method for processing messages according to a priority order and for reducing a message processing time when a response event occurs, in a PLC communication module. | 2015-04-30 |
20150121016 | Method, Apparatus and Device for Data Processing - A method for data processing is disclosed. A blank state is determined for several data bits based on a majority decision. Each data bit is represented by a group of at least two memory cells. The at least two memory cells of this group are complementary cells of a differential read memory. | 2015-04-30 |
20150121017 | REDUCING READ LATENCY USING A POOL OF PROCESSING CORES - In a read processing storage system, using a pool of CPU cores, the CPU cores are assigned to process either write operations, read operations, and read and write operations, that are scheduled for processing. A minimal number of the CPU cores are allocated for processing the write operations, thereby increasing write latency. Upon reaching a throughput limit for the write operations that causes the minimal number of the plurality of CPU cores to reach a busy status, the minimal number of the plurality of CPU cores for processing the write operations is increased. | 2015-04-30 |
20150121018 | SEMICONDUCTOR MEMORY SYSTEM AND VOLTAGE SETTING METHOD - A semiconductor memory system includes a memory controller and memory apparatus. The memory controller provides a first data having a first level and a second data having a second level. The memory apparatus adjusts a level of a reference voltage by comparing the reference voltage with each of the first data and the second data. | 2015-04-30 |
20150121019 | DATA PROCESSING DEVICE AND METHOD FOR INTERLEAVED STORAGE OF DATA ELEMENTS - A data processing device | 2015-04-30 |
20150121020 | STORAGE APPARATUS, METHOD OF CONTROLLING STORAGE APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN STORAGE APPARATUS CONTROL PROGRAM - A storage apparatus includes a processor. The processor calculates an upper limit of an input/output processing amount, which is determined based on priority levels set to a plurality of storage devices, for each storage device. The processor schedules an execution sequence of processes relating to input/output requests received from information processing apparatuses based on processing amounts relating to the input/output requests and the upper limits. The processor executes the processes relating to the input/output requests in the scheduled execution sequence. The processor is configured to determine, for each storage device, whether or not a processing amount of the storage device exceeds a processing bandwidth of the each storage device for a first predetermined time. The processor changes the upper limit for each storage device in a predetermined bandwidth accommodation unit in a case where the processing amount for each storage device is determined to exceed the processing bandwidth. | 2015-04-30 |
20150121021 | APPARATUS AND METHOD FOR CONTROLLING STORAGE DEVICES - Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands. | 2015-04-30 |
20150121022 | REDUNDANT LOCATION ADDRESS MAPPER - The present disclosure includes mapping redundant addresses in a multi-node system by receiving a first address and a first node ID, determining a first address type representing an address redundancy level for the first address, determining a first node ID type representing a node ID redundancy level for the first node ID, and determining a second address and a second node ID based on the first address type and the first node ID type. | 2015-04-30 |
20150121023 | Operating A Memory Management Controller - A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier. | 2015-04-30 |
20150121024 | Operating A Memory Management Controller - A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier. | 2015-04-30 |
20150121025 | WRITABLE CLONE DATA STRUCTURE - A memory system including parent data and clone data is disclosed, where the clone data represents a clone of the parent data. The system determines whether clone data to be accessed is different from corresponding data in the parent. The system also determines a physical location of the data to be accessed based on whether the data to be accessed is different from the corresponding parent data. The system also accesses the data based on the physical location. | 2015-04-30 |
20150121026 | SEMICONDUCTOR SYSTEM AND OPERATING METHOD THEREOF - A semiconductor system includes a semiconductor memory device suitable for storing data, and a host suitable for controlling the semiconductor memory device in response to an external command signal, in which the semiconductor memory device includes a buffer block suitable for storing first data programmed under control of the host, and a main block suitable for storing the second data programmed under control of the host or a copy of the first data stored in the buffer block at a sudden power fail. | 2015-04-30 |
20150121027 | ELECTRONIC APPARATUS AND METHOD - According to one embodiment, an apparatus includes a receiver, a requesting controller, a substitution operation controller, a reflection controller, and an access controller. The receiver receives protection area information transmitted from a first application. The protection area information describes a protection area within storage. The requesting controller requests a second application to register first data based on the protection area information in a data file within a nonvolatile memory device. The substitution operation controller attempts to register the first data in the data file. The reflection controller reflects the protection area information in a kernel setting. The access controller controls access to data within the storage based on the kernel setting. | 2015-04-30 |
20150121028 | STORAGE DEVICE SECURITY SYSTEM - A storage device security system includes a server that is coupled to a storage device, a storage controller, a configuration IHS, and a remote access controller. The remote access controller receives a storage device access key request and a storage controller Globally Unique Identifier (GUID) from the storage controller. The remote access controller also receives a server GUID from the server. The remote access controller also receives a security key from the configuration IHS over a network. The remote access controller is configured to use a remote access controller Media Access Control (MAC) address, the storage controller GUID, the server IHS GUID, and the security key to generate a storage device access key. The remote access controller may then provide the storage device access key to the storage controller, and storage controller may use the storage device access key to access the storage device coupled to the server IHS. | 2015-04-30 |
20150121029 | MEMORY MANAGEMENT WITH PRIORITY-BASED MEMORY RECLAMATION - A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage. | 2015-04-30 |
20150121030 | HIGH DENSITY MEMORY STRUCTURE - A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines. | 2015-04-30 |
20150121031 | ADAPTIVE GUARD BAND FOR IMPROVED DATA STORAGE CAPACITY - An adaptive guard band for a ramp load/unload device is disclosed to provide extended data storage. In illustrated embodiments, an adaptive guard band algorithm is configured to format one or more discs or media having a lower capacity device with the adaptive guard band and extended data zone utilizing capacity measurements. The algorithm formats the media to provide a track zero at a first cylinder if the capacity is at or above the threshold capacity and a second cylinder if the capacity is below the threshold capacity to provide the extended data storage zone. A size or width of the extended data zone is variable to provide additional capacity to meet the threshold capacity. | 2015-04-30 |
20150121032 | Data Deduplication in a Virtualization Environment - Techniques are described herein that are capable of optimizing (i.e., deduplicating) data in a virtualization environment. For example, optimization designations (a.k.a. deduplication designations) may be assigned to respective regions of a virtualized storage file. A virtualized storage file is a file that is configured to be mounted as a disk or a volume to provide a file system interface for accessing hosted files. In accordance with this example, each optimization designation indicates an extent to which the respective region is to be optimized (i.e., deduplicated). In another example, a virtualized storage file is mounted to provide a virtual disk that includes hosted files. In accordance with this example, optimization designations are assigned to the respective hosted files. In further accordance with this example, each optimization designation indicates an extent to which the respective hosted file is to be optimized. | 2015-04-30 |
20150121033 | INFORMATION PROCESSING APPARATUS AND DATA TRANSFER CONTROL METHOD - An address translation table stores therein an association relation between a logical address and a physical address, change information indicating a change in the association relation when the association relation is changed such that a physical address having been associated with each logical address is associated with a different logical address, and the different logical address. A table control unit, when receiving a command to move data between logical addresses from a CPU, changes the association relation in the address translation table such that a movement-destination logical address is associated with a physical address in which the data is stored, sets change information in a movement-source logical address, and stores the movement-destination logical address as a different logical address associated with the movement-source logical address. | 2015-04-30 |
20150121034 | Systems and Methods for Implementing Low-Latency Lookup Circuits Using Multiple Hash Functions - A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit (which may include a programmable hash table) may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the results. Each hash value may be used to access a location in a lookup table in memory to obtain its contents (e.g., a key and associated data). The circuit may include a selection sub-circuit that selects the data of one of the identified locations as an output of the lookup circuit (e.g., one whose key matches the input key). The circuit may modify obtained data prior to its selection and may output a signal indicating the validity of input keys. | 2015-04-30 |
20150121035 | Systems and Methods for Implementing Low-Latency Lookup Circuits Using Sparse Hash Functions - A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency. | 2015-04-30 |
20150121036 | CRYPTOGRAPHIC SUPPORT INSTRUCTIONS - A data processing system | 2015-04-30 |
20150121037 | COMPUTING ARCHITECTURE AND METHOD FOR PROCESSING DATA - A processing device includes an execute processor configured to execute data processing instructions; and an access processor configured to be coupled with a memory system to execute memory access instructions; wherein the execute processor and the access processor are logically separated units, the execute processor having an execute processor input register file with input registers, and a data processing instruction is executed as soon as all operands for the respective data processing instruction are available in the input registers. | 2015-04-30 |
20150121038 | PREFETCH STRATEGY CONTROL - A single instruction multiple thread (SIMT) processor | 2015-04-30 |
20150121039 | METHOD AND APPARATUS FOR SHUFFLING DATA - Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set. | 2015-04-30 |
20150121040 | PROCESSOR AND METHODS FOR FLOATING POINT REGISTER ALIASING - Methods, devices, and systems for accessing packed registers are presented. A state of the packed registers may be tracked and it may be determined whether the register is directly accessible based on the state. If the register is not directly accessible, an action may be performed which allows the register to be accessed directly. The action may include injecting at least one uop for reorganizing the physical storage of the register such that it is directly accessible. The action may include aligning the data with the least significant bit of a physical register or otherwise aligning the data with the datapath. The action may also include changing the state of the packed registers. | 2015-04-30 |
20150121041 | PROCESSOR AND METHODS FOR IMMEDIATE HANDLING AND FLAG HANDLING - Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to instructions. This allows an instruction to write exactly the flags that the instruction wants without having to create merge dependencies. Methods and processors are provided for handling immediate values embedded in instructions. A 16 bit immediate bus and a 4 bit encoding/control bus are added at the interface between decode and execution units. For an 8 or 12 bit immediate, the upper 4 bits of the immediate bus contain the encoding bits. For a 16 bit immediate, the encoding/control bus contains the encoding bits. The encoding/control bus indicates when to look at the top four bits of the immediate bus. | 2015-04-30 |
20150121042 | ARITHMETIC DEVICE - According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and based on an offset which is a value corresponding to a counter value and which is based on the address of the first piece of data, the address generating unit generates addresses of the memory device. The control unit controls the arithmetic processing unit in such a way that the arithmetic processing is done in a sequence determined in the encryption method, and that specifies an update of the counter value at a timing of modifying the type of data and at a timing of modifying data. | 2015-04-30 |
20150121043 | COMPUTER AND METHODS FOR SOLVING MATH FUNCTIONS - Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy. | 2015-04-30 |
20150121044 | MERGED FLOATING POINT OPERATION USING A MODEBIT - A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output. | 2015-04-30 |
20150121045 | READING A REGISTER PAIR BY WRITING A WIDE REGISTER - A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow registers. Based on determining the wide input operand is not available in the wide register, merging at least a portion of contents of the two narrow registers to obtain merged contents, writing the merged contents into the wide register, and continuing the read operation to obtain the wide input operand. Based on determining the wide input operand is available in the wide register, obtaining the wide input operand from the wide register. | 2015-04-30 |
20150121046 | ORDERING AND BANDWIDTH IMPROVEMENTS FOR LOAD AND STORE UNIT AND DATA CACHE - The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes a load order queue for cacheable operations that ordered for a particular address. | 2015-04-30 |
20150121047 | READING A REGISTER PAIR BY WRITING A WIDE REGISTER - A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow registers. Based on determining the wide input operand is not available in the wide register, merging at least a portion of contents of the two narrow registers to obtain merged contents, writing the merged contents into the wide register, and continuing the read operation to obtain the wide input operand. Based on determining the wide input operand is available in the wide register, obtaining the wide input operand from the wide register. | 2015-04-30 |
20150121048 | HETEROGENEITY WITHIN A PROCESSOR CORE - A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode. | 2015-04-30 |
20150121049 | SAFE CONDITIONAL-LOAD AND CONDITIONAL-STORE OPERATIONS - One embodiment is a computer-implemented method for safe conditional operation when storage access cannot be proven safe. The method includes receiving a portion of source code for a transaction by an enhanced compiler and. The portion of source code received is analyzed, by the enhanced compiler, to determine whether the portion of source code is a candidate for transformation. Responsive to a determination that the portion of source code analyzed by the enhanced compiler is a candidate for transformation, the portion of the source code analyzed is transformed, by a computer processor, to use a conditional operation in a first portion of the transformed code. The conditional operation uses hardware transaction memory to invoke retry operations within hardware. A branch is added, directed to an original code portion, in a second portion of transformed code, where the branch is a recovery portion containing the original code portion. | 2015-04-30 |
20150121050 | BANDWIDTH INCREASE IN BRANCH PREDICTION UNIT AND LEVEL 1 INSTRUCTION CACHE - A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken. | 2015-04-30 |
20150121051 | KERNEL FUNCTIONALITY CHECKER - A debugging system and method, referred to as a kernel functionality checker, is described for enabling debugging of software written for device-specific APIs (application program interfaces) without requiring support or changes in the software driver or hardware. Specific example embodiments are described for OpenCL, but the disclosed methods may also be used to enable debugging capabilities for other device-specific APIs such as DirectX® and OpenGL®. | 2015-04-30 |
20150121052 | THREE-DIMENSIONAL PROCESSING SYSTEM HAVING INDEPENDENT CALIBRATION AND STATISTICAL COLLECTION LAYER - Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein at least one chip layer has calibration control circuitry that is dedicated to calibrating/configuring one or more functional chip layers, and/or performance instrumentation control circuitry for testing and collecting performance data of one or more functional chip layers. | 2015-04-30 |
20150121053 | Loading An Operating System Of A Diskless Compute Node Using A Single Virtual Protocol Interconnect ('VPI') Adapter - Loading an operating system of a diskless compute node using a single Virtual Protocol Interconnect (VPI) adapter, including: setting, by a VPI firmware module during startup of the compute node, an operational mode of the VPI adapter to operate in accordance with a first data communications protocol, the VPI adapter including a preboot execution environment module that supports the first data communications protocol prior to loading an operating system and a driver for the first data communications protocol; retrieving, by the VPI firmware module from a network source via the VPI adapter in accordance with the first data communications protocol, the operating system and a driver for the second data communications protocol; and responsive to loading the operating system and the driver for the second data communications protocol, switching the operational mode of the VPI adapter to operate in accordance with the second data communications protocol. | 2015-04-30 |
20150121054 | Platform Secure Boot - A system and method for securing a boot process on the electronic device using a hardware-based secure processor are provided. The hardware-based secure processor receives a boot instruction. In response to the received boot instruction, the hardware-based secure processor authenticates the boot code in hardware while stalling the processor. Once the boot code is authenticated, the processor is released from the stall and processes the boot code. | 2015-04-30 |
20150121055 | FLEXIBLE BOOTSTRAP CODE ARCHITECTURE - The present disclosure is directed to flexible bootstrap code architecture. A device may comprise equipment for operating the device and an operating system (OS) for operating the equipment A boor, module may also be included in the device to execute boot operations. At least one flexible boot (FB) module in the boot module may interact with the equipment and/or OS during the boot operations to cause the boot operations to become device-specific. An example boot module may comprise a plurality of FB modules. An example FB module may verify a device/chipset identification and may control the boot operations based on the identification. Other example FB modules may select resources to load based on an OS type, may provide a boot configuration table location for use in OS runtime boot configuration or may load variables from a preload variable directory for use in configuring boot operations. | 2015-04-30 |
20150121056 | INFORMATION PROCESSING SYSTEM, MANAGEMENT APPARATUS, AND MANAGEMENT METHOD - By causing information processing apparatuses belonging to a same group to be in a same state and transmitting operation information received from an input unit to the information processing apparatuses belonging to the same group simultaneously or approximately simultaneously, the operations of the information processing apparatuses belonging to the same group are synchronized with each other, and operation results received from the synchronized information processing apparatuses belonging to the same group are output by an output unit. In this way, the plurality of grouped information processing apparatuses can be simultaneously operated. | 2015-04-30 |
20150121057 | Using an Idle Duration History to Configure an Idle State of an Entity in a Computing Device - The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state. | 2015-04-30 |
20150121058 | Intelligent Real-time Optimization - In one embodiment, a method determines real-time information regarding changes to input data used to run an optimization. The optimization is run using a first computing system to generate a first optimization result within a first time window and the first computing system is configured to run the optimization periodically within subsequent time windows. The method determines when the changes to the input data indicate the optimization should be rerun. When the optimization should be rerun, the method causes a re-running of the optimization after the time window ends using a second computing system different from the first computing system. The re-running of the optimization using the changes and generating a second optimization result before a next time window for the first computing system to periodically run the optimization starts. | 2015-04-30 |
20150121059 | SYNTHETIC DEVICE FOR INSTALLATION SOURCE MEDIA - In one embodiment, a computer system provides a process for executing software that cannot be executed in a first configuration. The computer system determines source media for the software stored in a first data store, the source media being in the first configuration. The computer system retrieves metadata relating to executing the software from the source media. The computer system next transforms the retrieved metadata to generate a second configuration of the source media according to a transformation rule set, where the software can be executed in the second configuration, and stores the transformed metadata in a second data store. Next, the computer system presents the second configuration of the source media based on the transformed metadata. Thereafter, the computer system satisfies a request relating to executing the software using the transformed metadata in the second data store, wherein the request is satisfied based on the second configuration. | 2015-04-30 |
20150121060 | METHODS FOR CONFIGURABLE HARDWARE LOGIC DEVICE RELOADING AND DEVICES THEREOF - A method and host computing device that restricts access by one or more applications to a configurable hardware logic device over a bus. At least a portion of the configurable hardware logic device is reconfigured. A determination is made when unplug and plug events have been generated by the configurable hardware logic device. The unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device. The configurable hardware logic device is re-enumerated on the bus when the determining indicates the unplug and plug events have been generated by the configurable hardware logic device. | 2015-04-30 |
20150121061 | SYSTEMS AND METHODS FOR MANAGING A GUEST VIRTUAL MACHINE EXECUTING WITHIN A VIRTUALIZED ENVIRONMENT - The present disclosure relates to methods and systems for managing a guest virtual machine executing within a virtualized environment. A daemon is established on a guest virtual machine executing within a virtualized environment. The daemon is configured to communicate with a management service virtual machine executing within the virtualized environment. The daemon receives, from the management service virtual machine via an application layer protocol, a request identifying an action type of a plurality of predetermined action types. The daemon identifies the action type of the plurality of predetermined action types from the received request and performs an action corresponding to the identified action type. In some implementations, the application layer protocol is one of Hypertext Transfer Protocol (HTTP) or Hypertext Transfer Protocol Secure (HTTPS). | 2015-04-30 |
20150121062 | METHOD AND SYSTEM FOR MODIFYING AN AUTHENTICATED AND/OR ENCRYPTED MESSAGE - A method and system for modifying an authenticated and/or encrypted message by a modifying party exchanged between a sending party and a receiving party based on a secure communication protocol, the method includes the steps of
| 2015-04-30 |
20150121063 | SYSTEM AND METHOD FOR SECURED CONTENT DELIVERY - A content delivery platform is provided that includes generating a first content package of content that is encrypted with a unique symmetric key, and a second content package including a link encrypted with the key to the first content package. The first content package is stored in a repository, and a request including the key is transmitted to a first computing device associated with a mail exchange for an encryption key file. An encryption key file is generated using the unique symmetric key and together with a authorizing token is received. A third content package is generated that is encrypted using the encryption key file and includes the encrypted link. The third content package is transmitted to a distributor gateway and the encrypted link is accessible in response to the consumer decrypting the third content package. The link is available to provide to access to the content for the consumer. | 2015-04-30 |
20150121064 | TECHNIQUES FOR SECURE MESSAGE OFFLOADING - Techniques for secure message offloading are presented. An intermediary is transparently situated between a user's local messaging client and an external and remote messaging client. The user authenticates to the local client for access and the intermediary authenticates the user for access to the remote client using different credentials unknown to the user. Messages sent from the local client are transparently encrypted by the intermediary before being passed to the remote client and messages received from the remote client are transparently decrypted before being delivered to the local client. | 2015-04-30 |
20150121065 | ELECTRONIC DEVICE AND ANTIPIRACY PROTECTING METHOD - In a method of protecting copyright of a digital media file in an electronic device, the electronic device receives a request for downloading the digital media file, from a recipient electronic device, the electronic device requires the recipient electronic device, to provide information of the recipient electronic device, the electronic device further requests a third-party authorization system, to allocate a key for the digital media file according to the information, once the electronic device locks the digital media file using the key, the electronic device sends the locked digital media file to the recipient electronic device. | 2015-04-30 |
20150121066 | Set of Servers for "Machine-to-Machine" Communications using Public Key Infrastructure - A set of servers can support secure and efficient “Machine to Machine” communications using an application interface and a module controller. The set of servers can record data for a plurality of modules in a shared module database. The set of servers can (i) access the Internet to communicate with a module using a module identity, (i) receive server instructions, and (iii) send module instructions. Data can be encrypted and decrypted using a set of cryptographic algorithms and a set of cryptographic parameters. The set of servers can (i) receive a module public key with a module identity, (ii) authenticate the module public key, and (iii) receive a subsequent series of module public keys derived by the module with a module identity. The application interface can use a first server private key and the module controller can use a second server private key. | 2015-04-30 |
20150121067 | DIGITAL CERTIFICATE ISSUER-CORRELATED DIGITAL SIGNATURE VERIFICATION - A message including a digital signature of a message originator is received at a processor. In response to determining that the message originator is authorized by a data protection policy to originate the message, a determination is made as to whether a specific authorized certificate issuer is configured for the message originator within a data protection policy. In response to determining that the specific authorized certificate issuer is configured for the message originator within the data protection policy, a determination is made as to whether a message originator certificate used to generate the digital signature of the message originator is issued by the specific authorized certificate issuer configured for the message originator within the data protection policy. | 2015-04-30 |
20150121068 | APPARATUS AND METHOD FOR IMPLEMENTING COMPOSITE AUTHENTICATORS - A system, apparatus, method, and machine readable medium are described for implementing a composite authenticator. For example, an apparatus in accordance with one embodiment comprises: an authenticator for authenticating a user of the apparatus with a relying party, the authenticator comprising a plurality of authentication components; and component authentication logic to attest to the model and/or integrity of at least one authentication component to one or more of the other authentication components prior to allowing the authentication components to form the authenticator. | 2015-04-30 |
20150121069 | EMBEDDED EXTRINSIC SOURCE FOR DIGITAL CERTIFICATE VALIDATION - A computer uses the information included within a digital certificate to obtain a current date and time value from a trusted source extrinsic to the computer. The computer requests and receives the trusted current date and time value and compares the trusted current date and time value to a validity period included in the digital certificate, to determine if the digital certificate is expired. The information included within the digital certificate specifying an extrinsic source for the current date and time value can be included in an extension of the digital certificate, and the information can specify a plurality of extrinsic sources. | 2015-04-30 |
20150121070 | FIRMWARE SECURITY - One embodiment provides an apparatus adapted to perform a secure firmware upgrade. The apparatus includes a first memory and a second memory. The first memory stores a private key for use in decrypting content and a unique identifier corresponding to the apparatus. The second memory includes a first version of firmware for the apparatus. The apparatus further includes a controller configured to perform an operation that includes receiving a first request to perform a firmware update operation for the apparatus. The operation also includes transmitting a second request for a second version of firmware to a remote server, the second request specifying the unique identifier corresponding to the apparatus. Additionally, in response to transmitting the second request, an encrypted firmware package is received from the remote server. The operation further includes decrypting the encrypted firmware package using the private key and installing the decrypted firmware package on the apparatus. | 2015-04-30 |
20150121071 | PROGRAMMING VEHICLE MODULES FROM REMOTE DEVICES AND RELATED METHODS AND SYSTEMS - Methods, apparatus and systems are provided for programming a vehicle module. An exemplary vehicle includes a first module, a gateway module communicatively coupled to the first module, and an update module communicatively coupled to the gateway module. The update module is configured to provide authorization information and programming data to the gateway module. The gateway module is configured to verify that programming of the first module is authorized based at least in part on the authorization information and provide the programming data to the first module after verifying that the programming of the first module is authorized. | 2015-04-30 |
20150121072 | OBJECT VERIFICATION APPARATUS AND ITS INTEGRITY AUTHENTICATION METHOD - There is provided an object verification apparatus comprising; a communication module receiving object information to verify an object and integrity of the object, and requesting original object information to an integrity authentication server in which the original object information for the object is registered and receiving the original object information from the integrity authentication server; and a control module determining whether current object information extracted from the object and the object information are identical or not, controlling the communication module according to the determined result, and comparing the original object information and the current object information to verify the final integrity of the object. | 2015-04-30 |
20150121073 | SOFTWARE FINGERPRINTING - A method of providing a receiver with a version of an initial item of software, the method comprising: for each of a plurality of sections of the initial item of software that together form the initial item of software, obtaining one or more respective versions of that section, wherein for at least one of the sections a respective plurality of different versions of that section are obtained; for each of the plurality of sections of the initial item of software, selecting a respective version of that section to be used by the receiver, said selecting being arranged so that the receiver is identifiable from the set of selected versions; and providing the receiver with a version of the initial item of software by providing the receiver with access to the selected versions of the sections of the initial item of software. | 2015-04-30 |
20150121074 | METHODS AND APPARATUS FOR PROTECTING DIGITAL CONTENT - An embodiment of the invention includes a processing system to provide protected digital content, the processing system comprising a processor and control logic which, when used by the processor, results in the processing system performing operations comprising determining first and second receivers, which are coupled to the processing system, are within a predetermined acceptable proximity to the processing system. The processing system is upstream to the first receiver and the first receiver is upstream to the second receiver. Other embodiments are provided herein. | 2015-04-30 |
20150121075 | ELECTRONIC MAIL SENDER VERIFICATION - An e-mail server decrypts attachments of an e-mail message with a key associated with a sending device such that failure of the decryption indicates the e-mail message can be harmful. The sending device inserts its device identifier into the e-mail message as a header and uses an encryption key associated with the device identifier and a digital fingerprint of the sending device to encrypt all attachments of the e-mail message. The delivering e-mail server processes the e-mail message. If the e-mail message contains no identifier, if no key is associated with the parsed identifier, or if attempted encryption fails, the e-mail server determines that the e-mail message is potentially harmful and disarms the e-mail message. | 2015-04-30 |
20150121076 | SIMPLIFYING IKE PROCESS IN A GATEWAY TO ENABLE DATAPATH SCALING USING A TWO TIER CACHE CONFIGURATION - Computational complexity, specifically, cryptographic operations, is removed from the IKE(Internet Key Exchange) process in a VPN gateway appliance, thereby enabling scaling of the number of datapaths that can be managed by a single IKE process. A two-tier cache configuration enables necessary cryptographic operations on packets in the gateway but does so without placing additional computational burdens on the IKE process. One cache containing security association data is local to the IPSec component of the datapath instance. The second cache is higher level and is populated by IKE with security association data upon completion of IKE Phase 2 negotiations. The local cache is searched first for security policy data and if found is used to encrypt/decrypt the data packet. If not found locally, the IKE centralized cache is searched and if found, the local cache is updated with the security association data. | 2015-04-30 |
20150121077 | METHOD AND APPARATUS FOR CONTROLLING LOCK STATE IN ELECTRONIC DEVICE SUPPORTING WIRELESS COMMUNICATION AND SYSTEM THEREFOR - A method and an apparatus for controlling a lock state of an electronic device, and a system therefor are provided. The method includes signing a lock state update request by using a unique key loaded in a confidence region of the electronic device when a lock state change is requested, generating a lock state control request message including the lock state update request, the signed lock state update request, and a certificate of the electronic device, transmitting the generated lock state control request message to a service provider server, and authenticating a lock state update command in a communication processor of the electronic device and updating a state of the communication processor according to the lock state update command when the lock state update command is received from the service provider server. | 2015-04-30 |
20150121078 | APPARATUS, SYSTEMS AND METHODS FOR AGILE ENABLEMENT OF SECURE COMMUNICATIONS FOR CLOUD BASED APPLICATIONS - Embodiments disclosed facilitate secure communication for cloud-based and/or distributed computing applications. In some embodiments, a method may comprise: instantiating a first Virtual Machine (VM) on a cloud infrastructure, wherein the at least one first VM is dynamically configured with a private key and a wildcard security certificate comprising a public key corresponding to the private key, and registering, with a domain name server, a domain name derived from an Internet Protocol (IP) address associated with the first VM and a Common Name associated with the wildcard security certificate. | 2015-04-30 |
20150121079 | SHARED INFORMATION DISTRIBUTING DEVICE, HOLDING DEVICE, CERTIFICATE AUTHORITY DEVICE, AND SYSTEM - A distributing device for generating private information correctly even if shared information is destroyed or tampered with. A shared information distributing device for use in a system for managing private information by a secret sharing method, including: segmenting unit that segments private information into a first through an n | 2015-04-30 |
20150121080 | COMPUTER-BASED OPTIMIZATION OF DIGITAL SIGNATURE GENERATION FOR RECORDS BASED ON EVENTUAL SELECTION CRITERIA FOR PRODUCTS AND SERVICES - A system for generating a digital signature may include a record management facility configured to group a first record with a second record and to generate a first digital signature based at least in part on the first record and the second record. | 2015-04-30 |
20150121081 | COMPUTER-BASED OPTIMIZATION OF DIGITAL SIGNATURE GENERATION FOR RECORDS BASED ON EVENTUAL SELECTION CRITERIA FOR PRODUCTS AND SERVICES - A method for generating a digital signature includes grouping, with a processing device, a first record with a second record, and generating a first digital signature based at least in part on the first record and the second record. | 2015-04-30 |
20150121082 | CRYPTOGRAPHIC WATERMARKING OF CONTENT IN FUEL DISPENSING ENVIRONMENTS - Systems and methods for watermarking content and authenticating watermarked content are provided. Content is rendered on a display while watermarking information embedded in portions of the content are obtained. The watermarking information is verified to authenticate the content. If the content is not authentic, or is not authenticated within a period of time, the content can be terminated or otherwise blocked from rendering on the display. | 2015-04-30 |
20150121083 | METHOD, DEVICE, AND TERMINAL FOR INSTALLING BROWSER PLUG-IN - The present invention relates to mobile terminals and provides a method, device, and terminal for installing a browser plug-in. The method includes: receiving an instruction of installing a browser plug-in which is applied in a designated browser; and judging whether the browser plug-in is legal according to digital signature information of the browser plug-in and browser information of the designated browser, if yes, installing the browser plug-in, otherwise, rejecting the installation of the browser plug-in. At the beginning of the installation of the browser plug-in, the browser plug-in is verified according to the digital signature information of the browser plug-in and the browser information of the designated browser corresponding to the browser plug-in, thus, the legality and traceability of the browser plug-in can be determined to prevent the harmful browser plug-in from calling API of the mobile terminal at random and further to improve the safety of the mobile terminal. | 2015-04-30 |
20150121084 | SECURE MESSAGE TRANSMISSION - A method and system are provided for securing messages within a communication network of an industrial process control system, such as a substation automation system. A multi-block message to be transmitted via a communication network is secured by a block-based authentication, encryption and/or integrity information. Only residue of the previous block in the form of block-based information is needed to generate the block based information of the next block. Therefore, the previous block can already be transmitted while block-based information of the next block is generated. The method and system of the present disclosure enable on-the-fly authentication of the multi-block message and authentication at an increased rate. | 2015-04-30 |
20150121085 | Cookie Information Sharing Method and System - This invention discloses a cookie information sharing method that comprises the following steps: reading cookie information in a parent browser, said parent browser being a browser which stores the cookie information; importing the cookie information read from the parent browser into a child browser, said child browser being a browser which needs to acquiring the cookie information from the parent browser. This application also provides a cookie information sharing system for realizing the proceeding method. The cookie information sharing method and system of this application are able to reduce occupancy of system resources by user's information records, and also to realize sharing of the user's information records. | 2015-04-30 |
20150121086 | SYSTEMS AND METHODS FOR SECURE PROCESSING WITH EMBEDDED CRYPTOGRAPHIC UNIT - Processor system with a general purpose processor and a cryptographic processor dedicated to performing cryptographic operations and enforcing the security of critical security parameters. The cryptographic processor prevents exposure of critical security parameters outside the cryptographic processor itself, and instead implements a limited scripting engine, which can be used by the general purpose processor to execute operations that require the critical security parameters. | 2015-04-30 |
20150121087 | Method and Apparatus for Secure Execution Using a Secure Memory Partition - A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code. | 2015-04-30 |
20150121088 | METHOD OF MANAGING ALIGNED AND UNALIGNED DATA BANDS IN A SELF ENCRYPTING SOLID STATE DRIVE - An apparatus includes a storage medium and a controller. The storage medium generally stores user data in logical pages. The controller may be configured to encrypt and decrypt user data during write and read operations, respectively. The user data is generally in a plurality of data bands. Each data band is encrypted and decrypted using a unique media encryption key. When a boundary between a pair of data bands is within a logical page, the controller may be configured to create two logical page instances, a first logical page instance storing data from a first data band of the pair of data bands and a second logical page instance storing data from a second data band of the pair of data bands. The first and second logical page instances are encrypted and decrypted using the unique media encryption key of the first and second data bands, respectively. | 2015-04-30 |
20150121089 | SYSTEM AND METHOD FOR COPYING FILES BETWEEN ENCRYPTED AND UNENCRYPTED DATA STORAGE DEVICES - Disclosed are systems, methods and computer program products for copying encrypted and unencrypted files between data storage devices. In one aspect, the system detects a request to copy a file from a first data storage device to a second data storage device, determines one or more parameters of the copied file, the first data storage device and the second data storage device, selects, based on the one or more parameters, a file encryption policy for the copies file, and applies the selected encryption policy to the copied file. | 2015-04-30 |
20150121090 | Method and Apparatus for Secure Execution Using a Secure Memory Partition - A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code. | 2015-04-30 |
20150121091 | Data Storage Device Control With Power Hazard Mode - In response to a warning that power may be interrupted, a non-volatile data storage sub-system of a host computer system re-orders machine readable instructions that the non-volatile data storage sub-system is going to perform. This re-ordering of instructions decreases the probability that important data will be lost. The re-ordering of instructions is performed according to rules. | 2015-04-30 |
20150121092 | REAL TIME GENERATING DEVICE - A real time generating device applied in an electronic apparatus is provided. The real time generating device includes a real time clock module and an energy harvesting module. The real time clock module is configured to generate real time information. The energy harvesting module electrically connected to the real time clock module harvests surrounding environment energy to generate electrical energy and supply power to the real time clock module. | 2015-04-30 |
20150121093 | DATA STORAGE DEVICE FOR FORCIBLY DISCHARGING RESIDUAL VOLTAGE, METHOD OPERATING THE SAME, AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A data storage device includes a voltage supply control circuit configured to receive an external voltage, generate different voltages from the external voltage, and supply the different voltages to loads, respectively, through voltage supply lines, respectively and a discharge control circuit configured to discharge residual voltages from the voltage supply lines in response to a control signal and the external voltage, the discharge control circuit configured to discharge the residual voltages in an order of a highest residual voltage to a lowest residual voltage. | 2015-04-30 |
20150121094 | COOPERATIVE REDUCED POWER MODE SUSPENSION FOR HIGH INPUT/OUTPUT ('I/O') WORKLOADS - Method of cooperative reduced power mode suspension for high input/output (‘I/O’) workloads, including: determining, by a transfer monitoring module, a size of a file to be transferred to a recipient, wherein the recipient includes a central processing unit (‘CPU’) operating in a reduced power mode; determining, by the transfer monitoring module, a desired transfer rate for transferring the file to the recipient; calculating, by the transfer monitoring module, an expected transfer completion time in dependence upon the size of the file and the desired transfer rate; and sending, by the transfer monitoring module, a message to the recipient requesting that the CPU suspend the reduced power mode in dependence upon the expected transfer completion time. | 2015-04-30 |
20150121095 | HUB DEVICE FOR UNIVERSAL SERIAL BUS AND POWER MANAGEMENT METHOD THEREOF - A hub apparatus for USB and a power management method thereof are provided. The hub apparatus includes at least one USB-PD port, at least one USB port and a control unit. The control unit detects whether the USB-PD port is connected to a first external device and whether the USB port is contacted to a second external device respectively. When the at least one first external device complies with a USB-PD interface and a connecting situation of the at least one first external device and the at least one second external device are changed, the control unit determines a required power supply determination value according to the connecting situation of the at least one first external device and the at least one second external device, and accordingly, the control unit communicates with the first external device to set a power transmission profile of the at least one USB-PD port. | 2015-04-30 |
20150121096 | SYSTEM AND METHOD FOR CONSERVING POWER CONSUMPTION IN A MEMORY SYSTEM - Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data. | 2015-04-30 |
20150121097 | REDUCED-POWER TRACE ARRAY FOR A PROCESSOR - A trace array having features that provide reduced power consumption/power dissipation in processor circuits. The trace array circuit stores processor states during program execution and provides a resulting trace for subsequent analysis. The trace array includes power management features that, responsive to a control signal, reduce the power consumption of the trace array. A first state of the control signal indicates that the trace array circuit is storing states during the execution of the program and a second state of the control signal is set to enable the trace array for reading the collected states. The trace array may have dynamic read bit-lines and static write bit-lines to further reduce power consumption, and the pre-charge circuits that charge the dynamic read bit-lines may be selectively disabled in response to the first state of the control signal. Write-through may also be selectively disabled and optionally bypassed during state collection. | 2015-04-30 |
20150121098 | DEVICE POWER MANAGEMENT BASED ON DETECTED POWER SOURCE - An aspect provides an information handling device, including: a connection to an external power supply; a processor; and a memory; the memory having instructions executable by the processor to: detect that the connection to the external power supply is providing an input of power; ascertain via the connection to the external power supply that the input of power is derived from a source having a predetermined characteristic; and automatically adjust a power consumption setting of the information handling device based on the predetermined characteristic. Other aspects are described and claimed. | 2015-04-30 |
20150121099 | DATA STORAGE SYSTEM AND METHOD ANALYZING NON-SIGNAL - A non-signal analyzing method for a data storage system including a storage device connected to a host via a data line and a power line includes; communicating a non-signal from the host to the storage device via the power line, detecting the non-signal in the storage device and return the non-signal through to the host via the data line, and analyzing the returned non-signal using a protocol analyzer to generate analysis results characterizing the returned non-signal. | 2015-04-30 |