18th week of 2009 patent applcation highlights part 63 |
Patent application number | Title | Published |
20090113081 | COMMUNICATION APPARATUS, COMMUNICATION PROTOCOL, AND METHODS OF COMMUNICATING BETWEEN DEVICES - A method of wireless communication between personal devices includes wirelessly transmitting and/or wirelessly receiving a message at a low data rate and with low latency data. The message may include at least one of a sync data field, a channel frequency field, a channel period field, a channel type field, a data format field, a control command field, a security field, a network field, a network level field, a manufacturer number field, a device type field, a device number field, a manufacturing date field, a model number field, a device identification field, a field of information to be communicated, and a checksum field. | 2009-04-30 |
20090113082 | Device, System, and Method of Speculative Packet Transmission - Device, system and method of speculative packet transmission. For example, an apparatus for speculative packet transmission includes: a credit-based flow control interconnect device to initiate speculative transmission of a Transaction Layer Packet if a number of available flow control credits is insufficient for completing the transmission. | 2009-04-30 |
20090113083 | Means of control for reconfigurable computers - A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when. | 2009-04-30 |
20090113084 | Controlling transmission on an asynchronous bus - In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed. | 2009-04-30 |
20090113085 | FLUSHING WRITE BUFFERS - A first node to cause flushing data units stored in a write buffer of a second node to a memory of the second node. While using a pin-based approach, the central processing unit (CPU) of the first node may activate a first pin coupled to a second pin of the second node that may cause a sequence of operations to flush the write buffer. While using a control-register based approach, the CPU or the memory controller hub (MCH) may configure the control register using an inter-node path such as the SMBus or a data transfer path that may cause a sequence of operations to flush the write buffer. While using an in-band flush mechanism, the CPU may send a message over the data transfer path after transferring the data units that may cause a sequence of operations to flush the write buffer. | 2009-04-30 |
20090113086 | Method for providing a buffer status report in a mobile communication network - A method for providing a buffer status report in a mobile communication network is implemented between a base station and a user equipment. When data arrives to buffers of the user equipment and the priority of a logical channel for the data is higher than those of other logical channels for existing data in the buffers, a short buffer status report associated with the buffer of a logical channel group corresponding to the arrival data is triggered. The user equipment is based on obtained resources allocated by the base station to fill all data of the buffer of the logical channel group in a Protocol Data Unit. If all data of the buffer of the logical channel group corresponding to the arrival data can be completely filled in the Protocol Data Unit, the short buffer status report is canceled. Otherwise, the user equipment transmits the short buffer status report. | 2009-04-30 |
20090113087 | STREAM DATA TRANSFER CONTROL DEVICE - There are provided a stream I/F section | 2009-04-30 |
20090113088 | METHOD AND DEVICE FOR INTEROPERABILITY IN HETEROGENEOUS DEVICE ENVIRONMENT - System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless interoperability between them. Computer program software and methods of and systems and devices for sharing of content, applications, resources and control across similar and dissimilar permanently or intermittently connected electronic devices. Devices, systems, appliances, and the like communicating and/or interoperating within the framework provided. Interoperability device, such as a DartDevice, provides a highly interoperable device by virtue of its running a compliant player such as a DartPlayer containing an engine such as a DartEngine and at least one communications protocol for connecting to other devices. | 2009-04-30 |
20090113089 | SOUND BOX WITH USB INTERFACE - An exemplary sound box with USB interface includes a power system and a USB interface. The power system includes a power terminal and a ground terminal. The USB interface includes a power terminal and a ground terminal corresponding to the power terminal and a ground terminal of the power system respectively, wherein the power terminal or the ground terminal is connected to the corresponding terminal of the sound box via a rheostat. A voltage received by the power system from the USB interface can be adjusted by the rheostat. | 2009-04-30 |
20090113090 | KEYBOARD - A keyboard is provided with at least one keypad, a housing, and at least one USB port, wherein the USB port is located behind an opening in a top of the housing and the opening is at least partially closed by a dirt and/or dust protector. | 2009-04-30 |
20090113091 | Digital Arts and Crafts Computer Peripheral Toy Device - A computer peripheral toy device is provided that connects to a personal computer and enables a child user to create drawings, animated figures, cards, posters, and other projects and items. The device includes a housing having a drawing tablet and a stylus that connects to the housing for use on the drawing tablet. There a plurality of buttons on the top surface of the housing that a user depresses when engaging in a drawing activity. Computer software is provided for installation on the personal computer in order to display data associated with a drawing activity. When executed by the computer, the computer software causes the computer to respond to the messages received from the controller to engage in a drawing activity using drawing style parameters based on which of the drawing style buttons, color palette buttons and design tool buttons are selected by a user. | 2009-04-30 |
20090113092 | SIGNAL CONVERTER FOR DEBUGGING THAT EXPANDS FIFO CAPACITY - A signal converter includes an interconnect interface, a FIFO set, which comprises a transmitter FIFO and a receiver FIFO respectively connected to the interconnect interface through a data bus, a parallel/serial converter connected to the transmitter FIFO and the receiver FIFO by two data buses respectively and kept apart from the FIFO set, and a serial I/O interface connected to the parallel/serial converter. | 2009-04-30 |
20090113093 | MOBILE STORAGE DEVICE - A mobile storage device is disclosed to include a connection interface connectable to an external electronic apparatus, an adapter interface for the connection of a mobile electronic device, a data storage device formed of a CPU, a charging unit, a voltage converter, a power indicator unit, a signal switch, a memory and a control chip. By means of the control of the CPU and the control of the signal switch and the control chip, storage data is transferable between the external electronic apparatus and the mobile electronic device or between the external electronic apparatus and the memory of the data storage device, and the battery of the charging unit or the battery of the mobile electronic device is chargeable by the external electronic apparatus. | 2009-04-30 |
20090113094 | System for performing a serial communication between a central control block and satellite components - The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information. | 2009-04-30 |
20090113095 | COMPUTER WITH COMPOUND AUDIO INTERFACE - An exemplary computer with compound audio interface includes a chassis, a USB interface arranged in the chassis, an audio interface arranged in the chassis, and a switch arranged in the chassis. The USB interface includes two signal terminals and a ground terminal. The audio interface includes two audio signal terminals and a ground terminal, wherein the audio signal terminals and the ground terminal of the audio interface are connected to the signal terminals and the ground terminal of the USB interface via the switch respectively. The audio signals received by the USB interface can be transmitted to an audio system in the chassis via the audio interface. | 2009-04-30 |
20090113096 | HIGH BANDWIDTH SPLIT BUS - A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment. | 2009-04-30 |
20090113097 | Method and Apparatus for Attaching Multiple Slave Devices to a Single Bus Controller Interface While Supporting Command Pipelining - In a method and apparatus associated with a bus controller, a set of mechanisms are selectively added to the bus controller, as well as to slave devices connected to the bus controller. A mechanism is also added to one or more master devices connected to the bus controller, in order to provide the master devices with a transaction ordering capability. The added mechanisms collectively achieve the objective of supporting connection of multiple slave devices to a common controller interface, and at the same time allowing pipelined operation of the slave devices. One embodiment of the invention is directed to a method for use with a bus and an associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices. The method comprises the steps of connecting one or more of the master devices to one of the master interfaces, and connecting each of a plurality of slave devices to the same one of the slave interfaces. The method further comprises operating a connected master device to send multiple commands to a selected one of the connected slave devices in accordance with a command pipelining procedure. | 2009-04-30 |
20090113098 | Method and Apparatus for Maintaining Memory Data Integrity in an Information Handling System Using Cache Coherency Protocols - An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus controller manages cache coherency bus interfaces to master devices and slave devices. In one embodiment, a master I/O device controller and a slave I/O device controller couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses. | 2009-04-30 |
20090113099 | ARBITER MODULE PROVIDING LOW METASTABILITY FAILURE PROBABILITY - An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units. | 2009-04-30 |
20090113100 | Logic gateway circuit for bus that supports multiple interrupt request signals - A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal output signal, an inverter having an input terminal connected to the interrupt request signal output terminal of the output OR gate and an output terminal, and a plurality of gateway circuits to respectively and selectively device-end interrupt request signals generated by a plurality of target devices to transmit through the gateway circuit to the output OR gate or to queue the device-end interrupt request signals in the gateway circuit. Each gateway circuit includes an AND gate and an OR gate, wherein the OR gate bases on the states of an output terminal of the AND gate and the interrupt request signal output terminal of the output OR gate to generate a gateway signal to a gateway signal input terminal of the AND gate. | 2009-04-30 |
20090113101 | ADAPTER FOR USB INTERFACE - An adapter for USB interfaces, includes a cable, and two interface units respectively electrically connected to ends of the cable. Each of the interfaces includes a main body and two different types of USB interfaces extending from the main body. | 2009-04-30 |
20090113102 | DETACHABLE EXPANSION DEVICE AND HOST - A host having a casing, a motherboard, and at least a detachable expansion device is provided. The casing has at least an expansion bay. The motherboard is disposed in the casing and has at least a bus expansion portion. The detachable expansion device is detachably disposed in the expansion bay and includes a circuit board, at least a bus connector, a panel, and at least a transmission portion. The bus connector is electrically connected to the circuit board and has a connection port. The panel is connected to a first side of the circuit board and exposes the connection port. A surface of the panel and the connection port are exposed outside the casing. The transmission portion is disposed on the circuit board and electrically connected to the circuit board. The bus connector is electrically connected to the bus expansion portion through the transmission portion. | 2009-04-30 |
20090113103 | CASCADE TYPE CHARGE ASSEMBLY - A cascade type charge assembly is provided. The cascade type charge assembly is shaped in an expansion card and can be detached according to different purposes. The cascade type charge assembly comprises at least a first adapter, a second adapter, a third adapter, and a cover. A first type universal serial bus (USB) connecting line is disposed on one side of the first adapter for electrically connecting to a computer, and a second type USB connector is disposed on the other side of the first adapter. The second adapter has a side to be cascaded with the second type USB connector, and at least one cylindrical male plug is disposed on the other of the second adapter. The third adapter has a side to be cascaded with the at least one cylindrical male plug, and an electrical connector disposed on the other side of the third adapter, which can be accommodated within the cover. | 2009-04-30 |
20090113104 | INPUT DEVICES AND METHODS OF OPERATING SAME - Input devices and methods of operating the same are described. In one aspect, an apparatus includes a housing, a display screen, a main input device, a wireless receiver, a carrier bay, and an auxiliary input device. The main input device translates user manipulations of the main input device into control signals. The auxiliary input device is sized and arranged to be carried in and attached to the carrier bay in a docked state and detached from the carrier bay in an undocked state. In the undocked state, the auxiliary input device translates user manipulations of the auxiliary input device into control signals and wirelessly transmits the control signals for reception by the wireless receiver. In the docked state, the auxiliary input device is unresponsive to user manipulations of the auxiliary input device. The apparatus additionally includes a graphics controller in the housing that presents a graphical user interface on the display screen in accordance with the control signals received by the wireless receiver from the main input device and the auxiliary input device. | 2009-04-30 |
20090113105 | Method of operation of a portable computer apparatus with thermal enhancements and multiple modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
20090113106 | Method of fabrication of a portable computer apparatus with thermal enhancements and multiple modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
20090113107 | DIFFERENTIAL TRANSMITTER CIRCUIT - A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated. | 2009-04-30 |
20090113108 | BUS TERMINATOR/MONITOR/BRIDGE SYSTEMS AND METHODS - Computing systems including first and second processors configured to control first and second buses, respectively, and a terminator-monitor-bridge (TMB) device coupled between the first and second buses are provided. The TMB device is configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively. TMB devices and methods for operating the TMB devices in accordance with the above configuration are also provided. | 2009-04-30 |
20090113109 | Using Virtual Machine Cloning To Create a Backup Virtual Machine in a Fault Tolerant System - Techniques for creating a fault tolerant system in a virtual machine environment utilize a primary VM and a backup VM. To initialize the fault tolerant system, the backup VM and primary VM start from the same state. To achieve this in one embodiment, the primary VM is suspended and the state of the primary VM is copied to the backup VM. Once the backup VM has received all the primary VM's state, the primary VM is resumed. Subsequent state changes of the primary VM are buffered until the backup VM resumes, connects to the primary VM, and starts consuming the buffered content. Thereafter, synchronization is maintained by the primary VM's writing relevant state changes to a log and the backup VM's reading such relevant state changes from the log. | 2009-04-30 |
20090113110 | Providing VMM Access to Guest Virtual Memory - A virtual-machine-based system provides a mechanism for a virtual machine monitor (VMM) to process a hypercall received from an application running in the virtual machine (VM). A hypercall interface causes the virtual memory pages, needed by the VMM to process the hypercall, to be available to the VMM. In one embodiment, when virtual memory pages needed by the VMM to process the hypercall are not available to the VMM, the application is caused to access the needed pages, in response to which the required virtual memory becomes available to the VMM. | 2009-04-30 |
20090113111 | SECURE IDENTIFICATION OF EXECUTION CONTEXTS - A virtual-machine-based system that identifies an application or process in a virtual machine in order to locate resources associated with the identified application. Access to the located resources is then controlled based on a context of the identified application. Those applications without the necessary context will have a different view of the resource. | 2009-04-30 |
20090113112 | DATA STORAGE DEVICE, MEMORY SYSTEM, AND COMPUTING SYSTEM USING NONVOLATILE MEMORY DEVICE - Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories. | 2009-04-30 |
20090113113 | METHOD AND APPARATUS FOR SANITIZING OR MODIFYING FLASH MEMORY CHIP DATA - A method and apparatus is provided for individually checking, sanitizing and/or otherwise altering data bits of a plurality of memory chips via one or more processes where the memory chips being processed at any given time may be of different unformatted memory capacities, may be of different memory types, and may have the process started at different times. The method utilizes a computer based program capable of multithreaded operation whereby a new procedure thread is initiated upon a determination by the main program that a given reader port is in recent initial communication with a memory chip. | 2009-04-30 |
20090113114 | Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip - System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller. | 2009-04-30 |
20090113115 | NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY - A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode. | 2009-04-30 |
20090113116 | Digital content kiosk and methods for use therewith - A digital content kiosk and methods for use therewith are disclosed. Various embodiments are disclosed relating to exemplary memory devices, memory architectures, and programming techniques that can be used with a digital content kiosk, exemplary mechanical and electrical components of a digital content kiosk, exemplary security aspects of a digital content kiosk, and exemplary uses of a digital content kiosk. Other embodiments are disclosed, and each of these embodiments can be used alone or in combination with one another. | 2009-04-30 |
20090113117 | RE-FLASH PROTECTION FOR FLASH MEMORY - A method for storing data includes providing a memory package including an integrated circuit containing a non-volatile memory and counter circuitry. The data is written to the non-volatile memory. The counter circuitry is operated to maintain a count of write operations performed on the non-volatile memory. The data and the count from the memory package are received at a controller, separate from the memory package, and the data is authenticated in response to the count. | 2009-04-30 |
20090113118 | MEMORY MODULE AND CONTROL METHOD OF SERIAL PERIPHERAL INTERFACE USING ADDRESS CACHE - A serial peripheral interface memory module using address cache comprises a flash memory array for storing data, a serial/parallel convertor for receiving serial signals and generating a control command, an address and data, an address register, an address accumulator for accumulating the address in the address register and storing the accumulated address back to the address register, and a flash memory controller for controlling the access to the flash memory array. When the control command is a standard command, the serial/parallel controller first stores the address following the control command into the address register and then the flash memory controller accesses data according to the address in the address register. When the control command is a specific command, the flash memory controller directly accesses data according to the address in the address register without waiting for an address update. | 2009-04-30 |
20090113119 | DATA WRITING METHOD - Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit. | 2009-04-30 |
20090113120 | States Encoding in Multi-Bit Cell Flash Memory for Optimizing Error Rate - To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware. | 2009-04-30 |
20090113121 | Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes - A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables. | 2009-04-30 |
20090113122 | CONTENT ADDRESSABLE MEMORY DEVICE HAVING MATCH LINE EQUALIZER CIRCUIT - In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other. | 2009-04-30 |
20090113123 | SYSTEM AND METHOD FOR USING REVERSED BACKUP OPERATION FOR MINIMIZING THE DISK SPINNING TIME AND THE NUMBER OF SPIN-UP OPERATIONS - A system and method for providing reversed backup operation for keeping local hard drives in a stand-by (non-spinning) mode thereby extending the life of local hard drives and reducing power consumption, heat and noise produced by the local drives. The present invention uses remote storage systems as primary storage systems when the network connectivity and its bandwidth are sufficient so that the local hard disk can stay in the stand-by mode. If the network connectivity is unavailable or insufficient to handle the data flow, the local hard disk is spun up and temporarily used as the primary storage for reads and writes. When necessary and possible, the data on both storage locations is synchronized. | 2009-04-30 |
20090113124 | VIRTUAL COMPUTER SYSTEM AND METHOD OF CONTROLLING THE SAME - In a virtual computer system controlling a disk volume and a virtual server which is connected to the disk volume, to which the area of the disk volume is allocated as a virtual disk and which executes a process using the allocated virtual disk, the virtual computer system erases information stored in the virtual disk allocated to the virtual server to be deleted correspondingly with the deletion of the virtual server. According to another embodiment of the present invention, an administrative server is provided to select a server system which is low in load from among plural server systems controlling virtual servers as a server system for erasing information stored in the virtual disk allocated to the virtual server to be deleted. | 2009-04-30 |
20090113125 | Electronic apparatus, disk switching method and computer program - There is provided an electronic apparatus including a plurality of hard disk drives having a standby state and an active state as power application state. The electronic apparatus includes a drive setting portion to set each of the plurality of hard disk drives to a cache hard disk drive or a storage hard disk drive so as to use one hard disk drive in the active state as a cache hard disk drive and use a remaining hard disk drive as a storage hard disk drive, and a power control portion to control application of power to each of the hard disk drives according to setting by the drive setting portion. | 2009-04-30 |
20090113126 | Method and apparatus for full backups in advance - An improved system and method are disclosed for the backup and restoration of data. An init image is created for a new system. Data is uploaded from a current system and a data image is generated. The resulting data image and the init image are combined to create a combined data image, which is then stored on an on-line backup host. A copy of the combined data image is transferred to the new system. The uploaded data is extracted from the copy of the combined data image and stored on the new system in the same location as the original system. Metadata describing the location of the combined data on the new system is captured and then applied to the combined data image stored on the on-line backup host. The extracted data on the new system is compared to the current data on the original system and the new system is updated. A differential backup is performed on the new system and then uploaded to the on-line backup host, where it is associated with the combined data image. | 2009-04-30 |
20090113127 | RAID Storage system with tandem operation using multiple virtual profiles - An improved RAID storage system adapted to selectively and automatically store the same data “in tandem” using two different storage profiles. In one embodiment, a first store operation occurs in accordance with first storage profile and, if a flag in the first storage profile is set, a second store operation automatically occurs in accordance with a second storage profile but with the same data as stored in the first store operation. The first and second storage profiles are stored sequentially in profile registers within a controller in the storage system. To speed the tandem operation, the data may be held in a re-readable FIFO buffer in the controller. The buffer is sized to hold the minimum size of data that can be stored to the physical disks in the storage system. Preferably, the size of the buffer is substantially equal to the minimum size. | 2009-04-30 |
20090113128 | METHOD AND SYSTEM FOR PREVENTING VIRUS INFECTIONS VIA THE USE OF A REMOVABLE STORAGE DEVICE - A method and system for preventing virus infections via the use of a removable storage device are described. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of gathering a first set of information associated with the removable storage device, processing the first set of information to generate a second set of information also associated with the removable storage device, sending the second set of information to the computer to cause the computer to identify the removable storage device as a read-only device, accessing an antivirus program stored in the removable storage device and causing the antivirus program to be launched on the computer, and sending a third set of information to the computer after the antivirus program is launched on the computer to cause the computer to identify the removable storage device as a writable device. | 2009-04-30 |
20090113129 | HIGHLY AVAILABLE REMOVABLE MEDIA STORAGE NETWORK ENVIRONMENT - A removable media storage network environment employs a media management system for managing a removable media system on behalf of client applications, and a media management agent to enhance the management of the removable media system by the media management system. The media management agent operates to determine an operational state of the removable media system, and to enhance an availability and a performance of the removable media system as managed by a media management system, wherein one or more one error recovery techniques are conditionally initiated based on the determined operational state of the removable media system and wherein the media management system is conditionally reconfigured based on the determined operational state of the removable media system. | 2009-04-30 |
20090113130 | SYSTEM AND METHOD FOR UPDATING DIRTY DATA OF DESIGNATED RAW DEVICE - A system and method for updating dirty data of designated raw device is applied in Linux system. A format of a command parameter for updating the dirty data of the designated raw device is determined, to obtain the command parameter with the correct format and transmit it into the Kernel of the Linux system. Then, a data structure of the designated raw device is sought based on the command parameter, to obtain a fast search tree of the designated raw device. Finally, all dirty data pages of the designated raw device are found by the fast search tree, and then are updated into a magnetic disk in a synchronous or asynchronous manner. Therefore, the dirty data of an individual raw device can be updated and written into the magnetic disk without interrupting the normal operation of the system, hereby ensuring secure, convenient, and highly efficient update of the dirty data. | 2009-04-30 |
20090113131 | METHOD AND APPARATUS FOR TRACKING LOAD-MARKS AND STORE-MARKS ON CACHE LINES - Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed. | 2009-04-30 |
20090113132 | PREFERRED WRITE-MOSTLY DATA CACHE REPLACEMENT POLICIES - A computer-implemented method of cache replacement includes steps of: determining whether each cache block in a cache memory is a read or a write block; augmenting metadata associated with each cache block with an indicator of the type of access; receiving an access request resulting in a cache miss, the cache miss indicating that a cache block will need to be replaced; examining the indicator in the metadata of each cache block for determining a probability that said cache block will be replaced; and selecting for replacement the cache block with the highest probability of replacement. | 2009-04-30 |
20090113133 | Synchronous Memory Having Shared CRC and Strobe Pin - A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC | 2009-04-30 |
20090113134 | Method and Cache Control Circuit for Replacing Cache Lines Using Alternate PLRU Algorithm and Victim Cache Coherency State - A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use. | 2009-04-30 |
20090113135 | MECHANISM FOR DATA CACHE REPLACEMENT BASED ON REGION POLICIES - A system and method for cache replacement includes: augmenting each cache block in a cache region with a region hint indicating a temporal priority of the cache block; receiving an indication that a cache miss has occurred; and selecting for eviction the cache block comprising the region hint indicating a low temporal priority. | 2009-04-30 |
20090113136 | CACHING FOR STRUCTURAL INTEGRITY SCHEMES - A method for data integrity protection includes storing items of data in a plurality of data blocks in a storage medium. Respective block signatures are stored in an integrity structure in the storage medium. A block signature of the given data block is computed in response to a first request to read a first data item from a given data block, and the computed signature is verified against a stored signature read from the integrity structure. The verified block signature is saved in a secure cache. The block signature is recomputed upon receiving a second request to read a second data item, subsequent to the first request, and is verified against the verified block signature in the secure cache. The data item is output from the storage medium in response to verifying the recomputed block signature. | 2009-04-30 |
20090113137 | PSEUDO LEAST RECENTLY USED (PLRU) CACHE REPLACEMENT - A multi-way cache system includes multi-way cache storage circuitry, a pseudo least recently used (PLRU) tree state representative of a PLRU tree, the PLRU tree having a plurality of levels, and PLRU control circuitry coupled to the multi-way cache storage circuitry and the PLRU tree state. The PLRU control circuitry has programmable PLRU tree level update enable circuitry which selects Y levels of the plurality of levels of the PLRU tree to be updated. The PLRU control circuitry, in response to an address hitting or resulting in an allocation in the multi-way cache storage circuitry, updates only the selected Y levels of the PLRU tree state. | 2009-04-30 |
20090113138 | Combined Response Cancellation for Load Command - A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption. | 2009-04-30 |
20090113139 | Avoiding snoop response dependency - In one embodiment, the present invention includes a method for receiving a request for data in a home agent of a system from a first agent, prefetching the data from a memory and accessing a directory entry to determine whether a copy of the data is cached in any system agent, and forwarding the data to the first agent without waiting for snoop responses from other system agents if the directory entry indicates that the data is not cached. Other embodiments are described and claimed. | 2009-04-30 |
20090113140 | Reducing latency in responding to a snoop request - In one embodiment, the present invention includes a method for receiving a snoop request, providing the snoop request to a coherency engine along a first path and providing the snoop request to a bypass logic along a bypass path, and generating a speculative invalid snoop response in the bypass logic and forwarding the speculative invalid snoop response to indicate that an address associated with the snoop response is not present in a cache memory. Other embodiments are described and claimed. | 2009-04-30 |
20090113141 | MEMORY PROTECTION SYSTEM AND METHOD - A shared memory controller is provided for controlling access to a shared memory by a plurality of processors. At least one device includes a storage area for storing a respective address range for each of a plurality of memory regions. The at least one device further includes a permission table containing, for each of the plurality of memory regions, read and write permission data for each of the plurality of processors. A memory fault detector is coupled to the at least one device and has an input for receiving a memory access request including a memory address, a processor identification and a read/write indicator. The memory fault detector includes logic for determining whether a memory access according to the memory access request would conflict with the read and write permission data in the permission table. | 2009-04-30 |
20090113142 | STORAGE HAVING LOGICAL PARTITIONING CAPABILITY AND SYSTEMS WHICH INCLUDE THE STORAGE - A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs. | 2009-04-30 |
20090113143 | SYSTEMS AND METHODS FOR MANAGING LOCAL AND REMOTE MEMORY ACCESS - A memory management unit (MMU) in an information handling system includes a translation module operable to receive a memory request identifying a memory address, and determine whether the identified memory address corresponds to a local memory resource associated with the information handling system or a remote memory resource coupled to the information handling system via a network. The MMU also includes at least one local memory access module operable to facilitate access to local memory resources if the memory address corresponds to a local memory resource, and at least one remote memory access module operable to facilitate access to remote memory resources via the network if the memory address corresponds to a remote memory resource. | 2009-04-30 |
20090113144 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, an electronic device includes a main memory, a main controller which controls the main memory, a system BIOS which stores default access parameter data of the main memory, a substrates including a memory device installing region in which the main memory and a memory device storing other access parameter data of the main memory are to be installed, and a setting section which sets, when a memory device is installed in the memory device installing region, access parameter data read out from the memory device to the memory controller, and sets, when a memory device is not installed in the memory element region, access parameter data read out from the system BIOS to the memory controller. | 2009-04-30 |
20090113145 | DATA TRANSFER - An apparatus, for connection to a storage device, comprising: a module for communication with a software application and operable to receive instructions to copy data to the storage device; a chunking and identifier generation module operable to receive the data, to process the data into one or more chunks, to generate a first chunk identifier, representative of the identity of a first of the or each chunk of data and, upon processing of the data, to initiate the issuance of a confirmation signal to the software application indicating that the data has been copied to the storage device; and an interface for communication with the storage device, wherein the interface is operable to send the first chunk identifier to the storage device, and to send the first chunk of data to the storage device upon receipt of a transfer instruction from the storage device. | 2009-04-30 |
20090113146 | SECURE PIPELINE MANAGER - A method for data storage includes supplying data to and from a host to a storage memory via a secure data path. A first CPU is employed to control operation of the storage memory, and a second CPU is employed to control operation of the secure data path. | 2009-04-30 |
20090113147 | ACCESS CONTROL APPARATUS AND ACCESS CONTROL METHOD - An access control apparatus includes a memory and a command executor executing an access process on a command with the command completion time limit. An address of an inaccessible recording area is stored in the memory. Data attempted to be written on the inaccessible recording area is obtained. The data is stored in association with the address in the memory. An automated alternate processor executes the automated alternate process of the inaccessible recording area in a predefined period of time after the process executed by the command executor is completed. A memory updater deletes the address of the inaccessible recording area whose automated alternate process has succeeded and the data attempted to be written in the recording area at the address. | 2009-04-30 |
20090113148 | METHODS FOR RESERVING INDEX MEMORY SPACE IN AVI RECORDING APPARATUS - A method for reserving memory space for storing chunk sizes during Audio Video Interleave (AVI) recording, wherein an AVI file contains a plurality of interleaved audio-video (A/V) chunks, includes: recording the AVI file sizes to the second storage; when the second storage reaches capacity, moving at least a first A/V chunk size to the first storage; and after the recording has finished, reading stored A/V chunks from the first storage to the second storage to create an index chunk. | 2009-04-30 |
20090113149 | STORAGE APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE SYSTEM - An object of the invention is to provide a storage apparatus that can effectively reduce power consumption without degrading response performance, a control method therefor, and a storage system. A journal (or more than one journals) that contains data volume modification history information is (are) created based on write data; the thus created journal is held in cache memory, or saved in a journal volume when necessary; the journal held by the cache memory or saved in the journal volume is transferred to an external storage device, and the proportion of the cache memory used for the journal is monitored during the above processes; and the journal volume is de-activated if the proportion is not more than a predetermined first threshold value, and activated if the proportion exceeds the first threshold value. | 2009-04-30 |
20090113150 | Storing Data Blocks - A method of storing data blocks onto sectors of a storage device comprises determining a specific number n of blocks, where n is greater than 1, storing n blocks consecutively onto consecutive sectors, such that each block begins directly after the previous block ends, repositioning the storing at the beginning of the next sector, and storing a further n blocks consecutively onto consecutive sectors, such that each block begins directly after the previous block ends. | 2009-04-30 |
20090113151 | Storage controller, storage system, and storage controller control method - A storage controller of the present invention can specify an updated file based on an updated block detected when a differential backup is carried out for a plurality of generations, and can carry out a virus scan for the updated file only. Difference data generated between a primary volume and a backup volume is managed in difference volumes of different generations. A file updated by the host is specified based on an updated block in which the difference data is stored. A virus scan, which makes use of the latest virus pattern file, is executed for this updated file. Furthermore, search information related to the updated file can be created, and this search information can also be saved. | 2009-04-30 |
20090113152 | STORAGE SYSTEM GROUP - A first storage system comprises a first logical volume, and a first controller that has a first memory. A second storage system comprises a second physical storage device that constitutes the basis of a second logical volume and a journal area, and a second controller that has a second memory. At least the first memory stores a write unit size, which is the size of a write data element. The journal area is a storage area in which is stored a journal data element, which is a data element that is stored in any block of a plurality of blocks configuring the first and/or second logical volume, or a data element that is written to this block. The size of the journal data element, and the size of the respective blocks that are managed as the respective components of the first and second logical volumes are the write unit size. | 2009-04-30 |
20090113153 | STORAGE SYSTEM GROUP - There is a journal area and one or more logical volumes comprising a first logical volume. The journal area is a storage area in which is stored a journal data element, which is a data element that is stored in any storage area of a plurality of storage areas configuring a logical volume, or a data element that is written to the storage area. A controller has a size receiver that receives a write unit size, which is the size of a write data element received from a computer, and a size setting unit that sets the received write unit size in a memory for one or more logical volumes. The size of a journal data element stored in a journal area based on the set write unit size is the write unit size. | 2009-04-30 |
20090113154 | Non-Volatile Memory Apparatus and Method of Accessing the Same - A non-volatile memory apparatus and an accessing method thereof are provided. A host accesses the non-volatile memory apparatus and gets the accessing result according to the predetermined protocol. Therefore, the host can identify whether the non-volatile memory apparatus has a data area or not and switch to access the data area. The host can then access the non-volatile memory apparatus with high capacity without changing the hardware of the host. | 2009-04-30 |
20090113155 | HARDWARE ANTI-PIRACY VIA NONVOLATILE MEMORY DEVICES - One embodiment of the present disclosure may take the form of protected or safeguard memory, such as a nonvolatile memory device. In operation, the nonvolatile memory device may not perform a command operation, such as a read operation, on locked password-protected sectors of a primary memory array. Once a password is provided to the nonvolatile memory device (for example, from or via an associated electronic device), the nonvolatile memory device may unlock the password-protected sectors. | 2009-04-30 |
20090113156 | MANAGEMENT METHOD OF PERFORMANCE HISTORY AND A MANAGEMENT SYSTEM OF PERFORMANCE HISTORY - A performance history management method and system are disclosed, in which the time-series performance history such as a volume included in a storage device is managed as one time-series performance history at the time of data rearrangement or device change. The data-oriented performance history providing the logical place of storage of the data stored in the volume is generated using the storage performance monitor program based on the rearrangement history information providing the information on the history of transfer of the data stored in the rearrangement history table and the volume of the storage device by the storage structure information acquisition program, the storage structure information stored in the storage structure information table and the performance history of each volume stored in the storage performance history table by the storage performance information acquisition program. The performance history can be displayed or the performance change detected to display an alert. | 2009-04-30 |
20090113157 | INITIALIZING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE HAVING BANK ACTIVE CONTROL CIRCUIT - An initializing circuit initializing a semiconductor memory device includes a command generating circuit generating a mode register set command in response to a reset command signal, a mode register set control circuit producing a reset signal in response to the mode register set command, and a bank active control circuit resetting the semiconductor memory device by generating an all-bank precharge command in response to the reset signal. | 2009-04-30 |
20090113158 | METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew. | 2009-04-30 |
20090113159 | Data processing with time-based memory access - Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access. | 2009-04-30 |
20090113160 | Method and System for Reorganizing a Storage Device - A method and system for reorganizing a storage device such as a disk drive or partition thereof represents the storage device as a set of concentric circles, with each circle containing blocks of storage with the concentric circles having a differing numbers of blocks of storage resulting in differing radii of the concentric circles. More frequently used files are moved towards the outer circles with larger radii, and less frequently used, often archival, files are moved to the inner circles of lesser radius, all under user control. Additionally, the storage device is represented similarly as concentric circles of blocks of storage, with the blocks displayed potentially containing parts of multiple files, and files being contained in multiple blocks. Users can zoom in or out, with more or fewer blocks displayed. | 2009-04-30 |
20090113161 | METHOD, APPARATUS AND PROGRAM PRODUCT FOR MANAGING MEMORY IN A VIRTUAL COMPUTING SYSTEM - A method for managing memory in a virtual computing system is provided. The method comprises providing updated monitor data for a plurality of data domains in the virtual computing system and determining based upon the updated monitor data provided whether there is a memory constraint in a memory of the virtual computing system. Further, the method comprises calculating based upon the updated monitor data, when the memory constraint is determined, a total release-amount of the memory that is to be released by the virtual computing system in order to relieve the memory constraint and issuing a notification to release the total release-amount of the memory in order to relieve the memory constraint. The method further comprises assessing based upon the updated monitor data, when the memory constraint is ended, a reuse-amount that can be reused by the plurality of virtual guests. | 2009-04-30 |
20090113162 | METHODS, SYSTEMS, AND DEVICES FOR MANAGEMENT OF A MEMORY SYSTEM - Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate of deactivate a memory block in response to a system call from the power savings manager. | 2009-04-30 |
20090113163 | Method and apparatus for managing a memory for storing potentially configurable entries in a list - A method and apparatus for managing a memory for storing potentially configurable entries in a list, associated with a resource coupled to a central resource manager, is provided. A number of potentially configurable entries in the list are determined. A block of memory for storing data associated with each potentially configurable entry is allocated from the memory. If the block of memory is insufficient for storing the data, at least one extended block of memory is allocated from the memory, for storing the data. | 2009-04-30 |
20090113164 | Method, System and Program Product for Address Translation Through an Intermediate Address Space - In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address. | 2009-04-30 |
20090113165 | Method and System for Automatically Distributing Real Memory Between Virtual Memory Page Sizes - A method, system and computer program product for allocating real memory to virtual memory page sizes when all real memory is in use is disclosed. In response to a page fault, a page frame for a virtual page is selected. In response to determining that said page does not represent a new page, a page is paged-in into said page frame a repaging rate for a page size of the page is modified in a repaging rates data structure. | 2009-04-30 |
20090113166 | HASHING METHOD FOR NAND FLASH MEMORY - In accordance with exemplary embodiments, a flash memory, such as a NAND flash memory, selectively updates blocks based on hash values associated with the blocks, wherein the hashing codes are generated for each block from the software image to be programmed into the flash memory. Selectively updating blocks in accordance with an embodiment of the present invention might reduce re-programming time and potentially destructive pre-mature aging of cells in the flash memory. | 2009-04-30 |
20090113167 | DATA PROCESSING APPARATUS AND METHOD OF PROCESSING DATA - Data processing apparatus comprising: a chunk store containing specimen data chunks, a manifest store containing at least one manifest that represents at least a part of a data set and that comprises at least one reference to at least one of said specimen data chunks, a sparse chunk index containing information on only those specimen data chunks having a predetermined characteristic, the processing apparatus being operable to process input data into input data chunks and to use the sparse chunk index to identify at least one of said at least one manifest that includes at least one reference to one of said specimen data chunks that corresponds to one of said input data chunks having the predetermined characteristic. | 2009-04-30 |
20090113168 | Software Pipelining Using One or More Vector Registers - A method for managing multiple values assigned to a variable during various stages of a software pipelined process executed in a computing environment. The method comprises allocating two or more slots in a vector register to two or more values associated with said variable during two or more stages of a pipeline process; and rotating values in each slot responsive to an instruction. | 2009-04-30 |
20090113169 | RECONFIGURABLE ARRAY PROCESSOR FOR FLOATING-POINT OPERATIONS - A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation. | 2009-04-30 |
20090113170 | Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations - A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions. | 2009-04-30 |
20090113171 | TPM DEVICE FOR MULTI-PROCESSOR SYSTEMS - In one embodiment, a computer system comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, at least one programmable trusted platform management device coupled to the processor via a hardware path which goes through at least one trusted platform management device controller which manages operations of the at least one programmable trusted platform device, and a routing device to couple the first and second computing cells. | 2009-04-30 |
20090113172 | NETWORK TOPOLOGY FOR A SCALABLE MULTIPROCESSOR SYSTEM - A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters. | 2009-04-30 |
20090113173 | COMPUTER SYSTEM AND METHOD THAT ELIMINATES THE NEED FOR AN OPERATING SYSTEM - A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices. Instead, the device microcontroller uses the embedded device driver to perform configuration and self diagnostic test as well as device operations. If the device is operational, the device microcontroller sends an identification signal to the hardware/firmware layer of the present to indicate availability of the device. | 2009-04-30 |
20090113174 | Sign Operation Instructions and Circuitry - A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value of a second operand, and an arithmetic inverse of the second operand value, in response to the sign bit of the first operand. This logic circuitry is arranged to operate according to | 2009-04-30 |
20090113175 | Processor architecture for concurrently fetching data and instructions - In one embodiment, a processor architecture for concurrently fetching data and patched instructions includes a microprocessor, an instruction patch, a dedicated instruction memory, a patch memory, and a dedicated data memory. The instruction patch is coupled to the microprocessor by an instruction bus, and is also coupled to the dedicated instruction memory and the patch memory. The patch memory and the dedicated data memory are coupled to the microprocessor by a data bus separate from the instruction bus. In one embodiment, the instruction patch has a number of comparators that can be individually enabled by respective enable signals. Each comparator that is enabled compares every bit on an instruction address with a corresponding bit of a patched instruction address to detect a patch condition. When a patch condition is detected, patched instructions are fetched from the patch memory, while the microprocessor can concurrently fetch data from the dedicated data memory. | 2009-04-30 |
20090113176 | Method of reducing data path width restrictions on instruction sets - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-04-30 |
20090113177 | INTEGRATED CIRCUIT WITH DMA MODULE FOR LOADING PORTIONS OF CODE TO A CODE MEMORY FOR EXECUTION BY A HOST PROCESSOR THAT CONTROLS A VIDEO DECODER - A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address. | 2009-04-30 |
20090113178 | Microprocessor based on event-processing instruction set and event-processing method using the same - Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated. | 2009-04-30 |
20090113179 | OPERATIONAL PROCESSING APPARATUS, PROCESSOR, PROGRAM CONVERTING APPARATUS AND PROGRAM - The present invention provides an operational processing apparatus which can guarantee a period for executing instructions in the shortest cycle when the operational processing apparatus synchronizes with a hardware accelerator. A processor in the present invention simultaneously issues and executes instructions including instruction groups having a simultaneously issueable instruction. The processor executes a program including a specific instruction. The specific instruction instructs to exclude an instruction subsequent to the specific instruction out of the instruction groups including the specific instruction, and to suspend issuing the instruction subsequent to the specific instruction only during a predetermined period immediately after the specific instruction is issued. | 2009-04-30 |
20090113180 | Fetch Director Employing Barrel-Incrementer-Based Round-Robin Apparatus For Use In Multithreading Microprocessor - A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities. | 2009-04-30 |