17th week of 2014 patent applcation highlights part 61 |
Patent application number | Title | Published |
20140115289 | DATA MIGRATION SYSTEM AND DATA MIGRATION METHOD - A second storage maps a migration source volume to a virtual volume of a migration destination volume according to storage virtualization technology. A host system including a host switches an access path from an access path to the migration source volume to an access path to the migration destination volume. The second storage executes copy processing of migrating, from the migration source volume to the migration destination volume, data in an assigned area of a virtual volume according to thin provisioning of the migration source volume based on the information contained in the first thin provisioning information in the first storage, and copying that data from the migration destination volume to a virtual volume according to thin provisioning of a copy destination volume in the second storage. The second storage associates the virtual volume of the copy destination volume with the migration destination volume in substitute for the original virtual volume. | 2014-04-24 |
20140115290 | SYSTEM AND METHOD FOR MIGRATION OF DIGITAL ASSETS - In accordance with the present disclosure, an information handling system for migrating digital assets may include a storage medium and a processor. The storage medium may be configured to store information regarding digital assets to be migrated from a source system to a target system. The processor may be configured to, for each of one or more digital assets of the source system, determine if the digital asset is a candidate for migration to a cloud storage provider. The processor may also be configured to, for each digital asset determined to be a candidate for migration to the cloud storage provider, determine if a user desires to migrate the digital asset to the cloud storage provider. The processor may further be configured to, for each digital asset the user desires to migrate to the cloud storage provider, transfer the digital asset from the source system to the cloud storage provider. | 2014-04-24 |
20140115291 | NUMA OPTIMIZATION FOR GARBAGE COLLECTION OF MULTI-THREADED APPLICATIONS - Methods and systems for garbage collection are provided. The method includes and the system is configured for assigning a garbage collection thread to execute on a first node of a plurality of nodes in a non-uniform memory access (NUMA) computing system, determining whether each of a plurality of application threads is a local thread that is active on the first node, and selecting the local thread for garbage collection by the garbage collection thread when the local thread is active on the first node. | 2014-04-24 |
20140115292 | DYNAMIC OBFUSCATION OF HEAP MEMORY ALLOCATIONS - Techniques, methods, systems, and computer-readable media for allocating and managing dynamically obfuscated heap memory allocations are described. In one embodiment a memory manager in a data processing system contains an addressor, to determine a first address of a program object in a first memory address space, and one or more encoders, to abstract memory access to the program object using the first address such that layout of the object data in the first address space differs from the layout of the object in a second address space. In one embodiment, a runtime system modifies object code of an executable file to include encoder routines to abstract memory accesses to data in an obfuscated heap. In one embodiment, a compiler system using an intermediate representation of a high level program generates an intermediate representation of a high level program capable of performing memory writes and memory reads using obfuscation encoder routines. | 2014-04-24 |
20140115293 | APPARATUS, SYSTEM AND METHOD FOR MANAGING SPACE IN A STORAGE DEVICE - Aspects of the present disclosure disclose systems and methods for managing space in storage devices. In various aspects, the disclosure is directed to providing more efficient method for managing free space in the storage system, and related apparatus and methods. In particular, the system provides for freeing blocks of memory that are no longer being used based on the information stored in a file system. More specifically, the system allows for reclaiming of large segments of free blocks at one time by providing information on aggregated blocks that were being freed to the storage devices. | 2014-04-24 |
20140115294 | MEMORY PAGE MANAGEMENT - According to one embodiment, a method for operating a memory device includes receiving a first request from a requestor, wherein the first request includes accessing data at a first memory location in a memory bank, opening a first page in the memory bank, wherein opening the first page includes loading a row including the first memory location into a buffer, the row being loaded from a row location in the memory bank and transmitting the data from the first memory location to the requestor. The method also includes determining, by a memory controller, whether to close the first page following execution of the first request based on information relating to a likelihood that a subsequent request will access the first page. | 2014-04-24 |
20140115295 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled. | 2014-04-24 |
20140115296 | Remapping Memory Cells Based on Future Endurance Measurements - A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group. | 2014-04-24 |
20140115297 | DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS - There is provided a system and a computer program product for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages. | 2014-04-24 |
20140115298 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 2014-04-24 |
20140115299 | COUNTER OPERATION IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers. | 2014-04-24 |
20140115300 | DATA PROCESSING SYSTEM WITH DATA CHARACTERISTIC BASED IDENTIFICATION OF CORRESPONDING INSTRUCTIONS - Some methods, computer program products, and data processing nodes identify a data unit in a data memory that is to be operated upon by a processor circuit, and uses a characteristic of the data unit to identify what instruction(s) within an instruction memory is be executed by the processor circuit to perform an operation upon the data unit. The data memory may be local to the processor circuit, and the instruction memory may be remotely accessible to the processor circuit through a data network. | 2014-04-24 |
20140115301 | PROCESSOR ARCHITECTURE AND METHOD FOR SIMPLIFYING PROGRAMMING SINGLE INSTRUCTION, MULTIPLE DATA WITHIN A REGISTER - The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element. | 2014-04-24 |
20140115302 | PREDICATE COUNTER - According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode. | 2014-04-24 |
20140115303 | DATA PROCESSING DEVICE - A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit. | 2014-04-24 |
20140115304 | COMPRESSED INSTRUCTION CODE STORAGE - Computer implemented techniques are disclosed for identification of repeated binary strings and for storing those binary strings in order to compress code. The binary strings can be longer instructions, data, or addresses. A table of binary strings is generated based on repeated occurrences, and a reference index is provided for accessing specific entries within the table. An opcode uses a shorter string as an index through which to access the table. The longer string is executed when the longer string is an instruction. When the longer string is an address or data, the appropriate address or data are accessed. | 2014-04-24 |
20140115305 | METHOD FOR INCREASING THE SPEED OF SPECULATIVE EXECUTION - A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been selected to optimize, executing the optimized sequence of instructions, and responding to an error during the execution of the optimized sequence of instructions by rolling back to the duplicate of instructions from the sequence of instructions. | 2014-04-24 |
20140115306 | Next Instruction Access Intent Instruction - Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction. | 2014-04-24 |
20140115307 | Method and System for Resetting a SoC - A method for resetting a so-called System on Chip SoC is described as well as a system adapted and configured to perform the method. A reset signal applied to the SoC resets the system but at the same time prevents loss and corruption of data that was processed at the time of signal application. | 2014-04-24 |
20140115308 | CONTROL METHOD, CONTROL DEVICE AND COMPUTER SYSTEM - A control method and a control device applied in a computer system, and a computer system are described. The control method according to the embodiments of the present invention is applied in a computer system, wherein the computer system includes a system memory containing two divided storage areas with the two storage areas being respectively a first storage area and a second storage area. The control method includes loading a first operating system into the first storage area; running the first operating system; and starting up a system memory access drive by the first operating system, so as to load into the second storage area the pre-stored memory mapping data of the second operating system by the system memory access drive. | 2014-04-24 |
20140115309 | VALIDATION OF STORAGE ARRAYS BASED ON INFORMATION STORED IN GLOBAL METADATA - A director node of a plurality of nodes determines a plurality of data arrays, where the plurality of data arrays have been discovered at boot time. The director node determines global metadata information, based on reading boot sectors of at least one of the plurality of data arrays discovered at boot time. A determination is made from the global metadata information as to how many data arrays had been previously configured. In response to determining that the plurality of data arrays discovered at boot time is not equal in number to the previously configured data arrays, the director node determines that all configured data arrays have not been discovered. | 2014-04-24 |
20140115310 | METHOD AND APPARATUS FOR GRACELESS REBOOT - Implementations of the present disclosure involve a system and/or method for gracelessly rebooting a storage appliance. The method and system includes a storage appliance in association with an event that will result in the loss of a state table from volatile memory that halts changes to at least one state table of the storage appliance. The state tables describe a plurality of file system states of one or more clients connected to the first storage appliance. The state information is written to a persistent memory of the storage appliance. The state table may then be repopulated using the state table information stored in persistent memory. | 2014-04-24 |
20140115311 | ELECTRONIC APPARATUS AND METHOD FOR DETERMINING A RESET THEREOF - An electronic apparatus and method for determining a reset thereof are provided. The electronic apparatus includes a switch, a sensor, a reset circuitry and a control circuitry. The switch generates a trigger signal as being triggered. The sensor senses a property of an object or an environment external to the electronic apparatus and to provide a sensing information based on the sensed property. The reset circuitry is coupled to the switch and counts from an initial value to a predetermined value when keep receiving the trigger signal from the switch, wherein the reset circuitry further resets the electronic apparatus when counting to the predetermined value. The control circuitry is coupled to the switch, the sensor and the reset circuit and generates a control signal, based on the sensing information, for controlling the reset circuit to re-count from the initial value to the predetermined value. | 2014-04-24 |
20140115312 | SERVER AND BOOTING METHOD THEREOF - The present invention discloses a server and a booting method thereof. The booting method includes the following steps. A motherboard and a hard disk driver backplane coupled to multiple hard disk drivers are provided, and a working voltage is provided for the hard disk driver backplane, wherein a power-up normal signal is generated when the hard disk driver backplane is powered up normally, and the motherboard includes a booting control circuit and a controller. In response to the power-up condition of the hard disk driver backplane, the hooting control circuit receives the power-up normal signal and outputs a power-up control signal to the controller. When receiving the power-up control signal, the controller controls the motherboard to be booted or maintained as off by determining the condition of the power-up control signal, for the data exchange between the motherboard and the hard disk driver. | 2014-04-24 |
20140115313 | ELECTRONIC DEVICE AND START-UP METHOD THEREOF - An electronic device and a method for starting up the same, wherein the electronic device includes a firmware control unit, a power supply state storage unit, a basic input output unit, and an Ethernet interface coupled to power supply apparatus to a Power over Ethernet to receive a power supply via a network cable. The firmware control unit determines whether the power supply state of the power supply is in a first power mode, by checking a power supply state signal. When the power supply state is not in the first power mode, the basic input output unit executes a second power booting program. The firmware control unit communicates with the power supply apparatus via a network, increases the rated power of the power supply, sets the power supply state signal for controlling the power supply state to be in the first power mode, and restarts the electronic device. | 2014-04-24 |
20140115314 | ELECTRONIC DEVICE AND SECURE BOOT METHOD - An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor. | 2014-04-24 |
20140115315 | OPTIMIZED COLD BOOT FOR NON-VOLATILE MEMORY - Various embodiments are directed to apparatuses and methods for faster solid state drive (SSD) boot-up. On boot-up, SSD control algorithms may load non-logical to physical (L2P) parts of a context and signal the system that the SSD is ready. The context may comprise various state data pertaining to the SSD. After signaling that the SSD may be ready to receive access requests, the SSD control algorithms may begin loading segments of the L2P table sequentially. Access to the L2P table may be blocked, however, when a requested segment has not yet been loaded. In such cases, the SSD control algorithms may then load the requested segment out of turn and then service the access request. | 2014-04-24 |
20140115316 | BOOT LOADING OF SECURE OPERATING SYSTEM FROM EXTERNAL DEVICE - A device for establishing a secure computing environment on a host computer. The device can include an interface configured to couple to the host computer. The device can also include a configuration module configured to identify a file that comprises configuration settings of the host computer's native boot loader that is used to load the host computer's native operating system. The configuration module can create a backup copy of the configuration settings of the native boot loader. The device includes a memory that holds a secure operating system. The device can also include a modification module configured to modify the configuration settings of the host computer's native boot loader to cause the secure operating system to be loaded from the device in place of the native operating system. | 2014-04-24 |
20140115317 | ELECTRONIC DEVICE AND METHOD FOR SWITCHING WORK MODE OF THE ELECTRONIC DEVICE - In a method for switching a work mode of an electronic device, if the electronic device receives a trigger signal when the electronic device is starting up, the electronic device enters the diagnostic mode. Otherwise, if the electronic device does not receive the trigger signal when the electronic device is starting up, the electronic device enters a production mode. When the electronic device receives the trigger signal in the production mode, operation parameters of the electronic device are stored into a storage system, and the electronic device switches from the production mode to the diagnostic mode. When the electronic device receives an exit command in the diagnostic mode, the electronic device switches from the diagnostic mode to the production mode. | 2014-04-24 |
20140115318 | METHOD AND APPARATUS FOR A POWER-EFFICIENT FRAMEWORK TO MAINTAIN DATA SYNCHRONIZATION OF A MOBILE PERSONAL COMPUTER TO SIMULATE A CONNECTED SCENARIO - An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed. | 2014-04-24 |
20140115319 | APPLICATION LAYER ENCRYPTED PACKET ROUTING - Mechanisms for cloaking, or otherwise masking, information in packets communicated between nodes. A source node generates a packet comprising communication layer data and encrypted application layer data. The encrypted application layer data includes a payload and waypoint data. The waypoint data includes a waypoint list that identifies one or more nodes of a path of nodes that the packet is to transit from the source node to the destination node. The source node addresses the packet to an intermediate node on the path, and sends the packet toward the intermediate node. | 2014-04-24 |
20140115320 | TCP/IP-BASED COMMUNICATION SYSTEM AND ASSOCIATED METHODOLOGY PROVIDING AN ENHANCED TRANSPORT LAYER PROTOCOL - A more secure TCP/IP protocol stack is provided having an enhanced transport layer. Encryption and decryption logic is arranged on the transmission side and on the reception side for processing a payload of a transport layer protocol, such as TCP or UDP. By employing this enhanced transport layer, a cryptograph process communication can be realized by dissolving various kinds of restrictions which a conventional IPsec or SSL possesses without affecting upper layer processing, and, at the same time, maintaining compatibility with the IP layer. | 2014-04-24 |
20140115321 | ENCRYPTED STATISTICAL PROCESSING SYSTEM, DEVICE, METHOD, AND PROGRAM - A service provider device includes key generation means, which generates a service public key for encrypting data and a secret key, and proxy key generation means, which inputs the service public key and the secret key and generates a proxy key. A data registration device includes encrypted data generation means, which generates encrypted data upon input of the service public key and data, and stores the generated encrypted data in a database. Proxy devices each includes encrypted portion statistical data generation means, which generates encrypted portion statistical data upon input of the proxy key with respect to the encrypted data stored in the database. An integrated data generation device includes encrypted statistical data generation means, which inputs the encrypted portion statistical data from each of the proxy devices, generates encrypted statistical data, and stores the generated encrypted statistical data in an integrated data storage device. | 2014-04-24 |
20140115322 | METHOD, APPARATUS AND SYSTEM FOR PERFORMING PROXY TRANSFORMATION - A method for performing proxy transformation between a user and a server includes: selecting a first proxy relationship between a target user and a first user from a proxy relationship library; selecting a random value, and generating a second proxy relationship according to the random value and the first proxy relationship; and encrypting original information according to the public key of the first user and the random value to obtain the encrypted information, and transmitting the encrypted information and the second proxy relationship to the server, so that the server performs proxy transformation on the encrypted information according to the second proxy relationship to obtain the transformed information. The method for performing proxy transformation thoroughly solves the security hazard that the server performs proxy transformation without user permission. The present invention further discloses a user terminal and a system for performing proxy transformation. | 2014-04-24 |
20140115323 | SECURE SYSTEM FOR ALLOWING THE EXECUTION OF AUTHORIZED COMPUTER PROGRAM CODE - Systems and methods for selective authorization of code modules are provided. According to one embodiment, a trusted service provider maintain a cloud-based whitelist containing cryptographic hash values including those of code modules that are approved for execution on computer systems of subscribers of the service provider. A code module information query, including a cryptographic hash value of a code module, is received from a computer system of a subscriber by the service provider. If the cryptographic hash value matches one the cryptographic hash values contained within the cloud-based whitelist and the code module is an approved code module, then the service provider responds with an indication that the code module is authorized for execution; otherwise, it (i) responds with an indication that the code module is an unknown code module; and (ii) causes one or more behavior analysis techniques to be performed on the code module. | 2014-04-24 |
20140115324 | System and Method for Secure Remote Biometric Authentication - Systems and methods for secure remote biometric authentication are provided. A network-based biometric authentication platform stores biometric templates for individuals which have been securely enrolled with the authentication platform. A plurality of sensor platforms separately establishes secure communications with the biometric authentication platform. The sensor platform can perform a biometric scan of an individual and generate a biometric authentication template. The sensor platform then requests biometric authentication of the individual by the biometric authentication platform via the established secure communications. The biometric authentication platform compares the generated biometric template to one or more of the enrolled biometric templates stored in memory at the biometric authentication platform. The result of the authentication is then communicated to the requesting sensor platform via the established secure communications. | 2014-04-24 |
20140115325 | Simplified Mechanism for Multi-Tenant Encrypted Virtual Networks - The present disclosure provides protection of customer data traveling across a network. A reverse cryptographic map (also referred to herein as a reverse crypto map) can be defined for a customer, where the reverse crypto map indicates how customer data should be protected. A reverse crypto map for a customer is applied to an interface of an edge device that is coupled to that customer's private subnet (or customer-facing interface). A reverse crypto map can be configured by a network administrator on a provider edge device, or can be pushed from a key server as part of group policy. A provider edge device can protect customer data by encrypting and decrypting the customer data according to the reverse crypto map. A provider edge device can also be configured with virtual routing and forwarding (VRF) tables that can be used to forward the VPN traffic flow across a provider network. | 2014-04-24 |
20140115326 | APPARATUS AND METHOD FOR PROVIDING NETWORK DATA SERVICE, CLIENT DEVICE FOR NETWORK DATA SERVICE - An apparatus for providing a network data service, comprising: a packet distributor for dividing data inputted through a transmission side network in the unit of a packet and distributing the divided packet data in parallel; an area detection unit for detecting an object in an interest area in the packet data distributed in parallel and performing encryption on the detected object in the interest area; and a data transmission unit for transmitting the packet data encrypted by the area detection unit to a reception side network. | 2014-04-24 |
20140115327 | TRUST SERVICES DATA ENCRYPTION FOR MULTIPLE PARTIES - In one scenario, a computer system accesses a first principal's public key to generate a group private key that is encrypted using the first principal's public key. The generated group private key provides access to data keys that are used to encrypt data resources. The computer system accesses a second principal's public key to encrypt the generated group private key using the second principal's public key and encrypts at least one of the data keys using a group public key, where the data key allows access to encrypted data resources. The first principal then decrypts the group private key using the first principal's private key, decrypts the data key using the decrypted group private key and accesses the data resource using the decrypted data key. The second principal also performs these functions with their private key to access the data resource. | 2014-04-24 |
20140115328 | FORMAT FRIENDLY ENCRYPTION - Techniques are disclosed for encrypting application data files using a format-friendly encryption process. A software agent may create an encrypted version of an application file using the same data file format of the unencrypted file. For example, when a user encrypts a word processing document, the software agent outputs a word processing document which includes an encrypted copy of the first word processing document. Application data files for other file formats may be encrypted in a similar manner. Further, format-friendly encrypted documents may include instructions for accessing the encrypted content, allowing the standard applications for accessing a given file format to present the instructions to a user. Creating encrypted document using the format-friendly encryption formats allows users who access an encrypted file hosted by a cloud storage provider to receive the information needed to access that application file. | 2014-04-24 |
20140115329 | SYSTEMS AND METHODS FOR DATA VERIFCATION AND REPLAY PREVENTION - A system and method are provided for the secure sharing of information stored using cloud storage services and for performing data verification and replay protection for information stored on an open network. | 2014-04-24 |
20140115330 | Set Top Box Architecture Supporting Mixed Secure and Unsecure Media Pathways - A media processing device, such as a set top box, having a plurality of selectable hardware and software components for supporting multiple media pathways providing differing levels of security. In general, each security level corresponds to a particular certification service boundary definition(s) or key/authentication and security management scheme for managing resources such as hardware acceleration blocks and software interfaces. Different sets of components may be adaptively employed to ensure composited compliance with one or more security constraints and to address component unavailability. Security constraints may be applied, for example, on a source or media specific basis, and different versions of a media item may be provided over multiple pathways providing corresponding levels of security. In one embodiment, a service operator or content provider may provide requisite certification or security requirements, or otherwise assist in selection of pathway components. | 2014-04-24 |
20140115331 | Secure Information Transfer Via Bar Codes - A method for providing a document using a secure bar code includes encrypting the document to generate an encrypted document, and mixing together bits for a security credential with bits for the encrypted document to generate a set of mixed bits having a predetermined order. The security credential is for decrypting the encrypted document. The method further includes inserting the set of mixed bits into the secure bar code and outputting the secure bar code. A bar code reader knows the predetermined order and is configured to read the secure bar code. The bar code reader may also be configured to un-mix the mixed bits based on the predetermined order, and decrypt the encrypted document with the security credential. | 2014-04-24 |
20140115332 | SECURE SHARING AND COLLABORATIVE EDITING OF DOCUMENTS IN CLOUD BASED APPLICATIONS - Collaboratively editing a document in a system of sharee clients includes creating a document change, generating a document token for encrypting the document change, encrypting the document change with the document token, making the encrypted document change available to the other sharee clients, and generating a plurality of copies of the sharee document token. Each sharee document token is encrypted with a respective sharee's public key. Each encrypted sharee document token is distributed to respective sharee clients. Each sharee client is configured to: decrypt a sharee document token using a respective private key, decrypt the encrypted document change using the share document token, and consolidate the document change into a document. | 2014-04-24 |
20140115333 | SECURE INFORMATION DELIVERY - A first network device is configured to receive a request for content from a user device, determine that the user device is not authenticated, and send information to the user device that the user device requires authentication. The first network device is configured further to receive a notification that the user device is authorized to receive content from multiple content providers. The first network device is configured further to generate a secret key and authenticate the user device by using the secret key. The first network device is further configured to send the content to the user device. | 2014-04-24 |
20140115334 | RETRIEVING ACCESS INFORMATION IN A DISPERSED STORAGE NETWORK - A method begins by a processing module obtaining a set of recovered random numbers, decoding encrypted share slices to produce a set of encrypted shares, and obtaining a set of personalized authenticating values regarding user access to data. The method continues with the processing module generating a set of hidden passwords based on the set of personalized authenticating values, generating a set of blinded passwords based on the set of hidden passwords and a set of blinded random numbers, and generating a set of passkeys based on the set of blinded passwords and the set of recovered random numbers. The method continues with the processing module generating a set of decryption keys based on the set of blinded random numbers and the set of passkeys, decrypting the set of encrypted shares to produce a set of shares, and decoding the set of shares to reproduce the data. | 2014-04-24 |
20140115335 | SECURE MACHINE-TO-MACHINE COMMUNICATION PROTOCOL - A task list server supports secure asynchronous communications between both a workstation and one or more machines. The task list server stores requests and responses initiated by either side and establishes secure communication channels used to forward the data between parties. The communication between workstation and machine may be delayed by hours or even days, depending on the work schedule and network access of both the workstation operator and machine. The machine may process requests in order from highest priority to lowest priority and from oldest to newest. Public key encryption may be used to establish secure channels between the task list server and the workstation or the one or more machines using a combination of certificate authorities including both manufacturers and owner/operators. | 2014-04-24 |
20140115336 | METHOD AND APPARATUS OF PROVISIONING HOME ENERGY MANAGEMENT SERVICES - A method for provisioning home energy management services includes supplying a service user with a list of home energy management services; and transmitting a request to subscribe to a service to a home energy management service provider server on a communication network. Further, the method includes performing an authentication with the home energy management service provider server and receiving a secret key for encryption and decryption of a message that is transmitted and received for the service; searching for home energy devices on a home network and transmitting a list of searched home energy devices to the home energy management service provider server; and sending the message received from the home energy management service provider server to the same home energy devices. | 2014-04-24 |
20140115337 | SYMMETRIC DYNAMIC AUTHENTICATION AND KEY EXCHANGE SYSTEM AND METHOD THEREOF - A symmetric dynamic authentication and key exchange system and a method thereof are provided. A client and a server obtain initial authentication information at the same time, the client generates first one-time temporary authentication information, a conference key and a standby identity identifier according to the initial authentication information, and transmits them to the server, and the server performs a dynamic authentication program. The server compares the initial authentication information of the client with the conference key to confirm an identity of the client, and then updates the initial authentication information of the server according to the first one-time temporary authentication information, and the server is enabled to have the first one-time temporary authentication information the same as that of the client, and then to generate second one-time temporary authentication information including the standby identity identifier according to the first one-time temporary authentication information and the initial authentication information. | 2014-04-24 |
20140115338 | DIGITAL BROADCAST METHODS USING SECURE MESHES AND WAVELETS - Methods and apparatuses are presented for securely providing digital streaming data to subscriber devices using encrypted wavelet meshes. A recorded image may be subdivided into three sources of data: light sources, camera angles, and the objects themselves. Each of these sources of data may be considered unique from each other, and the totality of the three sources of data may comprise a complete image. Without one of the sources of data, the image may not be complete. Each of the three sources of data may therefore be characterized as key spaces, wherein encrypting part of or the entirety of even one of these key spaces prevents the complete image from being viewed. Methods and apparatuses are provided for utilizing the concept of encrypting at least a portion of at least one of the three key spaces in order to securely and/or privately transmit image data to subscribers. | 2014-04-24 |
20140115339 | METHOD AND APPARATUS FOR SERIAL DEVICE REGISTRATION - Disclosed in the present invention are a method and apparatus for serial device registration. Said method comprises: a first serial device establishes connection with a second serial device; the first serial device reports the device attribute information of the first serial device to the second serial device, so as to initiate the process of registering the first serial device in the second device; in the registration process, after receiving the request of asking for signature certificate from the second serial device, the first serial device sends a first signature certificate to the second serial device; computing the received first challenge code returned from the second serial device, and obtaining a first signature value; sending the first signature value to the second serial device, so as to authenticate the first signature value by the second serial device and return the authentication result to the first serial device; after the authentication, the first serial device accomplishes the registration in the second serial device. The present invention solves the problem of lacking security authentication mechanism at the time of registering, thus improving communication security. | 2014-04-24 |
20140115340 | UNIQUE DEVICE IDENTIFIER PROVISION METHOD AND APPARATUS - A method and apparatus for providing a user device with a unique identifier for reinforcing the security of communication with a server includes displaying a CAPTCHA image including a security key received from a server in response to a connection attempt to the server; receiving a security key input by the user, the security key being included in the CAPTCHA image; computing a hash value using the security key input by a user; transmitting the hash value to the server; and registering, when a connection response is received from the server in response to the hash value, the security key based on hash value as a unique identifier necessary for connection with the server. | 2014-04-24 |
20140115341 | METHOD AND SYSTEM FOR ENABLING SECURE ONE-TIME PASSWORD AUTHENTICATION - An approach for facilitating a one-time password (OTP) authentication procedure is described. A dedicated validation appliance receives a one-time password authentication request via an application programming interface, which is a single point of access to the dedicated validation appliance. The dedicated validation appliance then determines a validity of the request based on the correlating of a submitted OTP against OTP values independently generated by the dedicated validation appliance based on a large secret key exclusive to a client device that initiated the request. The single point of access to the dedicated validation appliance as well as exclusive sharing of the secret key with only another dedicated validation appliance or one-time with the client device reduces the likelihood of attackers discovering the secret keys. | 2014-04-24 |
20140115342 | INFORMATION PROCESSING APPARATUS, INFORMATION STORAGE MEDIUM, CONTENT MANAGEMENT SYSTEM, DATA PROCESSING METHOD, AND COMPUTER PROGRAM - A configuration for achieving efficient content verification processing based on hash values is provided. Hash values of hash units set as segmented data of a content stored on an information storage medium are recorded in a content hash table and are stored on the information storage medium together with the content. An information processing apparatus for executing content playback executes hash-value comparison processing based on one or more randomly selected hash values. Regardless of the data amount of content, the configuration can perform hash-value determination and comparison processing based on hash units having a small amount of data, so that user equipment for executing content playback can perform efficient content verification. | 2014-04-24 |
20140115343 | INFORMATION PROCESSOR, METHOD FOR VERIFYING AUTHENTICITY OF COMPUTER PROGRAM, AND COMPUTER PROGRAM PRODUCT - A disc stores therein a computer program and encrypted information. A BIOS is executed at the time of start-up and starts the computer program. A TPM is connected to the BIOS by a low-speed bus. The TPM includes a register for storing data. A blob stores therein true hash values of the computer program and the BIOS in advance. The BIOS includes a hash value calculating unit that calculates hash values of the computer program and the BIOS and stores those hash values in the register. The TPM compares the hash values stored in the register with the hash values stored in the blob and decrypts information in the blob if the hash values agree with each other. | 2014-04-24 |
20140115344 | APPARATUS AND METHOD FOR OPERATING AND SWITCHING A SINGLE CONDUCTOR INTERFACE - This application discusses, among other things, communication apparatus and methods, and more particularly, a single conductor or single wire communication scheme. In an example, a method for communicating between a master device and a slave device using a first single conductor can include transmitting a first ping on the first single conductor using a master device, the first single conductor configured to couple the master device to a slave device, receiving a slave ping on the first single conductor at the master device during a ping interval, toggling a logic level of the first single conductor prior to sending a first data packet using pulses having a duration of less than one half of a unit interval, such as a unit interval associated with a bit interval. | 2014-04-24 |
20140115345 | METHODS AND DEVICES FOR OPTIMISING RENDERING OF AN ENCRYPTED 3D GRAPHICAL OBJECT - The graphical characteristics of 3D graphical objects encrypted using format-preserving encryption makes rendering of such objects quite inefficient by non-authorized devices. To optimise the rendering of a three-dimensional graphical object represented by a list of points and a list of surfaces defined by points in the list of points, a device receives the graphical object; encrypts the graphical object using a format-preserving encryption method to obtain an encrypted graphical object; encapsulates the encrypted graphical object to obtain an encapsulated graphical object by adding at least one encapsulation by adding for each encapsulation, to the list of surfaces, a plurality of surfaces that together enclose the encrypted graphical object and, in an embodiment, at least one point to the list of points; and outputs the encapsulated graphical object. Decryption is performed by essentially reversing the encryption. | 2014-04-24 |
20140115346 | METHOD AND APPARATUS FOR IMPLEMENTING MEMORY SEGMENT ACCESS CONTROL IN A DISTRIBUTED MEMORY ENVIRONMENT - Various methods for implementing memory segment access control in a distributed memory environment are provided. One example method may comprise during a first write state for a memory segment receiving a cryptographic key stream in association with a request from a first device for use of shared storage capacity of a second device and causing the cryptographic key stream to be stored in the memory segment. Further, during the second write state for the memory segment, the example method may comprise receiving data content, transforming the date content using the cryptographic key stream to form encrypted data content, and causing the encrypted data content to be stored in the memory segment. Finally, during the first read state, the example method may comprise causing the encrypted data content to be provided to one or more requesting devices. Similar and related example methods, example apparatuses, and example computer program products are also provided. | 2014-04-24 |
20140115347 | INFORMATION PROCESSING APPARATUS, SOFTWARE UPDATE METHOD, AND IMAGE PROCESSING APPARATUS - An information processing apparatus, a software update method, and an image processing apparatus capable of encrypting and decrypting information using values uniquely calculated from booted primary modules or booted backup modules with less effort are disclosed. The information processing apparatus includes primary modules and the same kinds of backup modules, and includes a value storage unit storing values calculated from the modules, an encryption information storage unit storing information unique to the modules, an information decryption unit decrypting the information unique to the modules using the values in the value storage unit, and an encryption information update unit, when the module is updated, encrypting the information unique to the modules based on a value calculated from the each kind of the primary modules or the backup modules after the update. | 2014-04-24 |
20140115348 | SERVER SYSTEM AND HEAT DISSIPATION CONTROL METHOD THEREOF - A server system and a heat dissipation control method thereof are provided. A main power supply and a standby power supply respectively supplying a main voltage and a standby voltage of the server system are provided. An extension card module including at least one extension card slot allowing at least one extension card to insert into, is provided. A fan module including at least one fan used for dissipating heat from the extension card module is provided. When the main voltage is applied to the server system, the main voltage is applied to the fan to drive the fan. When the standby voltage is applied to the server system, the extension card module is determined whether to be inserted in any extension card. If yes, the standby voltage is applied to the fan to drive the fan; otherwise, the standby voltage is interrupted to stop the fan. | 2014-04-24 |
20140115349 | COMPUTER APPARATUS AND WAKE-UP METHOD THEREOF - The disclosure provides a computer apparatus including a peripheral device, a hub unit and a control unit, and a wake-up method thereof. The peripheral device is configured to generate an input signal. The hub unit is coupled to the peripheral device. When the computer apparatus is in a power-saving state, the hub unit is configured to receive the input signal to generate a wake-up event (WUE). The control unit is coupled to the hub unit. When the computer apparatus is in the power-saving state, the control unit is configured to detect whether the WUE is generated, so as to wake up the computer apparatus, so that the computer apparatus is returned to a normal operating state from the power-saving state. | 2014-04-24 |
20140115350 | POWER CONTROL DEVICE FOR PROCESSOR - A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal. | 2014-04-24 |
20140115351 | DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 2014-04-24 |
20140115352 | ASYNCHRONOUS MANAGEMENT OF ACCESS REQUESTS TO CONTROL POWER CONSUMPTION - Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget. | 2014-04-24 |
20140115353 | System and Method for One-Line Power Mapping of Information Handling Systems in a Datacenter - A method of one-line power mapping in a datacenter includes providing from a management system a pre-defined pattern to a rack system, in response to providing the pre-defined pattern, directing the rack system to enable a power supply unit of the rack system and to modulate a power usage of the rack system to encode the pre-defined pattern onto a power cable, wherein the power supply unit receives operating power from a power distribution unit via the power cable, receiving at the management system a power level signal from the power distribution unit, decoding at the management system the pre-defined pattern from the power level signal, and determining that the rack system is connected to the power distribution unit in response to decoding the pre-defined pattern. | 2014-04-24 |
20140115354 | WIRELESS GATEWAY ADAPTER FOR A POWER-OVER-ETHERNET PORT - A PoE-enabled wireless device facilitates providing wireless access to a local area network (LAN) by receiving power from an Ethernet cable. The device includes a first Ethernet port that can receive a power signal. The device also includes a second Ethernet port that facilitates coupling the apparatus to the LAN, and includes a wireless module to provide a wireless network connection to the LAN. Specifically, the wireless module receives power from the power signal of the first Ethernet port to provide the wireless network connection. The wireless device can also include a third Ethernet port for providing power and a network connection to a remote network device. The wireless device can use the third Ethernet port to send an external-reset signal to the remote network device, which facilitates remotely resetting a configuration of the remote network device without having to physically access the remote network device. | 2014-04-24 |
20140115355 | COMPUTING DEVICE AND POWER SUPPLY METHOD OF CONNECTION MODULE - The disclosure discloses a computing device including a connection module, a processing unit and a logic expansion unit, and a power supply method of a connection module. The connection module includes a detection unit and a power switch. The detection unit is configured to detect whether the connection module is connected with an external peripheral device, and to generate a detection signal. The power switch is configured to receive a power switching signal and to provide a rated voltage to the connection module according to the power switching signal. The processing unit and the logic expansion unit are coupled to each other. When the computing device is at a normal mode, the processing unit is configured to provide the power switching signal, acquires a connection status between the connection module and the external peripheral device, and to control the logic expansion unit to record the connection status. | 2014-04-24 |
20140115356 | TRANSFORMER CAPABLE OF AUTOMATIC INPUT POWER ADJUSTMENT AND COMPUTER USING THE TRANSFORMER - A transformer and a computer capable of automatic input power adjustment are provided, and the computer includes an electronic apparatus and a transformer. The electronic apparatus has a power source module and a wake-up module. The transformer has a switch module, a power supply module and a detection module. The power supply module is connected to the switch module and the detection module. The switch module transmits external power to the power supply module. The power supply module transforms the external power to operation power, and transmits the operation power to a power source module. When the operation power is lower than a charge threshold, the detection module commands the switch module to stop receiving the external power. | 2014-04-24 |
20140115357 | Method and Apparatus for Adjusting Device Power Consumption - The present invention discloses a method for adjusting device power consumption including: grouping multiple devices into at least one device group, setting a group power consumption ceiling threshold (PCCT) for the device group, and setting a device PCCT for each device in the group; obtaining current total power consumption of the group, and when the current total power consumption of the group exceeds the group PCCT, determining whether current power consumption of each device in the group exceeds the device PCCT of the device; when the current power consumption of each device exceeds the device PCCT of the device, reducing power consumption of each device to the device PCCT of the device; and when current power consumption of a device exceeds a device PCCT of the device, setting a new PCCT for the device, and reducing power consumption of the device to/or less than the new PCCT. | 2014-04-24 |
20140115358 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR CONTROLLING AN OPERATING MODE OF AN ON-DIE MEMORY - An integrated circuit device comprising at least one instruction processing module, at least one memory comprising at least one memory bank configurable to operate in a first functional mode and at least one further, lower-power mode, and at least one memory mode control module arranged to control switching of the at least one memory bank between the first functional mode and the at least one further, lower-power modes. | 2014-04-24 |
20140115359 | COMPUTER SYSTEM, CONNECTION DEVICE, POWER SUPPLY CONTROL METHOD, AND POWER SUPPLY CONTROL PROGRAM RECORDING MEDIUM - A host monitoring unit in a host connection device ( | 2014-04-24 |
20140115360 | Method for Reducing Dynamic Power Consumption and Electronic Device - The present invention relates to a method for reducing dynamic power consumption and an electronic device. The method includes: receiving a bus signal; when information about access to the slave device exists in the bus signal, inputting a clock signal into the slave device and detecting a status signal sent by the slave device; and stopping inputting the clock signal into the slave device when the status signal of the slave device indicates that the slave device is in an idle state. A working clock of a device module, such as a slave device, in a chip is controlled by using a status signal of the slave device and a bus signal, which prevents unnecessary circuit turnover from occurring to the device module in the chip in a non-working state, thereby achieving a purpose of reducing dynamic power consumption of the device module in the chip. | 2014-04-24 |
20140115361 | LOAD STEP MANAGEMENT - Various embodiments of the present disclosure are directed to managing load steps caused by processing circuitry. The processing circuitry may generate a series of clock pulses at an average clock period. The processing circuitry may estimate a current consumption of the processing circuitry at each clock pulse. Accordingly, a clock pulse from the series of clock pulses may be omitted when a change in the current consumption exceeds a predetermined threshold amount, thereby increasing the average clock period. | 2014-04-24 |
20140115362 | OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES - For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed. | 2014-04-24 |
20140115363 | MODAL WORKLOAD SCHEDULING IN A HETEROGENEOUS MULTI-PROCESSOR SYSTEM ON A CHIP - Various embodiments of methods and systems for mode-based reallocation of workloads in a portable computing device (“PCD”) that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different performance capabilities or strengths, and because more than one of the processing components may be capable of processing a given block of code, mode-based reallocation systems and methodologies can be leveraged to optimize quality of service (“QoS”) by allocating workloads in real time, or near real time, to the processing components most capable of processing the block of code in a manner that meets the performance goals of an operational mode. Operational modes may be determined by the recognition of one or more mode-decision conditions in the PCD. | 2014-04-24 |
20140115364 | METHOD AND DEVICE FOR ADVANCED CONFIGURATION AND POWER INTERFACE (ACPI) SLEEP-STATE SUPPORT USING CPU-ONLY RESET - A mechanism for firmware to gain control from the operating system of an Advanced Configuration and Power Interface (ACPI)-compliant computing device during sleep-state transitions even if the computing device lacks a dedicated means for such a change to occur is discussed. Embodiments of the present invention report a CPU-only reset register in place of a sleep control register for an ACPI-compliant computing device in which an operating system is attempting a sleep-state transition. A CPU reset value is substituted for a sleep type value in a sleep-state object and written to the CPU-only reset register that was reported instead of the sleep control register thereby triggering a CPU-only reset. Firmware code operating at a known CPU reset vector may perform specified processing and then authorize a transition to the originally requested sleep-state. | 2014-04-24 |
20140115365 | ELECTRONIC DEVICE AND POWER MANAGEMENT METHOD - A power management method for use in an electronic system is provided. The electronic system has a processor and a power management unit. The method has the steps of: when the processor has entered a low power state and an awakening event occurs, calculating a staying time from the time point the processor enters the low power state till the time point the awakening event occurs, wherein the operation voltage of the processor is at a first voltage level in the low power state; and when the processing starts to exit the low power state according to the awakening event, determining a wait time, during which the operation voltage of the processor is recovered to a second voltage level of a working state from the first voltage level, wherein the first voltage level is lower than the second voltage level. | 2014-04-24 |
20140115366 | APPLICATION PROCESSOR, MOBILE DEVICE HAVING THE SAME, AND METHOD OF SELECTING A CLOCK SIGNAL FOR AN APPLICATION PROCESSOR - An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data. | 2014-04-24 |
20140115367 | ELECTRONIC DEVICE OPERATING IN A PLURALITY OF POWER STATES, CONTROL METHOD THEREOF, AND STORAGE MEDIUM - An electronic device with improved usability when activated. The electronic device is capable of operating in a plurality of power states including a first power state, and a second power state in which the electric device is less in power consumption than in the first power state. The power state after activation of the electronic device is decided, based on status of connection of an external apparatus to the electronic device. The electronic device is shifted to the decided power state after the activation of the electronic device. | 2014-04-24 |
20140115368 | CONSTRAINED BOOT TECHNIQUES IN MULTI-CORE PLATFORMS - Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that controls which specific core(s) are to be powered up/down and/or which power state these core(s) need to enter based, at least in part, on input from OS and/or software application(s). Other embodiments are also claimed and disclosed. | 2014-04-24 |
20140115369 | TECHNIQUE FOR PRESERVING CACHED INFORMATION DURING A LOW POWER MODE - A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache. | 2014-04-24 |
20140115370 | ELECTRONIC DEVICE AND METHOD FOR REDUCING ENERGY CONSUMPTION OF STORAGE DEVICES - In a method for reducing energy consumption of storage devices in an electronic device, a directory index of files stored in the storage devices is established, and the storage devices are turned off after establishing the directory index. In response to receiving a user request for processing a target file, the method determines a target storage device that stores the target file when the directory index includes information of the target file. The target storage device is turned on, and the user request is transmitted to the target storage device. The target file is processed in the target storage device according to the user request. | 2014-04-24 |
20140115371 | Decommission of a Server in Wireless Environment - An embodiment of the invention provides a device for monitoring activity of a computing device wirelessly connected to a network, wherein the device includes a first interface for connecting the device to the computing device. A second interface wirelessly connects the device to the network. A sensor connected to the second interface measures wireless network traffic to the computing device and/or wireless network traffic from the computing device. Another embodiment of the invention provides a computing device having an interface for wirelessly connecting to a network. A sensor connected to the interface measures wireless network traffic to the computing device and/or wireless network traffic from the computing device. A processor connected to the sensor compares the network traffic to the computing device and/or the network traffic from the computing device to one or more thresholds to determine whether the computing device should be decommissioned. | 2014-04-24 |
20140115372 | ENERGY MANAGEMENT BY DYNAMIC FUNCTIONALITY PARTITIONING - A sensor and processing system dynamically partitions or allocates functionality between various remote sensor nodes and a processing subsystem based on energy management management considerations. Redundant functionality is located at the processing subsystem and each of the various remote sensor nodes, and each sensor node coordinates with the processing subsystem to determine the location (e.g., at the processing subsystem or at the sensor node) at which a particular functionality is executed. | 2014-04-24 |
20140115373 | APPARATUSES AND METHODS AND FOR PROVIDING POWER RESPONSIVE TO A POWER LOSS - Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control logic, and an array. The power sensor may be configured to detect a power loss of a power supply and provide a power loss control signal responsive, at least in part, to detecting the power loss of the power supply. The write command control logic may be coupled to the power sensor and may be configured to receive the power loss control signal. The write command control logic may be further configured to provide a write command responsive, at least in part, to receipt of the power loss control signal. The array may include a plurality of capacitors configured to store power and further configured to provide power during the power loss. | 2014-04-24 |
20140115374 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence. | 2014-04-24 |
20140115375 | MULTI-LEVEL ENCODED DATA TRANSFER - Multi-level encoded data transfer is disclosed. 2 | 2014-04-24 |
20140115376 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 2014-04-24 |
20140115377 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 2014-04-24 |
20140115378 | SYSTEM AND METHOD FOR RESTORING NETWORK CONFIGURATION PARAMETERS - A system and a method for restoring network configuration parameters suitably adapted for automatically restoring the network configuration parameters to the ones before a power failure are provided. The method includes the following steps. A system chipset pre-stores network configuration parameters corresponding to a network unit. The system chipset executes a U-boot procedure when the power supply restores. Then the system chipset detects a status flag of the network unit. When the status flag is false, the system chipset writes the network configuration parameters into the network unit and sets the status flag to true. Then, the system chipset executes a shut-down procedure. | 2014-04-24 |
20140115379 | INTELLIGENT INTEGRATED NETWORK SECURITY DEVICE FOR HIGH-AVAILABILITY APPLICATIONS - Methods and apparatuses for inspecting packets are provided. A primary security system may be configured for processing packets. The primary security system may be operable to maintain flow information for a group of devices to facilitate processing of the packets. A secondary security system may be designated for processing packets upon a failover event. Flow records may be shared from the primary security system with the secondary security system. | 2014-04-24 |
20140115380 | FAILOVER SYSTEM AND METHOD - One aspect of the present invention provides a system for failover comprising at least one client selectively connectable to one of at least two interconnected server via a network connection. In a normal state, one of the servers is designated a primary server when connected to the client and a remainder of the servers are designated as backup servers when not connected to the client. The at least one client is configured to send messages to the primary server. The servers are configured to process the messages using at least one service that is identical in each of the servers. The services are unaware of whether a server respective to the service is operating as the primary server or the backup server. The servers are further configured to maintain a library, or the like, that indicates whether a server is the primary server or a server is the backup server. The services within each server are to make external calls via its respective library. The library in the primary server is configured to complete the external calls and return results of the external calls to the service in the primary server and to forward results of the external calls to the service in the backup server. The library in the secondary server does not make external calls but simply forwards the results of the external calls, as received from the primary server, to the service in the secondary server when requested to do so by the service in the secondary server. | 2014-04-24 |
20140115381 | MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY - Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period. | 2014-04-24 |
20140115382 | Scheduling Workloads Based on Detected Hardware Errors - Scheduling workloads based on detected hardware errors is provided. In response to determining that a hardware error is detected, it is determined whether the hardware error is a cache error. In response to determining that the hardware error is a cache error, it is determined whether execution of a workload on a processor is changing contents of a cache associated with the cache error more than a threshold value. In response to determining that the execution of the workload on the processor is changing the contents of the cache associated with the cache error more than the threshold value, it is determined whether the cache associated with the cache error is private to a core in the processor. In response to determining that the cache associated with the cache error is private to a core, the execution of the workload is scheduled on a different core of the processor. | 2014-04-24 |
20140115383 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 2014-04-24 |
20140115384 | FAST DATA RECOVERY FROM HDD FAILURE - A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives of the first plurality of hard disk drives. A first hard disk drive includes data or parity data of both a first stripe of the stripes and a second stripe of the stripes, while a second hard disk drive includes data or parity data of only one of the first stripe or the second stripe. During data recovery involving failure of one of the first plurality of hard disk drives, the data in the failed hard disk drive is recovered for each stripe by calculation using data and parity data in other hard disk drives for each stripe. | 2014-04-24 |
20140115385 | SOLVABLE EXCEPTIONS - A task unit included in an application is executed. The task unit includes instructions for executing an application task. An exception is thrown by the task unit. A program fragment for resolving the exception is identified and used to obtain user input to resolve the exception. | 2014-04-24 |
20140115386 | SERVER AND METHOD FOR MANAGING SERVER - In a method for managing a server, when the server malfunctions, a present abnormality of the server is determined according to data from a memory of the server. A reason of the present abnormality is determined according to a preset reason list, in response to determining that the present abnormality is a hardware abnormality. Use of the abnormal hardware is stopped and an operating system of the server is controlled to restart. Information of the abnormal hardware is acquired from a field replace unit (FRU) chip of the server. The present abnormality of the server, the reason of the present abnormality, and the information of the abnormal hardware is transmitted to the computing device. | 2014-04-24 |
20140115387 | IDENTIFYING A SLICE NAME INFORMATION ERROR IN A DISPERSED STORAGE NETWORK - A method begins by a processing module sending list digest requests to a set of dispersed storage (DS) units. The method continues with the processing module receiving list digest responses from at least some of the set of DS units and determining whether an inconsistency exists between first and second list digest responses of the list digest responses. The method continues with the processing module requesting at least a portion of each of the slice name information lists from first and second DS units of the set of DS units and identifying a slice name information error associated with the inconsistency based on the at least a portion of each of the slices name information lists of the first and second DS units when the inconsistency exists between first and second list digest responses of the list digest responses. | 2014-04-24 |
20140115388 | COMPUTING CORE APPLICATION ACCESS UTILIZING DISPERSED STORAGE - A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module. | 2014-04-24 |