16th week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140103412 | THREE-DIMENSIONAL IMAGE SENSORS AND METHODS OF FABRICATING THE SAME - A three-dimensional image sensor includes a first photoelectric converter in a first pixel region of a substrate, a second photoelectric converter in a second pixel region of the substrate, a first transfer gate structure disposed on the substrate at one side of the first photoelectric converter, a second transfer gate structure and a drain gate structure disposed on the substrate at opposite sides of the second photoelectric converter and whose gate insulating layers are thinner the gate insulating layer of the first transfer gate structure. The gate insulating layers can be fabricated by forming a first insulating layer on the pixel regions of the substrate, removing part of the first insulating layer from the second pixel region, and subsequently forming a second insulating layer on the substrate including over a part of the first insulating layer which remains on the first pixel region. | 2014-04-17 |
20140103413 | CMOS IMAGE SENSORS WITH PHOTOGATE STRUCTURES AND SENSING TRANSISTORS, OPERATION METHODS THEREOF, AND IMAGE PROCESSING SYSTEMS INCLUDING THE SAME - ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage. | 2014-04-17 |
20140103414 | Vertical Super-Thin Body Semiconductor on Dielectric Wall Devices and Methods of Their Fabrication - The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices. | 2014-04-17 |
20140103415 | Semiconductor Device and Method of Preventing Latch-Up in a Charge Pump Circuit - A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell. | 2014-04-17 |
20140103416 | SEMICONDUCTOR DEVICE HAVING ESD PROTECTION STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING - A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The semiconductor device further includes a semiconductor transistor formed in an active cell area of a substrate. The ESD protection structure is formed atop a termination area of the substrate and is of solid closed shape. The ESD protection structure includes a central doped zone of a first conductivity type and a plurality of second-conductivity-type doped zones and first-conductivity-type doped zones alternately disposed surrounding the central doped zone. The central doped zone occupies substantially the entire portion of the ESD protection structure that is overlapped by a gate metal pad, and is electrically coupled to the gate metal pad. The outmost first-conductivity-type doped zone is electrically coupled to a source metal. The ESD protection structure features a reduced resistance and an improved current uniformity and provides enhanced ESD protection to the transistor. | 2014-04-17 |
20140103417 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a pipe gate, word lines stacked on the pipe gate, first channel layers configured to pass through the word lines, and a second channel layer formed in the pipe gate to connect the first channel layers and having a higher impurity concentration than the first channel layers. | 2014-04-17 |
20140103418 | SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND METHODS TO FORM THE SAME - A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias. | 2014-04-17 |
20140103419 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a non-volatile memory device includes: (a) forming an isolation structure on a circuit-forming surface of a semiconductor substrate to define an array of cell forming regions; (b) forming a gate structure array including a plurality of gate structures disposed above the cell forming regions and each having a first side and a second side; (c) performing ion implantation to form drain regions and a common source region; and (d) forming drain contacts to the drain regions, and a common source contact to the common source region. | 2014-04-17 |
20140103420 | ADVANCED FARADAY SHIELD FOR A SEMICONDUCTOR DEVICE - One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate. | 2014-04-17 |
20140103421 | SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination. | 2014-04-17 |
20140103422 | STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 2014-04-17 |
20140103423 | METHOD OF PRODUCING PRECISION VERTICAL AND HORIZONTAL LAYERS IN A VERTICAL SEMICONDUCTOR STRUCTURE - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces ( | 2014-04-17 |
20140103424 | ELECTRONIC DEVICE COMPRISING CONDUCTIVE STRUCTURES AND AN INSULATING LAYER BETWEEN THE CONDUCTIVE STRUCTURES AND WITHIN A TRENCH - An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow R | 2014-04-17 |
20140103425 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer. A third semiconductor layer is on the second semiconductor layer. A fourth semiconductor layer is selectively in the first semiconductor layer. A first trench and second trench penetrate from a surface of the third layer through the second layer to reach the first layer. An embedded electrode is in the first trench. A control electrode is above the embedded electrode via an insulating film. A lower end of the second trench is connected to the fourth semiconductor layer. A first main electrode is electrically connected to the first layer. A second main electrode is provided in the second trench. A Schottky junction is formed by the first layer and the second main electrode at a sidewall of the second trench. | 2014-04-17 |
20140103426 | TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH MULTIPLE TRENCHED SOURCE-BODY CONTACTS FOR REDUCING GATE CHARGE - A trench MOSFET with multiple trenched source-body contacts is disclosed for reducing gate charge by applying multiple trenched source-body contacts in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement. | 2014-04-17 |
20140103427 | SEMICONDUCTOR TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×10 | 2014-04-17 |
20140103428 | TRENCH SUPERJUNCTION MOSFET WITH THIN EPI PROCESS - Methods for fabricating MOSFET devices with superjunction having high breakdown voltages (>600 volts) with competitively low specific resistance include growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, forming a trench in the epitaxial layer, and growing a second epitaxial layer along the sidewalls and bottom of the trench. The second epitaxial layer is doped with a dopant of first conductivity type. MOSFET devices with superjunction having high breakdown voltages include a first epitaxial layer of a second conductivity type disposed over a substrate of a first conductivity type and a trench formed in the epitaxial layer. The trench includes a second epitaxial layer grown along the sidewalls and bottom of the trench. | 2014-04-17 |
20140103429 | Method and Structure to Boost MOSFET Performance and NBTI - The present disclosure provides one embodiment of a method forming a p-type field effect transistor (pFET) structure. The method includes forming a mask layer on a semiconductor substrate, the mask layer including an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming a n-type well (n-well) in the semiconductor region by performing an ion implantation of a n-type dopant to the semiconductor substrate through the opening of the mask layer; and performing a germanium (Ge) channel implantation to the semiconductor substrate through the opening of the mask layer, forming a Ge channel implantation region in the n-well. | 2014-04-17 |
20140103430 | LATERAL HIGH-VOLTAGE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A lateral high-voltage transistor includes: a semiconductor substrate; a semiconductor layer being provided on one main surface of the semiconductor substrate; a source region being provided selectively in a surface of the semiconductor layer; a drain region being provided selectively in the surface of the semiconductor layer; a gate electrode provided on a part of the semiconductor layer between the source region and the drain region with interposition of the gate insulating film; and a drift region being provided selectively in the surface of the semiconductor layer. The drift region includes a stripe-shaped diffusion layer extending in parallel with a direction from the drain region toward the source region. The stripe-shaped diffusion layer includes linear diffusion layers each including stripe-shaped diffusion regions that are adjacent to each other such that double diffusion occurs in a portion where the stripe-shaped diffusion regions are adjacent to each other. | 2014-04-17 |
20140103431 | LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTORS HAVING A REDUCED SURFACE FIELD STRUCTURES - An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region. | 2014-04-17 |
20140103432 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region. As viewed in a direction perpendicular to the surface of the base region, the source region and at least a part of the drain region extend generally parallel in a line shape, and a length of a portion of the drift region sandwiched between the insulating layer and the base region is shorter in the generally parallel extending direction than in a direction generally perpendicular to the generally parallel extending direction. | 2014-04-17 |
20140103433 | HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME - A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region. | 2014-04-17 |
20140103434 | MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES - Structure and methods for a semiconductor transistor design. The transistor structure comprises a field effect transistor having a multi-finger gate and three or more diffusion regions. Each diffusion region is identified as either a source region or a drain region, and each diffusion region is further identified as either an inner diffusion region or an outer diffusion region. Electrical contacts are established in the inner diffusion regions and the outer diffusion regions. There are approximately twice as many contacts in an inner source region as in the outer source region. There are approximately twice as many contacts in an inner drain region as in the outer drain region. The number and locations of contacts in each diffusion region are adjusted to reduce the difference among source node voltages of all fingers and the difference among drain node voltages of all fingers. | 2014-04-17 |
20140103435 | VERTICAL SOURCE/DRAIN JUNCTIONS FOR A FINFET INCLUDING A PLURALITY OF FINS - Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures. After formation of a disposable template layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed by etching center portions of the semiconductor material portion employing the combination of the disposable template layer and the fin-defining mask structures as an etch mask. A first pad region and a second pad region laterally contact the plurality of semiconductor fins. A replacement gate structure is formed on the plurality of semiconductor fins. The disposable template layer is removed, and the first pad region and the second pad regions are vertically recessed. Vertical source/drain junctions can be formed by introducing dopants through vertical sidewalls of the recessed source and second pad regions. | 2014-04-17 |
20140103436 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT - A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates. | 2014-04-17 |
20140103437 | Random Doping Fluctuation Resistant FinFET - An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Three representative embodiments of the key structure are described in detail. | 2014-04-17 |
20140103438 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 2014-04-17 |
20140103439 | Transistor Device and Method for Producing a Transistor Device - A transistor device includes at least one transistor cell. The at least one transistor cell includes a semiconductor fin, and a source region, a drain region, a drift region and a body region in the semiconductor fin. The body region is arranged adjacent the source region and the drift region in a first direction of the semiconductor fin. The source region is arranged adjacent the drift region in a second direction of the semiconductor fin and dielectrically insulated from the drift region by a dielectric layer. The drift region is arranged adjacent the drain region in the first direction and has a doping concentration lower than a doping concentration of the drain region. A gate electrode is adjacent the body region in a third direction of the semiconductor fin. | 2014-04-17 |
20140103440 | I-SHAPED GATE ELECTRODE FOR IMPROVED SUB-THRESHOLD MOSFET PERFORMANCE - Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction. | 2014-04-17 |
20140103441 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench. | 2014-04-17 |
20140103442 | SEMICONDUCTOR DEVICE, METHOD OF FORMING SEMICONDUCTOR DEVICE, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region. | 2014-04-17 |
20140103443 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench. | 2014-04-17 |
20140103444 | SEMICONDUCTOR DEVICE WITH A DISLOCATION STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film. | 2014-04-17 |
20140103445 | SEMICONDUCTOR SRAM STRUCTURES AND FABRICATION METHODS - Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors. | 2014-04-17 |
20140103446 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region. A second active region is in the second well region. A third active region is in the third well region. The third active region is closer to the second active region than to the first active region. A fourth active region is in the third well region. The fourth active region is closer to the first active region than to the second active region. A first conductive pattern is across the first and third active regions. A second conductive pattern is across the second and fourth active regions and parallel to the first conductive pattern. | 2014-04-17 |
20140103447 | POWER RF AMPLIFIERS - A power transistor circuit uses first and second power transistors in differential mode. An inductor arrangement of inductors is formed by wire bonds between the drains. The transistors are in a mirrored configuration, and the inductor arrangement comprises wire bonds which extend between the drain connections across the space between the mirrored transistors. | 2014-04-17 |
20140103448 | METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURES - Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device. | 2014-04-17 |
20140103449 | OXYGEN FREE RTA ON GATE FIRST HKMG STACKS - A method of fabricating a semiconductor device with improved Vt and the resulting device are disclosed. Embodiments include forming an HKMG stack on a substrate; implanting dopants in active regions of the substrate; and performing an RTA in an environment of nitrogen and no more than 30% oxygen. | 2014-04-17 |
20140103450 | HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR - A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed. | 2014-04-17 |
20140103451 | FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS - A fin field-effect transistor (finFET) assembly includes a first finFET device having fins of a first height and a second finFET device having fins of a second height. Each of the first and second finFET devices includes an epitaxial fill material covering source and drain regions of the first and second finFET devices. The epitaxial fill material of the first finFET device has a same height as the epitaxial fill material of the second finFET device. | 2014-04-17 |
20140103452 | ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES - In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm. | 2014-04-17 |
20140103453 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 2014-04-17 |
20140103454 | Lightly Doped Source/Drain Last Method For Dual-EPI Integration - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. | 2014-04-17 |
20140103455 | FET Devices with Oxide Spacers - Transistors including oxide spacers and methods of forming the same. Embodiments include planar FETs including a gate on a semiconductor substrate, oxide spacers on the gate sidewalls, and source or drain regions at least partially in the substrate offset from the gate by the oxide spacers. Other embodiments include finFETs including a fin on an insulator layer, a gate formed over the fin, a first source or drain region on a first end of the fin, a second source or drain region on a second end of the fin, and oxide spacers on the gate sidewalls separating the first source or drain region and the second source or drain from the gate. Embodiments further include methods of forming transistors with oxide spacers including forming a transistor including sacrificial spacers, removing the sacrificial spacers to form recess regions, and forming oxide spacers in the recess regions. | 2014-04-17 |
20140103456 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 2014-04-17 |
20140103457 | FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure. | 2014-04-17 |
20140103458 | GATE ELECTRODE HAVING A CAPPING LAYER - A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. | 2014-04-17 |
20140103459 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 μm. | 2014-04-17 |
20140103460 | MEMS Device and Method of Manufacturing a MEMS Device - A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack. | 2014-04-17 |
20140103461 | MEMS Devices and Fabrication Methods Thereof - A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate. | 2014-04-17 |
20140103462 | MEMS Devices and Methods for Forming the Same - A method includes forming a Micro-Electro-Mechanical System (MEMS) device on a front surface of a substrate. After the step of forming the MEMS device, a through-opening is formed in the substrate, wherein the through-opening is formed from a backside of the substrate. The through-opening is filled with a dielectric material, which insulates a first portion of the substrate from a second portion of the substrate. An electrical connection is formed on the backside of the substrate. The electrical connection is electrically coupled to the MEMS device through the first portion of the substrate. | 2014-04-17 |
20140103463 | MEMS SENSOR PACKAGE SYSTEMS AND METHODS - Embodiments relate to sensor and sensing devices, systems and methods. In an embodiment, a micro-electromechanical system (MEMS) device comprises at least one sensor element; a framing element disposed around the at least one sensor element; at least one port defined by the framing element, the at least one port configured to expose at least a portion of the at least one sensor element to an ambient environment; and a thin layer disposed in the at least one port. | 2014-04-17 |
20140103464 | Microphone System with Integrated Passive Device Die - A microphone system has a package forming an interior chamber, and a MEMS microphone secured within the interior chamber. The package forms an aperture for permitting acoustic access to the interior of the chamber and thus, the MEMS microphone. The system also has two dies; namely, the system has a primary circuit die within the interior chamber, and an integrated passive device die electrically connected with the primary circuit die. The primary circuit die is electrically connected with the MEMS microphone and has at least one active circuit element. | 2014-04-17 |
20140103465 | Surface Acoustic Wave (SAW) Device Package and Method for Fabricating Same - A surface acoustic wave (SAW) device package and method for packaging a SAW device provide a surface excited device having a small footprint, low cost and fabricated according to a unique manufacturing process. A substrate including a SAW active area on a first side is bonded to another similar sized substrate with a space sufficient to allow the propagation of the SAW on a top surface of the substrate. The two substrates have similar thermal expansion coefficients such that stress from the sealing process is minimized. The two substrates are sealed using either a low melting point glass or an organic compound such that conductive pathways exist through the seal allowing the internal device to access an external electrical connection. | 2014-04-17 |
20140103466 | RESISTANT STRAIN GAUGE - The invention relates to measurement and control of mechanical values, in particular, to control of stress conditions of various structures and manufacturing sensors of resistant strain gauge type for measuring various mechanical values. It can be used in manufacturing sensors of deformation, force, pressure, movement, vibration etc. to increase accuracy in resistant strain gauge measuring at sensitivity preservation. The resistant strain gauge for deformation and pressure measuring represents a dielectric substrate with spread strain-sensing layer in state of polycrystalline film, which contains samarium sulfide, and metal contact pads. Pads are placed on the same side of a film and output signals are soldered to them. Strain-sensing layer comprises holes which connect the pads. According to the first option, strain-sensing layer has the following composition Sm | 2014-04-17 |
20140103467 | SENSOR DEVICE, MOTION SENSOR, AND ELECTRONIC DEVICE - A sensor device includes a first electrode disposed on active surface side of a silicon substrate, an external connecting terminal electrically connected to the first electrode, at least one stress relaxation layer disposed between the silicon substrate and the external connecting terminal, a connecting terminal disposed on the active surface side of the silicon substrate, and a vibration gyro element having weight sections as mass adjustment sections, the vibration gyro element is held by the silicon substrate due to connection between the connection electrode and the external connecting terminal, and a meltage protection layer formed in an area where the stress relaxation layer and the mass adjustment section overlap each other in a plan view is provided. | 2014-04-17 |
20140103468 | MICRO-ELECTROMECHANICAL PRESSURE SENSOR HAVING REDUCED THERMALLY-INDUCED STRESS - Thermally-induced stress on a silicon micro-electromechanical pressure transducer (MEMS sensor) is reduced by attaching the MEMS sensor to a plastic filled with low C | 2014-04-17 |
20140103469 | Seed Layer for Multilayer Magnetic Materials - A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof may be inserted between the seed layer and magnetic layer. The magnetic element has thermal stability to at least 400° C. | 2014-04-17 |
20140103470 | Multibit Cell of Magnetic Random Access Memory with Perpendicular Magnetization - A multi-bit cell of magnetic random access memory comprises a magnetoresistive element including first and second free layers, each free layer comprising a reversible magnetization direction directed substantially perpendicular to a layer plane in its equilibrium state and a switching current, first and second tunnel barrier layers, and a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers; a selection transistor electrically connected to a word line, and a bit line intersecting the word line; the magnetoresistive element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents. | 2014-04-17 |
20140103471 | Low Cost High Density Nonvolatile Memory Array Device Employing Thin Film Transistors and Back to Back Schottky Diodes - An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back Schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (TFTs). The device is substantially produced in BEOL facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost. | 2014-04-17 |
20140103472 | INVERTED ORTHOGONAL SPIN TRANSFER LAYER STACK - A magnetic device includes a pinned magnetic layer having a first fixed magnetization vector with a first fixed magnetization direction. The magnetic device also includes a free magnetic layer having a variable magnetization vector having at least a first stable state and a second stable state. The magnetic device also has a first non-magnetic layer and a reference. The first non-magnetic layer spatially separates the pinned magnetic layer and the free magnetic layer. The magnetic device also includes a second non-magnetic layer spatially separating the free magnetic layer and the reference magnetic layer. A magnetic tunnel junction, located below the pinned magnetic layer, is formed by the free magnetic layer, the second non-magnetic layer, and the reference magnetic layer. Application of a current pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device switches the variable magnetization vector. | 2014-04-17 |
20140103473 | INCREASED MAGNETORESISTANCE IN AN INVERTED ORTHOGONAL SPIN TRANSFER LAYER STACK - A magnetic device includes a pinned magnetic layer and a free magnetic layer including a first body-centered cubic material and having a variable magnetization vector that has a first stable state and a second stable state. The magnetic device also includes a first non-magnetic layer and a reference layer. The first non-magnetic layer spatially separates the pinned magnetic layer and the free magnetic layer and includes a second body-centered cubic material that interfaces with the first body-centered cubic material. The magnetic device includes a second non-magnetic layer spatially separating the free magnetic layer and the reference magnetic layer. A magnetic tunnel junction, located below the pinned magnetic layer, is formed by the free magnetic layer, the second non-magnetic layer, and the reference magnetic layer. Application of a current pulse through the magnetic device switches the variable magnetization vector. | 2014-04-17 |
20140103474 | TUNNELING MAGNETORESISTANCE SENSOR - A tunneling magnetoresistance sensor includes a substrate, an insulating layer, a tunneling magnetoresistance component and a first electrode array. The insulating layer is disposed on the substrate. The tunneling magnetoresistance component is in contact with the insulating layer and includes at least one magnetic tunneling junction unit. The first electrode array disposed in direct contact with the insulating layer. The first electrode array includes a number of first electrodes. Each of the at least one magnetic tunneling junction unit is electrically connected to two neighboring first electrodes of the first electrode array to form a current-in-plane tunneling conduction mode. | 2014-04-17 |
20140103475 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a multilayer wiring layer formed over the substrate, an MTJ (Magnetic Tunnel Junction) element formed in an insulating layer located lower than an uppermost wiring layer in the multilayer wiring layer, a wiring formed in a wiring layer immediately above the MTJ element and coupled to the MTJ element, and a shield conductor region provided in the wiring or a wiring layer immediately above the wiring, and covering an entirety of the MTJ element in a plan view. | 2014-04-17 |
20140103476 | METHOD FOR MAKING IMAGE SENSORS USING WAFER-LEVEL PROCESSING AND ASSOCIATED DEVICES - A method of making image sensor devices may include forming a sensor layer including image sensor ICs in an encapsulation material, bonding a spacer layer to the sensor layer, the spacer layer having openings therein and aligned with the image sensor ICs, and bonding a lens layer to the spacer layer, the lens layer including lens in an encapsulation material and aligned with the openings and the image sensor ICs. The method may also include dicing the bonded-together sensor, spacer and lens layers to provide the image sensor devices. Helpfully, the method may use WLP to enhance production. | 2014-04-17 |
20140103477 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device with a pixel region in which a plurality of pixels with photoelectric conversion films are arrayed and pixel isolation portions are interposed between the plurality of pixels. The photoelectric conversion film is a chalcopyrite-structure compound semiconductor composed of a copper-aluminum-gallium-indium-sulfur-selenium based mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenium based mixed crystal, and is disposed on a silicon substrate in such a way as to lattice-match the silicon substrate concerned. The pixel isolation portion is a compound semiconductor subjected to doping concentration control or composition control so as to become a potential barrier between the photoelectric conversion films. | 2014-04-17 |
20140103478 | SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS - A solid-state imaging device includes: unit pixels each having a light-receiving element which is divided into line widths shorter than or equal to a wavelength of light; a plurality of light-transmissive films in a concentric structure; and an effective refractive index distribution. Among the light-transmissive films, a light-transmissive film closest to a center of the concentric structure has an outer edge in a shape of a true circle, and a light-transmissive film far from the center of the concentric structure has an outer edge in a shape of an oval, a ratio of a long axis to a short axis of the oval increases as the light-transmissive film is farther away from the center of the concentric structure, and a direction of the long axis of the oval is orthogonal to a vector which connects the center of the concentric structure and a center of the solid-state imaging device. | 2014-04-17 |
20140103479 | Dispensing Systems with Improved Sensing Capabilities - A dispensing system includes a dispenser, at least one sensor, and a shroud including at least one aperture. A virtual shield is provided between the sensor and the shroud to reduce background noise. | 2014-04-17 |
20140103480 | Mask, TFT Glass Substrate and the Manufacturing Method Thereof - A mask for partially blocking ultraviolet rays in TFT glass substrate manufacturing process is disclosed. The mask includes a panel pattern area for forming the panel patterns, and an additional pattern area for forming additional patterns in a rim of the panel pattern area. In addition, a TFT glass substrate and the manufacturing thereof are also disclosed. By arranging the additional patterns in the rim of the panel patterns, the microstructures in the rim of the panel patterns are substantially the same with that in the middle of the panel patterns. | 2014-04-17 |
20140103481 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR SUSTRATE - A semiconductor substrate according to the present invention includes: a substrate; an electrode array which is provided on the surface on one side in a thickness direction of the substrate and in which a plurality of electrodes is two-dimensionally arranged in a plan view; and a resin layer which is provided on the surface on one side and seals peripheries of the plurality of electrodes. The plurality of electrodes protrudes by greater than or equal to 5% of its own height on the resin layer and is capable of being accommodated in the resin layer by being compressed in the thickness direction. | 2014-04-17 |
20140103482 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. | 2014-04-17 |
20140103483 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug. | 2014-04-17 |
20140103484 | ELECTROSTATIC DISCHARGE DEVICES AND METHOD OF MAKING THE SAME - In one embodiment, electrostatic discharge (ESD) devices are disclosed. | 2014-04-17 |
20140103485 | ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT - The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. | 2014-04-17 |
20140103486 | ROLLED-UP INDUCTOR STRUCTURE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT (RFIC) - A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises a conductive pattern layer on a strain-relieved layer, and the conductive pattern layer comprises at least one conductive strip having a length extending in a rolling direction. The at least one conductive strip thereby wraps around the longitudinal axis in the rolled configuration. The conductive pattern layer may also comprise two conductive feed lines connected to the conductive strip for passage of electrical current therethrough. The conductive strip serves as an inductor cell of the rolled-up inductor structure. | 2014-04-17 |
20140103487 | SEMICONDUCTOR DEVICE - A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface. | 2014-04-17 |
20140103488 | POP Structures and Methods of Forming the Same - A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line. | 2014-04-17 |
20140103489 | Electronic Device Comprising a Semiconductor Structure Having an Integrated Circuit Back End Capacitor and Thin Film Resistor and Method of Manufacturing the Same - An electronic device comprising a semiconductor structure having an integrated circuit back end capacitor and an integrated circuit back end thin film resistor and a method of manufacturing the same is provided. The semiconductor structure comprises a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. Furthermore, there is a second dielectric layer which is disposed on the bottom plate of the capacitor and on top of the thin film resistor body. A top plate of the capacitor is disposed on the second dielectric layer in a region of the second dielectric layer which is defined by the lateral dimensions of the bottom plate of the capacitor. The bottom plate and the resistor body are laterally spaced apart layers which are both disposed on the first dielectric layer and which are composed of a same thin film material. | 2014-04-17 |
20140103490 | METAL-OXIDE-METAL CAPACITOR STRUCTURE - A capacitor from a Metal-Oxide-Metal (“MoM”) process may include a plurality of metal layers arranged with different design structures. The metal layers may be connected with vias. The metal layers may include wires, such as rows and/or fingers that are arranged for maximizing capacitance between adjacent fingers, as well as between fingers of different metal layers. As the spacing of the fingers is increased, the reliability, yield of final product, and ease of manufacturing both increase. The capacitor increases the spacing of wires/fingers while either maintaining or improving the capacitance per unit area. | 2014-04-17 |
20140103491 | SEMICONDUCTOR DEVICES - The present inventive concept provides semiconductor devices that may include a capacitor including a lower electrode, a dielectric layer, and an upper electrode which are sequentially stacked. An electrode-protecting layer may be provided on the capacitor. The upper electrode may include a conductive metal oxide and the electrode-protecting layer may include a sacrificial reaction layer including a metal-hydrogen compound. | 2014-04-17 |
20140103492 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - The present invention provides a method for producing a silicon wafer from a defect-free silicon single crystal grown by a CZ method, the method comprising: preparing a silicon wafer obtained by slicing the defect-free silicon single crystal and subjected to mirror-polishing; then performing a heat treatment step of subjecting the mirror-polished silicon wafer to heat treatment at a temperature of 500° C. or higher but 600° C. or lower for 4 hours or more but 6 hours or less; and performing a repolishing step of repolishing the silicon wafer after the heat treatment step such that a polishing amount becomes 1.5 μm or more. Therefore, it is an object to provide a method by which a silicon wafer can be produced at a high yield, the silicon wafer in which LPDs are reduced to a minimum, the silicon wafer with a low failure-incidence rate in an inspection step and a shipment stage. | 2014-04-17 |
20140103493 | ARRANGEMENT AND METHOD FOR MANUFACTURING A CRYSTAL FROM A MELT OF A RAW MATERIAL AND SINGLE CRYSTAL - An arrangement for manufacturing a crystal of the melt of a raw material comprises: a furnace having a heating device with one or more heating elements, which are configured to generate a gradient temperature field directed along a first direction, a plurality of crucibles for receiving the melt, which are arranged within the gradient temperature field side by side, and a device for homogenizing the temperature field within a plane perpendicular to the first direction in the at least two crucibles. The arrangement further has a filling material inserted within a space between the crucibles wherein the filling shows an anisotropic heat conductivity. Additionally or alternatively, the arrangement may comprise a device for generating magnetic migration fields, both the filling material having the anisotropic heat conductivity and the device for generating magnetic migration fields being suited to compensate or prevent the formation of asymmetric phase interfaces upon freezing of the raw melt. | 2014-04-17 |
20140103494 | Nearly Buffer Zone Free Layout Methodology - The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation. | 2014-04-17 |
20140103495 | WAFER AND METHOD FOR PROCESSING A WAFER - A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening. | 2014-04-17 |
20140103496 | SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 2014-04-17 |
20140103497 | PRODUCTION PROCESS FOR A MICROMECHANICAL COMPONENT AND MICROMECHANICAL COMPONENT - A production process for a micromechanical component includes at least partially structuring at least one structure from at least one monocrystalline silicon layer by at least performing a crystal-orientation-dependent etching step on an upper side of the silicon layer with a given ( | 2014-04-17 |
20140103498 | SELECTIVE WET ETCHING OF HAFNIUM ALUMINUM OXIDE FILMS - Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO | 2014-04-17 |
20140103499 | ADVANCED HANDLER WAFER BONDING AND DEBONDING - A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler. | 2014-04-17 |
20140103500 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 2014-04-17 |
20140103501 | CIRCUIT BOARD WITH TWINNED CU CIRCUIT LAYER AND METHOD FOR MANUFACTURING THE SAME - A circuit board with twinned Cu circuit layer and a method for manufacturing the same are disclosed, wherein the method comprises the following steps: (A) providing a substrate with a first circuit layer formed thereon, wherein the first circuit layer comprises a conductive pad; (B) forming a first dielectric layer on the surface of the substrate; (C) forming plural openings in the first dielectric layer, wherein each opening penetrates through the first dielectric layer and communicates with the conductive pad to expose the conductive pad; (D) forming a Cu seeding layer in the openings; (E) forming a nano-twinned Cu layer in the openings with an electroplating process; and (F) annealing the substrate to transfer the material of the Cu seeding layer into nano-twinned Cu, wherein the nano-twinned Cu layer and the transferred Cu seeding layer are formed into a second circuit layer. | 2014-04-17 |
20140103502 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip held on a substrate and including an expanded portion expanding outward from a side surface of a body of the first semiconductor chip; a first wire connecting the expanded portion of the first semiconductor chip to the substrate; and a second wire connecting the body of the first semiconductor chip to the substrate. | 2014-04-17 |
20140103503 | Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability - A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate. | 2014-04-17 |
20140103504 | SEMICONDUCTOR DEVICE - A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure. | 2014-04-17 |
20140103505 | DIE DOWN INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SPREADER AND LEADS - Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (QFN) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material. The peripherally positioned leads are attached to a first surface of the heat spreader, and the die is attached to the first surface of the heat spreader within a ring formed by the leads. The encapsulating material encapsulates the die on the heat spreader, encapsulates bond wires, and fills a space between the leads. A second surface of the heat spreader is exposed from the package. End portions of the leads have surfaces that are flush with a surface of the package opposite the second surface of the heat spreader, and that are used as lands for the package. | 2014-04-17 |
20140103506 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 2014-04-17 |
20140103507 | Optical Device Package And System - Optical device packages and systems are disclosed. In one embodiment, a system may comprise first and second optical device packages. A respective first and second optical path length may be associated with the first and second optical device packages. The first and second optical path lengths may be adjusted differently. However, respective first and second sets of external dimensions of the first and second optical device packages may be the same or substantially the same. In one embodiment, one or more Quad Flat No Lead (QFN) packages may be employed. | 2014-04-17 |
20140103508 | ENCAPSULATING PACKAGE FOR AN INTEGRATED CIRCUIT - An apparatus is provided. An integrated circuit or IC is secured to a package housing. The IC has an IC substrate and an epitaxial layer formed over the substrate and having an active region and an upper surface. The upper surface is substantially exposed, and bond pads are formed over the epitaxial layer. Bond fixtures are each secured to and in electrical contact with at least one of the bond pads and with the package housing. A fill formed over at least a portion of the epitaxial layer so as to substantially encapsulate the active region, where the fill has a dielectric constant that is substantially equivalent to the dielectric constant of air. Additionally, the fill has a thickness, where the thickness is sufficiently large enough to confine parasitics of the active region at the upper surface of the epitaxial layer. | 2014-04-17 |
20140103509 | Semiconductor Device and Method of Forming Conductive Ink Layer as Interconnect Structure Between Semiconductor Packages - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device. | 2014-04-17 |
20140103510 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion. | 2014-04-17 |
20140103511 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE STORAGE METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view. | 2014-04-17 |