12th week of 2010 patent applcation highlights part 55 |
Patent application number | Title | Published |
20100072436 | Ceramic Conductor Pre-Treated by Oxidising for a Zinc Anode - The invention relates to an additive to the active mass of a zinc anode for an alkaline secondary electrochemical generator. Said additive contains conductive ceramic powder, preferably titanium nitride particles which is exposed to an oxidation pre-treatment prior to the incorporation thereof into the active mass of the anode. Said ceramic powder is used as electronic conduction in the anode active mass and as zincates retention which are produced by generator discharge. Ion order to use said retentive capacity, the powder is exposed to an oxidation pre-treatment, whereby making it possible to form the binding sites on the surface of ceramic grains. The inventive additive makes it possible, starting from the first cycles of the electrode formation, to form uniform zinc deposits, thereby increasing the service life for the cycling of the zinc anode. | 2010-03-25 |
20100072437 | COMPOSITION, COLOR FILTER AND PROCESS FOR PREPARING COLOR FILTER - The invention relates to a composition comprising at least a polymer which comprises a repeating unit represented by formula (1), a discotic compound and a pigment. In the formula, each of L | 2010-03-25 |
20100072438 | HEPTARYLENE-AND OCTARYLENETETRACARBOXIMIDES AND PREPARATION THEREOF - The present invention relates to heptarylene- and octarylenetetracarboximides of the general formula (I) | 2010-03-25 |
20100072439 | COMPOSITION AND METHOD OF PREPARING NANOSCALE THIN FILM PHOTOVOLTAIC MATERIALS - A photo-absorbing layer for use in an electronic device; the layer including metal alloy nanoparticles copper, indium and/or gallium made preferably from a vapor condensation process or other suitable process, the layer also including elemental selenium and/or sulfur heated at temperatures sufficient to permit reaction between the nanoparticles and the selenium and/or sulfur to form a substantially fused layer. The reaction may result in the formation of a chalcopyrite material. The layer has been shown to be an efficient solar energy absorber for use in photovoltaic cells. | 2010-03-25 |
20100072440 | APPARATUS AND METHOD FOR DRAWING A CABLE THROUGH AN OPENING | 2010-03-25 |
20100072441 | DEVICE FOR INTRODUCING A DRAW WIRE OR ELEMENT INTO TUBES - The invention relates to an apparatus for introducing a draw wire ( | 2010-03-25 |
20100072442 | Lift For Servicing Aircraft - A compact, easily maneuverable lift that may be readily positioned and operated by one person, that is quickly and accurately adjustable to the desired height, and that is particularly applicable to servicing heavy parts such as aircraft batteries. The lift is easy to manufacture and may include a load platform configured to fit into tight spaces. Other embodiments are disclosed. | 2010-03-25 |
20100072443 | Mid-span winch with a reel-enclosing support frame - The mid-span winch has a support frame, a reel mounted in this support frame and a handle affixed to the support frame. The mid-span winch has a longitudinal axis extending horizontally from the reel and a vertical axis intersecting the longitudinal axis at a point on the reel. The handle is mounted to the support frame at a location on the support frame which is coincidental with the vertical axis. Wobbling and twisting motions in the winch body are thereby readily perceived with a true amplitude. A corrective action can then be applied to the winch body without using an excessive or a shy force. In another aspect of the present invention, the handle has a hand grip which extends obliquely from the longitudinal axis, whereby both a wobbling motion and a twisting motion on the winch body can be stabilized at once in a same grasp. | 2010-03-25 |
20100072444 | WALL ASSEMBLY - A wall assembly for mixing polluted air with less polluted air to provide moderately polluted air. The wall assembly includes means for dividing air from the roadway region into a lower part and an upper part, and means for permitting at least a portion of the upper part to flow substantially in one or more flow directions toward the leeward region. The wall assembly also includes means for directing the lower part substantially upwardly in a direction substantially transverse to the flow direction to intersect with the upper part and to mix the polluted air with said less polluted air, to provide the moderately polluted air proximal to the leeward area. | 2010-03-25 |
20100072445 | MEMORY CELL THAT INCLUDES A CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided. | 2010-03-25 |
20100072456 | OPTO-ELECTRONIC READ HEAD - A read head for a scale reading apparatus, the head including a light source and an array of photodetector elements, wherein said light source and array of photodetector elements are fabricated in a lattice matched semiconductor compound. | 2010-03-25 |
20100072457 | LIGHT-RECEIVING DEVICE - A light-receiving element device capable of receiving near infrared to mid-infrared light of 1.7 μm-3.5 μm is provided. A substrate is formed of InP, and a superlattice light-receiving layer is formed of a superlattice of a type 2 junction formed by alternately being stacked a falling layer of a Group III-V compound semiconductor including In, Ga, As, N and a rising layer of a Group III-V compound semiconductor including Ga, As, Sb. The film thickness of the falling layer and the rising layer is each 3 nm-10 nm. The entire thickness of the superlattice light-receiving layer is 2 μm-7 μm. The lattice mismatch of the constituent film of the superlattice light-receiving layer to InP is ±0.2% or less. | 2010-03-25 |
20100072458 | Methods For Sorting Nanotubes By Wall Number - The present teachings provide methods for sorting nanotubes according to their wall number, and optionally further in terms of their diameter, electronic type, and/or chirality. Also provided are highly enriched nanotube populations provided thereby and articles of manufacture including such populations. | 2010-03-25 |
20100072459 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 2010-03-25 |
20100072460 | NANOELECTRONIC DEVICE - An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device. | 2010-03-25 |
20100072461 | THERMO-ELECTRIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars. | 2010-03-25 |
20100072462 | PLANARIZING AGENTS AND DEVICES - Use of certain materials in hole injection layer and/or hole transport layer can improve operational lifetimes in organic devices. Polymers having fused aromatic side groups such as polyvinylnaphthol polymers can be used in conjunction with conjugated polymers. Inks can be formulated and cast as films in organic electronic devices including OLEDs, SMOLEDs, and PLEDs. One embodiment provides a composition comprising: at least one conjugated polymer, and at least one second polymer different from the conjugated polymer comprising at least one optionally substituted fused aromatic hydrocarbon side group. The substituent can be hydroxyl. Aqueous-based inks can be formulated. | 2010-03-25 |
20100072463 | LAMINATE STRUCTURE AND ITS MANUFACTURING METHOD - A disclosed laminate structure is capable of having its surface free energy changed with a small amount of UV irradiation. The invention also discloses a method of manufacturing the laminate structure; an electronic device having the laminate structure; an electronic device array having a plurality of the electronic devices; and a display apparatus having the electronic device array. The laminate structure includes a substrate | 2010-03-25 |
20100072464 | ORGANIC THIN-FILM TRANSISTOR SUBSTRATE, ITS MANUFACTURING METHOD, IMAGE DISPLAY PANEL, AND ITS MANUFACTURING METHOD - The present invention is a method for manufacturing an organic thin-film transistor substrate including an organic thin-film transistor as a transistor element, and an object of the invention is to provide a manufacturing method capable of forming a bank in a smaller number of steps. The method for manufacturing the organic thin-film transistor substrate of the present invention, in which an organic thin-film transistor is formed in a first region on a substrate, a second region for forming a light-emitting element in abutment with the first region is included, and a bank part is formed in a peripheral part of the second region, is characterized by including: a first step of forming the organic thin-film transistor in the first region on the substrate and forming at least one of the gate insulation layer and the organic semiconductor layer included by this organic thin-film transistor as far as the second region, thereby forming, in the second region, a bank precursor layer composed of a laminated structure formed on the second region; and a second step of removing the regions of the bank precursor layer other than the peripheral part, thereby forming the bank part made of the remaining bank precursor layer. | 2010-03-25 |
20100072465 | BARIUM COPPER SULFUR FLUORIDE TRANSPARENT CONDUCTIVE THIN FILMS AND BULK MATERIAL - The present invention is generally directed to a bulk barium copper sulfur fluoride (BCSF) material made by combining Cu | 2010-03-25 |
20100072466 | Electronic Circuit with Repetitive Patterns Formed by Shadow Mask Vapor Deposition and a Method of Manufacturing an Electronic Circuit Element - An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements. | 2010-03-25 |
20100072467 | SEMICONDUCTOR DEVICE - A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate. | 2010-03-25 |
20100072468 | DISPLAY DEVICE - A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel. | 2010-03-25 |
20100072469 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - To provide a structure suitable for a common connection portion provided in a display panel. A common connection portion provided in an outer region of a pixel portion has a stacked structure of an insulating layer formed using the same layer as a gate insulating layer, an oxide semiconductor layer formed using the same layer as a second oxide semiconductor layer, and a conductive layer (also referred to as a common potential line) formed using the same layer as the conductive layer, in which the conductive layer (also referred to as the common potential line) is connected to a common electrode through an opening in an interlayer insulating layer provided over the first oxide semiconductor layer and an electrode opposite to a pixel electrode is electrically connected to the common electrode through conductive particles. | 2010-03-25 |
20100072470 | DISPLAY DEVICE - A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved. | 2010-03-25 |
20100072471 | DISPLAY DEVICE - A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved. | 2010-03-25 |
20100072472 | Nanostructures With 0, 1, 2, and 3 Dimensions, With Negative Differential Resistance and Method for Making These Nanostructures - Nanostructures with 0, 1, 2 and 3 dimensions, with negative differential resistance and method for making these nanostructures. A nanostructure according to the invention may notably be used in nanoelectronics. It comprises at least one structure ( | 2010-03-25 |
20100072473 | TACK ADHESION TESTING DEVICE - A tack adhesion testing device for quantitatively measuring tack adhesion between a material and an object with a planar surface for contact with the material. The device has a material mount for mounting a quantity of the material such that the quantity of material presents an exposed flat face, an object mount for securely holding the object such that the planar surface is in flat contact with the exposed flat surface, the material mount and the object mount being movable relative to each other, a contact force applicator for applying a known force urging the exposed flat face and the planar surface into contact and, separation mechanism for applying a variable force to the material mount and the object mount to slide the flat face and the planar surface relative to each other such that the variable force can be increased until the flat face and the planar surface slide relative to each other. | 2010-03-25 |
20100072474 | Semiconductor Device - A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor. | 2010-03-25 |
20100072475 | SELF-ALIGNED MASKS USING MULTI-TEMPERATURE PHASE-CHANGE MATERIALS - A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask. | 2010-03-25 |
20100072476 | PIXEL STRUCTURE, DISPLAY PANEL, PHOTOELECTRIC DEVICE AND MANUFACTURING METHOD THEREOF - A pixel structure includes a substrate, a first and a second patterned conductive layers, and a pixel electrode. The first patterned conductive layer, disposed on the substrate, includes at least one scan line, at least one gate, and at least one common electrode line. The second patterned conductive layer, disposed on the first patterned conductive layer, includes at least one data line, at least one source/drain, and at least one first patterned layer partly disposed on the common electrode line. The pixel electrode, disposed on the second patterned conductive layer, includes at least one first part and one second part. The first part partly covers the first patterned layer and the common electrode line. The second part, connected to the source/drain, covers the other part of the first patterned layer. The first and second patterned layers compose at least one first capacitance. | 2010-03-25 |
20100072477 | Liquid crystal display device - A liquid crystal display device includes a first substrate and a second substrate facing each other having a pixel region; a color filter layer on the first substrate corresponding to the pixel region; a planarization layer on the color filter layer having a groove; a common electrode on the planarization layer; a pixel electrode on the second substrate; and a liquid crystal layer between the common electrode and the pixel electrode. | 2010-03-25 |
20100072478 | Flat panel display - A flat panel display that can prevent a voltage drop of a driving power and, at the same time, minimizes the characteristic reduction of electronic devices located in a circuit region where various circuit devices are located includes: a substrate; an insulating film arranged on the substrate; a pixel region including at least one light emitting diode, the pixel region arranged on the insulating film and adapted to display an image; a circuit region arranged on the insulating film and including electronic devices adapted to control signals supplied to the pixel region; and a conductive film interposed between the substrate and the insulating film in a region corresponding to the pixel region and electrically connected to one electrode of the light emitting diode. | 2010-03-25 |
20100072479 | LCD Pixel Array Structure - Only five photomasks are used to fabricate a LCD pixel array structure. A gate dielectric layer of the LCD pixel array structure is formed by two deposition steps to increase the storage capacity of the storage capacitor. | 2010-03-25 |
20100072480 | Thin film transistor and method of manufacturing the same - A thin film transistor (TFT) and a method of manufacturing the same are provided, the TFT including a gate insulating layer on a gate. A channel may be formed on a portion of the gate insulating layer corresponding to the gate. A metal material may be formed on a surface of the channel. The metal material crystallizes the channel. A source and a drain may contact side surfaces of the channel. | 2010-03-25 |
20100072481 | Method and Resulting Structure Using Silver for LCOS Devices - A method for fabricating an LCOS device. The method includes providing a semiconductor substrate and forming a plurality of MOS transistor devices formed on a portion of the semiconductor substrate. The method includes forming a first dielectric layer overlying the plurality of transistor devices and forming a first metal layer overlying the first dielectric layer. The method includes forming a second dielectric layer overlying the first metal layer and forming a plurality of pixel regions made substantially of silver bearing material overlying the second dielectric layer. In a preferred embodiment, the silver bearing material has much higher reflectivity for wavelengths of 450 nanometers and greater. | 2010-03-25 |
20100072482 | ORGANIC LIGHT EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - Disclosed are an organic light emitting display and a method of manufacturing the same. The organic light emitting includes a first substrate, a first electrode, an organic light emitting layer, and a second electrode. The first substrate includes a pixel region showing an image and a peripheral region surrounding the pixel region. The first electrode is formed in the pixel region of the first substrate. The organic light emitting layer is formed on the first electrode. The second electrode is formed on the organic light emitting layer and extends to the peripheral region. An auxiliary electrode is formed on the second electrode to contact the second electrode on an entire surface of the first substrate, thereby applying a voltage having the same voltage level as that of the second electrode. | 2010-03-25 |
20100072483 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening. | 2010-03-25 |
20100072484 | HETEROEPITAXIAL GALLIUM NITRIDE-BASED DEVICE FORMED ON AN OFF-CUT SUBSTRATE - Embodiments include but are not limited to apparatuses and systems including a heteroepitaxial gallium nitride-based device formed on an off-cut substrate, and methods for making the same. Other embodiments may be described and claimed. | 2010-03-25 |
20100072485 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD - One atomic layer of Si atoms 3 is grown on an Si-terminated SiC surface 1 | 2010-03-25 |
20100072486 | WAVELENGTH CONVERTING ELEMENTS WITH REFLECTIVE EDGES - A light emitting device ( | 2010-03-25 |
20100072487 | LIGHT EMITTING DIODE, PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED), a fabricating method thereof, and a package structure thereof are provided. The LED includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, a current distribution modifying pattern, a first electrode and a second electrode. The active layer and the second semiconductor layer form a mesa structure and expose a part of the first semiconductor layer. The current distribution modifying pattern is disposed on the second semiconductor layer. The first electrode is disposed on and electrically connected to the first semiconductor layer exposed by the mesa structure. The second electrode is disposed on the current distribution modifying pattern and is electrically connected to the second semiconductor layer. The LED has superior light emitting efficiency. | 2010-03-25 |
20100072488 | LED WITH CONTROLLED ANGULAR NON-UNIFORMITY - A light source that uses a light emitting diode with a wavelength converting element is configured to produce a non-uniform angular color distribution, e.g., Δu′v′>0.015 within an angular distribution from 0° to 90°, that can be used with specific light based device that translate the angular color distribution into a uniform color distribution. The ratio of height and width for the wavelength converting element is selected to produce the desired non-uniform angular color distribution. The use of a controlled angular color non-uniformity in the light source and using it in applications that translate the non-uniformity into a uniform color distribution, e.g., with a uniformity of Δu′v′<0.01, increases the efficiency of the system compared to conventional systems in which a uniform angular light emitting diode is used. | 2010-03-25 |
20100072489 | SEMICONDUCTOR LIGHT EMITTING DEVICES GROWN ON COMPOSITE SUBSTRATES - A plurality of III-nitride semiconductor structures, each comprising a light emitting layer disposed between an n-type region and a p-type region, are grown on a composite substrate. The composite substrate includes a plurality of islands of III-nitride material connected to a host by a bonding layer. The plurality of III-nitride semiconductor structures are grown on the III-nitride islands. The composite substrate may be formed such that each island of III-nitride material is at least partially relaxed. As a result, the light emitting layer of each semiconductor structure has an a-lattice constant greater than 3.19 angstroms. | 2010-03-25 |
20100072490 | LOW COST FLEXIBLE DISPLAY SHEET - Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, onto a subsequent flexible surface using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used with an intermediate transfer member. In some embodiments the IC element can be incorporated into a subsequent flexible surface including components for a TV, radiographic detector, sensor array, or any similar product having a requirement to emit, detect, or collect energy. In addition, the IC elements can be RF emitting, or visually emitting. | 2010-03-25 |
20100072491 | LED chip module - A LED chip module comprises a base board comprising a PCB circuit therein; and a LED chip mounting on the base board comprising a supporting frame comprising a case having a peripheral wall defining an inner room therein, and a plurality of pairs of pins provided at both sides of the case, wherein each pair of pins extending through the peripheral wall of both sides of the case respectively from the inner room of the case to the outside of the case connecting with the PCB circuit; and a LED circuit is disposed in the case, which comprises a plurality of LEDs and a plurality of pairs of conducting wires, wherein each pair of conducting wire have one end connecting to the both sides of a LED respectively, and has another end connecting to a pair of pins in the inner room of the case respectively. | 2010-03-25 |
20100072492 | Package Substrate and Light Emitting Device Using the Same - A package substrate of the present invention at least comprises a metal substrate and a plurality of light emitting dies. The metal substrate is provided thereon with at least one trench. The trench is recessed into the surface of the metal substrate through an insulating layer. The light emitting dies are secured in the trench and electrically connected to a predetermined wiring layer on the metal substrate by metal wires, thereby obtaining a light emitting die package substrate with good thermal conductivity, high heat dissipation, separate electrical and thermal paths and a simple and firm structure. | 2010-03-25 |
20100072493 | ACTIVE MATRIX SUBSTRATE - In an active matrix substrate ( | 2010-03-25 |
20100072494 | LIGHT EMITTING DIODE HAVING LIGHT EMITTING CELL WITH DIFFERENT SIZE AND LIGHT EMITTING DEVICE THEREOF - There is provided a light emitting diode operating under AC power comprising a substrate; a buffer layer formed on the substrate; and a plurality of light emitting cells formed on the buffer layer to have different sizes and to be electrically isolated from one another, the plurality of light emitting cells being connected in series through metal wires. | 2010-03-25 |
20100072495 | CONTACT STRUCTURE AND SEMICONDUCTOR DEVICE - To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion ( | 2010-03-25 |
20100072506 | ULTRAVIOLET LIGHT EMITTING DIODE PACKAGE - An ultraviolet light emitting diode package for emitting ultraviolet light is disclosed. The ultraviolet light emitting diode package comprises an LED chip emitting light with a peak wavelength of 350 nm or less, and a protective member provided so that surroundings of the LED chip is covered to protect the LED chip, the protective member having a non-yellowing property to energy from the LED chip. | 2010-03-25 |
20100072507 | Lead frame, and light emitting diode module having the same - A light emitting diode (LED) module includes a lead frame having a number (N) of conducting arms spaced apart from each other, where N≧3, and at least one LED die mounted on one of any two neighbor conducting arms. Any two neighbor conducting arms are electrically coupled each other. | 2010-03-25 |
20100072508 | Group III nitride semiconductor light-emitting device and method for producing the same - A method for producing a Group III nitride semiconductor light-emitting device with a face-up configuration including a p-type layer and a transparent electrode composed of ITO is provided in which a p-pad electrode on the transparent electrode and an n-electrode on an n-type layer are simultaneously formed. The p-pad electrode and the n-electrode are composed of Ni/Au. The resultant structure is heat treated at 570° C. and good contact can be established in the p-pad electrode and the n-electrode. The heat treatment also provides a region in the transparent electrode immediately below the p-pad electrode, the region and the p-type layer having a higher contact resistance than that of the other region of the transparent electrode and the p-type layer. Thus, a region of an active layer below the provided region does not emit light and hence the light-emitting efficiency of the light-emitting device can be increased. | 2010-03-25 |
20100072509 | Lead frame assembly, lead frame and insulating housing combination, and led module having the same - A unitary lead frame assembly having a plurality of lead frame sets each comprises a first lead frame unit. The first lead frame unit has a pair of first and second frame portions extending along a first direction and spaced apart from each other along a second direction different from the first direction. The lead frame set further comprises at least two second lead frame units disposed between the first and second frame portions and spaced apart from each other along the second direction. Each of the second lead frame units cooperates with the first lead frame unit to define at least one first die-bonding area therebetween. | 2010-03-25 |
20100072510 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE/CAP HEAT SPREADER - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post, a base and a cap. The post extends upwardly from the base into an opening in the adhesive, the base extends below and laterally from the post, and the cap extends above and laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal and the heat spreader provides thermal dissipation between the cap and the base. | 2010-03-25 |
20100072511 | SEMICONDUCTOR CHIP ASSEMBLY WITH COPPER/ALUMINUM POST/BASE HEAT SPREADER - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post and a base that include a copper surface layer and an aluminum core. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal. | 2010-03-25 |
20100072512 | Silicon break over diode - A Break Over Diode (“BOD”) device is a gate-less two terminal high power semiconductor switch in which transitions from a blocking state to a conducting state are triggered by a dV/dt pulse to the anode. The BOD device can be thought of as two cross-coupled PNP and NPN transistors, and includes both anode and cathode shorts which reduce the gain of the NPN and PNP transistors by shunting some current away from their bases directly to their emitters, thereby improving blocking. Moreover, the anode and cathode shorts in conjunction with the device blocking junction form PN diodes which are distributed throughout the bulk of the material and function as anti-parallel diodes to the base-emitter junctions of the PNP and NPN transistors, which enables the BOD device to handle a larger current reversal for a longer period of time. The P base layer may be made thin to decrease the voltage fall time from full blocking to full conduction, and the cathode and anode shorts may be provided in a honeycomb pattern. | 2010-03-25 |
20100072513 | SEMICONDUCTOR HETEROSTRUCTURES AND MANUFACTURING THEREOF - A semiconductor heterostructure ( | 2010-03-25 |
20100072514 | HIGH OPERATING TEMPERATURE BARRIER INFRARED DETECTOR WITH TAILORABLE CUTOFF WAVELENGTH - A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array. | 2010-03-25 |
20100072515 | FABRICATION AND STRUCTURES OF CRYSTALLINE MATERIAL - A surface of the first semiconductor crystalline material has a reduced roughness. A semiconductor device includes a low defect, strained second semiconductor crystalline material over the surface of the first crystalline material. A surface of the strained second semiconductor crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters that reduce impurities at an interfacial boundary between the first and second semiconductor crystalline materials. In one embodiment, the first semiconductor crystalline material can be confined by an opening in an insulator having an aspect ratio sufficient to trap defects using Aspect Ratio Trapping techniques. | 2010-03-25 |
20100072556 | Semiconductor device and associated methods - A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode. | 2010-03-25 |
20100072557 | Semiconductor Constructions - Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C | 2010-03-25 |
20100072558 | METHOD FOR MANUFACTURING HIGH-STABILITY RESISTORS, SUCH AS HIGH OHMIC POLY RESISTORS, INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer. | 2010-03-25 |
20100072559 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations. | 2010-03-25 |
20100072560 | Nonvolatile Memory Device and Method of Manufacturing the same - A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed. | 2010-03-25 |
20100072561 | METHOD FOR FABRICATING MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) DEVICE - A micro-electro-mechanical system (MEMS) device includes a substrate, having a first side and second side, the second side has a cavity and a plurality of venting holes in the substrate at the second side with connection to the cavity. However, the cavity is included in option without absolute need. A structural dielectric layer has a dielectric structure and a conductive structure in the dielectric structure. The structural dielectric layer has a chamber in connection to the cavity by the venting holes. A suspension structure layer is formed above the chamber. An end portion is formed in the structural dielectric layer in fix position. A diaphragm has a first portion of the diaphragm fixed on the suspension structure layer while a second portion of the diaphragm is free without being fixed. | 2010-03-25 |
20100072562 | FUNCTIONAL ELEMENT PACKAGE AND FABRICATION METHOD THEREFOR - A functional element package includes a silicon substrate with a functional element having one of a mobile portion and a sensor thereon; a seal member being bonded with the silicon substrate to form an airtightly sealed space therein, and including a step portion in its height direction; a first wiring portion being connected with the functional element and extending from the airtightly sealed space to an outside thereof; a second wiring portion being different from the first wiring portion and extending from the step portion to an upper surface of the seal member; and a bump on the second wiring portion, in which the first wiring portion is bent towards the airtightly sealed space and connected via a photoconductive member with the second wiring portion on the step portion. | 2010-03-25 |
20100072563 | SUBSTRATE BONDED MEMS SENSOR - A MEMS sensor includes a first substrate; a second substrate; a movable electrode portion and a fixed electrode portion which are arranged between the first substrate and the second substrate, wherein: conductive supporting portions of the movable electrode portion and the fixed electrode portion are, respectively, fixedly secured to a surface of the first substrate via a first insulating layer; a second insulating layer, a lead layer buried into the second insulating layer, and connection electrode portions that are electrically connected to the lead layer to be individually connected to the conductive supporting portions are provided on a surface of the second substrate; a metallic connection layer is formed on the surface of one of the respective conductive supporting portions; one of the respective connection electrode portions and the metallic connection layer are bonded together by eutectic bonding or diffusion bonding; and, at least each of the connection electrode portions has a thickness of about 4 μm or smaller. | 2010-03-25 |
20100072564 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of the invention includes: a substrate having a hollowed hollow section on a top surface; a semiconductor chip mounted in the hollow section of the substrate; and a lid having a substantially plate-shaped top plate section that opposes the substrate and covers the hollow section, and having at least one pair of side wall sections that project from a circumference of the top plate section towards the substrate and that engage with a side surface of the substrate. The substrate and the lid can be accurately positioned. | 2010-03-25 |
20100072565 | Soft Mems - A microscale polymer-based apparatus comprises a substrate formed from a first polymer material and at least one active region integrated with the substrate. The at least one active region is patterned from a second polymer material that is modified to perform at least one function within the at least one active region. | 2010-03-25 |
20100072566 | Magnetic Element Utilizing Protective Sidewall Passivation - Exemplary embodiments of the invention are directed to magnetic elements including a passivation layer for isolation from other on-chip elements. One embodiment is directed to an apparatus comprising a magnetic tunnel junction (MTJ) element. The MTJ element comprises: a first ferromagnetic layer; a second ferromagnetic layer; an insulating layer disposed between the first and second ferromagnetic layers; and an MTJ passivation layer forming protective sidewalls disposed adjacent to the first ferromagnetic layer, the second ferromagnetic layer, and the insulating layer. | 2010-03-25 |
20100072567 | Image Sensor and Method For Manufacturing the Same - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes an isolation trench formed in a semiconductor substrate corresponding to a logic region and a pixel separating trench formed on the semiconductor substrate corresponding to a pixel region and having a depth shallower than a depth of the isolation trench of the logic region, a barrier region formed below the pixel separating trench, a pixel separator formed inside the pixel separating trench, a gate formed above the semiconductor substrate, a first doped region formed at a deep region of the semiconductor substrate corresponding to one side of the gate, an additionally-doped region interposed between the first doped region and the barrier region, and a second doped region formed at a shallow region of the semiconductor substrate such that the second doped region makes contact with the first doped region. | 2010-03-25 |
20100072568 | Image Sensor and Method of Manufacturing the Same - An image sensor and a method of manufacturing the same are disclosed. The image sensor includes a plurality of photodiodes on a substrate, an dielectric layer on the plurality of the photodiodes, a metal line layer in the dielectric layer corresponding to a border region between neighboring photodiodes, the metal line layer having a curved backside, a color filter layer on the dielectric layer, and a microlens on the color filter layer. | 2010-03-25 |
20100072569 | Method of forming an isolation layer, method of manufacturing a semiconductor device using the same, and semiconductor device having an isolation layer - In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids. | 2010-03-25 |
20100072570 | Semiconductor Device and Method of Forming Embedded Passive Circuit Elements Interconnected to Through Hole Vias - A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via. | 2010-03-25 |
20100072571 | EFFECTIVE EFUSE STRUCTURE - An electrically programmable fuse (eFuse) comprises a semiconductor layer, a silicide layer overlying the semiconductor layer, and first and second contact structures electrically coupled to the silicide layer. The first contact structure is configured to function as an anode and the second contact structure is configured to function as a cathode. The eFuse further comprises a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure. Responsive to (i) a programming voltage potential supplied between the first and second contact structures and (ii) a voltage potential supplied to the back-gate structure, silicide of the silicide layer operates to migrate, with an enhanced migration, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures. | 2010-03-25 |
20100072572 | SEMICONDUCTOR DEVICE - One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil. | 2010-03-25 |
20100072573 | METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 2010-03-25 |
20100072574 | Semiconductor Device and Manufacturing Method Thereof - A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resistor unit is electrically disconnected as necessary. The first resistor units may be either a unit including a single resistor or may be a unit including a plurality of resistors. | 2010-03-25 |
20100072575 | LAYOUT PATTERNS FOR DEEP WELL REGION TO FACILITATE ROUTING BODY-BIAS VOLTAGE - Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors. | 2010-03-25 |
20100072586 | QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed. | 2010-03-25 |
20100072587 | IC SOCKET HAVING HEAT DISSIPATION FUNCTION - It is an object of the present invention to provide an IC socket that has a configuration to promote heat dissipation from an IC device in a simple configuration, and prevent overheating of the IC device under test. Contact pins | 2010-03-25 |
20100072588 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same - The present invention discloses a structure of device package comprising a first substrate with a die metal pad, a first wiring circuit on top surface of said first substrate and a second wiring circuit on bottom surface of said first substrate. A die is disposed on the die metal pad. A second substrate has a die opening window for receiving the die, a third wiring circuit on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. | 2010-03-25 |
20100072589 | SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD - A semiconductor package system includes: providing a leadframe with a lead; making a die support pad separately from the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the lead; and connecting a bonding pad on the semiconductor die to the lead using a bonding wire. | 2010-03-25 |
20100072590 | Stacking Quad Pre-Molded Component Packages, Systems Using the Same, and Methods of Making the Same - Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads. | 2010-03-25 |
20100072591 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ANTI-PEEL PAD - An integrated circuit package system includes: forming an anti-peel pad having both a concave ring and an external terminal with the concave ring, having a peripheral wall, surrounding the external terminal; connecting an integrated circuit with the anti-peel pad; and forming an encapsulation over the integrated circuit, the concave ring, and the external terminal with the encapsulation under the peripheral wall. | 2010-03-25 |
20100072592 | LIGHT SOURCE USING A LIGHT-EMITTING DIODE - A light source is described herein. An embodiment of the light source comprises a mounting surface and a first lead frame. The first lead frame extends from the mounting surface. The first lead frame comprises a first portion extending from the mounting surface; a cup portion having a cup portion first side and a cup portion second side, the cup portion first side configured to receive a light-emitting diode, the cup portion second side being located opposite the cup portion first side; and a second portion extending between the first portion and the cup portion second side. | 2010-03-25 |
20100072593 | Semiconductor package and method for manufacturing the same - A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected. | 2010-03-25 |
20100072594 | LOW COST DIE PLACEMENT - Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer. | 2010-03-25 |
20100072595 | METHOD AND SYSTEM FOR SEALING A SUBSTRATE - A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate to a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane. | 2010-03-25 |
20100072596 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT - An integrated circuit package system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect. | 2010-03-25 |
20100072597 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES - An integrated circuit package system provides: forming a stack module including: providing a stack die and encapsulating the stack die with an insulating material having a protruding support and a pad connected to the stack die; mounting the stack module on a package base; connecting the pad to the package base; mounting a top die on the protruding support; connecting the top die to the package base; and encapsulating the top die, the package base, and the stack module with a package encapsulant. | 2010-03-25 |
20100072598 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 2010-03-25 |
20100072599 | Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection - A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps. | 2010-03-25 |
20100072600 | FINE-PITCH OBLONG SOLDER CONNECTIONS FOR STACKING MULTI-CHIP PACKAGES - A semiconductor PoP device ( | 2010-03-25 |
20100072601 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises a substrate and a first semiconductor element. The substrate comprises an inner layer conductor and a cavity comprising the bottom surface on which a part of the inner layer conductor is exposed. The first semiconductor element contacts, in the cavity, the inner layer conductor directly or via a good heat conductor material. | 2010-03-25 |
20100072602 | STACKED INTEGRATED CIRCUIT PACKAGE USING A WINDOW SUBSTRATE - An integrated circuit (IC) package is disclosed. The IC package includes a first substrate having a first surface having first substrate bond pads, a second surface having second substrate bond pads, and an opening that extends from the first surface to the second surface. The IC package further includes a first IC having a first IC surface that includes first bond pads and that is directly attached to the second surface of the first substrate, and a second IC surface. The first bond pads are accessible through the opening. The IC package also includes a second IC having a third IC surface that is directly attached to the second IC surface, and a fourth IC surface that includes second bond pads. At least one of the first bond pads is connected to at least one of the first substrate bond pads using one or more bond wires. At least one of the second bond pads is connected to at least one of the second substrate bond pads using one or more bond wires. The opening has a first side and a second side. The first substrate bond pads are located adjacent to only the first side of the opening. | 2010-03-25 |
20100072603 | SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES WITH EDGE CONTACTS AND SACRIFICIAL SUBSTRATES AND OTHER INTERMEDIATE STRUCTURES USED OR FORMED IN FABRICATING THE ASSEMBLIES OR PACKAGES - A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device. | 2010-03-25 |
20100072604 | SEMICONDUCTOR DEVICE - To provide a technique of supplying a voltage generated in any of a plurality of semiconductor chips to the other chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. | 2010-03-25 |
20100072605 | Semiconductor Package With a Controlled Impedance Bus and Method of Forming Same - An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points. | 2010-03-25 |