12th week of 2015 patent applcation highlights part 18 |
Patent application number | Title | Published |
20150076568 | Junction Field Effect Transistor with Vertical PN Junction - An embodiment relates to a JFET with a channel region and a gate region forming a pn junction. Between a source region and a drain region in a semiconductor portion, the pn junction extends along a vertical direction perpendicular to a first surface of the semiconductor portion. The source, channel and drain regions have a first conductivity type and are arranged along the vertical direction. The gate region and a shielding region between the gate and drain regions have a second, complementary conductivity type. An auxiliary region separates the gate and shielding regions in the semiconductor portion. | 2015-03-19 |
20150076569 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The dummy fin region, comprising a plurality of dummy fins, is formed on two sides of the active fin region, and the dummy fins are formed on two sides of the gate strip. | 2015-03-19 |
20150076570 | Semiconductor Module and Method for Manufacturing the Same - There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and the wiring pattern on the substrate by solder mounting operation, in the same process of solder mounting operation for mounting the bare-chip transistor or other surface mounting devices on the wiring patterns on the substrate. A semiconductor module includes: a plurality of wiring patterns formed on an insulating layer; a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; and a copper connector constituted of a copper plate for jointing an electrode formed on a top surface of the bare-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder. | 2015-03-19 |
20150076571 | METHOD OF FABRICATING METAL-INSULATOR-SEMICONDUCTOR TUNNELING CONTACTS USING CONFORMAL DEPOSITION AND THERMAL GROWTH PROCESSES - A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator. | 2015-03-19 |
20150076572 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a plurality of photoelectric conversion elements arranged on the semiconductor substrate to collectively form an image sensor, a plurality of trenches each formed between the photoelectric conversion elements adjacent to each other, and a plurality of impurity diffusion layers each provided at a bottom of the trench at a position deeper than a p-n junction of the photoelectric conversion element. | 2015-03-19 |
20150076573 | METHOD FOR PRODUCING AN OPTICAL FILTER IN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes a substrate and an interconnect part above the substrate, and further includes a photosensitive region in the substrate. A filter is provided aligned with the photosensitive region. The filter is formed by at least one layer of filter material. In one implementation for front side illumination, the layer of filter material is positioned above the photosensitive region between the interconnect part and the substrate. In another implementation for back side illumination, the layer of filter material is positioned below the photosensitive region opposite the interconnect part. The layer of filter material is configured such that a product of the thickness of the layer of filter material and the imaginary part of the refractive index of the layer of filter material is above 1 nm. | 2015-03-19 |
20150076574 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREFOR - A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion. | 2015-03-19 |
20150076575 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED COUPLING CAPACITOR - An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line. | 2015-03-19 |
20150076576 | DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed. | 2015-03-19 |
20150076577 | Three Dimensional Three Semiconductor High-Voltage Capacitors - An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor. | 2015-03-19 |
20150076578 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device is provided with a memory-cell region; a peripheral-circuit region disposed adjacent to the memory-cell region a first memory-cell unit disposed in a first layer located in the memory-cell region; a second memory-cell unit disposed in a k-th layer of the memory-cell region where k is an integer equal to or greater than 2, the second memory-cell unit having an element region extending in a first direction and having a first width in a second direction crossing the first direction; and a peripheral-circuit element disposed in the first layer located in the peripheral-circuit region. Two or more dummy element each having a second width 2n+1 times greater than the first width in the second direction are disposed in the k-th layer located in the peripheral-circuit region where n is an integer equal to or greater than 0. | 2015-03-19 |
20150076579 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a semiconductor memory device, a block selection transistor is provided between a stacked body and a word line in a hierarchy selection area. The block selection transistor includes a plurality of semiconductor bodies, a plurality of gate insulating films, and a gate electrode. The plurality of semiconductor bodies respectively extend from the end portions of the respective electrode layers to the respective word lines. The plurality of gate insulating films are provided on the side walls of the respective semiconductor bodies. The gate electrode faces the side wall of the semiconductor body through the gate insulating film. | 2015-03-19 |
20150076580 | METHOD OF INTEGRATING SELECT GATE SOURCE AND MEMORY HOLE FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening. | 2015-03-19 |
20150076581 | MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICE OF THE SAME - A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate. | 2015-03-19 |
20150076582 | TRANSISTOR AND FABRICATION METHOD THEREOF - A transistor is provided. The transistor includes a substrate, a gate electrode formed on the substrate, and multiple floating gates formed on the substrate. A fixed distance is designed between the adjacent floating gates. Wherein, the substrate, the multiple floating gates, and the gate electrode are separated by a plurality of active regions. | 2015-03-19 |
20150076583 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate and memory cell transistors having a gate electrode above the substrate, and an oxide film. The gate electrode includes a charge storage layer above the substrate, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, the control gate electrode including a metal film. The oxide film is disposed on the metal film. | 2015-03-19 |
20150076584 | HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION - A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion. | 2015-03-19 |
20150076585 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of sidewalls defining a width of the trench that is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth that is closer to the bottom of the trench than the first depth and the trench has an insulating material covering at least the trench sidewalls. Further embodiments include a memory device including a stack of material layers and an active memory cell region defined between a pair of trenches, and within the active region the stack comprises alternating layers of a first material and a second material, and outside of the active region the stack comprises alternating layers of the first material and a third material. | 2015-03-19 |
20150076586 | SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device. | 2015-03-19 |
20150076587 | NONVOLATILE MEMORY DEVICES HAVING A THREE DIMENSIONAL STRUCTURE - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 2015-03-19 |
20150076588 | VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer. | 2015-03-19 |
20150076589 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment has a first conductive type first semiconductor layer, a second conductive type second semiconductor layer provided in the first semiconductor layer having a first lateral surface and a first bottom portion contacting the first semiconductor layer. The second semiconductor layer has a first void portion inside. A second conductive type impurity concentration decreases from the first lateral surface toward the first void portion. And the device has a second conductive type third semiconductor layer provided in the first semiconductor layer such that the first semiconductor layer is sandwiched between the third semiconductor layer and the second semiconductor layer. The third semiconductor layer has a second lateral surface and a second bottom portion contacting the first semiconductor layer. The third semiconductor layer has a second void portion inside. A second conductive type impurity concentration decreases from the second lateral surface toward the second void portion. | 2015-03-19 |
20150076590 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. | 2015-03-19 |
20150076591 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes first and second trenches extending from the first surface into the semiconductor body. The semiconductor device further includes at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches. The semiconductor device further includes at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. | 2015-03-19 |
20150076592 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a trench on a semiconductor layer of a first conductive type; forming a first insulation film which covers an inner surface of the trench; forming a first conductive material on the first insulation film; etching the first conductive material and then the first insulation film such that the semiconductor layer is exposed on an inner surface of an upper portion of the trench and an upper end portion of the first conductive material is positioned above an upper end portion of the first insulation film; re-etching the first conductive material; forming a second insulation film which covers the semiconductor layer exposed on the inner surface of the upper portion of the trench and the first conductive material; and forming a second conductive material on the first insulation film and the second insulation film. | 2015-03-19 |
20150076593 | POWER DEVICES, STRUCTURES, COMPONENTS, AND METHODS USING LATERAL DRIFT, FIXED NET CHARGE, AND SHIELD - Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended. | 2015-03-19 |
20150076594 | SUPER-JUNCTION STRUCTURES HAVING IMPLANTED REGIONS SURROUNDING AN N EPITAXIAL LAYER IN DEEP TRENCH - A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier. | 2015-03-19 |
20150076595 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on the drift layer so as to contact the trench gate; a first conductive type source region formed on the well region so as to contact the trench gate; and a device protection region formed below a height of a lowermost portion of the source region in a height direction. | 2015-03-19 |
20150076596 | ASYMMETRIC SEMICONDUCTOR DEVICE - A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance. | 2015-03-19 |
20150076597 | SEMICONDUCTOR COMPONENT HAVING A PASSIVATION LAYER AND PRODUCTION METHOD - A semiconductor component and a method for producing a semiconductor component are described. The semiconductor component includes a semiconductor body including an inner zone and an edge zone, and a passivation layer, which is arranged at least on a surface of the semiconductor body adjoining the edge zone. The passivation layer includes a semiconductor oxide and that includes a defect region having crystal defects that serve as getter centers for contaminations. | 2015-03-19 |
20150076598 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a switching element and a diode provided on a substrate. The switching element includes a first semiconductor layer, a drain region, a source region, a channel region, a gate insulating film, and a gate electrode. The diode includes a second semiconductor layer, an anode region, and a cathode region. | 2015-03-19 |
20150076599 | SUPER JUNCTION SEMICONDUCTOR DEVICE - There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area. | 2015-03-19 |
20150076600 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions. | 2015-03-19 |
20150076601 | LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A liquid crystal display panel includes a substrate, a thin film transistor array, a circuit, and a dummy circuit. One surface of the substrate is divided into a display region and a wiring region. The thin film transistor array is formed on the display region. The circuit and the dummy circuit are formed on the wiring region, the dummy circuit is adjacent to the circuit, and the circuit and the dummy circuit protrude from the substrate. | 2015-03-19 |
20150076602 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure, comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance. | 2015-03-19 |
20150076603 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void. Short-channel effects are significantly suppressed through forming super-steep retrograde well (SSRW). | 2015-03-19 |
20150076604 | FIELD EFFECT TRANSISTOR INCLUDING A RECESSED AND REGROWN CHANNEL - At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer. | 2015-03-19 |
20150076605 | Switching Device with Free-Wheeling Diode - The disclosure provides a switching device with a free-wheeling diode, including a switching tube; a heat radiating substrate is arranged on the drain electrode of the switching tube; the switching device further includes a heat radiating component, which is connected with the heat radiating substrate of the switching tube by contact; the free-wheeling diode is a compression joint type diode; the anode end face of the free-wheeling diode is abutted against the heat radiating component, and is electrically connected with the drain electrode of the switching tube via the heat radiating component, which not only realizes the heat radiation function by using the heat radiating component, but also realizes the electric connection to the heat radiating substrate by using the electrical conductivity of the heat radiating component. | 2015-03-19 |
20150076606 | SEMICONDUCTOR DEVICE WITH LOW-K SPACER - A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner. | 2015-03-19 |
20150076607 | FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS - Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions. The contiguous metal semiconductor alloy region is in contact with angled surfaces of the plurality of raised active regions, and can provide a greater contact area and lower parasitic contact resistance than a semiconductor structure including merged semiconductor fins of comparable sizes. Merged fins enable smaller, and/or fewer, contact via structures than a total number of raised active regions can be employed to reduce parasitic capacitance between a gate electrode and the contact via structures. | 2015-03-19 |
20150076608 | DUAL EPITAXY REGION INTEGRATION - A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region | 2015-03-19 |
20150076609 | METHODS OF FORMING STRESSED LAYERS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer. | 2015-03-19 |
20150076610 | Field Effect Transistor Structure Having One or More Fins - A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A raised source terminal is disposed on a fin adjacent to a sidewall spacer of a gate structure. The drain terminal and a first portion of the gate structure overlie a first well of a first conductivity type. A raised drain terminal is disposed such that it is spaced apart from the gate structure sidewalls. In some embodiments the drain terminal is disposed on a second, separate fin. the drain terminal and a second portion of the gate structure overlie a second well of a second conductivity type. | 2015-03-19 |
20150076611 | Semiconductor Device and Manufacturing Method Thereof - Provided are a semiconductor device in which the occurrence of a short circuit between a gate electrode and either of the source/drain regions of a transistor can be suppressed and a manufacturing method thereof. In the semiconductor device, a first insulating layer formed over the gate electrode and containing a silicon nitride has an upper surface having a depressed portion which is formed in a region over a second electrode layer of the gate electrode containing a silicide. | 2015-03-19 |
20150076612 | Semiconductor Device - The semiconductor device includes a bit line, a word line intersecting the bit line, a plurality of first contact patterns, and a plurality of second contact patterns. The word line extends so as to intersect the bit line in plan view. Each of the first contact patterns is elongated in the direction in which the bit line extends in plan view. Each of the second contact patterns is elongated in directions inclined with respect to the respective directions in which the bit line and the word line extend in plan view. The first contact patterns and the second contact patterns are formed in the same layer over the main surface of a semiconductor substrate. | 2015-03-19 |
20150076613 | OVERLAY MARK - An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The length of the first feature is greater than the width of the first feature. The overlay mark also comprises a second feature in a second layer over the first layer. The second feature has a length extending in the second longitudinal direction and a width extending in the first longitudinal direction. The length of the second feature is greater than the width of the second feature. The overlay mark further comprises a third feature in a third layer over the second layer. The third feature is a box-shaped opening in the third layer. | 2015-03-19 |
20150076614 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 2015-03-19 |
20150076615 | INTERDIGITATED FINFETS - A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer. | 2015-03-19 |
20150076616 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern. | 2015-03-19 |
20150076617 | METHODS OF FORMING PATTERNS OF A SEMICONDUCTOR DEVICE - Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask. | 2015-03-19 |
20150076618 | INTEGRATED CIRCUITS WITH A CORRUGATED GATE, AND METHODS FOR PRODUCING THE SAME - Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator. | 2015-03-19 |
20150076619 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Variations in the contact area between contact plugs are suppressed to suppress fluctuations in contact resistance. In three third interlayer insulating films, a contact hole is self-alignedly formed to extend through the portions thereof interposed between two wiring portions and the portions thereof interposed between two gate wiring portions and reach a first polysilicon plug. In the contact hole, a second polysilicon plug is formed to come in contact with the first polysilicon plug. | 2015-03-19 |
20150076620 | METHOD FOR MANUFACTURING TRANSISTORS AND ASSOCIATED SUBSTRATE - The disclosed technology generally relates to semiconductor devices, and more particularly to different types of transistors having different channel materials. In one aspect, a method of fabricating a semiconductor device includes providing a substrate comprising a silicon substrate having a main surface oriented in a {100} crystal plane and having a notch oriented in a <100> direction. The method additionally includes forming a plurality of silicon protrusions in a first predetermined region by recessing portions of the main surface surrounding the silicon protrusions. The method additionally includes forming shallow trench isolation (STI) structures adjacent to the silicon protrusions to electrically isolate the silicon protrusions, thereby defining channel areas of a transistor of a first type. The method further includes removing at least upper portions of the silicon protrusions, thereby forming trenches between neighboring STI structures and filling the trenches with a III-V material. | 2015-03-19 |
20150076621 | Epitaxial Formation Mechanisms of Source and Drain Regions - The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH | 2015-03-19 |
20150076622 | REDUCING GATE EXPANSION AFTER SOURCE AND DRAIN IMPLANT IN GATE LAST PROCESS - A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed. | 2015-03-19 |
20150076623 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 2015-03-19 |
20150076624 | INTEGRATED CIRCUITS HAVING SMOOTH METAL GATES AND METHODS FOR FABRICATING SAME - Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal. | 2015-03-19 |
20150076625 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a gate wire including a laminated film in which a polysilicon film, a barrier conductive film, and a metal film are laminated in this order; a first contact plug/upper layer wire arranged above the source or the drain; a second upper layer wire arranged above an element isolation region; a second contact plug arranged apart from the second upper layer wire and connecting the metal film and the polysilicon film above a channel region; and a third contact plug formed apart from the polysilicon film in the element isolation region and connecting the second upper layer wire and the metal film. The second contact plug includes a barrier metal in contact with the polysilicon film and the barrier conductive film is made of WN, TaN, or Ta and the barrier metal is made of Ti or TiN. | 2015-03-19 |
20150076626 | ELECTRONIC DEVICE - According to one embodiment, an electronic device includes a substrate, a first electrode provided stationary above the substrate and used for a variable capacitor, a second electrode provided movable above or below the first electrode and used for the variable capacitor, a first protective insulation film provided on a first surface of the first electrode, the first surface facing the second electrode, and a second protective insulation film provided on a second surface of the second electrode, the second surface facing the first electrode. | 2015-03-19 |
20150076627 | MEMS-MICROPHONE WITH REDUCED PARASITIC CAPACITANCE - A MEMS microphone with reduced parasitic capacitance is provided. A microphone includes a protection film covering a rim-sided area of the backplate. | 2015-03-19 |
20150076628 | MULTI-PORT DEVICE PACKAGE - An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening. | 2015-03-19 |
20150076629 | MICROPHONE - There is provided a microphone including: a thin film member including leg members extended in a direction not in parallel with a vibration direction; first supports supporting first points of the leg members, respectively; and a piezoelectric member connected to second points of the leg members and converting vibrations of the thin film member into electrical signals. | 2015-03-19 |
20150076630 | SIDE VENTED PRESSURE SENSOR DEVICE - A semiconductor sensor device has a pressure sensing die and at least one other die mounted on a substrate, and electrical interconnections that interconnect the pressure sensing die and the at least one other die. An active region of the pressure sensing die is covered with a pressure sensitive gel material, and a cap having a cavity is mounted over the pressure sensing die such that the pressure sensing die is positioned within the cavity. The cap has a side vent hole that exposes the gel covered active region of the pressure sensing die to ambient atmospheric pressure outside the sensor device. Molding compound on an upper surface of the substrate encapsulates the at least one other die and at least a portion of the cap. | 2015-03-19 |
20150076631 | REDUCTION OF CHIPPING DAMAGE TO MEMS STRUCTURE - A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE. | 2015-03-19 |
20150076632 | METHOD AND APPARATUS FOR RELEASE-ASSISTED MICROCONTACT PRINTING OF MEMS - The disclosure provides methods and apparatus for release-assisted microcontact printing of MEMS. Specifically, the principles disclosed herein enable patterning diaphragms and conductive membranes on a substrate having articulations of desired shapes and sizes. Such diaphragms deflect under applied pressure or force (e.g., electrostatic, electromagnetic, acoustic, pneumatic, mechanical, etc.) generating a responsive signal. Alternatively, the diaphragm can be made to deflect in response to an external bias to measure the external bias/phenomenon. The disclosed principles enable transferring diaphragms and/or thin membranes without rupturing. | 2015-03-19 |
20150076633 | MEMORY CELLS, METHODS OF FABRICATION, AND SEMICONDUCTOR DEVICES - A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. Thus, the diffusible species is removed from the magnetic material to the attracter material. The removal accommodates crystallization of the depleted magnetic material. The crystallized, depleted magnetic material enables a high tunnel magneto resistance, high energy barrier, and high energy barrier ratio. The magnetic region may be formed as a continuous magnetic material, thus enabling a high exchange stiffness, and positioning the magnetic region between two magnetic anisotropy-inducing oxide regions enables a high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed. | 2015-03-19 |
20150076634 | MAGNETIC DEVICE WITH A SUBSTRATE, A SENSING BLOCK AND A REPAIR LAYER - A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a bottom electrode, a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer. | 2015-03-19 |
20150076635 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a base layer; a first magnetic layer formed on the base layer, and including a first magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the first magnetic film including Mn | 2015-03-19 |
20150076636 | Current Sensor Device - A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor. | 2015-03-19 |
20150076637 | PHOTO DIODE AND METHOD OF FORMING THE SAME - A method for forming a photo diode is provided. The method includes: forming a first bottom electrode corresponding to a first pixel and a second bottom electrode corresponding to a second pixel over a substrate; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a top electrode over the photo conversion layer; forming a color filter layer over the top electrode, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filer layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer. | 2015-03-19 |
20150076638 | MECHANISMS FOR FORMING BACKSIDE ILLUMINATED IMAGE SENSOR DEVICE STRUCTURE - Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The backside illuminated image sensor device structure includes a substrate having a frontside and a backside and a pixel array formed in the frontside of the substrate. The backside illuminated image sensor device structure further includes an antireflective layer formed over the backside of the substrate, and the antireflective layer is made of silicon carbide nitride. | 2015-03-19 |
20150076639 | OPTICAL SHIELD IN A PIXEL CELL PLANARIZATION LAYER FOR BLACK LEVEL CORRECTION - A pixel array includes a plurality of photodiodes disposed in a semiconductor layer and arranged in the pixel array. A color filter layer is disposed proximate to the semiconductor layer. Light is to be directed to at least a first one of the plurality of photodiodes through the color filter layer. An optical shield layer is disposed proximate to the color filter layer. The color filter layer is disposed between the optical shield layer and the semiconductor layer. The optical shield layer shields at least a second one of the plurality of photodiodes from the light. | 2015-03-19 |
20150076640 | OPTICAL MODULE - To suppress appearance of a ghost. | 2015-03-19 |
20150076641 | Avalanche Photodiodes with Defect-assisted Silicon Absorption Regions - An avalanche photodiode with a defect-assisted silicon absorption region. An example includes a substrate; a layer of silicon on the substrate, the layer of silicon including a positively-doped region, a negatively-doped region, and an absorption region between the positively-doped and negatively-doped regions, the absorption region including defects in its crystal structure; and contacts in electrical communication with the positively-doped and negatively-doped regions to receive a bias potential. | 2015-03-19 |
20150076642 | PHOTODETECTION DEVICE AND SENSOR PACKAGE - A photodetection device of the present invention includes a semiconductor substrate which is defined such that a first light-receiving portion and a second light-receiving portion are spaced from one another, and an optical filter which is formed on the semiconductor substrate, and includes a first filter which is disposed so as to cover the first light-receiving portion, to selectively allow an optic element in a first wavelength band to transmit through, and a second filter which is disposed so as to cover the second light-receiving portion, to selectively allow an optic element in a second wavelength band different from the first wavelength band, to transmit through, and the optical filter has a filter laminated structure which is defined such that edge portions of the first filter and the second filter overlap one another on a boundary region between the first light-receiving portion and the second light-receiving portion. | 2015-03-19 |
20150076643 | SOLID-STATE IMAGING APPARATUS, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging apparatus includes a plurality of phase difference detection pixels configured adjacent to one another; and an isolation structure arranged so as to isolate light entering each of light-receiving units of the plurality of phase difference detection pixels, in which the isolation structure is formed so as to have a inclined side wall surface whose cross section is tapered. | 2015-03-19 |
20150076644 | METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSOR - A method for manufacturing a solid-state image sensor, comprising preparing a substrate including a pixel region where a plurality of pixels are provided and a peripheral region, forming a structure including a wiring layer and an interlayer insulation film on the pixel region and the peripheral region, forming a first wiring pattern only on the structure located in the peripheral region, forming a protective film covering the first wiring pattern and the structure, forming a second wiring pattern on a convex portion of the protective film formed by steps between an upper surface of the first wiring pattern and the structure so that an end of the second wiring pattern is located away from the pixel region than an end of the first wiring pattern in a state that the protective film covers the first wiring pattern, and forming an optical system. | 2015-03-19 |
20150076645 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Phosphate-based glass doped with copper ions having infrared blocking filter characteristics is formed into particles and is mixed with a transparent encapsulating resin to encapsulate a semiconductor element. The glass particles have a particle diameter four times or more as large as a wavelength of infrared radiation to be blocked. An optical semiconductor device can be obtained having a stable filter characteristics thereof even if an incident light angle changes and is resistant to moisture. | 2015-03-19 |
20150076646 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A backside illumination semiconductor image sensing device includes a semiconductor substrate. The semiconductor substrate includes a radiation sensitive diode and a peripheral region. The peripheral region is proximal to a sidewall of the backside illumination semiconductor image sensing device. The backside illumination semiconductor image sensing device further includes a first anti reflective coating (ARC) on a backside of the semiconductor substrate and a dielectric layer on the first anti reflective coating. Additionally, a radiation shielding layer is disposed on the dielectric layer. Moreover, the backside illumination semiconductor image sensing device has a photon blocking layer on the sidewall of the of the backside illumination semiconductor image sensing device. The at least a portion of a sidewall of the radiation shielding layer is not covered by the photon blocking layer and the photon blocking layer is configured to block photons penetrating into the semiconductor substrate. | 2015-03-19 |
20150076647 | GALLIUM ARSENIDE AVALANCHE PHOTODIODE - An avalanche photodiode can include: an avalanche region having one or more layers prepared from GaAs; an N | 2015-03-19 |
20150076648 | PIXEL ISOLATION STRUCTURES IN BACKSIDE ILLUMINATED IMAGE SENSORS - Systems and methods are provided for fabricating a backside illuminated image sensor including an array of pixels. An example image sensor includes a first pixel, a second pixel, and an isolation structure. The first pixel is disposed in a front side of a substrate and is configured to generate charged carriers in response to light incident upon a backside of the substrate. The second pixel is disposed in the front side of the substrate and is configured to generate charged carriers in response to light incident upon the backside of the substrate. The isolation structure is disposed to separate the second pixel from the first pixel, and extends from the backside of the substrate toward the front side of the substrate. The isolation structure includes a sidewall substantially vertically to the front side of the substrate. | 2015-03-19 |
20150076649 | STACK TYPE IMAGE SENSORS AND METHODS OF MANUFACTURING THE SAME - An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer. | 2015-03-19 |
20150076650 | Semiconductor Device and a Method for Forming a Semiconductor Device - A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first doping region arranged at a main surface of the semiconductor substrate, an emitter layer arranged at a back side surface of the semiconductor substrate, at least one first conductivity type area separated from the first doping region by a second doping region of the semiconductor substrate and at least one temperature-stabilizing resistance area. The first doping region has a first conductivity type and the emitter layer has at least mainly a second conductivity type. The second doping region has the second conductivity type and the at least one first conductivity type area has the first conductivity type. The at least one temperature-stabilizing resistance area is located within the second doping region and adjacent to the at least one first conductivity type area. Further, the at least one temperature-stabilizing resistance area has a lower variation of a resistance over a range of an operating temperature of the semiconductor device than at least a part of the second doping region located adjacent to the at least one temperature-stabilizing resistance area. | 2015-03-19 |
20150076651 | THERMOCOUPLE, THERMOPILE, INFRARED RAY SENSOR AND METHOD OF MANUFACTURING INFRARED RAY SENSOR - An infrared ray sensor includes a thermopile. The thermopile includes a first semiconductor material part and a second semiconductor material part, the first semiconductor material part and the second semiconductor material part are laminated, and a dielectric film is provided between the first semiconductor material part and the second semiconductor material part. | 2015-03-19 |
20150076652 | POWER SEMICONDUCTOR DEVICE - There is provided a power semiconductor device, including: a first semiconductor layer of a first conductive type having a thickness of t1 so as to withstand a reverse voltage of 600V; and a second semiconductor layer of a second conductive type formed inside an upper portion of the first semiconductor layer and having a thickness of t2, wherein t1/t2 is 15 to 18. | 2015-03-19 |
20150076653 | OVERLAY PERFORMANCE FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification. | 2015-03-19 |
20150076654 | ENLARGED FIN TIP PROFILE FOR FINS OF A FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Approaches for providing enlarged fin tips for a set of fins of a fin field effect transistor device (FinFET) are disclosed. Specifically, approaches are provided for patterning a hardmask formed over a substrate; forming a set of fin tips from the substrate using a first etch; and forming a set of fins from the substrate using a second etch, wherein each of the set of fin tips has a width greater than a most narrow section of each of the set of fins. Each of the fin tips has a tapered profile that enlarges towards a top end thereof to compensate for erosion losses during processing. | 2015-03-19 |
20150076655 | Fuse Structure and Method of Blowing the Same - A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line. | 2015-03-19 |
20150076656 | ELECTRONIC FUSE HAVING A SUBSTANTIALLY UNIFORM THERMAL PROFILE - An electronic fuse includes a body, an anode coupled to the body, and a cathode coupled to the body. Each of the anode and the cathode includes a first line contacting the body. The first line is discontinuous along its length and includes a first portion and a second portion with a space therebetween. A second line is disposed above the first line and a plurality of vias couple the first and second lines. The first portion of the first line is coupled to a first subset of the plurality of vias and the second portion of the first line is coupled to a second subset of the vias. | 2015-03-19 |
20150076657 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer. | 2015-03-19 |
20150076658 | Semiconductor Device Including Capacitor and Method of Manufacturing the Same - A semiconductor device includes a lower electrode including at least one of a noble metal and a conductive noble metal oxide, a dielectric layer disposed on the lower electrode and including titanium oxide, a protection insulating layer disposed on the dielectric layer and including tantalum oxide and a barrier oxide, and an upper electrode disposed on the protection insulating layer. | 2015-03-19 |
20150076659 | CAPACITOR - A capacitor having a configuration in which capacitors are coupled in series to each other is described. The capacitor formed on a substrate according to an exemplary embodiment of the present invention includes: a polysilicon layer doped with an impurity; a first insulation layer formed on the polysilicon layer; a first metal layer formed on the first insulation layer and including first and second areas; a second insulation layer formed on the first metal layer; and a second metal layer formed on the second insulation layer and coupled to the second area of the first metal layer. The second metal layer is overlapped with at least a part of the first area of the first metal layer. | 2015-03-19 |
20150076660 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10. | 2015-03-19 |
20150076661 | ASSEMBLY AND A CHIP PACKAGE - An assembly ( | 2015-03-19 |
20150076662 | COMPOSITE SUBSTRATE MANUFACTURING METHOD, SEMICONDUCTOR ELEMENT MANUFACTURING METHOD, COMPOSITE SUBSTRATE, AND SEMICONDUCTOR ELEMENT - Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first raw board having at least one surface as a minor surface into a state in which the minor surface warps outward; and a joining step of joining, after the first raw board deforming step, a protruding surface of the first substrate and one surface of a second substrate to each other, thereby manufacturing a composite substrate including the first substrate and the second substrate, in which the second substrate is any one substrate selected from a substrate having both surfaces as substantially flat surfaces and a substrate that warps so that a surface thereof to be joined to the first substrate warps outward. Also provided are a semiconductor element manufacturing method, a composite substrate and a semiconductor element manufactured. | 2015-03-19 |
20150076663 | Patterned Bases, and Patterning Methods - Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases. | 2015-03-19 |
20150076664 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities. | 2015-03-19 |
20150076665 | ALIGNMENT MARK STRUCTURE - A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and under the wiring layer. The first wiring layer includes a main pattern and the via layer includes a closed frame pattern corresponding to the main pattern of the first wiring layer. | 2015-03-19 |
20150076666 | SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA - A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface. | 2015-03-19 |
20150076667 | SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING CHANNEL AND METHOD OF FORMING A SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING CHANNEL - A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall. | 2015-03-19 |