12th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150076468 | LIGHT EXTRACTION PRODUCT FOR SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE - A light extraction product ( | 2015-03-19 |
20150076469 | ORGANIC ELECTROLUMINESCENT ELEMENT - The organic electroluminescent element has a pair of electrodes and at least two organic functional layers including a light-emitting layer on a substrate. The light-emitting layer contains a host compound and a phosphorescent dopant. The light-emitting layer or the layer adjacent to the light-emitting layer contains quantum dots. | 2015-03-19 |
20150076470 | Luminescent Cyclometallated Iridium (III) Complexes Having Acetylide Ligands - The present invention relates to phosphorescent (triplet-emitting) organometallic materials. The phosphorescent materials of the present invention comprise Ir(III)cyclometallated alkynyl complexes for use as triplet light-emitting materials. The Ir(III)cyclometallated alkynyl complexes comprise at least one cyclometallating ligand and at least one alkynyl ligand bonded to the iridium. Also provided is an organic light emitting device comprising an anode, a cathode and an emissive layer between the anode and the cathode, wherein the emissive layer comprises a Ir(III)cyclometallated alkynyl complex as a triplet emitting material. | 2015-03-19 |
20150076471 | DISPLAY DEVICE AND SEMICONDUCTOR DEVICE - A display device includes a first electrode, a second electrode, an organic light emitting layer, a first transistor, and a second transistor. The first transistor includes a first semiconductor layer, a first conductive unit, a second conductive unit, a first gate electrode, and a first gate insulating film. The second transistor includes a second semiconductor layer, a third conductive unit, a fourth conductive unit, a second gate electrode, and a second gate insulating film. An amount of hydrogen included in the first gate insulating film is larger than an amount of hydrogen included in the second gate insulating film. | 2015-03-19 |
20150076472 | LIGHT-EMITTING DEVICE, LIGHTING DEVICE, AND DISPLAY DEVICE - A light-emitting device, a lighting device, a display device, or the like in which the state of a back surface side can be observed when light is not emitted is provided. The light-emitting device includes a plurality of light-emitting portions and a region transmitting visible light in a region other than the light-emitting portions. Alternatively, the light-emitting device includes a plurality of light-transmitting portions transmitting visible light and a light-emitting portion that can emit light in a region other than the light-transmitting portions. When light is not emitted, the state of a back surface side of the light-emitting device is visible through the region transmitting visible light. When light is emitted, the state of the back surface side of the light-emitting device can be made less visible by diffusion of light emitted from the light-emitting portion. | 2015-03-19 |
20150076473 | DISPLAY DEVICE - A display device having high display quality is provided. In the display device that includes a plurality of display regions having different normal directions, the arrangement directions of a plurality of subpixels included in pixels vary between the display regions. | 2015-03-19 |
20150076474 | METHOD FOR PACKAGING DISPLAY PANEL AND PACKAGING STRUCTURE OF DISPLAY PANEL - A method for packaging display panel is provided. The method comprises following steps: providing a first substrate; pasting a frit on the first substrate; pre-sintering the frit in a specific temperature; forming a color filter unit on the first substrate; providing a second substrate oppositely disposed on the first substrate; and assembling the first substrate and the second substrate with the frit by way of laser sealing. | 2015-03-19 |
20150076475 | Light-Emitting Device, Information Processing Device, and Imaging Device - Provided is a light-emitting device and an information processing device which include a light-emitting element mounted on a housing and an optical component detachable from the housing. The optical component is capable of condensing light emitted from the light-emitting element. This structure allows a user to select the emission of diffused light and condensed light by attaching or detaching the optical component. | 2015-03-19 |
20150076476 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE AND METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - A method of manufacturing an organic electroluminescent display device includes the steps of: forming a first insulating layer on a substrate; forming a first patterning layer; forming a second patterning layer; forming a trench portion; and forming an electrode layer on the second patterning layer and in the trench portion, wherein in the step of forming the trench portion, an end of the first patterning layer exposed within the trench portion is etched to an outside more than an end of the second patterning layer exposed within the trench portion in a plan view, and in the step of forming the electrode layer, the electrode layer formed within the trench portion is isolated from the electrode layer formed outside of the trench portion. | 2015-03-19 |
20150076477 | ORGANIC EL DISPLAY PROVIDED WITH GEL-STATE ENCAPSULANT INCORPORATING A DESICCANT AND A HIGH MOLECULAR-WEIGHT MEDIUM - A sealing substrate is arranged to oppositely face an element substrate on which organic EL layers are formed in a matrix array with a sealing material sandwiched therebetween. A gel-state desiccant is filled in an inner space surrounded by the element substrate, the sealing substrate and the sealing material. Since the gel-state desiccant is in a gel state, the gel-state desiccant is flexibly filled in the inner space of the organic EL display device thus completely eliminating a gap. Since the inner space is filled with the gel-state desiccant, moisture hardly intrudes into the inner-space from the outside and, at the same time, a mechanical strength of the organic EL display device is also enhanced. | 2015-03-19 |
20150076478 | LUMINESCENCE DEVICE AND DISPLAY APPARATUS - A metal coordination compound represented by any one of formulas (1)-(5). An organic luminescence device including an anode, a cathode, and an organic layer, which contains the metal coordination compound, disposed between the anode and the cathode. | 2015-03-19 |
20150076479 | ORGANIC COMPOUND, CHARGE-TRANSPORTING MATERIAL, COMPOSITION CONTAINING THE COMPOUND, ORGANIC ELECTROLUMINESCENT ELEMENT, DISPLAY DEVICE, AND LIGHTING DEVICE - The invention provides an organic compound incorporating a specific structure into a pyridine skeleton or a 1,3,5-triazine skeleton and adapting the molecular weight to a specific range, a composition comprising the organic compound and a solvent, organic electroluminescent element comprising a layer that is formed by using the composition, and the uses thereof. | 2015-03-19 |
20150076480 | ORGANIC LIGHT EMITTING DEVICE COMPRISING 9,10-DIHYDROACRIDINE DERIVATIVE - Provided is an organic light emitting device (OLED) comprising 9,10-dihydroacridine derivative represented by the following Formula (I): | 2015-03-19 |
20150076481 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A display device and method for manufacturing same are provided. The display device including a plurality of unit pixels disposed in the matrix on a substrate, each of the unit pixels has a thin film transistor at a place other than the center of the pixel, and unit pixels in a first row and unit pixels in a second row adjacent to the first row are arranged so that they are symmetric with respect to a first virtual plane orthogonal to a main surface of the substrate. | 2015-03-19 |
20150076482 | ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURING METHOD - An electronic device including: a substrate; a bank formed on an upper surface of the substrate, surrounding an area of the upper surface of the substrate, and defining an aperture from which the area is exposed; a liquid-philic layer formed on a peripheral portion of the area, and not overlapping a central portion of the area; a semiconductor layer formed within the aperture, and attaching to at least a portion of the central portion and to an upper surface of the liquid-philic layer; and a pair of electrodes that are in contact with an area of the semiconductor layer, the area of the semiconductor layer not overlapping the liquid-philic layer in plan view. The bank has a liquid-phobic lateral surface surrounding the aperture, and the upper surface of the liquid-philic layer has a higher degree of liquid-philicity than the upper surface of the substrate. | 2015-03-19 |
20150076483 | ORGANIC ELECTROLUMINESCENT ELEMENT, ORGANIC ELECTROLUMINESCENT LIGHTING DEVICE AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - An organic electroluminescent element comprising: an anode; a cathode; a luminescent layer provided between the anode and the cathode; and a hole injecting and transporting layer provided between the anode and the cathode and adjacent to the luminescent layer, wherein at least the luminescent layer is formed by a wet film forming method, and contains a charge transporting material and a luminescent material, in which the charge transporting material contains a hole transporting material and an electron transporting material each having a specific partial structure, and the luminescent material contains at least three kinds of materials and has an emission spectrum having at least two kinds of emission maximums. | 2015-03-19 |
20150076484 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion. | 2015-03-19 |
20150076485 | MEMORY CELLS, METHODS OF FABRICATION, SEMICONDUCTOR DEVICES, MEMORY SYSTEMS, AND ELECTRONIC SYSTEMS - A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“MA”) with the free region, enhancing the MA strength of the free region. A getter material proximate to the secondary oxide region is formulated and configured to remove oxygen from the secondary oxide region to reduce an oxygen concentration and, thus, an electrical resistance of the secondary oxide region. Thus, the secondary oxide region contributes only minimally to the electrical resistance of the cell core. Embodiments of the present disclosure therefore enable a high effective magnetoresistance, low resistance area product, and low programming voltage along with the enhanced MA strength. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed. | 2015-03-19 |
20150076486 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - The pixel structure includes a scan line, a data line, a thin-film transistor, a first electrode layer, a protective layer and a second electrode layer. The thin-film transistor is electrically connected to the scan line and the data line, and includes a gate, an oxide semiconductor layer, an insulating layer, a source and a drain. The first electrode layer is in the same layer as the oxide semiconductor layer, and is surrounded by the scan line and the data line. The second electrode layer is located on the first electrode layer, and the protective layer is located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage. The second electrode layer includes a plurality of slits exposing an area of the first electrode layer. | 2015-03-19 |
20150076487 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A thin film transistor | 2015-03-19 |
20150076488 | THIN FILM TRANSISTOR - Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IGZO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; In: 25% or less (excluding 0%); Ga: 5% or more; Zn: 30.0 to 60.0%; and Sn: 8 to 30%. | 2015-03-19 |
20150076489 | OXIDE FOR SEMICONDUCTOR LAYER IN THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, DISPLAY DEVICE, AND SPUTTERING TARGET - Provided is an oxide semiconductor configured to be used in a thin film transistor having high field-effect mobility; a small shift in threshold voltages against light and bias stress; excellent stress resistance. The oxide semiconductor has also excellent resistance to a wet-etchant for patterning of a source-drain electrode. The oxide semiconductor comprises In, Zn, Ga, Sn and O, and satisfies the requirements represented by expressions (1) to (4) shown below, wherein [In], [Zn], [Ga], and [Sn] represent content (in atomic %) of each of the elements relative to the total content of all the metal elements other than oxygen in the oxide. | 2015-03-19 |
20150076490 | VOLTAGE NONLINEAR RESISTOR AND MULTILAYER VARISTOR USING SAME - A voltage nonlinear resistor includes a plurality of N-type ZnO crystal grains, a grain boundary layer, and an oxide grain as a P-type semiconductor. The grain boundary layer is formed between the ZnO crystal grains, and contains at least one kind of oxide of alkaline-earth metal. The oxide grain is disposed between the ZnO crystal grains via the grain boundary layer. | 2015-03-19 |
20150076491 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having low off-state current (current in an off state) is provided. Alternatively, a semiconductor device including the transistor is provided. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a conductive film overlapping with the oxide semiconductor film with the first insulating film or the second insulating film provided between the oxide semiconductor film and the conductive film. The composition of the oxide semiconductor film changes continuously between the first insulating film and the second insulating film. | 2015-03-19 |
20150076492 | DISPLAY DEVICE - To provide a display device with excellent display quality, in a display device including a signal line, a scan line, a transistor, a pixel electrode, and a common electrode in a pixel, the common electrode is included in which an extending direction of a region overlapping with the signal line differs from an extending direction of a region overlapping with the pixel electrode in a planar shape and the extending directions intersect with each other between the signal line and the pixel electrode. Thus, a change in transmittance of the pixel can be suppressed; accordingly, flickers can be reduced. | 2015-03-19 |
20150076493 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a transistor having high field effect mobility. To provide a transistor having stable electrical characteristics. To provide a transistor having low off-state current (current in an off state). To provide a semiconductor device including the transistor. The semiconductor device includes a semiconductor; a source electrode and a drain electrode including regions in contact with a top surface and side surfaces of the semiconductor; a gate insulating film including a region in contact with the semiconductor; and a gate electrode including a region facing the semiconductor with the gate insulating film provided therebetween. A length of a region of the semiconductor, which is not in contact with the source and drain electrodes, is shorter than a length of a region of the semiconductor, which is in contact with the source and drain electrodes, in a channel width direction. | 2015-03-19 |
20150076494 | Synthesis of Metal Oxide Semiconductor Nanoparticles from a Molecular Cluster Compound - A method of preparing metal oxide nanoparticles is described herein. The method involves reacting nanoparticle precursors in the presence of a population of molecular cluster compounds. The molecular cluster compound may or may not contain the same metal as will be present in the metal oxide nanoparticle. Likewise, the molecular cluster compound may or may not contain oxygen. The molecular cluster compounds acts a seeds or templates upon which nanoparticle growth is initiated. As the molecular cluster compounds are all identical, the identical nucleation sites result in highly monodisperse populations of metal oxide nanoparticles. | 2015-03-19 |
20150076495 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a transistor having highly stable electric characteristics and also a miniaturized structure. Further, also high performance and high reliability of a semiconductor device including the transistor can be achieved. The transistor is a vertical transistor in which a first electrode having an opening, an oxide semiconductor layer, and a second electrode are stacked in this order, a gate insulating layer is provided in contact with side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode, and a ring-shaped gate electrode facing the side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode with the gate insulating layer interposed therebetween is provided. In the opening in the first electrode, an insulating layer in contact with the oxide semiconductor layer is embedded. | 2015-03-19 |
20150076496 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a gate electrode having higher Gibbs free energy for oxidation than a gate insulating film. An oxide semiconductor layer having a fin shape is formed over an insulating surface, a gate insulating film is formed over the oxide semiconductor layer, a gate electrode including an oxide layer and facing top and side surfaces of the oxide semiconductor layer with the gate insulating film located therebetween is formed, and then by performing heat treatment, a gate electrode is reduced and oxygen is supplied to the oxide semiconductor layer through the gate insulating film. | 2015-03-19 |
20150076497 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an oxide semiconductor layer including a channel formation region which includes an oxide semiconductor having a wide band gap and a carrier concentration which is as low as possible, and a source electrode and a drain electrode which include an oxide conductor containing hydrogen and oxygen vacancy, and a barrier layer which prevents diffusion of hydrogen and oxygen between an oxide conductive layer and the oxide semiconductor layer. The oxide conductive layer and the oxide semiconductor layer are electrically connected to each other through the barrier layer. | 2015-03-19 |
20150076498 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 2015-03-19 |
20150076499 | System and Method for Test Key Characterizing Wafer Processing State - Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group. | 2015-03-19 |
20150076500 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film. | 2015-03-19 |
20150076501 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture. | 2015-03-19 |
20150076502 | METHOD OF PRODUCING DISPLAY DEVICE, DISPLAY DEVICE, METHOD OF PRODUCING THIN-FILM TRANSISTOR SUBSTRATE, AND THIN FILM TRANSISTOR SUBSTRATE - A method of producing a display device includes the steps of forming gate electrodes on a substrate so that an arrangement of a source and a drain, in a pixel row direction, of a thin-film transistor formed in each of pixels on the substrate is reversed every pixel row; forming a gate insulating film and an amorphous semiconductor thin film on the substrate in that order so as to cover the gate electrodes; crystallizing the semiconductor thin film by irradiating the semiconductor thin film with an energy beam so that a scanning direction of the energy beam is the same with respect to the arrangement of the source and the drain in the pixel row direction; and forming a light-emitting element connected to the thin-film transistor. | 2015-03-19 |
20150076503 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device of the invention includes a thin film transistor, an insulating layer covering the thin film transistor, an electrode which is electrically connected to the thin film transistor through a contact hole formed on the insulating layer, and a light emitting element formed by interposing a light emitting layer between a first electrode which is electrically connected to the electrode and a second electrode. The light emitting device further includes a layer formed of a different material from that of the insulating layer only between the electrode and the first electrode over the insulating layer and the insulating layer. | 2015-03-19 |
20150076504 | ADVANCED EXCIMER LASER ANNEALING FOR THIN FILMS - The present disclosure relates to a new generation of laser-crystallization approaches that can crystallize Si films for large displays at drastically increased effective crystallization rates. The particular scheme presented in this aspect of the disclosure is referred to as the advanced excimer-laser annealing (AELA) method, and it can be readily configured for manufacturing large OLED TVs using various available and proven technical components. As in ELA, it is mostly a partial-/near-complete-melting-regime-based crystallization approach that can, however, eventually achieve greater than one order of magnitude increase in the effective rate of crystallization than that of the conventional ELA technique utilizing the same laser source. | 2015-03-19 |
20150076505 | PATTERNED OPTO-ELECTRICAL SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a patterned opto-electrical substrate, comprising a substrate, the substrate has a first patterned structure, a spacer region and a second patterned structure, wherein the second patterned structure is formed on one or both of the first patterned structure and the spacer region, and the first patterned structure is a micron-scale protruding structure or a micron-scale recessing structure, while the second patterned structure is a submicron-scale recessing structure. The present invention also relates to a method for manufacturing the aforementioned patterned opto-electrical substrate and light emitting diodes having the aforementioned patterned opto-electrical substrate. | 2015-03-19 |
20150076506 | SEMICONDUCTOR DEVICE - This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer. | 2015-03-19 |
20150076507 | EPITAXY SUBSTRATE, METHOD FOR PRODUCING AN EPITAXY SUBSTRATE AND OPTOELECTRONIC SEMICONDUCTOR CHIP COMPRISING AN EPITAXY SUBSTRATE - An epitaxy substrate ( | 2015-03-19 |
20150076508 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a first semiconductor layer of a first GaN based semiconductor, a second semiconductor layer of a second GaN based semiconductor having a band gap narrower than the first GaN based semiconductor, a third semiconductor layer of a third GaN based semiconductor having a band gap wider than the second GaN based semiconductor, a fourth semiconductor layer of a fourth GaN based semiconductor having a band gap narrower than the third GaN based semiconductor, a fifth semiconductor layer of a fifth GaN based semiconductor having a band gap wider than the fourth GaN based semiconductor, a gate dielectric provided directly on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, a gate electrode provided on the gate dielectric, a source and drain electrodes provided above the fifth semiconductor layer. | 2015-03-19 |
20150076509 | SEMICONDUCTOR DEVICE WITH BUFFER LAYER MADE OF NITRIDE SEMICONDUCTOR - A semiconductor device includes a buffer layer made of nitride semiconductor on a substrate, a first semiconductor layer made of nitride semiconductor on the buffer layer, a second semiconductor layer made of nitride semiconductor on the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, wherein the buffer layer has elements doped therein that include both an element selected from a group consisting of C, Mg, Fe, and Co and an element selected from a group consisting of Si, Ge, Sn, and O. | 2015-03-19 |
20150076510 | Heterostructure Power Transistor with AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 2015-03-19 |
20150076511 | SEMICONDUCTOR DEVICE - A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In | 2015-03-19 |
20150076512 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING - A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate. | 2015-03-19 |
20150076513 | Field Effect Transistor with Conduction Band Electron Channel and Uni-Terminal Response - A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H | 2015-03-19 |
20150076514 | METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION - Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. | 2015-03-19 |
20150076515 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A Schottky barrier diode and a method of manufacturing the diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and a plurality of p+ regions disposed within the n− type epitaxial layer. An n+ type epitaxial layer is disposed on the n− type epitaxial layer, a Schottky electrode is disposed on the n+ type epitaxial layer, and an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. The n+ type epitaxial layer includes a plurality of pillar parts disposed on the n− type epitaxial layer and a plurality of openings disposed between the pillar parts and that expose the p+ regions. Each of the pillar parts includes substantially straight parts that contact the n− type epitaxial layer and substantially curved parts that extend from the substantially straight parts. | 2015-03-19 |
20150076516 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor device includes a semiconductor element and a metal film. The semiconductor element has a first surface and a second surface opposite to the first surface. The metal film is provided above the second surface of the semiconductor element. The metal film includes Cr. | 2015-03-19 |
20150076517 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal. | 2015-03-19 |
20150076518 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention aims at providing a semiconductor device having a conductive film formed on a semiconducting substrate so that heating of the substrate and contamination by impurities can be suppressed and Schottky resistance can be reduced, and at providing a method of manufacturing the same. The metal film formation method used in manufacturing the semiconductor device according to an embodiment of the present invention includes the steps of: irradiating one surface of the substrate with a femtosecond laser having energy in the vicinity of the processing threshold value to form a nano-periodic structure in the form of minute irregularities; and forming a metal film on the nano-periodic structure of the substrate. It is thereby possible to reduce the Schottky resistance at the interface between the substrate and the metal film and obtain an ohmic contact while suppressing heating of the substrate and contamination by impurities. | 2015-03-19 |
20150076519 | VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD OF VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS - A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer. | 2015-03-19 |
20150076520 | SILICON CARBIDE SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF - In a fabrication method of a silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, dicing is added to form at least one dicing line in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate. Thus, a silicon carbide semiconductor element and fabrication method thereof is provided such that even if the semiconductor substrate is made thinner to reduce the on-resistance, the strength of the substrate can be maintained and cracking of the wafer during wafer processing can be reduced. | 2015-03-19 |
20150076521 | VERTICAL HIGH-VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a high voltage is applied, and a fabrication method thereof, a vertical mosfet has a semiconductor layer and a base layer joined instead of a well region | 2015-03-19 |
20150076522 | SEMICONDUCTOR DEVICES WITH HETEROJUNCTION BARRIER REGIONS AND METHODS OF FABRICATING SAME - An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed. | 2015-03-19 |
20150076523 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region. | 2015-03-19 |
20150076524 | SEALING RESIN, SEMICONDUCTOR DEVICE, AND PHOTOCOUPLER - A semiconductor device includes: a sealing resin and a semiconductor element. The sealing resin includes a base resin and a curing agent. The base resin includes isocyanuric acid having an epoxy group. The curing agent includes an acid anhydride having an acid anhydride group. A mole ratio of the acid anhydride group to the epoxy group is not less than 0.67 and not more than 0.8. A semiconductor element is covered with the sealing resin. | 2015-03-19 |
20150076525 | LIGHT RECEIVING ELEMENT AND OPTICALLY COUPLED INSULATING DEVICE - A light receiving element includes: a semiconductor layer; a first layer; and a second layer. The semiconductor layer has a first impurity concentration. The first layer of a first conductivity type is provided inward from an upper surface of the semiconductor layer. The first layer has a second impurity concentration higher than the first impurity concentration. The first layer has a surface region on an upper surface of the semiconductor layer side and an inner region being narrower than the first region. The second layer of a second conductivity type is provided inward from the upper surface of the first semiconductor layer. The second layer has a third impurity concentration higher than the first impurity concentration. | 2015-03-19 |
20150076526 | LIGHT RECEIVING ELEMENT AND OPTICALLY COUPLED INSULATING DEVICE - A light receiving element includes: a semiconductor layer; an insulating layer; an interconnect layer; and a film. The semiconductor layer includes a light receiving unit configured to convert a signal light incident on the light receiving unit into an electrical signal. The insulating layer is provided on the semiconductor layer. The interconnect layer is provided on the insulating layer. The film is provided on the insulating layer to cover the light receiving unit and be connected to the interconnect layer, the film being made of a metal or a metal nitride. | 2015-03-19 |
20150076527 | IMAGING DEVICE - Objects are to provide a small imaging device that can take an image of a thick book without distortion of an image of a gutter and to improve the portability of an imaging device by downsizing the imaging device. The imaging device has imaging planes on both surfaces. All elements included in the imaging device are preferably provided over one substrate. In other words, the imaging device has a first imaging plane and a second imaging plane facing opposite to the first imaging plane. | 2015-03-19 |
20150076528 | ADHESIVE WAFER BONDING WITH SACRIFICIAL SPACERS FOR CONTROLLED THICKNESS VARIATION - A method and structure for forming an array of micro devices is disclosed. An array of micro devices is formed over an array of stabilization posts included in a stabilization layer. Patterned sacrificial spacers are formed between the stabilization posts and between the micro devices. The patterned sacrificial spacers are disposed upon the patterned sacrificial spacers. | 2015-03-19 |
20150076529 | LIGHT-EMITTING DEVICE - A light-emitting device includes a resin layer and a plurality of luminous bodies disposed on the resin layer and spaced from each other. Each luminous body has a first side contacting the resin layer and a second side opposite the first side. A wiring element connects the luminous bodies to each other with the wiring element contacting the luminous bodies on the first side. At least some portion of the wiring element is in the resin layer. Separate phosphor layers are disposed on the second side of each luminous body such that each phosphor layer is spaced from each other phosphor layer. | 2015-03-19 |
20150076530 | LIGHT-EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device package is disclosed. The light-emitting device package includes a metal substrate. An insulating layer is on the metal substrate, wherein the insulating layer has at least one opening to expose the metal substrate. At least one light-emitting device is disposed in the at least one opening of the insulating layer. A sidewall of the at least one opening of the insulating layer is covered by an optical spacer. The disclosure also provides a method for manufacturing the light-emitting device package. | 2015-03-19 |
20150076531 | CHIP-ON-FILM (COF) PACKAGE, COF PACKAGE ARRAY INCLUDING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - A chip-on-film (COF) package includes a base film, an integrated circuit chip, and a plurality of signal interconnections. The base film includes a bonding region and a non-bonding region. The integrated circuit chip is at the non-bonding region. Each of the plurality of signal interconnections is coupled to the integrated circuit chip and extend to the bonding region along a first direction. The plurality of signal interconnections are spaced from each other along a second direction substantially crossing the first direction. The plurality of signal interconnections alternate on a first surface and a second surface opposite to the first surface of the base film along the second direction. | 2015-03-19 |
20150076532 | LIGHT EMITTING DIODE - AC LED according to the present invention comprises a substrate, and at least one serial array having a plurality of light emitting cells connected in series on the substrate. Each of the light emitting cells comprises a lower semiconductor layer consisting of a first conductive compound semiconductor layer formed on top of the substrate, an upper semiconductor layer consisting of a second conductive compound semiconductor layer formed on top of the lower semiconductor layer, an active layer interposed between the lower and upper semiconductor layers, a lower electrode formed on the lower semiconductor layer exposed at a first corner of the substrate, an upper electrode layer formed on the upper semiconductor layer, and an upper electrode pad formed on the upper electrode layer exposed at a second corner of the substrate. The upper electrode pad and the lower electrode are respectively disposed at the corners diagonally opposite to each other, and the respective light emitting cells are arranged so that the upper electrode pad and the lower electrode of one of the light emitting cells are symmetric with is respect to those of adjacent another of the light emitting cells. | 2015-03-19 |
20150076533 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 2015-03-19 |
20150076534 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a first light-emitting element disposed on a substrate, a convex-shaped first sealing resin that includes an annular portion formed in a closed annular shape in a top view and seals the first light-emitting element, a second light-emitting element disposed on the substrate in a region surrounded by the annular portion of the first sealing resin, and a second sealing resin filled in the region surrounded by the annular portion so as to seal the second light-emitting element. One of the first and second sealing resin includes a phosphor particle or the first and second sealing resins include a phosphor particle to emit a different fluorescent color from each other. | 2015-03-19 |
20150076535 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes a substrate; a plurality of conductive dielectric nano rods spaced apart from each other on the substrate; light emitting structures on the conductive dielectric nano rods, respectively; and a carbon nano electrode layer on the light emitting structures. | 2015-03-19 |
20150076536 | LIGHT-EMITTING ELEMENT HAVING A PLURALITY OF LIGHT-EMITTING STRUCTURES - A light-emitting element comprises a first semiconductor layer, a first light-emitting structure and a second light-emitting structure on the first semiconductor layer, a first electrode on the first semiconductor layer, a second electrode on the first light-emitting structure, and a first trench between the first light-emitting structure and the second light-emitting structure, exposing the first semiconductor layer, wherein the first trench is devoid of the first electrode and the second electrode formed therein. | 2015-03-19 |
20150076537 | LIGHT-EMITTING DIODE - The present disclosure provides a light-emitting diode, including: a silicon substrate having a first surface and a second surface opposite to the first surface; a buffer layer disposed over the first surface of the substrate, wherein the buffer layer includes alternating SiC and In | 2015-03-19 |
20150076538 | SEALED SEMICONDUCTOR LIGHT EMITTING DEVICE - A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates. | 2015-03-19 |
20150076539 | SINGLE-PHASE AND FULL-COLOR PHOSPHOR - A composition of matter including a phosphor having an emission peak in each of a blue, green, and red color region of the Electromagnetic spectrum, wherein the phosphor is excitable by light having a wavelength between 350 nanometers (nm) and 420 nm. | 2015-03-19 |
20150076540 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light emitting device includes a laminate body, a first electrode, a second electrode, and a phosphor layer having a light emitting surface. The laminate body includes a first layer of a first-conductivity-type, a first part of a second layer of a second-conductivity-type, and a light emitting layer containing a nitride semiconductor between the first layer and the second layer. The first electrode is formed on a surface of the first layer. The second electrode is formed on a surface of a second part of the second layer that is formed between the laminate body and the phosphor layer. At least one of the laminate body, the second part of the second layer, and the phosphor layer has a lateral width that increase toward the light emitting surface. | 2015-03-19 |
20150076541 | LIGHT-EMITTING DEVICE - A light-emitting device includes a first and second lead frame spaced from each other. A light-emitting element is mounted on the first lead frame and electrically connected to the first and second lead frames. A first frame body is disposed on the first lead frame and the second lead frame and surrounds the light-emitting element. A resin including a phosphor is disposed on the light-emitting element and fills a frame formed by the first frame body. A second frame body surrounds the first frame body. The second frame body has an upper surface that higher than an upper surface of the first frame body. | 2015-03-19 |
20150076542 | LIGHT EMITTING MODULE - The present disclosure provides a light emitting module, which includes a base board, a light emitting diode chip, a transparent thermoplastic layer, and fluorescent glue. The base board includes a die-bonding zone. The light emitting diode chip is bonded on the die-bonding zone. The light emitting diode chip includes an upper surface, a lower surface opposite to the upper surface, and a plurality of side surfaces adjoined between the upper surface and lower surfaces. A transparent thermoplastic layer encloses at least one portion of the light emitting diode chip. The fluorescent glue disposed over to cover the base board, the light emitting diode chip, and the transparent thermoplastic layer. | 2015-03-19 |
20150076543 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a base, a light emitting element, and a fluorescent body-containing layer. The light emitting element is installed on the base, has an upper surface and a lower surface, and includes a light emitting unit on the upper surface. The fluorescent body-containing layer is provided on the light emitting element and has a lower surface having an area smaller than an area of the light emitting unit and an upper surface having an area larger than an area of the light emitting unit. | 2015-03-19 |
20150076544 | RADIATION-EMITTING COMPONENT, TRANSPARENT MATERIAL AND FILLER PARTICLES, AND METHOD OF PRODUCING SAME - A radiation-emitting component includes a radiation source; a transparent material disposed in the beam path of the component and including a polymer material and filler particles, wherein the filler particles include an inorganic filler material and a phosphonic acid derivative or phosphoric acid derivative attached to a surface thereof and through which the filler particles are crosslinked with the polymer material. | 2015-03-19 |
20150076545 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING SAME - There is provided a method for manufacturing an electronic component package. The method includes the steps: (i) disposing a metal pattern layer on an adhesive carrier; (ii) placing at least one kind of electronic component on the adhesive carrier, the placed electronic component being not overlapped with respect to the metal pattern layer; (iii) forming a sealing resin layer on the adhesive carrier, and thereby producing a precursor of the electronic component package; (iv) peeling off the adhesive carrier of the precursor, whereby the metal pattern layer and an electrode of the electronic component are exposed at the surface of the sealing resin layer; and (v) forming a metal plating layer such that the metal plating layer is in contact with the exposed surface of the metal pattern layer and the exposed surface of the electrode of the electronic component. | 2015-03-19 |
20150076546 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked body, first and second electrodes. The stacked body includes a light emitting layer. The first and second electrodes are provided on the stacked body. The device further includes an insulating layer covering the stacked body, a first conversion electrode electrically connected to the first electrode, a second conversion electrode electrically connected to the second electrode ( | 2015-03-19 |
20150076547 | Group III Nitride Semiconductor Light-Emitting Device - The present invention provides a Group III nitride semiconductor light-emitting device exhibiting improved emission performance. A p-electrode comprises a wire bonding portion being connected to a wire, a wiring portion extending in a wiring pattern from the wire bonding portion, and a contact portion being connected to the wiring portion and being in contact with a transparent electrode via holes. A current blocking layer is provided in a specific region between a p-type layer and a transparent electrode. The current blocking layer is formed of an insulating and transparent material with a refractive index lower than that of the p-type layer. Specific region is a region including the contact portion in plan view. The current blocking layer is not provided in regions overlapping with the wire bonding portion and the wiring portion. The current blocking layer is larger by 0 μm to 9 μm in width than the contact portion. | 2015-03-19 |
20150076548 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE INCLUDING LIGHT EMITTING ELEMENT AND WAVELENGTH CONVERTING MEMBER - A light emitting device includes a light emitting element and a wavelength converting member bonded with each other. The light emitting element has, from the wavelength converting member side, a first region and a second region. The wavelength converting member has, from the light emitting element side, a third region and a fourth region. The first region has an irregular atomic arrangement compared with the second region. The third region has an irregular atomic arrangement compared with the fourth region. The first region and the third region are directly bonded. | 2015-03-19 |
20150076549 | Method for Producing Optoelectronic Semiconductor Components, Arrangement and Optoelectronic Semiconductor Component - In at least one embodiment of the method, the method is used to produce optoelectronic semiconductor components. A lead frame assemblage includes a plurality of lead frames. The lead frames each includes at least two lead frame parts and the lead frames in the lead frame assemblage are electrically connected to one another by connecting webs. The lead frame assemblage is fitted on an intermediate carrier. At least a portion of the connecting webs is removed and/or interrupted. Additional electrical connecting elements are fitted between adjacent lead frames and/or lead frame parts. A potting body mechanically connects the lead frame parts of the individual lead frames to one another. The resulting structure is singulated to form the semiconductor components. | 2015-03-19 |
20150076550 | LIGHT EMITTING ELEMENT - A light-emitting element includes a semiconductor portion, an upper electrode and a lower electrode. The upper electrode includes a plurality of first external connectors, a plurality of second external connectors, a first inward elongated portion extending from each of the first external connectors, a second inward elongated portion extending from each of the second external connectors, a first outward elongated portion extending from each of the first external connectors toward a side opposite to a side where the second external connectors are disposed, and connecting two first external connectors next to each other, and a second outward elongated portion extending from each of the second external connectors toward a side opposite to a side where the first external connectors are disposed, and connecting two second external connectors next to each other. | 2015-03-19 |
20150076551 | METHODS OF FABRICATING WAFER-LEVEL FLIP CHIP DEVICE PACKAGES - In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon. | 2015-03-19 |
20150076552 | SILICONE RESIN COMPOSITION, SEMI-CURED MATERIAL SHEET, PRODUCING METHOD OF SILICONE CURED MATERIAL, LIGHT EMITTING DIODE DEVICE, AND PRODUCING METHOD THEREOF - A silicone resin composition contains a polysiloxane containing at least one pair of condensable substituted groups capable of condensation by heating and at least one pair of addable substituted groups capable of addition by an active energy ray. | 2015-03-19 |
20150076553 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode is provided on the semiconductor layer via the gate dielectric film. A drain layer of a first conductivity type is provided in a part of the semiconductor layer on a side of a first end of the gate electrode. A source layer of a second conductivity type is provided in a part of the semiconductor layer on a side of a second end of the gate electrode and below the gate electrode. The source layer has a substantially uniform impurity concentration at the part of the semiconductor layer below the gate electrode. Voltages of a same polarity are applied to the gate electrode and the drain layer. | 2015-03-19 |
20150076554 | Insulated Gate Bipolar Transistor with Mesa Sections Between Cell Trench Structures and Method of Manufacturing - An IGBT includes a mesa section that extends between two cell trench structures from a first surface of a semiconductor portion to a layer section of the semiconductor portion. A source region, which is electrically connected to an emitter electrode, is formed in the mesa section. A doped region, which is separated from the source region by a body region of a complementary conductivity type, includes a first portion with a first mean net impurity concentration and a second portion with a second mean net impurity concentration exceeding at least ten times the first mean net impurity concentration. In the mesa section the first portion extends from the body region to the layer section. The second portions of the doped region virtually narrow the mesa sections in a normal on-state of the IGBT. | 2015-03-19 |
20150076555 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; and a body region and a drift region formed in the semiconductor substrate. The semiconductor device also includes a bulk region and a source region formed in the body region. Further, the semiconductor device includes a drain region and a first shallow trench isolation structure having a ladder-like bottom formed in the drift region. Further, the semiconductor device also includes a gate structure spanning over an edge of the body region and an edge of the drift region formed on the semiconductor substrate and covering a portion of the first shallow trench isolation structure. | 2015-03-19 |
20150076556 | INTEGRATED CIRCUIT DEVICE AND A METHOD FOR PROVIDING ESD PROTECTION - An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node. | 2015-03-19 |
20150076557 | SIGNAL IO PROTECTION DEVICES REFERENCED TO SINGLE POWER SUPPLY AND METHODS OF FORMING THE SAME - Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation. | 2015-03-19 |
20150076558 | SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF - The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure. | 2015-03-19 |
20150076559 | INTEGRATED CIRCUITS WITH STRAINED SILICON AND METHODS FOR FABRICATING SUCH CIRCUITS - Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium. | 2015-03-19 |
20150076560 | INTEGRATED CIRCUITS INCLUDING EPITAXIALLY GROWN STRAIN-INDUCING FILLS DOPED WITH BORON FOR IMPROVED ROBUSTNESS FROM DELIMINATION AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer. | 2015-03-19 |
20150076561 | SILICON-ON-NOTHING FINFETS - A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer. | 2015-03-19 |
20150076562 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device is provide that can reduce contact resistance of an ohmic electrode and a nitride semiconductor layer. In a GaN HFET, recesses ( | 2015-03-19 |
20150076563 | METHOD OF MAKING A CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN AND CIRCUIT FORMED - A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain. | 2015-03-19 |
20150076564 | MULTI-THRESHOLD CIRCUITRY BASED ON SILICON-ON-INSULATOR TECHNOLOGY - Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors. | 2015-03-19 |
20150076565 | ULTRAHIGH-VOLTAGE SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein. | 2015-03-19 |
20150076566 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions. | 2015-03-19 |
20150076567 | MOLECULAR RECEPTOR-BASED CHEMICAL FIELD-EFFECT TRANSISTOR (CHEMFET) DEVICES, SYSTEMS, AND METHODS FOR IN-SITU NITRATE MONITORING IN FIELD SOILS - Embodiments include a method for securing a membrane material to a gate of a molecular receptor-based chemical field-effect transistor (CHEMFET). The method can include casting a membrane material onto an exposed region of the gate, curing the membrane material, placing the CHEMFET into a mold, inserting a single application of impervious electrically insulative resin into the mold, and securing edges of the membrane material by the single application of the impervious electrically insulative resin, thereby physically preventing lifting off of the membrane material from the gate. Embodiments include a sensor module. The sensor module can include a CHEMFET, an amplifier circuit, one or more sensor pins for contacting field ground soil, a data logger, and a wireless transceiver, among other components. | 2015-03-19 |