12th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090072309 | Semiconductor device - The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode of the SJMOSFET. | 2009-03-19 |
20090072310 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 2009-03-19 |
20090072311 | MOS transistor and manufacturing method thereof - There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and the gate, a silicon layer formed on the gate oxide layer, and a source region and a drain region formed in the silicon layer to be in contact with the gate oxide layer. | 2009-03-19 |
20090072312 | Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS - A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack. | 2009-03-19 |
20090072313 | HARDENED TRANSISTORS IN SOI DEVICES - A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors. | 2009-03-19 |
20090072314 | Depletion Mode Field Effect Transistor for ESD Protection - The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode | 2009-03-19 |
20090072315 | Semiconductor Manufacturing Process Charge Protection Circuits - Embodiments of the invention relate to semiconductor manufacturing process charge protection circuits, integrated circuits and to methods for manufacturing a semiconductor manufacturing process charge protection circuit. In an embodiment of the invention, a charge protection circuit includes a first terminal coupled to a charge receiving region, a second terminal providing a discharge path, and a rectifying circuit coupled between the first terminal and the second terminal, the rectifying circuit including at least two anti-parallel coupled rectifying components. | 2009-03-19 |
20090072316 | DOUBLE LAYER STRESS FOR MULTIPLE GATE TRANSISTORS - Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer. | 2009-03-19 |
20090072317 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 2009-03-19 |
20090072318 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a gate insulating layer on a semiconductor substrate, a gate electrode on the gate insulating layer and source/drain regions in the semiconductor substrate at sides of the gate electrode. The gate electrode includes a first gate electrode and a second gate electrode on and electrically connected to the first gate electrode. | 2009-03-19 |
20090072319 | SEMICONDUCTOR DEVICE WITH RELATIVELY HIGH BREAKDOWN VOLTAGE AND MANUFACTURING METHOD - A semiconductor device includes at least one active component ( | 2009-03-19 |
20090072320 | Asymmetrical layout for complementary metal-oxide-semiconductor integrated circuit to reduce power consumption - A Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit design layout incorporating an asymmetrical polysilicon gate and diffusion is disclosed. The resulting asymmetrical CMOS integrated circuit exhibits reduced current flow during operation to thereby decrease power consumption. | 2009-03-19 |
20090072321 | THIN FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor element is operated without being affected even when the substrate is largely affected by heat shrink such as a large substrate. Furthermore, a thin film semiconductor circuit and a thin film semiconductor device each having the semiconductor element. Also, a semiconductor element is operated without being affected even if there is slight mask deviation. In view of them, a plurality of gate electrodes formed so as to overlap a lower concentration impurity region of a semiconductor layer than drain regions on a drain region side. Also, source regions and the drain regions corresponding to the respective gate electrodes are formed so that current flows in opposite directions each other through channel regions corresponding to the gate electrodes. Further, the number of the channel regions in which a current flows in a first direction is equal to the number of the channel regions in which a current flows in a direction opposite to the first direction. | 2009-03-19 |
20090072322 | SEMICONDUCTOR DEVICES INCLUDING LINE PATTERNS SEPARATED BY CUTTING REGIONS - Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction. | 2009-03-19 |
20090072323 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate. | 2009-03-19 |
20090072324 | SEMICONDUCTOR DEVICE HAVING AN ELEVATED SOURCE/DRAIN STRUCTURE OF VARYING CROSS-SECTION - A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate. | 2009-03-19 |
20090072325 | METAL-OXIDE SEMICONDUCTOR TRANSISTOR - A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar. | 2009-03-19 |
20090072326 | ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer. | 2009-03-19 |
20090072327 | Semiconductor Storage Device and Method for Manufacturing the Same - [Problems] To provide a semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by means of favorable nitrogen concentration profile of a gate insulating film, and to provide a method for manufacturing such a device. | 2009-03-19 |
20090072328 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a first gate insulating film over a cell region of a semiconductor substrate. A conductive layer is formed over the semiconductor substrate including the cell region and a peripheral region. An oxidizing process is performed on the conductive layer to form a second gate insulating film in the cell region and a third gate insulating film in the peripheral region. | 2009-03-19 |
20090072329 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a field effect transistor comprising a gate insulating film having the film thickness of 1 nm or more, wherein at least an area of the gate insulating film which extending up to 1 nm from the side of the semiconductor layer in the thickness direction thereof comprises a silicon oxynitride film (SiON), the atom number ratio (O/Si) of oxygen to silicon in the area is 0.01 to 0.30, and the atom number ratio (N/Si) of nitrogen to silicon in the area is 0.05 to 0.30. | 2009-03-19 |
20090072330 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less. | 2009-03-19 |
20090072331 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less. | 2009-03-19 |
20090072332 | SYSTEM-IN-PACKAGE PLATFORM FOR ELECTRONIC-MICROFLUIDIC DEVICES - The present invention relates to an integrated electronic-micro fluidic device an integrated electronic-micro fluidic device, comprising a semiconductor substrate ( | 2009-03-19 |
20090072333 | SENSOR ARRAY HAVING A SUBSTRATE AND A HOUSING, AND METHOD FOR MANUFACTURING A SENSOR ARRAY - In a sensor array having a substrate and a housing, and in a method for manufacturing a sensor array are proposed, the housing substantially completely surrounds the substrate in a first substrate area, the housing is provided in a second substrate area at least partly open via an opening, and the second substrate area is provided protruding from the housing in the area of the opening. | 2009-03-19 |
20090072334 | Semiconductor device, pre-mold package, and manufacturing method therefor - A pre-mold package of a semiconductor device is constituted of a lead frame, a mold resin having a box-like shape constituted of a side wall and a bottom for mounting at least one semiconductor chip, and a cover composed of a conductive material. The lead frame includes a shield plate embedded in the bottom of the mold resin, a plurality of arms, and a plurality of external terminals that are exposed on the backside of the bottom of the mold resin. The arms are embedded in the side wall so that the distal ends thereof are exposed on the upper end of the side wall and are electrically connected to the cover. Instead of the arms, a plurality of internal terminals is included in the lead frame so that the distal ends thereof are exposed on the upper surfaces of racks formed inside of the mold resin. | 2009-03-19 |
20090072335 | Image sensor package - An image sensor package is provided. The image sensor package may include a semiconductor substrate, an image sensor stacked over an upper surface of the semiconductor substrate, a pad formed on a lower surface of the semiconductor substrate and electrically connected with the image sensor, and a passive component formed by a thin film process on a lower surface of the semiconductor substrate and electrically connected with the pad. | 2009-03-19 |
20090072336 | Solid-state imaging device and method for manufacturing thereof as well as driving method of solid-state imaging device - A solid-state imaging device having an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area. | 2009-03-19 |
20090072337 | IMAGE SENSORS INCLUDING PHOTOELECTRIC CONVERTING UNITS HAVING MULTIPLE IMPURITY REGIONS AND METHODS OF FORMING THE SAME - An image sensor includes a semiconductor layer, and first and second photoelectric converting units including first and second impurity regions in the semiconductor layer that are spaced apart from each other and that are at about an equal depth in the semiconductor layer, each of the impurity regions including an upper region and a lower region. A width of the lower region of the first impurity region may be larger than a width of the lower region of the second impurity region, and widths of upper regions of the first and second impurity regions are equal. | 2009-03-19 |
20090072338 | SEMICONDUCTOR PHOTODETECTOR AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a semiconductor photodetector includes: forming an insulating film on a semiconductor substrate; forming an electrode on and in contact with a predetermined area of a surface of the semiconductor substrate; forming a resist on the insulating film after forming the electrode; forming a power supply layer of a metal on the resist and the electrode; plating a surface of a portion of the power supply layer with a metal coating, after forming the power supply layer, the portion overlying and being in contact with the electrode; after the plating, etching and removing a part of the power supply layer leaving a portion that is covered with the metal coating and is an extension of the electrode; and removing the resist after etching the power supply layer. | 2009-03-19 |
20090072339 | Semiconductor device having diode and IGBT - A semiconductor device includes: a semiconductor substrate including a first conductive type layer; a plurality of IGBT regions, each of which provides an IGBT element; and a plurality of diode regions, each of which provides a diode element. The plurality of IGBT regions and the plurality of diode regions are alternately arranged in the substrate. Each diode region includes a Schottky contact region having a second conductive type. The Schottky contact region is configured to retrieve a minority carrier from the first conductive type layer. The Schottky contact region is disposed in a first surface portion of the first conductive type layer, and adjacent to the IGBT region. | 2009-03-19 |
20090072340 | EDGE TERMINATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE - High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection. | 2009-03-19 |
20090072341 | BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES - Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line. | 2009-03-19 |
20090072342 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming an ion implanted region on a semiconductor substrate in a cell/core region. The semiconductor substrate is selectively etched to form a recess. The recess exposes a boundary of the ion implanted region. The ion implanted region exposed at the bottom of the recess is removed to form an under-cut space in the semiconductor substrate. An insulating film is formed to form a substrate having a silicon-on-insulator (SOI) structure in the cell/core region. The insulating film fills the under-cut space and the recess. | 2009-03-19 |
20090072343 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE - A high-performance semiconductor device using an SOI substrate in which a low-heat-resistance substrate is used as a base substrate. Further, a high-performance semiconductor device formed without using chemical polishing. Further, an electronic device using the semiconductor device. An insulating layer over an insulating substrate, a bonding layer over the insulating layer, and a single-crystal semiconductor layer over the bonding layer are included, and the arithmetic-mean roughness of roughness in an upper surface of the single-crystal semiconductor layer is greater than or equal to 1 nm and less than or equal to 7 nm. Alternatively, the root-mean-square roughness of the roughness may be greater than or equal to 1 nm and less than or equal to 10 nm. Alternatively, a maximum difference in height of the roughness may be greater than or equal to 5 nm and less than or equal to 250 nm. | 2009-03-19 |
20090072344 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns. | 2009-03-19 |
20090072345 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - In a semiconductor device having element isolation made of a trench-type isolating oxide film | 2009-03-19 |
20090072346 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - In a semiconductor device having element isolation made of a trench-type isolating oxide film | 2009-03-19 |
20090072347 | Semiconductor Constructions, and Electronic Systems - The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H | 2009-03-19 |
20090072348 | Integrated Circuits; Methods for Manufacturing an Integrated Circuit and Memory Module - Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate, at least one first electrode disposed in or above the substrate, ion conductor doping material disposed above the at least one first electrode, ion conductor material disposed above the ion conductor doping material, and at least one second electrode disposed above the ion conductor material. | 2009-03-19 |
20090072349 | Semiconductor device and method of manufacturing the same - Example embodiments provide a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may include a lower electrode including a first lower electrode and a second lower electrode, and the second lower electrode may be formed on at least a part of the first lower electrode using a material different from the first lower electrode. A dielectric film may be formed on at least a part of the second lower electrode and a first upper electrode may be formed on the dielectric film. | 2009-03-19 |
20090072350 | SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole. | 2009-03-19 |
20090072351 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SAID METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 2009-03-19 |
20090072352 | GALLIUM NITRIDE BULK CRYSTALS AND THEIR GROWTH METHOD - A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm | 2009-03-19 |
20090072353 | METHOD FOR INCREASING THE AREA OF NON-POLAR AND SEMI-POLAR NITRIDE SUBSTRATES - A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions. | 2009-03-19 |
20090072354 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device includes an upper electrode line structure and a lower electrode line structure provided over a semiconductor substrate. The semiconductor device also includes a guard contact having a first portion and a second portion. The guard contact is disposed between the upper electrode line structure and the lower electrode line structure. The first and second portions of the guard contact have different line widths. | 2009-03-19 |
20090072355 | DUAL SHALLOW TRENCH ISOLATION STRUCTURE - A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths. | 2009-03-19 |
20090072356 | High-Heat-Resistant Semiconductor Device - In a wide gap semiconductor device of SiC or the like used at a temperature of 150 degrees centigrade or higher, the insulation characteristic of a wide gap semiconductor element is improved and a high-voltage resistance is achieved. For these purposes, a synthetic high-molecular compound, with which the outer surface of the wide gap semiconductor element is coated, is formed in a three-dimensional steric structure which is formed by linking together organosilicon polymers C with covalent bonds resulting from addition reaction. The organosilicon polymers C have been formed by linking at least one organosilicon polymers A having a crosslinked structure using siloxane (Si—O—Si combination) with at least one organosilicon polymers B having a linear linked structure using siloxane through siloxane bonds. | 2009-03-19 |
20090072357 | Integrated shielding process for precision high density module packaging - An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules ( | 2009-03-19 |
20090072358 | Semiconductor Integrated Circuit Package, Printed Circuit Board, Semiconductor Apparatus, and Power Supply Wiring Structure - A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside. | 2009-03-19 |
20090072359 | STACKED SYNCHRONOUS BUCK CONVERTER - A multichip module buck converter | 2009-03-19 |
20090072360 | Molded semiconductor device including IC-chip covered with conductor member - A semiconductor device according to the present invention includes a conductor member, an IC-chip and leads, all molded together with a resin mold. The conductor member is composed of a base portion on which the IC-chip is mounted, a cover portion for covering a functioning surface of the IC-chip, and a bent portion connecting the cover portion to the base portion. The base portion includes a lead portion that is grounded. The cover portion and the base portion are positioned substantially in parallel to each other, and the IC-chip is disposed in an inner space between the cover portion and the base portion. The lead portion to be grounded and the leads electrically connected to the IC-chip extend out of the resin mold. Since the IC-hip is disposed in the inner space of the conductor member that is grounded, the IC-chip is protected from the electromagnetic noises and from electrostatic charges otherwise accumulated in the resin mold. | 2009-03-19 |
20090072361 | Multi-Chip Stacked Package Structure - A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads. | 2009-03-19 |
20090072362 | THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE - A semiconductor package includes a semiconductor device | 2009-03-19 |
20090072363 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH LEADS - An integrated circuit package-in-package system includes: forming an integrated circuit package system including: connecting a first integrated circuit die and a lead, and forming an inner encapsulation covering the first integrated circuit die and a portion of the lead; mounting a second integrated circuit die to the integrated circuit package system; connecting the second integrated circuit die and the lead; and forming a package encapsulation covering the integrated circuit package system and the second integrated circuit die with the lead exposed. | 2009-03-19 |
20090072364 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADS SEPARATED FROM A DIE PADDLE - An integrated circuit package system is provided including forming a leadframe having a frame and a die paddle having leads thereon. The leads are held with respect to the die paddle. The leads are separated from the die paddle, and a die is attached to the die paddle. Bond wires are bonded between the leads and the die. The die and bond wires are encapsulated. The leadframe is singulated to separate the frame and the die paddle. | 2009-03-19 |
20090072365 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTERNAL INTERCONNECTS AT HIGH DENSITY - An integrated circuit package system includes: connecting an integrated circuit die and external interconnects; forming an encapsulation over the integrated circuit die and a portion of the external interconnects; and forming an isolation hole between the external interconnects and into a side of the encapsulation exposing the external interconnects. | 2009-03-19 |
20090072366 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY - An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side. | 2009-03-19 |
20090072367 | LEADFRAME - Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface of the die attach pad. | 2009-03-19 |
20090072368 | PACKAGE FOR MONOLITHIC COMPOUND SEMICONDUCTOR (CSC) DEVICES FOR DC TO DC CONVERTERS - A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame. | 2009-03-19 |
20090072369 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. In the semiconductor device, a rectangular header with two mounting regions is folded, and two semiconductor chips are then fixed respectively to the mounting regions facing each other. Thereby, a stacked structure of the semiconductor chips is achieved while a mounting area of a package remains the same as the area for one semiconductor chip of a conventional type. Furthermore, characteristics of the two semiconductor chips can be obtained. Accordingly, compared with a case in which one semiconductor chip is used, on-resistance is decreased due to an increase in the number of transistor cells. Thereby, the semiconductor device can be driven at a low voltage. In addition, a larger current capacity can be achieved. Moreover, compared with a case in which two semiconductor chips are mounted next to each other on the header, a mounting area of a package outline can be reduced. | 2009-03-19 |
20090072370 | MULTILAYER WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - There is provided a multilayer wiring substrate on which at least one semiconductor element is mounted. The multilayer wiring substrate includes: a baseboard; a first wiring layer formed on the baseboard and having a plurality of first wiring portions; an insulating layer formed on the baseboard; a second wiring layer formed on the insulating layer and having a plurality of second wiring portions, the second wiring portions being electrically connected to each other via a conductor wire, the conductor wire being arranged within the insulating layer three-dimensionally in a curved manner; and conductor portions configured to pass through the insulating layer and connecting the first wiring portions and the second wiring portions. | 2009-03-19 |
20090072371 | Methods And Articles Incorporating Local Stress For Performance Improvement Of Strained Semiconductor Devices - A packaged semiconductor device ( | 2009-03-19 |
20090072372 | Planar Array Contact Memory Cards - A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors. | 2009-03-19 |
20090072373 | PACKAGED INTEGRATED CIRCUITS AND METHODS TO FORM A STACKED INTEGRATED CIRCUIT PACKAGE - Packaged integrated circuits and methods to form a thermal stacked integrated circuit package are disclosed. A disclosed method comprises attaching a first integrated circuit to at least one of a plurality of pads of a substrate, mounting a second integrated circuit above the first integrated circuit, placing a heat conductor in thermal contact with a top surface of the second integrated circuit, and encapsulating the first and second integrated circuits while leaving a surface of the heat conductor exposed to dissipate heat. | 2009-03-19 |
20090072374 | Electric Device, Stack of Electric Devices, and Method of Manufacturing a Stack of Electric Devices - According to one embodiment of the present invention, an electric device includes: a top surface and a bottom surface; a contact hole extending from the top surface through the device to the bottom surface; a conductive sealing element which seals the contact hole at or near the bottom surface; a conductive connection which is coupled to the conductive sealing element and which extends through the contact hole to the top surface; and solder material which is provided on a bottom surface of the conductive sealing element. | 2009-03-19 |
20090072375 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE - An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive. | 2009-03-19 |
20090072376 | Carrier Structure Stacking System and Method - The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits. | 2009-03-19 |
20090072377 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DELAMINATION PREVENTION STRUCTURE - An integrated circuit package system includes: mounting an integrated circuit die over a carrier; attaching a delamination prevention structure over the integrated circuit die; and encapsulating the delamination prevention structure and the integrated circuit die. | 2009-03-19 |
20090072378 | MEMORY DEVICE SYSTEM WITH STACKED PACKAGES - An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end of the base package for connection to an electrical interconnect. | 2009-03-19 |
20090072379 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness. | 2009-03-19 |
20090072380 | Microelectromechanical Device Packages with Integral Heaters - A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding the first and second package substrates so as to package the microelectromechanical device inside, a sealing medium layer is deposited, and heated by the heater so as to bond the first and second package substrates together. | 2009-03-19 |
20090072381 | SEMICONDUCTOR DEVICE WITH DOUBLE-SIDED ELECTRODE STRUCTURE AND ITS MANUFACTURING METHOD - According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring. | 2009-03-19 |
20090072382 | MICROELECTRONIC PACKAGE AND METHOD OF FORMING SAME - A microelectronic package includes a carrier ( | 2009-03-19 |
20090072383 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT MODULE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor element is provided with a heat dissipating path defined by a non-through hole in a first principal surface and that is filled with a conductive material. The semiconductor element is bonded to a heat sink with the conductive material disposed therebetween. Solder can be used as the conductive material, for example. By introducing molten solder into the non-through hole while having solder disposed between the semiconductor element and the heat sink, the heat dissipating path is provided and the heat sink is bonded to the semiconductor element. | 2009-03-19 |
20090072384 | Packaging substrate having heat-dissipating structure - Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads. | 2009-03-19 |
20090072385 | Electronic Assemblies Providing Active Side Heat Pumping and Related Methods and Structures - An electronic assembly may include a packaging substrate, an integrated circuit (IC) semiconductor chip, a plurality of metal interconnection structures, and a thermoelectric heat pump. The integrated circuit (IC) semiconductor chip may have an active side including input/output pads thereon and a back side opposite the active side, and the IC semiconductor chip may be arranged with the active side facing the first surface of the packaging substrate. The plurality of metal interconnection structures may be between the active side of the IC semiconductor chip and the first surface of the packaging substrate, and the plurality of metal interconnection structures may provide mechanical connection between the active side of the IC semiconductor chip and the first surface of the packaging substrate. The thermoelectric heat pump may be coupled to the packaging substrate with the thermoelectric heat pump being configured to actively pump heat between the IC semiconductor chip and the packaging substrate. Related methods and structures are also discussed. | 2009-03-19 |
20090072386 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY - A semiconductor package includes a main body having a semiconductor device accommodating portion accommodating a basic circuit including a semiconductor device, external connection terminal members protruding outside the main body, and a cooling structure reducing heat generated by the device from the main body. The cooling structure includes a coolant flowing portion including a coolant supply port to which coolant is supplied, a coolant moving space which is positioned adjacent to the accommodating portion and in which the coolant moves in a back side of the basic circuit of the accommodating portion, and a coolant discharge port which discharges the coolant from the moving space. The semiconductor package assembly includes a package support body which supports the package and which includes a coolant circulation structure supplying coolant to the flowing portion of the main body through the supply port and collecting the supplied coolant through the discharge port. | 2009-03-19 |
20090072387 | CURVILINEAR HEAT SPREADER/LID WITH IMPROVED HEAT DISSIPATION - A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip. | 2009-03-19 |
20090072388 | SEMICONDUCTOR DEVICE WITH INDUCTOR - One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip. | 2009-03-19 |
20090072389 | STRUCTURE AND METHOD FOR FORMING A CAPACITIVELY COUPLED CHIP-TO-CHIP SIGNALING INTERFACE - A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad. | 2009-03-19 |
20090072390 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A semiconductor apparatus ( | 2009-03-19 |
20090072391 | Structurally-enhanced integrated circuit package and method of manufacture - A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps. | 2009-03-19 |
20090072392 | Techniques For Forming Solder Bump Interconnects - Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer. | 2009-03-19 |
20090072393 | Structure and Method for Fabricating Flip Chip Devices - A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad ( | 2009-03-19 |
20090072394 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer. | 2009-03-19 |
20090072395 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element, a lead, and a gold wire electrically connecting an electrode of the semiconductor element and the lead. In the semiconductor device, the gold wire is covered with a metal and is a continuous film formed by plating. | 2009-03-19 |
20090072396 | Method of Forming Low Stress Multi-Layer Metallurgical Structures and High Reliable Lead Free Solder Termination Electrodes - Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed. The barrier layer prevents formation of an intermetallic compound in proximity to the first layer by precluding diffusion of tin from the termination electrode to the first layer. In a specific embodiment, the first layer includes stress release copper underneath a barrier layer which includes nickel. | 2009-03-19 |
20090072397 | REDISTRIBUTION LAYER FOR WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD THEREFOR - In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern ( | 2009-03-19 |
20090072398 | INTEGRATED CIRCUIT, CIRCUIT SYSTEM, AND METHOD OF MANUFACTURING - An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material. | 2009-03-19 |
20090072399 | SEMICONDUCTOR MOUNTING BONDING WIRE - There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or equal to 100% thereof. | 2009-03-19 |
20090072400 | CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED - Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric layer, and second forming an upper contact portion to the lower contact portion through a second dielectric layer over the first dielectric layer. A contact may include a first contact portion contacting a silicide region, the first contact portion having a width less than 100 nm; and a second contact portion coupled to the first contact portion from above, the second contact portion having a width greater than the width of the first contact portion. | 2009-03-19 |
20090072401 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER - Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure. | 2009-03-19 |
20090072402 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device comprising forming a metal layer on a semiconductor substrate, patterning the metal layer to form a plurality of metal wires having side surfaces, forming spacers on both side surfaces of each of the metal wires, and forming an insulating layer between the spacers of the adjacent metal wires, the insulating layer having voids formed therein and being formed with material having a dielectric constant which differs from that of the spacers, and a semiconductor device made by this method. | 2009-03-19 |
20090072403 | Wiring Structure, Semiconductor Device and Manufacturing Method Thereof - A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls. | 2009-03-19 |
20090072404 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal. | 2009-03-19 |
20090072405 | Semiconductor device - The semiconductor device according to the present invention includes: a first wire made of a material mainly composed of Cu; a second wire made of a material mainly composed of Cu; an interlayer dielectric film formed between the first wire and the second wire; a via, made of a material mainly composed of Cu, penetrating through the intermediate dielectric film to be connected to the first wire and the second wire; and a dummy via, made of a material mainly composed of Cu, smaller in via diameter than the via and connected to the first wire while not contributing to electrical connection between the first wire and the second wire. | 2009-03-19 |
20090072406 | INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME - An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal. In accordance with the present invention, the metallic interfacial layer also does not form an alloy with any portion of the diffusion barrier liner. | 2009-03-19 |
20090072407 | THERMO-COMPRESSION BONDED ELECTRICAL INTERCONNECT STRUCTURE AND METHOD - An electrical structure and method for forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure and a first solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. A second portion of the non-solder metallic core structure is thermo-compression bonded to the second electrically conductive pad. | 2009-03-19 |
20090072408 | Connecting and Bonding Adjacent Layers with Nanostructures - An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same. | 2009-03-19 |