11th week of 2016 patent applcation highlights part 54 |
Patent application number | Title | Published |
20160078887 | MAIN POLE LAYER WITH AT LEAST TWO SACRIFICIAL LAYERS AND A GAP LAYER - In accordance with one embodiment, a method may be implemented by depositing a non-magnetic gap layer of material above a main pole layer of magnetic material; depositing a sacrificial layer of material above the non-magnetic gap layer of material; etching a portion of the sacrificial layer of material while not entirely removing the sacrificial layer of material; and depositing additional sacrificial material to the etched sacrificial layer. | 2016-03-17 |
20160078888 | UNDERLAYER FOR REFERENCE LAYER OF POLYCRYSTALLINE CPP GMR SENSOR STACK - Embodiments disclosed herein generally relate to a magnetic head having an amorphous ferromagnetic reference layer. The ferromagnetic reference layer may have amorphous structure as a result of an amorphous ferromagnetic underlayer that the ferromagnetic reference layer is deposited thereon. The amorphous ferromagnetic reference layer enhances magnetoresistance, leading to an improved magnetic head. | 2016-03-17 |
20160078889 | SENSOR STRUCTURE HAVING LAYER WITH HIGH MAGNETIC MOMENT - A reader sensor having a composite shield and a sensor stack. The composite shield includes a high magnetic moment layer having a magnetic moment greater than 1.0 T, a low magnetic moment layer, and a spacer therebetween. The high magnetic moment layer is closer to the stack than the low magnetic moment layer. The high magnetic moment layer may be a single layer or have a plurality of layers. | 2016-03-17 |
20160078890 | HEAD GIMBAL ASSEMBLY AND STORAGE DEVICE PROVIDED WITH THE SAME - A head gimbal assembly includes a load beam, a wiring member including a metal plate disposed on the load beam, a magnetic head attached to a tip section of the wiring member, and a piezoelectric element that is fixed to and supported by supporting pads and deforms in response to a voltage applied thereto. The metal plate includes a tip section to which the magnetic head is fixed, and a base section that is spaced apart from the tip section and is fixed to the load beam. The supporting pads include first and second supporting pads proximate to the tip section and distal from the base section and a third supporting pad proximate to the base section and distal to the tip section, each of supporting pads separated from and independent of both the tip section and the base section. | 2016-03-17 |
20160078891 | GLASS SUBSTRATE FOR INFORMATION RECORDING MEDIUM AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a method for manufacturing a glass substrate for an information recording medium having a high level of cleanness and superior smoothness. The manufacturing method includes a step for washing a disk-shaped glass plate with an acid washing liquid, a step for removing at least part of a surface layer, which is formed on the surface of the glass plate, by performing grinding with diamond abrasion grains, and a step for washing the surface with a neutral or alkaline washing liquid. | 2016-03-17 |
20160078892 | MAGNETIC RECORDING MEDIUM AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic recording medium including a substrate and a magnetic recording layer formed on the substrate and including a plurality of projections is obtained. The array of the plurality of projections includes a plurality of domains in which the projections are regularly arranged, and a boundary region between the domains, in which the projections are irregularly arranged. The boundary region is formed along a perpendicular bisector of a line connecting the barycenters of adjacent projections. | 2016-03-17 |
20160078893 | OPTICAL INFORMATION RECORDING AND REPRODUCING DEVICE AND OPTICAL INFORMATION RECORDING AND REPRODUCING METHOD - An optical information recording and reproducing device performs high-speed reproduction without having to sequentially change the wavelength of a reproduction light source. The device includes: a laser light source which generates a signal light and a reference light; a temperature measurement unit which measures temperature at least at two or more positions; a wavelength adjustment unit which adjusts a wavelength of the laser light source according to a result of measurement by the temperature measurement unit; a temperature distribution calculation unit which calculates a temperature distribution on the basis of the result of measurement by the temperature measurement unit; and a control unit which controls a recording operation and a reproducing operation. The control unit controls permission and prohibition of the recording operation or the reproducing operation according to the temperature distribution calculated by the temperature distribution calculation unit. | 2016-03-17 |
20160078894 | BASE MEMBER, SPINDLE MOTOR HAVING THE SAME, AND RECORDING DISK DRIVING DEVICE - There is provided a spindle motor including: a stator core around which a coil is wound; a base member to which the stator core is fixedly attached and in which a coil lead hole is disposed below the stator core; and a coating layer which is provided in the coil lead hole and in the vicinity of the coil lead hole. | 2016-03-17 |
20160078895 | SPINDLE MOTOR AND HARD DISK DRIVE INCLUDING THE SAME - A spindle motor includes a stator, and a rotor forming a bearing clearance filled with a lubricating fluid, together with the stator. At least one of the rotor and the stator is provided with a circulation hole through which air bubbles contained in the lubricating fluid are discharged, and a portion of the bearing clearance connected to one end portion of the circulation hole and disposed at an outer side of the circulation hole in a radial direction has a width allowing an amount of force applied to the other side of the air bubble to be less than that of force applied to one side of the air bubble when one side of the air bubble is disposed in the circulation hole and the other side thereof is disposed in the portion of the bearing clearance connected to the circulation hole. | 2016-03-17 |
20160078896 | SPINDLE MOTOR AND HARD DISK DRIVE INCLUDING THE SAME - A spindle motor includes a stator, and a rotor forming a bearing clearance with the stator. The rotor is provided with an insertion groove formed therein into which a portion of the stator is inserted, and first and second sealing parts having liquid-vapor interfaces formed therein, respectively, are formed inside and outside the insertion groove, respectively. The first and second sealing parts are in communication with each other via a connection hole. | 2016-03-17 |
20160078897 | RECORDING AND PLAYBACK DEVICE - The recording and playback device includes a recording unit configured to record AV data on a recording medium as an AV data file, a file management unit configured to provide an access system depending on a use to the AV data file, an updating unit configured to update file information about access restrictions on the AV data file depending on the access system being provided depending on a use, based on a rule associated with the access system, and a communication unit configured to open the AV data relating to the updated file information to the outside. | 2016-03-17 |
20160078898 | Error Correction for Storage Devices - The present disclosure describes systems and techniques relating to storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR). According to an aspect of the described systems and techniques, a device includes: circuitry configured to write stored data and parity data to discrete portions of a Shingled Magnetic Recording (SMR) track in a SMR storage device; and circuitry configured to recover stored data for one of the discrete portions of the SMR track using the parity data and the stored data read from remaining ones of the discrete portions of the SMR track. | 2016-03-17 |
20160078899 | CONTENT INFORMATION PROCESSING DEVICE AND METHOD FOR DISPLAYING IDENTIFIED OBJECT IMAGES WITHIN VIDEO CONTENT - An information processing apparatus comprising that includes a reproduction unit to reproduce video content comprising a plurality of frames; a memory to store a table including object identification information identifying an object image, and frame identification information identifying a frame of the plurality of frames that includes the object image; and a processor to extract the frame including the object image from the video content and generate display data of a reduced image corresponding to the frame for display. | 2016-03-17 |
20160078900 | ELASTIC CLOUD VIDEO EDITING AND MULTIMEDIA SEARCH - Technologies for cloud-based media search and editing include a video editor configured to build a media query and associate the media query with a dynamic content slot of a media program. When generating video output based on the media program, the video editor transmits the media query to a cloud analytics server and receives 5 search results identifying one or more media clips produced by a number of mobile computing devices. The video editor may display a list of clips for selection by the user or may automatically include one of the clips in the output. The cloud analytics server transmits an acceptance policy defining criteria for acceptable media, based on the media query, to the mobile computing devices. The mobile computing devices con | 2016-03-17 |
20160078901 | DATA TRANSMISSION METHOD, DATA PLAYBACK METHOD, DATA TRANSMISSION DEVICE, AND DATA PLAYBACK DEVICE - A data transmission method according to one aspect of the present disclosure includes: generating a plurality of MPUs, reference clock time information, and leading clock time information indicating a leading PTS that is a clock time at which a leading access unit in the MPU is presented, transmitting the generated plurality of MPUs, reference clock time information, and leading clock time information, wherein the leading clock time information indicates the leading PTS of the plurality of MPUs of which presentation is started after the leading clock time information is transmitted in the generated plurality of MPUs, and each of the generated plurality of MPUs indicates a time point at which each access unit that does not exist in a head of the MPU is presented as a relative value to a time point of another access unit in the MPU. | 2016-03-17 |
20160078902 | CONTENT REPRODUCTION METHOD AND APPARATUS - The content reproduction method includes receiving a select signal for selecting one or more pieces of content; and reproducing the selected pieces of content and one or more pieces of content which were generated or reproduced together with the selected pieces of content in a temporal space within a range. | 2016-03-17 |
20160078903 | SHARING AND SYNCHRONIZING CONTENT - A device may provide a video content item for display and receive a request to share the video content item with another device for a synchronized playing of the video content item by the device and the other device. The device may generate a stream of the video content item based on a point within the video content item currently played by the device and transmit the stream to the other device to synchronize playing of the video content item by the device and the other device. The device may obtain information identifying a particular point within the video content item currently played by the other device, determine a synchronization point, in the video content item, based on the obtained information, and update, based on the synchronization point, to synchronize the stream. The device may transmit the synchronized stream, to the other device, to re-synchronize playing of the video content item. | 2016-03-17 |
20160078904 | CONTENT MANAGEMENT SYSTEM, MANAGEMENT CONTENT GENERATING METHOD, MANAGEMENT CONTENT PLAY BACK METHOD, AND RECORDING MEDIUM - In a content management system, the still image extracting unit extracts a plurality of frames of still image data from the moving image data based on the motion of the person of interest. The scene determining unit determines a scene of the moving image including a still image corresponding to each of the plurality of frames of the still image data. The management marker registration unit registers, as a management marker, each of the plurality of frames of still image data or an image feature amount of each still image in association with a scene of a moving image corresponding to each still image. The management image generator generates management image data including at least two pieces of the still image data. | 2016-03-17 |
20160078905 | VIDEO RECORDING METHOD AND VIDEO RECORDING DEVICE - A video recording device including: a format control section defining a video file record to produce a file via a format defined having a BDMV directory and at least directories to record the video signal and to record Play List data further arranged below the BDMV directory, and forms the format so one Play Item is produced in each of segments of video scenes to be acquired and a plurality of Play Items are arranged within one piece of the Play List data; and a recording control section recording the video information on the recording medium according to the format formed by the format control section, wherein when video acquired by the camera is recorded where a first piece of Play List data is produced, Items are produced within the first piece of the Play List data without generating a new piece of Play List data. | 2016-03-17 |
20160078906 | SEMICONDUCTOR DEVICE - According to one embodiment, electrodes are provided in stacked M (M is an integer of 2 or more) semiconductor chips, a transmission units are provided for the semiconductor chips and, based on a chip identification information on a semiconductor chip in the present stage, transmits the chip identification information on a semiconductor chip in the next stage via the electrodes, or transmit a data for setting the chip identification information, and the direction in which an external signal is sent via the electrodes is opposite to the direction in which the chip identification information is transmitted via the electrodes. | 2016-03-17 |
20160078907 | MEMORY DEVICE CAPABLE OF OPERATION IN WIDE TEMPERATURE RANGE AND DATA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME - A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a temperature at the data processing system and generate a temperature signal. The controller is configured to control whether the first memory is enabled or disabled and whether the second memory is enabled or disabled based on the temperature signal and based on a first temperature threshold associated with the first memory and a second temperature threshold associated with the second memory. | 2016-03-17 |
20160078908 | SEMICONDUCTOR MEMORY APPARATUS AND OPERATION METHOD USING THE SAME - A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal. | 2016-03-17 |
20160078909 | OUTPUT BUFFER CIRCUIT WITH LOW SUB-THRESHOLD LEAKAGE CURRENT - A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive. | 2016-03-17 |
20160078910 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - According to one embodiment, a driving method of a semiconductor memory device, the semiconductor memory device has a stacked body, in which a first electrode film, a second electrode film, a third electrode film are stacked in this order via insulating films, a first semiconductor pillar extending in a stacking direction of the first electrode film, the second electrode film, and the third electrode film and provided in the stacked body, and a memory film. The driving method comprises applying a first voltage to the third electrode film, the first voltage being lower than a second voltage applied to the first electrode film, in case applying a program voltage to the second electrode film, the program voltage to inject charges from the first semiconductor pillar to a portion of the memory film located between the first semiconductor pillar and the second electrode film. | 2016-03-17 |
20160078911 | SEMICONDUCTOR MEMORY DEVICE HAVING COUNT VALUE CONTROL CIRCUIT - A device includes a data storing cell array including a plurality of groups of data storing cells each configured to be accessed responsive to the input of the corresponding one of the row addresses and a count value control circuit coupled to each of the groups of the data storing cells. The count value control circuit is configured to update a count value stored in each of the groups of data storing cells by a first value responsive to the input of the corresponding one of the row addresses in a first operation mode and to set the count value stored in each of the groups of the data storing cells to a second value responsive to the input of the corresponding one of the row addresses in a second operation mode. | 2016-03-17 |
20160078912 | STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL - A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell. | 2016-03-17 |
20160078913 | MAGNETIC MEMORY, SPIN ELEMENT, AND SPIN MOS TRANSISTOR - A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage. | 2016-03-17 |
20160078914 | STT-MRAM SENSING TECHNIQUE - Embodiments are directed to a system for sensing a data state of a selected memory cell. The system includes a first reference cell, a sample-and-hold sense amplifier and a switching system. During a first sensing phase the switching system is configured to open a first series communication path that places the selected memory cell in series with the first reference cell, thereby creating a first series voltage divider. During the first sensing phase, the switching system is further configured to open a first branch communication path that taps an input of the sample-and-hold sense amplifier into a first divided voltage between the selected memory cell and the first reference cell. | 2016-03-17 |
20160078915 | RESISTANCE CHANGE MEMORY - According to one embodiment, according to one embodiment, a resistance change memory includes a memory cell, a sense amplifier, a control circuit and a storage unit. The memory cell includes a resistance change element. The sense amplifier compares a reference current with a cell current flowing through the memory cell. The control circuit calculates offset information of the reference current. The storage unit is provided for the sense amplifier and stores the offset information. The storage unit corresponds to the sense amplifier one to one. | 2016-03-17 |
20160078916 | FAST PROGRAMMING OF MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage. | 2016-03-17 |
20160078917 | Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors - Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors. | 2016-03-17 |
20160078918 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed to when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation. | 2016-03-17 |
20160078919 | SEMICONDUCTOR MEMORY DEVICE COMPENSATING DIFFERENCE OF BITLINE INTERCONNECTION RESISTANCE - A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance. | 2016-03-17 |
20160078920 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device including a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction, a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction, a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other, a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers. | 2016-03-17 |
20160078921 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 2016-03-17 |
20160078922 | SRAM CELLS WITH VERTICAL GATE-ALL-ROUND MOSFETS - A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary. | 2016-03-17 |
20160078923 | SEMICONDUCTOR MEMORY DEVICE - In an embodiment, a semiconductor memory device includes a memory cell that includes a first inverter having a first input and a first output, and a second inverter having a second input connected to the first output and a second output connected to first input portion. A first bit line that is connected to the first output of the first inverter via a first transmission transistor. A second bit line is connected to the second output of the second inverter via a second transmission transistor. A first p channel MOS transistor has a drain connected to the first bit line, and a gate connected to the second bit line. A second p channel MOS transistor has a drain connected to the second bit line and a gate connected to the first bit line. | 2016-03-17 |
20160078924 | MEMORY DEVICE WITH MEMORY CELLS SRAM (STATIC RANDOM ACCESS MEMORIES) AND CONTROLLING THE POLARIZATION OF BOXES OF TRANSISTORS OF THE MEMORY CELLS - A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns. | 2016-03-17 |
20160078925 | SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 2016-03-17 |
20160078926 | DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) - In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit. | 2016-03-17 |
20160078927 | DESIGN-FOR-TEST APPARATUSES AND TECHNIQUES - Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include an SRAM cell, read/write (R/W) circuitry to provide a nominal word line (WL) voltage and a nominal BL voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed. | 2016-03-17 |
20160078928 | NAND ARRAY HIARCHICAL BL STRUCTURES FOR MULTIPLE-WL AND ALL-BL SIMULTANEOUS ERASE, ERASE-VERIFY, PROGRAM, PROGRAM-VERIFY, AND READ OPERATIONS - Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred V | 2016-03-17 |
20160078929 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, a sense amplifier electrically connected to the bit line, and a controller configured to perform a read operation including first and second read operations on the memory cell. During the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line. | 2016-03-17 |
20160078930 | REPRESENTING DATA USING A GROUP OF MULTILEVEL MEMORY CELLS - A memory device includes a group or block of k-level memory cells, where k>2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels. | 2016-03-17 |
20160078931 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a first wiring line extending in a first direction, a second wiring line extending in a first direction, the first wiring line and the second wiring line being separated from each other, a third wiring line separated from the first wiring line and the second wiring line, at least one portion of the third wiring line extending in a second direction crossing the first direction, a fourth wiring line separated from the first wiring line and the second wiring line, at least one portion of the fourth wiring line extending in the second direction, a first interconnect connected between a side surface of the first wiring line and a side surface of the third wiring line, and a second interconnect connected between a side surface of the second wiring line and a side surface of fourth wiring line. | 2016-03-17 |
20160078932 | SEMICONDUCTOR STORAGE DEVICE - An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. | 2016-03-17 |
20160078933 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode. | 2016-03-17 |
20160078934 | 1T-1R ARCHITECTURE FOR RESISTIVE RANDOM ACCESS MEMORY - A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal. | 2016-03-17 |
20160078935 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: first and second wiring lines; resistive change memories disposed intersection regions of the first and second wiring lines; and a control circuit controlling the first and second drivers to select one of the first wiring lines and one of the second wiring lines, the control circuit changing a resistance of the selected one of the resistive change memories from the first resistive state to the third resistive state, and then changing the resistive state of the selected one of the resistive change memories from the third resistive state to the second resistive state. | 2016-03-17 |
20160078936 | VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. | 2016-03-17 |
20160078937 | RESISTIVE MEMORY DEVICE AND CONTROL METHOD THEREOF - A resistive memory device is provided. A first cell is coupled to a word line, a first bit line and a source line. A second cell is coupled to the word line, a second bit line and the source line. A control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell and execute a reset operation for the second cell. After the set and the reset operations, the resistance of the first cell is less than the resistance of the second cell. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level. | 2016-03-17 |
20160078938 | METHOD AND APPARATUS FOR PROVIDING MULTI-PAGE READ AND WRITE USING SRAM AND NONVOLATILE MEMORY DEVICES - A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string. | 2016-03-17 |
20160078939 | APPOINTING SEMICONDUCTOR DICE TO ENABLE HIGH STACKING CAPABILITY - Briefly, in accordance with one or more embodiments, a memory array comprises two or more volumes, the volumes comprising two or more dice, respectively. The volumes are connected in a daisy chain configuration such that an output of a first volume is coupled to an input of a next volume, and the dice are connected in a daisy chain configuration such that an output of a first die is coupled to an input of a next die within the volume. In such a configuration, a first die in a first volume is capable of being appointed as part of a second volume. | 2016-03-17 |
20160078940 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes first word lines equipped with flag-like portions on one side of the block in the row direction and equipped with no flag-like portions on the other side of the block in the row direction, and second word lines equipped with no flag-like portions on the one side of the block in the row direction and equipped with flag-like portions on the other side of the block in the row direction. | 2016-03-17 |
20160078941 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A NAND STRING - A semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a first memory cell of the first NAND string selected by of the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell. | 2016-03-17 |
20160078942 | OPERATING CHARACTERISTICS OF A SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines, a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate, and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate. | 2016-03-17 |
20160078943 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - According to one embodiment, a semiconductor memory device includes: semiconductor member; electrode member; charge accumulation member; a memory unit; and a control unit. Memory cell is formed at each crossing portion of the semiconductor member and the electrode member. The memory unit retains information indicating that the memory cell belongs to first group or second group. The control unit performs first step and second step, when reducing the charge accumulated in the charge accumulation member. In the first step, first voltage is applied both between the semiconductor member and the electrode member of the first group and between the semiconductor member and the electrode member of the second group. In the second step, second voltage is applied between the semiconductor member and the electrode member constituting the memory cell belonging to the second group. | 2016-03-17 |
20160078944 | WORD LINE REPAIR FOR 3D VERTICAL CHANNEL MEMORY - A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, a top plane of conductive strips, and an additional intermediate plane. A plurality of vertical structures is arranged orthogonally to the plurality of stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of vertical structures. A stack of linking elements is connected to conductive strips in respective intermediate planes and to the additional intermediate plane. Decoding circuitry is coupled to the plurality of intermediate planes and the additional intermediate plane, and is configured to replace an intermediate plane indicated to be defective with the additional intermediate plane. | 2016-03-17 |
20160078945 | INCREMENTAL STEP PULSE PROGRAMMING - The disclosed technology provides enables incremental step pulse programming (ISPP) operations with variable pulse step height control. In particular, a storage device is configured to select a pulse step height for an ISPP operation of one or more memory cells of a storage device based on a write frequency of data programmed via the ISPP operation. The storage device saves the data by applying a series of electrical pulses to the one or more memory cells, each subsequent pulse increasing in magnitude by the selected pulse step height. | 2016-03-17 |
20160078946 | MEMORY SYSTEM AND OPERATION METHOD THEREOF - A memory system includes a memory device having a plurality of memory blocks, each including a plurality of pages, each page including a plurality of memory cells, wherein data provided from a host device is written on the plurality of pages and the plurality of memory cells coupled to a plurality of word lines; and a controller suitable for setting word line zones by grouping the plurality of word lines by a predetermined number, and performing a bad management for the memory blocks in each of the word line zones. | 2016-03-17 |
20160078947 | MEMORY SYSTEM AND CONTROLLER - A memory system includes a semiconductor memory device and a controller. The semiconductor memory device performs a writing operation with either a first writing method or a second writing method. The controller selects one of the first writing method and the second writing method upon receipt of a write instruction and output a write command indicating the selected writing method to the semiconductor memory device. The controller selects the writing method in accordance with a storage location in the semiconductor memory device targeted by the write instruction. | 2016-03-17 |
20160078948 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory string including a first memory cell and a second memory cell, a second memory string including a third memory cell, a bit line connected to both one end of the first memory string and one end of the second memory string, a first word line connected to gates of the first and third memory cells, a second word line connected to a gate of the second memory cell, and a control circuit configured to determine a program condition of the first memory cell that have been selected for a write operation, and perform the write operation for the third memory cell based on the program condition of the first memory cell. | 2016-03-17 |
20160078949 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells. | 2016-03-17 |
20160078950 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more program voltages. | 2016-03-17 |
20160078951 | PROGRAMMING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A programming method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first write command; and selecting a first physical erasing unit and sending a first skipping write command sequence according to the first write command. The first skipping write command sequence instructs to execute a first skipping programming process. The first skipping programming process includes: programming first data into a first word line of the first physical erasing unit; and after the first word line is programmed, skipping a second word line adjacent to the first word line, and programming the first data into a third word line not adjacent to the first word line. | 2016-03-17 |
20160078952 | OPERATING METHOD OF NAND FLASH MEMORY UNIT - A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased. | 2016-03-17 |
20160078953 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell, a first bit line that is electrically connected to the first memory cell, a second bit line that is electrically connected to the second memory cell, a first sense module that is electrically connected to the first bit line through a first transistor, and a second sense module that is electrically connected to the second bit line through a second transistor. During sensing of the first and second bit lines, the first and second transistors are turned on for first and second periods of time, respectively, to electrically connect the first and second sense modules to the corresponding first and second bit lines. The first period of time is longer than the second period of time. | 2016-03-17 |
20160078954 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell. When data is read from the first memory cell, a first voltage and a second voltage is applied to the first word line. A voltage of the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage changes a second number of times different from the first number of times while the second voltage is applied to the first word line. | 2016-03-17 |
20160078955 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 2016-03-17 |
20160078956 | Memory Device - A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells when the common source line forms a first electrical connection path and is connected to the ground voltage. | 2016-03-17 |
20160078957 | MEMORY, DISPLAY DEVICE INCLUDING THE SAME, AND WRITING METHOD OF THE SAME - A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines. | 2016-03-17 |
20160078958 | Single Ended Word Line and Bit Line Time Constant Measurement - In non-volatile memories, bit lines and word lines commonly to driving and decoding circuitry on a single end. Techniques are presented for determining the time constant associated with charging the far end of such lines from the near end, at which the circuitry is connected. While driving a discharged line from the near end, the number of clock cycles for the current to drop from a first level to a second level can be used to estimate the time constant for the far end. Alternately, the line can be initially charged up, after which the current is monitored at the near end. The differences in time constants for different word lines can be used to vary the time used when accessing a selected word line. | 2016-03-17 |
20160078959 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a plurality of memory cells including a first memory cell and a second memory cell stacked above the first memory cell, a plurality of word lines including first and second word lines connected to first and second memory cells, respectively, a driver circuit connected to gates of the memory cells to supply voltages of different levels to the gates of the memory cells, and a control circuit configured to control the driver circuit to apply, during a reading operation on a selected memory cell, a first voltage to other, non-selected memory cells at a first timing and a second voltage to the selected memory cell at a second timing that is after a time period after the first timing. The time period when the first memory cell is the selected memory cell is less than the time period when the second memory cell is the selected memory cell. | 2016-03-17 |
20160078960 | METHOD AND APPARATUS FOR WRITING DATA TO NON-VOLATILE MEMORY - Devices and methods implemented therein are disclosed for storing data in memory pages of a non-volatile memory of the storage device. The device comprises a non-volatile memory, a reading circuit, a programming circuit and a read disturb detector. The non-volatile memory has an erased memory page comprising a plurality of multi-layer cells (MLCs). The reading circuit is configured to read a respective electric charge stored in each of the plurality of MLCs. The programming circuit is configured to store data in the plurality of MLCs at either one of a first storage density or a second storage density. The read disturb detector is configured to determine whether the erased memory page is read disturbed and if the erased memory page is read disturbed, cause the programming circuit to store data into the MLCs at the second storage density that is less than the first storage density. | 2016-03-17 |
20160078961 | METHOD OF ERASING A NONVOLATILE MEMORY FOR PREVENTING OVER-SOFT-PROGRAM - A method of erasing a nonvolatile memory for preventing over-soft-program comprises performing an erase operation on at least one cell among a plurality of cells in the nonvolatile memory; applying a first soft program verify operation; applying a second soft program verify operation, wherein the second verify voltage is lower than the first verify voltage; determining whether the threshold voltage of the cell is lower than the first verify voltage or the second verify voltage; performing a soft program operation with a first soft program voltage when the threshold voltage of the cell is lower than the first verify voltage and higher than the second verify voltage; and performing the soft program operation with a second soft program voltage higher than the first soft program voltage when the threshold voltage of the cell is lower than both of the first verify voltage and the second verify voltage. | 2016-03-17 |
20160078962 | ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL AND ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAYS - An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width. | 2016-03-17 |
20160078963 | PROGRAMMING OF ANTIFUSE CELLS - For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated. | 2016-03-17 |
20160078964 | METHOD FOR TESTING REDUNDANCY AREA IN SEMICONDUCTOR MEMORY DEVICE - A method tests a redundancy area of a semiconductor memory device. The method includes receiving a redundancy address to select a redundancy area including spare memory cells to repair normal memory cells, checking the redundancy address based on repair use information to determine whether the redundancy area is an actually repaired area, enabling the redundancy area when the redundancy area is the actually repaired area, and outputting data read from the enabled redundancy area to practically perform a redundancy area test. | 2016-03-17 |
20160078965 | SCANNABLE MEMORIES WITH ROBUST CLOCKING METHODOLOGY TO PREVENT INADVERTENT READS OR WRITES - An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit. | 2016-03-17 |
20160078966 | METHOD OF PERFORMING WEAR MANAGEMENT IN NON-VOLATILE MEMORY DEVICES - A method is provided for performing wear management in a non-volatile memory device which includes a plurality of storage units. A first error count associated with the amount of error bits generated in a specific storage unit during a first access is acquired. A second error count associated with an amount of error bits generated in the specific storage unit during a second access is retrieved, wherein the second access occurs earlier than the first access. An early retirement threshold is set to a first value when the difference between the first error count and the second error count does not exceed the predetermined value, or set to a second value smaller than the first value when the difference between the first error count and the second error count exceeds the predetermined value. The specific storage unit is marked as a bad storage unit when the first error count exceeds the early retirement threshold. | 2016-03-17 |
20160078967 | Power Loss Test Device And Method For Nonvolatile Memory Device - A power loss test apparatus for a non-volatile memory device includes a test-board including at least one socket into which at least one test target non-volatile memory device is inserted, a micro controller that determines whether to supply power to the test target non-volatile memory device based on current consumption information or operating state information of the test target non-volatile memory device, and a tester that performs a power loss test for the test target non-volatile memory device based on whether the power is supplied to the test target non-volatile memory device. | 2016-03-17 |
20160078968 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes: a non-volatile memory circuit suitable for storing hard repair data; a data bus suitable for transmitting the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers suitable for storing repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit suitable for selecting a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank suitable for performing a repair operation based on the data stored in a register that is activated among the plurality of the registers. | 2016-03-17 |
20160078969 | EFFICIENT CODING FOR MEMORY REDUNDANCY - A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories. | 2016-03-17 |
20160078970 | METHOD AND SYSTEM FOR THERMAL NUCLEAR FUSION - A method for nuclide bombardment includes providing a nuclide bombardment target, which includes a metallic single-crystalline layer having a hydrogen-absorbing metallic element. The single-crystalline layer includes lattice channels disposed therein. The target also includes first hydrogen isotopes, configured as interstitial elements in the lattice channels in the single-crystalline layer. The method further includes injecting second hydrogen isotopes into the target substantially along the direction of the lattice channels. | 2016-03-17 |
20160078971 | System And Method For Generating Molybdenum-99 And Metastable Technetium-99, And Other Isotopes - Accelerator based systems are disclosed for the generation of isotopes, such as molybdenum-98 (“99Mo”) and metastable technetium-99 (“99mTc”) from molybdenum-98 (“98Mo”). Multilayer targets are disclosed for use in the system and other systems to generate 99mTc and 98Mo, and other isotopes. In one example a multilayer target comprises a first, inner target of 98Mo surrounded, at least in part, by a separate, second outer layer of 98Mo. In another example, a first target layer of molybdenum-100 is surrounded, at least in part, by a second target layer of 98Mo. In another example, a first inner target comprises a Bremsstrahlung target material surrounded, at least in part, by a second target layer of molybdenum-100, surrounded, at least in part, by a third target layer of 98Mo. | 2016-03-17 |
20160078972 | METHOD FOR MANUFACTURING A COLLIMATOR MODULE AND METHOD FOR MANUFACTURING A COLLIMATOR BRIDGE AS WELL AS COLLIMATOR MODULE, COLLIMATOR BRIDGE, COLLIMATOR AND TOMOGRAPHY DEVICE - A method for manufacturing a collimator module and/or a collimator bridge is disclosed, as well as a collimator module, a collimator bridge, a collimator and a tomography device. A collimator module for a radiation detector includes a plurality of collimator layers. These collimator layers each have a flat lattice structure. In an embodiment, a first collimator layer has a holder structure and the collimator layers are aligned relative to one another by the holder structure on a first holder tool. With such a holder structure it is possible to glue the aligned collimator layers to one another such that the glued collimator layers form the collimator module with absorber walls disposed in a lattice shape. In such cases, the collimator layers can be aligned to one another in an especially simple and yet precise manner. Through this the actual lattice shape corresponds especially accurately to a prespecified lattice shape. | 2016-03-17 |
20160078973 | ALFVEN-WAVE GYRATING NON-LINEAR INERTIAL-CONFINEMENT REACTOR - A fusion reactor includes an improved ability to modulate a plasma for specific purposes. The reactor operates on the ability to change at least four separate variables in each of a plurality of lenses that are independent of the other lenses. This allows for the generation of Alfvén waves and modulation of the internal plasma dynamics, actively leading to higher states of efficiency. By combining modulation of a plasma in the form of an ion beam with a solid state metal target, an efficient fast neutron source can be produced. This can lead to industrial applications such as energy generation, nuclear clean-up, the production of rare earth metals out of semi-rare ones, and helium production. | 2016-03-17 |
20160078974 | XRF ANALYZER ROTATIONAL FILTER - An XRF analyzer can include a rotatable filter structure to separately position at least two different x-ray source modification regions between an x-ray source and a focal point and at least two different x-ray detector modification regions between an x-ray detector and the focal point. | 2016-03-17 |
20160078975 | Method and Technique to Control Laser Effects Through Tuning of Parameters Such as Repetition Rate - A technique for controlling the effects generated by the interaction of a plurality of laser pulses with a medium by selecting or varying the successive pulse parameters comprising: generating a plurality of laser pulses interacting with a medium; and selecting or varying the properties/parameters characterizing said laser pulses to control the effects resulting from the interaction among said plurality of laser pulses and said medium. | 2016-03-17 |
20160078976 | Corrosion Resistant Barrier Formed by Vapor Phase Tin Reflow - A copper substrate for use as a contact having tin plating, nickel plating and gold plating overlying the substrate. A combination of tin plating is applied over a copper substrate; nickel plating is applied over the tin plating; and gold plating is applied over the nickel plating to form a stack. The stack is then processed by a vapor phase tin reflow step that results in the formation of intermetallics and eliminates stannous oxide layers that may otherwise form on the tin layer. The intermetallic layers provide excellent corrosion resistance, and serve as diffusion barriers to prevent the further migration of either nickel atoms or copper atoms into the tin, and tin atoms outwardly into either the nickel or the copper. Regardless of the thickness, the interfaces are substantially free of oxides, in particular tin oxide, and not prone to delamination. | 2016-03-17 |
20160078977 | CONDUCTIVE POLYMER MATERIAL AND SUBSTRATE - The present invention provides a conductive polymer material including (A) a π-conjugated polymer, (B) a dopant polymer which contains a repeating unit having a sulfo group and has a weight-average molecular weight in the range of 1,000 to 500,000, and (C) either or both of sulfonium salt compounds represented by the following general formulae (1-1) and (1-2). There can be provided a conductive polymer material that has low acidity, can suppress the gradual agglomeration of particles, and has excellent solution-stability. | 2016-03-17 |
20160078978 | CONDUCTIVE COMPOSITION, CONDUCTOR AND SOLID ELECTROLYTIC CAPACITOR USING CONDUCTIVE COMPOSITION - A conductive composition according to the present invention contains a conductive polymer (A) having a sulfonic acid group and/or a carboxyl group; and an alkali metal hydroxide and/or an alkaline earth metal hydroxide (B). In such a conductive composition, the amount of the hydroxide (B) is set at 0.2˜0.65 mol per 1 mol of a repeating unit that contains a sulfonic acid group and/or a carboxyl group in the conductive polymer (A). | 2016-03-17 |
20160078979 | INSULATING TAPE FOR COVERING, AND METHOD FOR PRODUCING STRUCTURE - To provide an insulating tape for covering, in which a polyimide film and a fluorinated resin film are laminated with excellent adhesion, and a method for producing a structure, which comprises covering a conductor with such an insulating tape for covering, followed by thermal treatment. The insulating tape for covering, comprises a polyimide film and a fluorinated resin film directly laminated on one or both surfaces of the polyimide film, wherein the fluorinated resin film contains a fluorinated copolymer (A) which has a melting point of from 220 to 320° C. and can be melt-molded and which has at least one type of functional groups selected from the group consisting of carbonyl group-containing groups, hydroxy groups, epoxy groups and isocyanate groups. | 2016-03-17 |
20160078980 | COPPER BOND WIRE AND METHOD OF MAKING THE SAME - The invention is related to a bonding wire containing a core having a surface. The core contains copper as a main component, an average size of crystal grains in the core is between 2.5 μm and 30 μm, and a yield strength of the bonding wire is less than 120 MPa. | 2016-03-17 |
20160078981 | SIGNAL CABLE AND WIRE HARNESS - A signal cable is provided with a pair of power supply wires and a pair of signal wires. Each of the pair of the power supply wires is provided with a conductor and an insulator with which the conductor of the power supply wire is coated. Each of the pair of the signal wires comprises a conductor and an insulator with which the conductor of the signal wire is coated. The pair of the power supply wires and the pair of the signal wires are respectively disposed diagonally. The power supply wires and the signal wires are collectively twisted together, and the conductors of the power supply wires and the conductors of the signal wires are respectively twisted together in a state that strains of the conductors of the power supply wires and the conductors of the signal wires are within a range of an elastic region. | 2016-03-17 |
20160078982 | METHODS FOR COVERING AN ELONGATE SUBSTRATE - A cover assembly for covering an elongate substrate includes a holdout device and a resilient, elastically radially expanded sleeve member. The holdout device includes a core having an axially extending slit defined therein and defining a core passage to receive the substrate, and a designated target region. The sleeve member defines an axially extending sleeve passage. The sleeve member is mounted on the core such that the core is disposed in the sleeve passage and the sleeve member exerts a radially compressive recovery force on the core. When the substrate is disposed in the core passage and a radially directed release force is applied to the target region, the core will reduce in circumference and collapse around the substrate under the recovery force of the sleeve member to a collapsed position. | 2016-03-17 |
20160078983 | EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE | 2016-03-17 |
20160078984 | CONDUCTOR MARKER - The invention relates to a conductor marker ( | 2016-03-17 |
20160078985 | DUAL RESOLUTION POTENTIOMETER - An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism. | 2016-03-17 |
20160078986 | COIL COMPONENT AND BOARD HAVING THE SAME - There are provided a coil component and a board having the same. The coil component includes: a magnetic body including a substrate having two cores, first and second coil parts disposed on one surface of the substrate and wound in the same direction, and third and fourth coil parts disposed on the other surface of the substrate to be spaced apart from each other; and first to fourth external electrodes disposed on outer surfaces of the magnetic body and connected to the first to fourth coil parts. | 2016-03-17 |