11th week of 2014 patent applcation highlights part 21 |
Patent application number | Title | Published |
20140070828 | METHOD AND APPARATUS FOR MASSIVELY PARALLEL MULTI-WAFER TEST - Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation. | 2014-03-13 |
20140070829 | DEVICE FOR DETECTING THE THINNING DOWN OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT CHIP - A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge. | 2014-03-13 |
20140070830 | MEASURING DEVICE, MEASURING METHOD, AND ELEMENT MANUFACTURING METHOD INCLUDING MEASURING METHOD - A measuring device includes: a probe applying a voltage to an electrode of an element; and a supplying member supplying an insulating liquid to a contact portion between the electrode and the probe via a surface of the probe. Accordingly, the insulating liquid can be securely supplied to the contact portion between the electrode and the probe via the surface of the probe positioned relative to the electrode. | 2014-03-13 |
20140070831 | SYSTEM AND METHOD OF PROTECTING PROBES BY USING AN INTELLIGENT CURRENT SENSING SWITCH - An apparatus and method for protecting probes used in automated testing is disclosed. The apparatus comprises a probe operable to provide power to a device under test (DUT) from a device power source (DPS), wherein the probe is coupled to a contact point on the DUT and a probe protector circuit connected to the probe in series between the DPS and the DUT. The probe protector circuit further comprises a current sense module operable to monitor a flow of current from the DPS to the DUT to determine if the current flow is below a predetermined threshold current level and a switch for controlling the connection from the DPS to the DUT. The switch is coupled to the current sense module and is operable to be used in conjunction with the current sense module to limit the current flow if it exceeds the predetermined threshold current level. | 2014-03-13 |
20140070832 | INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS - An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad. | 2014-03-13 |
20140070833 | METHOD AND APPARATUS FOR DETECTING A LOOSE ELECTRICAL CONNECTION IN PHOTOVOLTAIC SYSTEM - A power circuit configured to generate and distribute DC electrical power, the power circuit includes a photovoltaic (PV) system that includes an array of PV modules electrically coupled to a combiner box, and an inverter positioned to receive DC electrical power from the array of PV modules and output AC electrical power. The PV system also includes a signal generator coupled to a first portion of the PV system, and a signal detector coupled to a second portion of the PV system, the signal detector configured to detect secondary signals generated at a loose connection of an electrical joint in the PV system, wherein the secondary signals result from a signal generated by the signal generator. | 2014-03-13 |
20140070834 | PROBE CARD FOR TESTING INTEGRATED CIRCUITS - An embodiment of a probe card adapted for testing at least one integrated circuit integrated on a corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested. | 2014-03-13 |
20140070835 | TFT-LCD array substrate and test method for the same - The present invention discloses a TFT-LCD array substrate comprising a display area comprising a plurality of data lines and a plurality of gate lines; a peripheral area located at a periphery of the display area and provided with a first test short bar provided with a plurality of data test lines for transmitting a test signal for the data lines in the display area, and a second test short bar provided with a gate test line for transmitting a test signal for the gate lines in the display area; and a connecting device comprising a first connection layer and a second connection and provided at a connection location between one of the data test lines in the first test short bar and one of the data lines in the display area, or provided at a connection location between the gate test line in the second test short bar and one of the gate lines in the display area. The present invention also provides a corresponding test method. The present invention can achieve testing the TFT-LCD array substrate twice. | 2014-03-13 |
20140070836 | APPARATUS FOR SIMULATING SUNLIGHT - An apparatus for simulating sunlight includes a light source for generating light rays, a first reflector having a curved surface that is disposed to receive and reflect the light rays from the light source to form first reflected parallel light rays that travel in a first direction, and a second reflector disposed to face the first reflector and disposed to receive and reflect the first reflected parallel light rays from the first reflector to form second reflected parallel light rays that travel in a second direction. The first and second directions are mutually orthogonal. | 2014-03-13 |
20140070837 | SOLAR MONITOR FOR SOLAR DEVICE - A solar monitor measures electrical characteristics of a designated solar device within an array of solar devices that are coupled in series. The solar monitor includes a charge storage element and a charger coupled to the charge storage element to establish a positive voltage and/or a negative voltage on the charge storage element. A switch within the solar monitor is coupled in a shunt configuration with the designated solar device and with a subsequent device in the array. The switch selectively couples the charge storage element to the designated solar device to vary an operating current that flows between the designated solar device and the subsequent solar device. The solar monitor includes a current detector to measure the current of the designated solar device, and a voltage detector to measure the voltage of the designated solar device. | 2014-03-13 |
20140070838 | CHARGE SHARING TESTING OF THROUGH-BODY-VIAS - In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described. | 2014-03-13 |
20140070839 | SEMICONDUCTOR DEVICE AND METHOD OF DETECTING WIRE OPEN FAILURE THEREOF - In a semiconductor device, two series connections are arranged to be connected between respective split emitter electrodes and a gate electrode with Zener diode units connected in series to respective resistors, with the cathode sides thereof directed to the gate electrode side. The numbers of the Zener diodes in the Zener diode units in the respective series connections are different between the respective Zener diode units. Thus, a semiconductor device can be provided which is capable of detecting an open failure of a bonding wire regardless of the number of a plurality of the bonding wires connected in parallel, by a simple electrical test to make it possible to reliably sort out a semiconductor device with a wire open failure at an early stage. | 2014-03-13 |
20140070840 | Semiconductor Integrated Circuit, Operating Method of Semiconductor Integrated Circuit, and Debug System - A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced. | 2014-03-13 |
20140070841 | LATCH ARRAY UTILIZING THROUGH DEVICE CONNECTIVITY - A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices. | 2014-03-13 |
20140070842 | ADJUSTABLE IMPEDANCE CIRCUIT AND IMPEDANCE SETTING METHOD FOR PROVIDING DIFFERENTIAL-MODE IMPEDANCE MATCHING AND COMMON-MODE IMPEDANCE MATCHING - An adjustable impedance circuit includes a calibration module, an impedance module, a first switch module and a second switch module. The calibration module is arranged to generate a calibration signal. The impedance module has a plurality of impedance elements. The first switch module is coupled to the calibration module, and is arranged to receive the calibration signal and make a first portion of the impedance elements be selectively coupled between a differential input port and at least one reference voltage according to the calibration signal. The second switch module is coupled to a common-mode voltage output node, and is arranged to receive a control signal and make a second portion of the impedance elements be selectively coupled between the common-mode voltage output node and the differential input port according to the control signal. | 2014-03-13 |
20140070843 | IMPEDANCE CALIBRATION CIRCUIT AND METHOD - An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled. | 2014-03-13 |
20140070844 | VOLATILE/NON-VOLATILE MEMORY CELL - The invention concerns a memory device comprising at least one memory cell comprising: a first transistor ( | 2014-03-13 |
20140070845 | TRANSMITTER SWING CONTROL CIRCUIT AND METHOD - Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver. | 2014-03-13 |
20140070846 | Interface Circuitry For A Test Apparatus - In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed. | 2014-03-13 |
20140070847 | CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT EMPLOYING THE SAME - A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit. | 2014-03-13 |
20140070848 | POWER EFFICIENT MULTIPLEXER - A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs. | 2014-03-13 |
20140070849 | METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS - Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed | 2014-03-13 |
20140070850 | CIRCUITS AND METHODS FOR FIELD-BASED COMMUNICATION - Several circuits and methods for field-based communication are provided. In an embodiment, a field-based communication circuit includes a receiver circuit, a detection circuit and a control circuit. The receiver circuit is configured to receive a field input signal from a field source. The detection circuit includes a voltage detection circuit and a current detection circuit configured to detect a voltage signal and a current signal, respectively associated with the field input signal. The control circuit is configured to trigger a selection of one of the voltage detection circuit and the current detection circuit based on a detection of a signal magnitude of one of the voltage signal and the current signal relative to at least a first predetermined threshold level, wherein the selection of one of the voltage detection circuit and the current detection circuit facilitates a demodulation of one of the voltage signal and the current signal. | 2014-03-13 |
20140070851 | SEMICONDUCTOR DEVICE - The present invention is directed to solve a problem that, in a semiconductor device capable of generating a clock signal by coupling a quartz oscillator to an external terminal to which an I/O port is coupled, leak current of the I/O port which is in the inactive state disturbs activation of a clock. The semiconductor device has a first terminal, an amplification circuit coupled to the first terminal, and an output buffer whose output terminal is coupled to the first terminal. The output buffer has first and second transistors of a first conduction type coupled in series via a first node between a first power supply line and an output terminal, and the conduction states of the first and second transistors of the first conduction state are controlled in response to a first control signal which is applied commonly to the gate of each of the first and second transistors. | 2014-03-13 |
20140070852 | POWER SEMICONDUCTOR DEVICE - According to one or more embodiments of the present invention, a power semiconductor device comprise a plurality of gate electrodes, first to third electrodes, and first to fifth semiconductor layers The second semiconductor layer is formed on the first semiconductor layer. A plurality of the third semiconductor layers are formed in the second semiconductor layer and arranged in a direction perpendicular to the stacking direction. The fourth semiconductor layer is formed on the second semiconductor layer. The fifth semiconductor layer is formed on the fourth semiconductor layer. The gate electrodes are formed above the second semiconductor layer and each gate electrode is arranged between the adjacent third semiconductor layers. The first electrodes are formed below the gate electrodes. One of the first electrodes is connected to the gate electrode. One of the first electrodes is connected to the third electrode. | 2014-03-13 |
20140070853 | RF LOGIC DIVIDER - An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch. | 2014-03-13 |
20140070854 | INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY - Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples. | 2014-03-13 |
20140070855 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 2014-03-13 |
20140070856 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 2014-03-13 |
20140070857 | MULTI-PHASE FRACTIONAL DIVIDER - Described is an apparatus comprising: a multi-modulus divider; and a phase provider to receive a multiphase periodic signal and operable to rotate phases of the multiphase periodic signal to generate an output which is received by the multi-modulus divider. | 2014-03-13 |
20140070858 | SIGNAL TRANSMISSION CIRCUIT - A clock generation circuit | 2014-03-13 |
20140070859 | System and Method for Frequency Multiplier Jitter Correction - A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal. | 2014-03-13 |
20140070860 | APPARATUSES INCLUDING SCALABLE DRIVERS AND METHODS - Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described. | 2014-03-13 |
20140070861 | Flip-Flop Circuit and Semiconductor Device - A flip-flop circuit consuming lower power than a conventional flip-flop circuit is provided. Further, a flip-flop circuit having a smaller number of transistors than a conventional flip-flop circuit to have a reduced footprint is provided. An n-channel transistor is used as a transistor which is to be turned on at a high level potential and a p-channel transistor is used as a transistor which is to be turned on at a low level potential, whereby the flip-flop circuit can operate only with a clock signal and without an inverted signal of the clock signal, and the number of transistors that operate only with a clock signal in the flip-flop circuit can be reduced. | 2014-03-13 |
20140070862 | TIMING CALIBRATION FOR ON-CHIP INTERCONNECT - One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect. | 2014-03-13 |
20140070863 | SEMICONDUCTOR INTEGRATED CIRCUIT - There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S | 2014-03-13 |
20140070864 | CLOCK FEATHERED SLEW RATE CONTROL SYSTEM - A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate. | 2014-03-13 |
20140070865 | DEVICE AND METHOD FOR A MULTIPLEXOR/DEMULTIPLEXOR RESET SCHEME - Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted. | 2014-03-13 |
20140070866 | MIXER AND ASSOCIATED SIGNAL CIRCUIT - A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed. | 2014-03-13 |
20140070867 | CIRCUIT FOR COMBINING SIGNALS - Signals generated by an array of photodiodes are applied to the inputs of corresponding edge detection circuits. Each edge detection circuit generates an output that changes state in response to a detected edge of the photodiode generated signal. The edge detection circuits may be formed by toggle flip-flop circuits. The outputs of the edge detection circuits are logically combined using exclusive OR logic to generate an output. The exclusive OR logic may be formed by a cascaded tree of exclusive OR circuits. | 2014-03-13 |
20140070868 | COMPLEMENTARY BIASING CIRCUITS AND RELATED METHODS - Embodiments of complementary biasing circuits and related methods are described herein. Other embodiments and related implementations are also disclosed herein. | 2014-03-13 |
20140070869 | SEMICONDUCTOR DEVICE AND CIRCUIT FOR CONTROLLING POTENTIAL OF GATE OF INSULATED GATE TYPE SWITCHING DEVICE - A semiconductor device outputs a signal to control a gate potential a switching device. The semiconductor device includes a first signal output terminal, and is capable of receiving or internally creating a reference signal, which varies between a first potential and a second potential. The semiconductor device can switch between first and second operations. The first operation outputs to the first signal output terminal a signal that is at a third potential when the reference signal is at the first potential, and that is at a fourth potential higher than the third potential when the reference signal is at the second potential. The second operation outputs to the first signal output terminal a signal that is at the fourth potential when the reference signal is at the first potential, and that is at the third potential when the reference signal is at the second potential. | 2014-03-13 |
20140070870 | Multipurpose Half Bridge Signal Output Circuit - The present invention discloses a multipurpose half bridge signal output circuit. The multipurpose half bridge signal output circuit is capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode. The multipurpose half bridge signal output circuit includes: a first output pin; a second output pin; a first circuit zone having a first common end coupled to the first output pin; and a second circuit zone having a second common end coupled to the second output pin. | 2014-03-13 |
20140070871 | LOW POWER ISOLATED OUTPUT CIRCUIT - An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers. | 2014-03-13 |
20140070872 | RF Switch Circuit, RF Switch and Method for Switching RF Signals - An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors. | 2014-03-13 |
20140070873 | LOW-POWER RESISTOR-LESS VOLTAGE REFERENCE CIRCUIT - A method for generating a reference voltage is disclosed. The method includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to the PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complimentary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent. | 2014-03-13 |
20140070874 | APPARATUS AND METHOD FOR OUTPUTTING SIGNAL - There is provided an apparatus for outputting a signal, including: a reference signal generating unit outputting a first temperature coefficient signal having a positive temperature coefficient and a second temperature coefficient signal having a negative temperature coefficient; and an output unit outputting an output signal having a plurality of temperature coefficients, based on the first temperature coefficient signal and the second temperature coefficient signal. | 2014-03-13 |
20140070875 | ROUTING TRACE COMPENSATION - A capacitive input device includes first and second pluralities of sensor electrodes disposed in a first region of a substrate. The first and second pluralities of sensor electrodes are substantially orthogonal to one another. The first region is configured to overlap a display screen. At least one routing trace is disposed in a second region of the substrate and is ohmically coupled to a sensor electrode of one of the first and second pluralities of sensor electrodes and also to a processing system. The second region comprises a non-display screen overlapping portion of the substrate. A compensation trace is disposed in the second region and ohmically coupled to the processing system. The compensation trace has substantially the same length as and is substantially parallel and proximate to the at least one routing trace. The compensation trace is not ohmically coupled to any sensor electrode located in the first region. | 2014-03-13 |
20140070876 | LINEAR VOLTAGE REGULATOR BASED ON-DIE GRID - Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted. | 2014-03-13 |
20140070877 | LIMITING CIRCUIT FOR A SEMICONDUCTOR TRANSISTOR AND METHOD FOR LIMITING THE VOLTAGE ACROSS A SEMICONDUCTOR TRANSISTOR - A limiting circuit for at least one semiconductor transistor. The circuit includes a limiting path which is coupled between a first power terminal and a second power terminal of the semiconductor transistor. The limiting path includes a limiting transistor. A node of the limiting path located between the limiting transistor and the second power terminal of the semiconductor transistor is coupled to a control terminal of the semiconductor transistor. A voltage source is coupled to the control terminal of the limiting transistor and is designed to apply a control voltage to said control terminal of the limiting transistor. The control voltage corresponds to a critical voltage for the voltage between the first power terminal and the second power terminal of the semiconductor transistor. The limiting transistor is switched to a conductive state when said critical voltage is exceeded at a power terminal of said limiting transistor. | 2014-03-13 |
20140070878 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a voltage monitor circuit; a storage circuit storing an output target characteristic value of the voltage monitor circuit; a comparator configured to compare the output characteristic value of the voltage monitor circuit and the target characteristic value; and a switch control circuit configured to control the number of the plurality of turned-on discrete supply switches based on the comparison result of the comparator. | 2014-03-13 |
20140070879 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a delay monitor circuit having a delay path whose amount of delay changes in accordance with a change in the voltage value of the local power source, and whose output logical value changes in accordance with the amount of delay of the delay path; and a switch control circuit configured to control the number of the plurality of discrete supply switches based on the output logical value of the delay monitor circuit. | 2014-03-13 |
20140070880 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which change in characteristics of a transistor is suppressed and an output signal is changed sharply without increasing W/L of the transistor can be provided. Two transistors are connected in parallel between a wiring to which a low potential is supplied and an output terminal. When the low potential is output from the output terminal, both of the two transistors are turned on and then one of them is turned off. Thus, change in characteristics of the transistor can be suppressed and an output signal can be changed sharply without increasing W/L of the transistor. | 2014-03-13 |
20140070881 | QUIESCENT CURRENT DETERMINATION USING IN-PACKAGE VOLTAGE MEASUREMENTS - Apparatus, systems, and fabrication methods are provided for biasing amplifier arrangements inside device packages to a target quiescent current. In one embodiment, an amplifier device has an output interface and includes an amplifier arrangement having an amplifier output and impedance matching circuitry coupled between the amplifier output and the output interface. A method for biasing the amplifier arrangement involves measuring or otherwise obtaining a voltage between the amplifier output and the output interface, determining an estimated quiescent current through the amplifier arrangement based on that voltage, and adjusting a bias voltage provided to the input of the amplifier arrangement based on a difference between the estimated quiescent current. In exemplary embodiments, the bias voltage is adjusted until the estimated quiescent current is substantially equal to a target quiescent current. | 2014-03-13 |
20140070882 | DISTRIBUTION AMPLIFIER WITH INTELLECTUAL SIGNALING - A distribution amplifier with intellectual signaling comprises a first connector, a first amplifier, a second connector, a power regulator, an inductive coil, a voltage detecting circuit, a first indicating lamp, a second amplifier and a second indicating lamp. The distribution amplifier with intellectual signaling may effectively display whether the distribution amplifier operates normally or not according to the above-mentioned arrangement. | 2014-03-13 |
20140070883 | High Efficiency Amplifier - High efficiency Doherty amplifiers are described. Contemplated Doherty amplifiers can include an input hybrid coupler having first and second inputs, and first and second drivers that individually drive respective first and second inputs. In this manner, the driver output power to the main and auxiliary amplifiers can be dynamically controlled as a function of an input signal's envelope. This advantageously allows for a substantial decrease in the amount of power wasted by the driver, especially when used with digitally modulated signals. | 2014-03-13 |
20140070884 | Power Amplification Circuits - A circuit for amplifying the power of signal, the circuit comprising a power amplifier, a transformer and a load; wherein the transformer comprises a primary inductor and a secondary inductor, the first inductor being coupled to, and capable of being driven by, the power amplifier, and the secondary inductor coupled to, and capable of driving, the load; wherein a first one of the primary and secondary inductors is a variable inductor whose inductance is variable responsive to a control input in order to change the output power of the amplifier. | 2014-03-13 |
20140070885 | POWER SUPPLY ARRANGEMENT FOR SINGLE ENDED CLASS D AMPLIFIER - A power supply arrangement for a single ended class D amplifier, including a first primary winding connected in series with a first switch between the positive supply rail and ground, a second primary winding in phase with said first primary winding and connected in series with a second switch between the negative supply rail and ground, and a controller adapted to apply a control signal to said first and second switches, said control signal (Q) having ON-pulses of a predefined pulse time separated by a dead time. In use, the primary winding connected to the supply rail with the highest numerical voltage will transform the rail voltage difference to the supply rail with the lowest numerical voltage through the opposite primary winding thus reducing any voltage unbalance between the windings. | 2014-03-13 |
20140070886 | AMPLIFIER WITH VOLTAGE AND CURRENT FEEDBACK ERROR CORRECTION - Amplifiers with voltage and current feedback error correction are provided. In one embodiment, an amplifier includes a first input terminal, a second input terminal, an output terminal, a first stage, and a voltage feedback amplification circuit. The first stage can be used to generate first and second output currents, which can be used to control a voltage level of the output terminal. The first and second output currents can change in response to a current feedback signal and a differential input signal received between the first and second input terminals. The first stage can also generate a voltage feedback signal, which can be used by the voltage feedback amplification circuit to control a voltage level of the second input terminal based on a voltage level of the first input terminal. | 2014-03-13 |
20140070887 | IMPEDANCE COMPENSATION FOR OPERATIONAL AMPLIFIERS USED IN VARIABLE ENVIRONMENTS - A dual compensation operational amplifier is suitable for use in an environment that experiences fluctuations in ambient energy levels. A dual compensation impedance can be determined to nullify or compensate for effects of an input offset voltage or an input bias current or both. Adjustments to the dual compensation impedance can be made based on calibration data for various environmental conditions so that the dual compensation impedance can be either pre-set for anticipated conditions in different target operational environments, or automatically adjusted in-situ. Target operational environments that may benefit from such a dual compensation impedance include remote areas that experience extreme or variable temperatures, high altitudes, space, or high radiation environments. | 2014-03-13 |
20140070888 | Buffering Apparatus and Method - The output impedance of an amplifier is substantially matched to an input impedance of a receiver using a buffer circuit. The buffer circuit includes a primary transistor and a secondary transistor. A first back gate terminal of the primary transistor is coupled to a second back gate terminal of the secondary transistor and the primary transistor is configured to have an output for the buffer circuit. An input signal is received from the amplifier at a gate terminal of the secondary transistor. The first back gate terminal of the primary transistor is responsively driven independently from the output of the buffer circuit to effectively adjust a transconductance of the primary transistor and substantially match an output impedance of the amplifier with an input impedance of the receiver. | 2014-03-13 |
20140070889 | LOW-QUIESCENT CURRENT HEADSET DRIVER - A low quiescent current amplifier and driver having multiple amplifiers (e.g. Class AB and B amplifiers) work in concert to independently amplify all or a portion of a signal into multiple amplified signals combined into a unified signal. Operation of a second amplifier is slaved to operation of a first amplifier. Each amplifier may have its own feedback loop providing the same gain transfer function to align transitions of the multiple amplified signals. Operation of the first amplifier may be detected using a replica of a signal, stage or transconductance in the first amplifier. At the same threshold, operation of the first and second amplifiers may be transitioned, e.g., the second amplifier may transition between providing increasing or decreasing current and providing zero current while the first amplifier may transition between providing constant current and providing increasing or decreasing current. | 2014-03-13 |
20140070890 | POWER AMPLIFIER - A power amplifier includes: an amplification element amplifying an input signal; and a bias circuit supplying a bias current to an input of the amplification element. The bias circuit includes a reference voltage terminal to which a battery voltage is applied from a battery, a first resistor having a first end connected to the reference voltage terminal, a second resistor connected between a second end of the first resistor and ground, and a first transistor. The first transistor has a control terminal connected to a connection point between the first resistor and the second resistor, a first terminal connected to a power supply, and a second terminal connected to the input of the amplification element. The first and second resistors are the same material. | 2014-03-13 |
20140070891 | HIGH FREQUENCY AMPLIFIER - To prevent a wrap-around signal from an output detection circuit unit that occurs when commonality is achieved between the power supply of the output detection circuit unit and the bias power supply of a power amplification unit. When commonality is achieved between the power supply of a diode of an output detection circuit unit and the power supply of a bias circuit, a resonance circuit is connected between the bias circuit and the output detection circuit unit, thereby preventing a wrap-around signal from the output side of a power amplification transistor from being input to the input side of the power amplification transistor. | 2014-03-13 |
20140070892 | CONSTANT-TEMPERATURE PIEZOELECTRIC OSCILLATOR AND METHOD OF MANUFACTURING THE SAME - A constant-temperature piezoelectric oscillator includes: a piezoelectric vibrator; an oscillation circuit; a frequency voltage control circuit; a temperature control section; and an arithmetic circuit, wherein the temperature control section includes a temperature-sensitive element, a heating element, and a temperature control circuit, the frequency voltage control circuit includes a voltage-controlled capacitance circuit capable of varying the capacitance value in accordance with the voltage, and a compensation voltage generation circuit, and the arithmetic circuit makes the compensation voltage generation circuit generate a voltage for compensating a frequency deviation due to a temperature difference between zero temperature coefficient temperature Tp of the piezoelectric vibrator and setting temperature Tov of the temperature control section based on a frequency-temperature characteristic compensation amount approximate formula adapted to compensate the frequency deviation, and then applies the voltage to the voltage-controlled capacitance circuit to compensate the frequency. | 2014-03-13 |
20140070893 | High Frequency Oscillator - A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator. | 2014-03-13 |
20140070894 | ATOM CELL MODULE, QUANTUM INTERFERENCE DEVICE, ELECTRONIC APPARATUS, AND ATOM CELL MAGNETIC FIELD CONTROL METHOD - An atom cell module includes an atom cell in which atoms are enclosed, a heating unit that heats the atom cell by generating heat when a current flows, and a magnetic field generator that generates a magnetic field inside the atom cell. A magnetic field at a predetermined position inside the atom cell generated by the magnetic field generator includes a magnetic field component in an opposite direction to a magnetic field at the predetermined position generated on the basis of a current flowing through the heating unit. | 2014-03-13 |
20140070895 | MANUFACTURING METHOD OF QUANTUM INTERFERENCE DEVICE, QUANTUM INTERFERENCE DEVICE, ELECTRONIC APPARATUS, AND ATOM CELL MODULE - A manufacturing method of an atom oscillator (an example of a quantum interference device) includes assembling the atom oscillator (an example of the quantum interference device) by respectively disposing a gas cell, a semiconductor laser, a light detector, ICs of a circuit unit, heaters, and coils at desired locations, and adjusting at least one of currents which flow through the coils, and positions and shapes of the coils such that a frequency-temperature characteristic of a pair of resonance light beams becomes approximately flat. | 2014-03-13 |
20140070896 | MAGNETIC FIELD FEEDBACK BASED SPINTRONIC OSCILLATOR - The embodiments herein relate to a magnetic field feedback based spintronic microwave oscillator driven by DC current. The microwave oscillator works based on a magnetic tunnel junction structure connected to a feedback waveguide. Any fluctuation in the magnetization direction of free magnetization layer of MTJ drives an oscillating current through the feedback waveguide which in turn exerts an oscillating magnetic field on the free layer and amplifies the magnetization fluctuations. If the DC current passing through the MTJ is more than a critical value, continuous processing states of the magnetization are possible. The critical current is independent of the thickness and magnetization of the free layer. A MTJ can be driven into spontaneous oscillations with DC current and magnetic field feedback circuit and can act as a spintronic microwave oscillator. | 2014-03-13 |
20140070897 | OSCILLATOR CIRCUIT - An oscillator circuit ( | 2014-03-13 |
20140070898 | Low Phase Noise Voltage Controlled Oscillators - A voltage controlled oscillator (VCO) with low phase noise and a sharp output spectrum is desirable. The present disclosure provides embodiments of LC tank VCOs that generate output signals with less phase noise compared with conventional LC tank VCOs, while at the same time limiting additional cost, size, and/or power. The embodiments of the present disclosure can be used, for example, in wired or wireless communication systems that require low-phase noise oscillator signals for performing up-conversion and/or down-conversion. | 2014-03-13 |
20140070899 | CANCELLING SUPPLY NOISE IN A VOLTAGE CONTROLLED OSCILLATOR CIRCUIT - A voltage controlled oscillator (VCO) core for cancelling a supply noise is described. The VCO core includes an input node that receives the supply noise. The VCO core also includes a noise path coupled to the input node. The VCO core additionally includes a cancellation path coupled to the input node and the noise path. The cancellation path includes a programmable gain circuit coupled with a first terminal of a varactor. The supply noise passes through the programmable gain circuit to produce a cancellation noise. | 2014-03-13 |
20140070900 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING THE SAME, AND OSCILLATOR - An electronic device includes a substrate, a cavity part formed above the substrate with a functional device placed therein, a coating structure that defines the cavity part, and the coating structure has a first surrounding wall formed around the cavity part above the substrate, a second surrounding wall formed around the cavity part above the first surrounding wall, a coating layer that defines an upper surface of the cavity part, wherein the second surrounding wall is located inside the first surrounding wall in a plan view. | 2014-03-13 |
20140070901 | RESONATOR ELEMENT, RESONATOR, OSCILLATOR, ELECTRONIC APPARATUS, AND MOBILE OBJECT - A resonator element includes a base section, a pair of vibrating arms projecting toward the same side from the base section, and disposed side by side in a predetermined direction, a support arm projecting from the base section toward the same side as the pair of vibrating arms, disposed between the pair of vibrating arms, and having a recessed portion disposed on one principal surface, and a first electrically-conductive pad and a second electrically-conductive pad disposed side by side across the recessed portion. | 2014-03-13 |
20140070902 | BINARY BI-PHASE SHIFT MODULATOR - A binary bi-phase shift modulator having an input piezoelectric transducer and an output piezoelectric transducer connected in series between a radio frequency input and a radio frequency output. A fixed DC pole voltage having a first polarity is connected to one of the transducers. A DC switched pole voltage is connected to the other transducer which switches between the pole voltage of the first polarity arid a pole voltage of the opposite polarity m accordance with a dinar data signal The polarity of the radio frequency input relative to the radio frequency output varies as a function of the polarity of the DC switched pole voltage. | 2014-03-13 |
20140070903 | STRUCTURAL CAPACITOR, CONNECTOR AND COMMUNICATION APPARATUS USING THE CONNECTOR - The present disclosure discloses a structural capacitor, a connector comprising the structural capacitor and a communication apparatus using the connector. The structural capacitor comprises a rod and a holder. The rod comprises a first section and a second section connected with the first section, and the holder comprises a through hole. The first section and the second section are fitted into the through hole to accomplish the connection between the first section and the second section in an axial direction. The connector of the present disclosure features a simple structure, a convenient manufacturing process and a low cost. The communication apparatus of the present disclosure has advantages such as a simple manufacturing process, parameters that can be easily guaranteed, a low processing cost and a stable product performance. | 2014-03-13 |
20140070904 | METALIZED MOLDED PLASTIC COMPONENTS FOR MILLIMETER WAVE ELECTRONICS AND METHOD FOR MANUFACTURE - Waveguide components that have a high degree of performance accuracy over the temperature range of interest are provided. The components require no post-formation trimming steps, are light-weight, and dimensionally stable. In addition, a method for the manufacture of these millimeter wave components is provided. | 2014-03-13 |
20140070905 | WIDE RANGE CONTINUOUSLY TUNABLE CAPACITOR BANK - A wide range tunable capacitor bank is provided. The capacitor bank comprises a variable capacitor, the capacitance value of which is adjustable within a predetermined capacitance range defined by a minimum capacitance value and a maximum capacitance value. The capacitor bank further comprises one or more switched capacitors each electrically connected in circuit to the variable capacitor. The variable capacitor is configured to allow the capacitance value thereof to be adjusted within the predetermined capacitance range and the one or more switched capacitors are configured to be selectively actuated to permit continuous tuning of the capacitor bank over a second capacitance range that is greater than the predetermined capacitance range. Applications in which the capacitor bank may be implemented, and a method of fabricating an integrated system comprising a plurality of passive components, such as, for example, those of the capacitor bank and high quality factor inductors, are also provided. | 2014-03-13 |
20140070906 | ELASTIC WAVE DEVICE - An elastic wave device includes a piezoelectric substrate, a pair of reflectors disposed on the piezoelectric substrate along the propagation direction of an elastic wave, and first to fifth comb electrode pairs disposed in this order between the pair of reflectors. Ground comb electrodes of adjacent comb electrode pairs are connected by an even number of connection electrode fingers or by an odd number of connection electrode fingers. | 2014-03-13 |
20140070907 | GALVANIC ISOLATION INTERFACE FOR HIGH-SPEED DATA LINK FOR SPACECRAFT ELECTRONICS, AND METHOD OF USING SAME - Under one aspect of the present invention, a structure for providing galvanically isolated communication between first and second spacecraft electronic components includes a semi-insulating substrate; an input port disposed on the substrate and configured to receive a signal from the first spacecraft electronic component; a coupling structure disposed on the substrate, coupled to the input port so as to receive the signal, and configured to provide an isolated replica of the received signal as an output; a signal conditioner disposed on the substrate, coupled to the coupling structure so as to receive the isolated replica of the received signal, and configured to condition the isolated replica; and an output port disposed on the substrate, coupled to the signal conditioner so as to receive the conditioned isolated replica, and configured to provide the conditioned isolated replica to the second spacecraft electronic component. | 2014-03-13 |
20140070908 | STATIONARY CONTACT ARM ASSEMBLY FOR MOLDED CASE CIRCUIT BREAKER - A stationary contact arm assembly for a molded case circuit breaker includes a stationary contact arm having a terminal portion and a contact portion provided at both end portions thereof in the length direction, and an inclined extension portion provided between the contact portion and the terminal portion, a flat extension portion forming a space between the flat extension portion and a bottom surface of the contact potion, a bent portion formed from the flat extension portion to the terminal portion; a magnet assembly having a plurality of steel plates at least part of which is installed to be pushed into a space between the flat extension portion and contact portion in the stationary contact arm; and an elastic support plate having an elastic support portion installed on the flat extension portion of the stationary contact arm to support the magnet assembly. | 2014-03-13 |
20140070909 | ELECTRIC MAGNET DEVICE AND SWITCH PROVIDED THEREWITH - An aspect of the present invention provides an electric magnet device, in which a smooth movement of an armature is ensured and, even if a vibration or an impact is applied, an attraction state between a yoke and the armature is maintained to prevent a malfunction, and a switch provided therewith, where the electric magnet device includes: a coil adapted to insert through an armature and a yoke so as to attract surfaces of the yoke and the armature, which are opposed to each other, to receive a voltage, to excite for separating the surfaces of the yoke and the armature; the armature disposed on one end side of the coil; and the yoke disposed on the other end side of the coil and adapted to oscillate, such that an oscillation angle of the yoke is greater than that of the armature. | 2014-03-13 |
20140070910 | ELECTROMAGNETIC SWITCHING DEVICE - Disclosed is an electromagnetic switching device. The electromagnetic switching device includes a coil assembly provided therein with a coil for generating a magnetic force; and a yoke which surrounds a portion of an outer surface of the coil assembly and into which the coil assembly is inserted, wherein the yoke includes a yoke upper part which forms a top surface; yoke side parts which are provided at one side of the yoke upper part to block the magnetic force generated from the coil; and a connection part which is disposed between the yoke upper part and the yoke side parts such that the yoke upper part and the yoke side parts are integrally formed with each other. | 2014-03-13 |
20140070911 | Liquid MEMS Magnetic Component - A liquid micro-electro-mechanical system (MEMS) magnetic component includes a board, a channel, one or more windings, a magnetizing-doped droplet, and a droplet activating module. The channel is implemented or embedding in one or more layers of the board and the one or more windings are proximally positioned to the channel. The magnetizing-doped droplet is contained in the channel and is modified by the droplet activating module based on the control signal. By modifying the magnetizing-doped droplet with respect to the one or more windings changes an electromagnetic property of the liquid MEMS magnetic component. | 2014-03-13 |
20140070912 | ELECTRONIC COMPONENT - A laminated body is formed by stacking insulating layers to be formed into a rectangular parallelepiped shape. A linear conductor is stacked together with the insulating layers and connects end surfaces of the laminated body that are opposed to each other with respect to a first direction. Lengths of the end surfaces of the laminated body in a second direction, which is perpendicular to the stacking direction and the first direction, are equal to or smaller than the lengths of the end surfaces in the stacking direction. | 2014-03-13 |
20140070913 | System and Method for a Coreless Transformer - In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil. | 2014-03-13 |
20140070914 | MAGNETIC CORE, MAGNETIC COMPONENT AND DESIGN METHOD OF MAGNETIC CORE - A magnetic core including a winding core portion; and a flange portion provided on the axial end side of at least one of the winding core portion, wherein the flange portion is formed such that contour line OL | 2014-03-13 |
20140070915 | ELECTRONIC SUBSTRATE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - An electronic substrate including: a base substrate having an active face and a rear face; and a plurality of inductor elements formed on or above the active face, or formed on or above the rear face. | 2014-03-13 |
20140070916 | METAL POWDER AND ELECTRONIC COMPONENT - Metal powder has composite particles each coated with a Zn-based ferrite film not containing Ni. | 2014-03-13 |
20140070917 | APPARATUS AND METHOD FOR REGISTERING USERS AND MANAGING BIOMETRIC DATA THEREOF IN A VEHICLE - An apparatus for managing biometric information for a vehicle is provided. The apparatus comprising a first key, a second key, and a vehicle controller. The first and the second key each for transmitting an access signal to the vehicle. The vehicle controller for receiving the access signal from one of the first key and the second key to enable operation of the vehicle. The vehicle controller being operably coupled to a biometric database for storing first data indicative of an administrator and second data indicative of at least one of a member and biometric information for the member. The vehicle controller being configured to receive the access signal from each of the first key and the second key and to determine that a user is the administrator in response to receiving the access signal from each of the first key and the second key. | 2014-03-13 |
20140070918 | TRAIN CONTROL SYSTEM USING DRIVER'S BIOMETRIC INFORMATION - A train control system is disclosed, the system including a biometric information input device configured to receive a driver's biometric information through a sensor and to transmit the driver's biometric information to a cab signal device, wherein the cab signal device compares the biometric information of a driver intending to operate a train with a pre-registered driver's biometric information to verify a relevant driver, and verification of a driver intending to operate a train is realized by biometric information, and unauthorized person's access can be fundamentally avoided because biometric information cannot be copied or leaked due to person's biometric information being intrinsic. | 2014-03-13 |
20140070919 | User Identification and Location Determination in Control Applications - A system in which a portable electronic device communicates with an external device to determine a location. Upon determining its location, the portable electronic device transmits this information as well as identifying information to a control processor. The control processor controls one or more controllable devices according to the location and identifying information. The portable electronic device may determine the location via NFC tag or via one or more RF beacons transmitting information according to the Bluetooth 4.0 protocol. | 2014-03-13 |
20140070920 | METHOD FOR OPENING/CLOSING OF A SECURE HANDS-FREE ACCESS BY DETECTION OF MOVEMENT OF A LOWER MEMBER OF A USER - A reliable and secure activation of an access based on a detection of movement in a remote access system by providing a secure method for opening/closing of an access in hands-free access mode. The detection of movement relates to the displacement of a lower member of a user by a remote access system, this access system including at least two elements of detection which each emit a signal whose variations ( | 2014-03-13 |
20140070921 | NEAR FIELD COMMUNICATION METHOD, BETWEEN A MOBILE DEVICE AND A MOTOR VEHICLE AND CORRESPONDING DEVICE - A near field communication method between a vehicle and a mobile device includes the following steps:
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20140070922 | DOORBELL SYSTEM, APPARATUS, AND METHOD - Provided in various example embodiments is a system, apparatus, and method specially adapted to replace conventional doorbell systems in environments having access to wireless networks connected to the Internet, which provides wireless communication between the doorbell button unit and mobile devices without requiring additional or different power sources or wiring, aside from preexisting, conventional doorbell wiring. | 2014-03-13 |
20140070923 | Method for Preventing Unauthorized Diversion of NFC Tags - A method, system and apparatus for pairing authorized NFC enabled RFID devices with an intended object or product. The method, system and apparatus can include a primary RFID with a radio frequency identification chip, a coil antenna, a bridge and a substrate; an association of the at least primary RFID device with an object; an integration of a material into one of the at least primary RFID device and the object that provides the RFID device with a predetermined resonant frequency; and the detuning of one or more secondary communication devices located proximate the RFID device. | 2014-03-13 |
20140070924 | System and Method for Identifying a Power Tool - A system for identifying a type of a power tool, the system comprising: a power tool having an electric motor; and a usage attachment configured to couple to the power tool, the usage attachment having a vibration sensor that generates vibration data when the power tool vibrates, a memory that stores the vibration data generated by the vibration sensor, and an identification subsystem that receives the vibration data from the memory, and identifies the type of the power tool by comparing the received vibration data to predetermined vibration data of a known type of power tool. | 2014-03-13 |
20140070925 | SYSTEM AND METHOD OF CONTROLLING EXTERNAL APPARATUS CONNECTED WITH DEVICE - A method of controlling an external apparatus connected with a device includes: providing user input information used to determine a user's intention; identifying an external apparatus controllable by a device; providing apparatus information of the identified external apparatus; receiving control information about the external apparatus, which is generated based on the based on the user's intention and the apparatus information; and transmitting a control command to the external apparatus which is generated based on the received control information. | 2014-03-13 |
20140070926 | PORTABLE ELECTRONIC DEVICE BASED USER-DEFINABLE REMOTE-CONTROL INTERFACE SYSTEM AND OPERATING METHOD THEREOF - A portable electronic device based user-definable remote-control interface system and operating method thereof is disclosed. The system integrates remote control information of a variety of remotely controllable devices into one single interface allocation information map, which is stored in and can be shown on a portable electronic device. To operate the user-definable remote-control interface, first show the interface allocation information map on the portable electronic device and define at least an object and a button in the map. Then, search a network platform for a built-in remote-control code that corresponds to the button, or receive a learning signal from a remote controller of a device to be remotely controlled with the button to generate a learnt remote-control code corresponding to the button. Finally, store the built-in or the learnt remote-control code in a storage unit of the portable electronic device and relate the remote-control code to its corresponding button. | 2014-03-13 |
20140070927 | APPLIANCE REMOTE CONTROL ENABLE MODE - A system and method of remotely interacting with an appliance system are provided. A remote device, such as a computer, a smartphone, a tablet, etc., can initiate communications with an appliance through a communications network. When a remote enablement mode is initiated at the appliance, the remote device can interact with the appliance. For instance, the remote device can initiate operational cycles, activate notifications, perform diagnostic routines, etc. The remote enablement mode can be initiated by a user within the proximity of the appliance using a remote enable interface. The remote enable interface can be a mechanical device, an electromechanical device, and/or a selection through a user interface coupled to the appliance. | 2014-03-13 |