11th week of 2015 patent applcation highlights part 46 |
Patent application number | Title | Published |
20150072445 | LITHOGRAPHY APPARATUS AND METHOD OF MANUFACTURING ARTICLE - A lithography apparatus which performs writing on a substrate using a charged particle beam is provided. The apparatus comprises a plurality of column units each of which comprises a charged particle optical system, a plurality of stages each of which is movable while holding the substrate, and a controller. The controller moves the stages in synchronization with each other in a positional relationship corresponding to an arrangement of the column units, and performs writing on substrates held in the stages simultaneously. | 2015-03-12 |
20150072446 | METHODS FOR TAILORING ELECTRODE WORK FUNCTION USING INTERFACIAL MODIFIERS FOR USE IN ORGANIC ELECTRONICS - The present invention is directed to methods for tailoring the work function of electrodes in organic electronics using interfacial modifiers comprising functionalized semiconducting polymers and/or small molecules. | 2015-03-12 |
20150072447 | DETECTION OF DISASSEMBLY OF MULTI-DIE CHIP ASSEMBLIES - A multi-die chip assembly is described, the multi-die chip assembly including at least one detection apparatus which detects manipulations of the multi-die chip assembly, the detection apparatus including a distributed circuit including a circuit whose elements are distributed among those dies which include the elements of a local reference circuit, the distributed circuit including a free running clock, at least one local reference circuit disposed in at least one die of the multi-die chip assembly, each of the local reference circuits including a free running clock, and at least one non-volatile memory, in which is stored during manufacture of the multi-die chip assembly, an allowed range of a result of a function having at least two arguments for each reference circuit a value of the frequency of the local reference circuit as manufactured, and a value of the frequency of the distributed circuit as manufactured, at least one element of the plurality of memories being disposed in each die including the elements of the local reference circuit. Related methods, apparatus, and systems are also described. | 2015-03-12 |
20150072448 | METHOD FOR MANUFACTURING SiC SEMICONDUCTOR DEVICE - A method for manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) implanting an impurity into a surface layer of an SiC substrate at a concentration of 1×10 | 2015-03-12 |
20150072449 | METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING TOUCH PANEL - A manufacturing method of an organic light emitting diode (“OLED”) display includes: forming a contact pattern on a panel region of a surface of a board glass, where the board glass includes the panel region, and a peripheral area which surrounds the panel region; contacting the paper glass with a surface of the contact pattern corresponding to the panel region and the surface of the board glass corresponding to the peripheral area; adhering the surface of the board glass corresponding to the peripheral area to a surface of the paper glass; forming an organic light emitting element on the paper glass corresponding to the panel region; and separating the paper glass from the board glass by cutting the paper glass at a position corresponding to an end portion of the panel region adjacent to the peripheral area. | 2015-03-12 |
20150072450 | Semiconductor Wafer Bonding Incorporating Electrical and Optical Interconnects - Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods for bonding of semiconductor wafers incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers. | 2015-03-12 |
20150072451 | Method for Producing an Electronic Component and Electronic Component - A method for producing an electronic component and an electronic component, having barrier layers for the encapsulation of the component. The method involves providing a substrate ( | 2015-03-12 |
20150072452 | METHODS FOR MASKING AND APPLYING PROTECTIVE COATINGS TO ELECTRONIC ASSEMBLIES - One or more masks may be used to control the application of protective (e.g., moisture-resistant, etc.) coatings to one or more portions of various components of an electronic device during assembly of the electronic device. A method for applying a protective coating to an electronic device includes assembling two or more components of the electronic device with one another. A mask may then be applied to the resulting electronic assembly. The mask may shield selected portions of the electronic assembly, while other portions of the electronic assembly, i.e., those to which a protective coating is to be applied, may remain exposed through the mask. With the mask in place, application of a protective coating to portions of the electronic assembly exposed through the mask may commence. After application of the protective coating, the mask may be removed from the electronic assembly. Embodiments of masked electronic assemblies are also disclosed. | 2015-03-12 |
20150072453 | VAPOR DEPOSITION APPARATUS, VAPOR DEPOSITION METHOD AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS - A vapor deposition apparatus for depositing thin films on a substrate includes a supply unit including a plurality of linear supply members configured to supply at least one gas; and a nozzle unit including a plurality of nozzle members connected to the plurality of supply members and configured to supply the at least one gas toward the substrate, wherein two adjacent nozzle members of the plurality of nozzle members are connected to at least one common supply member of the plurality of supply members. | 2015-03-12 |
20150072454 | METHOD FOR MANUFACTURING DISPLAY PANEL - A method of manufacturing a display panel is provided. A release layer is formed on a support substrate. A thin film substrate is formed on the release layer and the support substrate. A pixel and an encapsulation member are formed on a part of the thin film substrate. The part of the thin film substrate is overlapped with the release layer. The part of the thin film substrate is separated from the support substrate. The release layer includes siloxane and polyimide silane. | 2015-03-12 |
20150072455 | METHOD FOR FABRICATING LIGHT EMITTING DIODE (LED) DICE WITH WAVELENGTH CONVERSION LAYERS - A method for fabricating light emitting diode (LED) dice includes the step of providing a wavelength conversion layer on a substrate on an adhesive layer configured to have reduced adhesiveness upon exposure to a physical energy, such as electromagnetic radiation or heat. The method also includes the step of exposing the adhesive layer on the substrate to the physical energy to reduce the adhesiveness of the adhesive layer, removing the wavelength conversion layer from the substrate, and attaching the wavelength conversion layer to the light emitting diode (LED) die. | 2015-03-12 |
20150072456 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer. A plurality of apertures penetrates the metal portion along the direction, each of the apertures viewed along the direction having equivalent circle diameters of not less than 10 nanometers and not more than 5 micrometers, and a Schottky barrier is provided between the second semiconductor layer and the metal portion. | 2015-03-12 |
20150072457 | METHOD FOR MANUFACTURING LIQUID CRYSTAL DEVICE - A manufacturing method of a liquid crystal display includes: forming a first alignment layer on a passivation layer and a pixel electrode to form a first display panel; forming a second alignment layer on a common electrode to form a second display panel; and combining the first and the second display panels, wherein formation of the first and second alignment layers includes spraying a first alignment mixture and second alignment mixture on, respectively, the first and second display panels using an inkjet head while moving the inkjet head across the first and second display panels to form a first alignment mixture layer and a second alignment mixture layer, and hardening the first and second alignment mixture layers, and spray progressing directions of the first and second alignment mixture are more than 7 degrees to less than 45 degrees with respect to the first substrate and the second substrate respectively. | 2015-03-12 |
20150072458 | INKJET DEVICE AND MANUFACTURING METHOD FOR ORGANIC EL DEVICE - An ink jet device includes: an ink jet head including a nozzle through which ink droplet is ejected by applying voltage to piezoelectric element; and an ejection control unit controlling ink droplet ejection amount by varying voltage, voltage waveform of the voltage includes: preliminary vibration wave form part for preliminary drive operation of pushing ink toward outer edge of the nozzle to the extent that the droplet is not ejected; and main vibration waveform part for main drive operation of ejecting the droplet through the nozzle after the preliminary drive operation, the ejection control unit performs the preliminary and main drive operations according to the preliminary vibration waveform part and the main vibration waveform part, respectively, and proportion of displacement amount X of the voltage for the preliminary drive operation to displacement amount Y of the voltage for the main drive operation is set to 20%≦X/Y≦40%. | 2015-03-12 |
20150072459 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body and an electrode. The stacked structure body has a first conductivity type first semiconductor layer including a nitride-based semiconductor, a second conductivity type second semiconductor layer including a nitride-based semiconductor, and a light emitting layer provided between the first and second semiconductor layers. The electrode has first, second and third metal layers. The first metal layer is provided on the second semiconductor layer and includes silver or silver alloy. The second metal layer is provided on the first metal layer and includes at least one element of platinum, palladium, rhodium, iridium, ruthenium, osmium. The third metal layer is provided on the second metal layer. A thickness of the third metal layer along a direction from the first toward the second semiconductor layer is equal to or greater than a thickness of the second metal layer. | 2015-03-12 |
20150072460 | DEVICE AND METHOD FOR PRECIPITATING A LAYER ON A SUBSTRATE - The invention relates to a device for depositing a layer made of at least two components on an object, with a deposition chamber for disposing the object, at least one source with material to be deposited, as well as at least one device for controlling the deposition process, implemented such that the concentration of at least one component of the material to be deposited can be modified in its gas phase prior to deposition on the substrate by selective binding of a specified quantity of the at least one component, wherein the selectively bound quantity of the at least one component can be controlled by modifying at least one control parameter that is actively coupled to a binding rate or the component. It further relates to a device for depositing a layer made of at least two components on an object, wherein a device for controlling the deposition process has at least one gettering element made of a reactive material, wherein the reactive material includes copper and/or molybdenum. It further relates to a method for depositing a layer made of at least two components on an object, wherein a selectively bound quantity of at least one component is controlled by modifying a binding rate of a device for controlling the deposition process. | 2015-03-12 |
20150072461 | ION IMPLANT SYSTEM HAVING GRID ASSEMBLY - An ion implantation system having a grid assembly. The system includes a plasma source configured to provide plasma in a plasma region; a first grid plate having a plurality of apertures configured to allow ions from the plasma region to pass therethrough, wherein the first grid plate is configured to be biased by a power supply; a second grid plate having a plurality of apertures configured to allow the ions to pass therethrough subsequent to the ions passing through the first grid plate, wherein the second grid plate is configured to be biased by a power supply; and a substrate holder configured to support a substrate in a position where the substrate is implanted with the ions subsequent to the ions passing through the second grid plate. | 2015-03-12 |
20150072462 | TANDEM NANOFILM PHOTOVOLTAIC CELLS JOINED BY WAFER BONDING - An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 μm to about 10 μm. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means. | 2015-03-12 |
20150072463 | Methods Of Printing Solar Cell Contacts - Silicon solar cells and contacts thereof are printed in at least a two stage printing process where the busbars and fingerlines may be printed separately. A reduction in silver content in busbars and fingerlines through use of the techniques of the invention have been realized, including the use of certain base metals, while maintaining low contact resistance similar to silver pastes. | 2015-03-12 |
20150072464 | METHOD AND STRUCTURE FOR THIN FILM TANDEM PHOTOVOLTAIC CELL - A tandem photovoltaic cell. The tandem photovoltaic cell includes a bifacial top cell and a bottom cell. The top bifacial cell includes a top first transparent conductive oxide material. A top window material underlies the top first transparent conductive oxide material. A first interface region is disposed between the top window material and the top first transparent conductive oxide material. The first interface region is substantially free from one or more entities from the top first transparent conductive oxide material diffused into the top window material. A top absorber material comprising a copper species, an indium species, and a sulfur species underlies the top window material. A top second transparent conductive oxide material underlies the top absorber material. A second interface region is disposed between the top second transparent conductive oxide material and the top absorber material. The bottom cell includes a bottom first transparent conductive oxide material. A bottom window material underlies the first bottom transparent conductive oxide material. A bottom absorber material underlies the bottom window material. A bottom electrode material underlies the bottom absorber material. The tandem photovoltaic cell further includes a coupling material free from a parasitic junction between the top cell and the bottom cell. | 2015-03-12 |
20150072465 | ORGANIC-INORGANIC HYBRID JUNCTION DEVICE USING REDOX REACTION AND ORGANIC PHOTOVOLTAIC CELL OF USING THE SAME - Provided are an organic-inorganic hybrid junction device in which organic and inorganic materials are connected by junction, and a depletion layer is formed at a junction interface, and an organic photovoltaic cell using the same. A basic metal oxide solution is applied to a top surface of a P-doped organic layer. The basic metal oxide solution has N-type characteristics. An oxidation-reduction reaction occurs in response to the application of the basic metal oxide solution at a junction interface of the organic layer, and the metal oxide layer is simultaneously gelated. A free charge is removed from a surface region of the P-doped organic layer by the oxidation-reduction reaction at the interface, which is converted into a depletion region. According to the introduction of the depletion region, P-N junction occurs, and thus the device has a diode characteristic in an electrical aspect. Also, an organic photovoltaic cell including the organic layer, the depletion layer and the metal oxide layer is fabricated. | 2015-03-12 |
20150072466 | Doping An Absorber Layer Of A Photovoltaic Device Via Diffusion From A Window Layer - Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer on a transparent substrate, where the window layer includes at least one dopant (e.g., copper). A p-n heterojunction can be formed on the window layer, with the p-n heterojunction including a photovoltaic material (e.g., cadmium telluride) in an absorber layer. The dopant can then be diffused from the window layer into the absorber layer (e.g., via annealing). | 2015-03-12 |
20150072467 | SHALLOW JUNCTION PHOTOVOLTAIC DEVICES - A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 10 | 2015-03-12 |
20150072468 | METHOD FOR FABRICATING SILICON-DOPED OR BORON-DOPED ALUMINUM ELECTRODE - A method for fabricating a silicon-doped or boron-doped aluminum electrode is revealed. Aluminum target or aluminum paste prepared by selectively doped with silicon and/or boron is arranged at a silicon wafer with a passivation layer by physical deposition or screen printing. Then the doped aluminum layer is melted in linear or dot pattern to pass through the passivation layer and contact with the silicon wafer. Thus contact resistance between an aluminum back electrode and the silicon wafer of crystalline silicon solar cells is reduced and acceptor concentration on a surface layer of the silicon wafer is increased. Therefore the process speed is faster and the energy conversion efficiency of the solar cell is improved. | 2015-03-12 |
20150072469 | SODIUM DOPED THIN FILM CIGS/CIGSS ABSORBER FOR HIGH EFFICIENCY PHOTOVOLTAIC DEVICES AND RELATED METHODS - A method of processing a thin-film absorber material with enhanced photovoltaic efficiency. The method includes providing a soda-lime glass substrate having a surface region and forming a barrier material overlying the surface region, followed by formation of a stack structure including a first thickness of a first precursor, a second thickness of a second precursor, and a third thickness of a third precursor. The first thickness of the first precursor is sputtered with a first target device including a first mixture of copper, gallium, and a first sodium species. The method further includes subjecting the soda-lime glass substrate having the stack structure in a thermal treatment process with at least H | 2015-03-12 |
20150072470 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced. | 2015-03-12 |
20150072471 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer. | 2015-03-12 |
20150072472 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. | 2015-03-12 |
20150072473 | DIE ATTACHMENT APPARATUS AND METHOD UTILIZING ACTIVATED FORMING GAS - A die attachment apparatus for attaching a semiconductor die onto a substrate having a metallic surface comprises a material dispensing station for dispensing a bonding material onto the substrate and a die attachment station for placing the semiconductor die onto the bonding material which has been dispensed onto the substrate. An activating gas generator positioned before the die attachment station introduces activated forming gas onto the substrate in order to reduce oxides on the substrate. | 2015-03-12 |
20150072474 | BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed. | 2015-03-12 |
20150072475 | METHOD OF MANUFACTURING A DISPLAY DEVICE COMPRISING FIRST AND SECOND POLARIZING PLATE AND PHASE DIFFERENCE PLATE COMBINATIONS AND A STEP OF SIMULTANEOUSLY POLISHING A SECOND SUBSTRATE AND A SEMICONDUCTOR CHIP TO HAVE THE SAME THICKNESS AS EACH OTHER - A display device including: a first substrate with a pixel switch and drivers mounted thereon; a second substrate disposed in facing relation to the first substrate; a material layer held between the first substrate and the second substrate and having peripheral edges sealed by a seal member, the material layer having an electrooptical effect; and a semiconductor chip mounted as a COG component on the first substrate, the semiconductor chip having a control system configured to control the drivers; wherein the semiconductor chip having a thickness equal to the total thickness of the seal member and the second substrate or larger than the thickness of the seal member and smaller than the total thickness. | 2015-03-12 |
20150072476 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 2015-03-12 |
20150072477 | ADHESIVE SHEET FOR PRODUCTION OF SEMICONDUCTOR DEVICE WITH BUMP ELECTRODE, AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - An adhesive sheet for production of a semiconductor device with bump electrode, including a soft film and an alkali-soluble adhesive film formed on the soft film is capable of exposing the bump electrode without imparting damage to the bump electrode, and then wet etching of an adhesive on bump tops using an aqueous alkali solution makes it possible to put into a state where no adhesive exists on the bump tops, thus enabling the production of a semiconductor device which is excellent in connection reliability after flip chip packaging. | 2015-03-12 |
20150072478 | DIVINYLARENE DIOXIDE COMPOSITIONS HAVING REDUCED VOLATILITY - Compositions containing a divinylarene dioxide and a hydroxy-substituted dioxide compound and having relatively low viscosity and reduced volatility are used as underfills in the manufacture of electronic assemblies. | 2015-03-12 |
20150072479 | ABLATION METHOD AND RECIPE FOR WAFER LEVEL UNDERFILL MATERIAL PATTERNING AND REMOVAL - Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material. | 2015-03-12 |
20150072480 | IMPLANT REGION DEFINITION - Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage. | 2015-03-12 |
20150072481 | SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths. | 2015-03-12 |
20150072482 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR - A method of manufacturing a thin-film transistor is provided, including preparing ink including a solution in which a graphene oxide, a reduced graphene oxide, or a combination thereof is dispersed, forming the ink on a substrate in the form of a pattern, and forming a source electrode and a drain electrode that are positioned at edges of the pattern and a semiconductor channel positioned between the electrodes by a coffee-ring effect in the ink by using the graphene oxide, the reduced graphene oxide, or the combination thereof within the formed pattern. | 2015-03-12 |
20150072483 | Thin Film Transistor Substrate and Method for Manufacturing the Same and Organic Light Emitting Device Using the Same - Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode. | 2015-03-12 |
20150072484 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side. | 2015-03-12 |
20150072485 | MANUFACTURING METHOD FOR SILICON CARBIDE SEMICONDUCTOR DEVICE - In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region. | 2015-03-12 |
20150072486 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed. | 2015-03-12 |
20150072487 | Semiconductor Device and Method of Forming the Same - A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film. | 2015-03-12 |
20150072488 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 2015-03-12 |
20150072489 | NON-VOLATILE MEMORY (NVM) CELL AND HIGH-K AND METAL GATE TRANSISTOR INTEGRATION - A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region. | 2015-03-12 |
20150072490 | VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION - Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length. | 2015-03-12 |
20150072491 | 3-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another. | 2015-03-12 |
20150072492 | METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed. | 2015-03-12 |
20150072493 | METHOD OF FORMING TRENCH GATE MOSFET - A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench. | 2015-03-12 |
20150072494 | Bi-Layer Metal Deposition in Silicide Formation - A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy. The method further includes performing a second sputtering to form a second metal film over and contacting the first metal film, wherein the first and the second metal films includes a same metal. The second sputtering is performed using a second ion energy lower than the first ion energy. An annealing is performed to react the first and the second metal films with the semiconductor region to form a metal silicide. | 2015-03-12 |
20150072495 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 2015-03-12 |
20150072496 | METHOD OF MAKING AN INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE - A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region. | 2015-03-12 |
20150072497 | SEMICONDUCTOR MEMORY DEVICE HAVING LOWERED BIT LINE RESISTANCE - A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes. | 2015-03-12 |
20150072498 | NON-PLANAR III-V FIELD EFFECT TRANSISTORS WITH CONFORMAL METAL GATE ELECTRODE & NITROGEN DOPING OF GATE DIELECTRIC INTERFACE - A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface. | 2015-03-12 |
20150072499 | MEMORY ELEMENT WITH ION SOURCE LAYER AND MEMORY DEVICE - A method of making memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer. | 2015-03-12 |
20150072500 | METHOD FOR FABRICATING RESISTIVE RANDOM ACCESS MEMORY - A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes. | 2015-03-12 |
20150072501 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal. | 2015-03-12 |
20150072502 | SEMICONDUCTOR DEVICE INCLUDING BURIED GATE, MODULE AND SYSTEM, AND METHOD FOR MANUFACTURING - An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device. | 2015-03-12 |
20150072503 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes dry-etching a member containing silicon in a first pressure range equal to or more than a first pressure or in a second pressure range equal to or less than a second pressure, wherein the first pressure is obtained by multiplying a saturated pressure by 0.85, the saturated pressure is defined as a pressure under which an etching rate is one of a maximum value or a value obtained by multiplying the maximum value by a predetermined coefficient, and the etching rate is a half value of the maximum value under the second pressure. | 2015-03-12 |
20150072504 | HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS - According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing. | 2015-03-12 |
20150072505 | METHOD AND APPARATUS OF HOLDING A DEVICE - Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. | 2015-03-12 |
20150072506 | WAFER PROCESSING METHOD - A wafer is divided into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The wafer has a substrate, a functional layer formed on the front side of the substrate, and an SiO | 2015-03-12 |
20150072507 | DEVICE WAFER PROCESSING METHOD - A device wafer has a plurality of devices individually formed in a plurality of separate regions on the front side of the wafer, the separate regions being defined by a plurality of crossing division lines. The wafer is processed by imaging the front side of the wafer to detect and store a target pattern, holding the front side of the wafer and grinding the back side of the wafer to thereby reduce the thickness to a predetermined thickness, imaging the front side of the wafer and next positioning the wafer with respect to a ring frame according to the target pattern stored so that the wafer is oriented to a predetermined direction, and attaching an adhesive tape to the back side of the wafer to thereby mount the wafer through the adhesive tape to the ring frame. | 2015-03-12 |
20150072508 | DIRECTIONAL SIO2 ETCH USING PLASMA PRE-TREATMENT AND HIGH-TEMPERATURE ETCHANT DEPOSITION - Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products. | 2015-03-12 |
20150072509 | PECVD MICROCRYSTALLINE SILICON GERMANIUM (SIGE) - Embodiments of the present invention generally relate to methods for forming a SiGe layer. In one embodiment, a seed SiGe layer is first formed using plasma enhanced chemical vapor deposition (PECVD), and a bulk SiGe layer is formed directly on the PECVD seed layer also using PECVD. The processing temperature for both seed and bulk SiGe layers is less than 450 degrees Celsius. | 2015-03-12 |
20150072510 | METHOD FOR FORMING ULTRA-SHALLOW BORON DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment. | 2015-03-12 |
20150072511 | Oxidation and Etching Post Metal Gate CMP - A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen. | 2015-03-12 |
20150072512 | METHODS AND APPARATUSES INCLUDING STRINGS OF MEMORY CELLS FORMED ALONG LEVELS OF SEMICONDUCTOR MATERIAL - Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed. | 2015-03-12 |
20150072513 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. An barrier film is formed over sidewalls of the bit line, and a storage node contact plug is obtained by filling a space between the bit lines so that an upper portion of the storage node contact is wider than a lower portion of the storage node contact. As a result, the process can be simplified and a short between the storage node contact plug and the bit line can be prevented. | 2015-03-12 |
20150072514 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates. | 2015-03-12 |
20150072515 | LASER ABLATION METHOD AND RECIPE FOR SACRIFICIAL MATERIAL PATTERNING AND REMOVAL - A method including introducing a passivation material over contact pads on a surface of an integrated circuit substrate; patterning a sacrificial material on the passivation material to define openings in the sacrificial material to the contact pads; introducing solder to the contact pads; and after introducing the solder, removing the sacrificial material with the proviso that, where the sacrificial material is a photosensitive material, removing comprises using temporally coherent electromagnetic radiation. A method including introducing a passivation material over contact pads; exposing the contact pads; patterning a photosensitive material on the passivation material; introducing solder to the contact pads; and after introducing the solder, removing the photosensitive material using temporally coherent electromagnetic radiation. A method including introducing a passivation material over contact pads; exposing the contact pads; patterning a non-photosensitive material on the passivation material; introducing solder to the contact pads; and after introducing the solder, removing the non-photosensitive material. | 2015-03-12 |
20150072516 | METHOD FOR REMOVING ELECTROPLATED METAL FACETS AND REUSING A BARRIER LAYER WITHOUT CHEMICAL MECHANICAL POLISHING - A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer. | 2015-03-12 |
20150072517 | FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE - A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability. | 2015-03-12 |
20150072518 | BUMP STRUCTURES IN SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - The bump structure includes a metal pattern disposed on an electrode pad to have a vertical sidewall and a recessed region surrounded by the vertical sidewalls, a metal post including a lower portion inserted into the recessed region and a protruded portion upwardly extending from the lower portion, and a passivation spacer on a sidewall of the metal post. The metal post is electrically connected to the electrode pad. | 2015-03-12 |
20150072519 | Metal and Via Definition Scheme - A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer. | 2015-03-12 |
20150072520 | VIA NETWORK STRUCTURES AND METHOD THEREFOR - A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact. | 2015-03-12 |
20150072521 | MICROSTRUCTURE MANUFACTURING METHOD - A microstructure manufacturing method includes forming a first insulating film on an Si substrate, exposing an Si surface by removing a part of the first insulating film, forming a recessed portion by etching the Si substrate from the exposed Si surface, forming a second insulating film on a sidewall and a bottom of the recessed portion, forming an Si exposed surface by removing at least a part of the second insulating film formed on the bottom of the recessed portion, and filling the recessed portion with a metal from the Si exposed surface by electrolytic plating. | 2015-03-12 |
20150072522 | ABRASIVE PARTICLE, POLISHING SLURRY, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are an abrasive particle including auxiliary particles formed on a surface of a mother particle, a polishing slurry prepared by mixing the abrasive particles with a polishing accelerating agent and a pH adjusting agent, and a method of manufacturing a semiconductor device in which an insulating layer is polished by the polishing slurry while using a conductive layer as a polishing stop layer. | 2015-03-12 |
20150072523 | Methods of Forming Diodes - Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer. | 2015-03-12 |
20150072524 | METHOD OF REPAIRING DEFECT AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in a method of repairing a defect on a template substrate for imprint lithography using a charged particle beam, a drift correction mark to correct drift of the charged particle beam is formed on the template substrate. The defect on the template substrate is repaired while correcting the drift of the charged particle beam with reference to the drift correction mark. The drift correction mark is removed. | 2015-03-12 |
20150072525 | POLISHING LIQUID AND POLISHING METHOD - A method for chemical mechanical polishing of a body to be polished in a planarization process for manufacturing of a semiconductor integrated circuit. The body to be polished including at least a first layer containing polysilicon or modified polysilicon and a second layer containing at least one selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxynitride. The method including supplying a polishing liquid to a polishing pad on a polishing platen, rotating the polishing platen, and thereby causing relative motion of the polishing pad and a surface to be polished of the body to be polished while in contact with each other for carrying out selective polishing of the second layer with respect to the first layer, and the polishing liquid including a colloidal silica particles, an organic acid, and an anionic surfactant. | 2015-03-12 |
20150072526 | METHODS FOR REMOVING CARBON CONTAINING FILMS - Embodiments of methods for removing carbon-containing films are provided herein. In some embodiments, a method for removing a carbon-containing layer includes providing an ammonia containing process gas to a process chamber having a substrate with a silicon oxide layer disposed atop the substrate and a carbon-containing layer disposed atop the silicon oxide layer disposed in the process chamber; providing RF power to the process chamber to ignite the ammonia containing process gas to form a plasma; and exposing the substrate to NH and/or NH | 2015-03-12 |
20150072527 | METHOD FOR PATTERNING A PLURALITY OF FEATURES FOR FIN-LIKE FIELD-EFFECT TRANSISTOR (FINFET) DEVICES - Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer. | 2015-03-12 |
20150072528 | Hard Mask Edge Cover Scheme - A method includes forming at least one trench in a dielectric layer using a hard mask. An edge cover layer is formed over the hard mask. The at least one trench is filled with a metal layer. | 2015-03-12 |
20150072529 | METHOD OF FORMING VIA HOLE - The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area. | 2015-03-12 |
20150072530 | METHODS FOR ETCHING MATERIALS USING SYNCHRONIZED RF PULSES - Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points. | 2015-03-12 |
20150072531 | METHOD FOR FORMING LAYOUT PATTERN - A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate. | 2015-03-12 |
20150072532 | PATTERNING METHOD - A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask. | 2015-03-12 |
20150072533 | Etching Method, Etching Apparatus, and Storage Medium - Provided is a method of etching a silicon oxide film, which includes supplying a mixture gas of a halogen element-containing gas and a basicity gas onto a surface of the silicon oxide film; modifying the silicon oxide film to produce a reaction product; and heating the reaction product to remove the reaction product. Modifying the silicon oxide film and heating the reaction product are performed using one chamber. In heating the reaction product, the reaction product is selectively heated by a heating unit. | 2015-03-12 |
20150072534 | ETCHING METHOD OF MULTILAYER FILM - A plasma processing apparatus for performing a plasma process on a substrate includes: a mounting table configured to mount thereon the substrate; an electromagnet including a core member and a plurality of coils; a current source connected to both ends of the coils for supplying currents to the coils; and a control unit configured to control the current source to start or stop and to control a current value of the current source. The core member is made of a magnetic material and has a structure including a column-shaped member, multiple cylindrical members, and a base member. The plurality of coils are accommodated in grooves and wound around an outer peripheral surface of the column-shaped member and the cylindrical members, and the grooves are formed between the column-shaped member and one of the cylindrical members and between the cylindrical members. | 2015-03-12 |
20150072535 | INSULATING FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm | 2015-03-12 |
20150072536 | PATTERN FORMING METHOD, PATTERN FORMING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - A photoresist pattern used for forming a pattern of a block copolymer is formed on a substrate, and then an acid solution is supplied and an alkaline solution is further supplied to the photoresist pattern so as to slim and smooth the photoresist pattern. A block copolymer solution is applied to the substrate on which the smoothed photoresist pattern has been formed, to form a film of the block copolymer, and the film is heated. | 2015-03-12 |
20150072537 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: forming a thin film containing silicon, oxygen and carbon or a thin film containing silicon, oxygen, carbon and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a precursor gas serving as a silicon source and a carbon source or a precursor gas serving as a silicon source but no carbon source, and a first catalyst gas to the substrate; supplying an oxidizing gas and a second catalyst gas to the substrate; and supplying a modifying gas containing at least one selected from the group consisting of carbon and nitrogen to the substrate | 2015-03-12 |
20150072538 | METHOD AND APPARATUS FOR REMOTE PLASMA TREATMENT FOR REDUCING METAL OXIDES ON A METAL SEED LAYER - Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal oxide surface on a substrate is reduced. A remote plasma apparatus can treat the metal oxide surface as well as cool, load/unload, and move the substrate within a single standalone apparatus. The remote plasma apparatus includes a processing chamber and a controller configured to provide a substrate having a metal seed layer in a processing chamber, move the substrate towards a substrate support in the processing chamber, form a remote plasma of a reducing gas species, expose a metal seed layer of the substrate to the remote plasma, and expose the substrate to a cooling gas. In some embodiments, the remote plasma apparatus is part of an electroplating apparatus. | 2015-03-12 |
20150072539 | USB INTERFACE AND TERMINAL - A USB interface and a terminal comprising the USB interface. The USB interface comprises a USB jack ( | 2015-03-12 |
20150072540 | APPARATUS FOR HOUSING PLUG-IN UNIT AND PLUG-IN UNIT - An apparatus for housing a plug-in unit that includes at least one movable piece including a permanent magnet in a portion of a casing. The apparatus includes a plurality of slots, each of the plurality of slots houses the plug-in unit; a connector provided in an inner or innermost portion of the slot and electrically connects with the plug-in unit; an advancement blocking member disposed within the slot and blocks connection of the plug-in unit to the connector by coming into contact with the movable piece; an electromagnet that generates a magnetic field applied to the permanent magnet of the plug-in unit; and a control device that controls the electromagnet so as to generate a magnetic field having a predetermined polarity that moves the movable piece of the plug-in unit to a position in which the movable piece does not come into contact with the advancement blocking member. | 2015-03-12 |
20150072541 | CONNECTOR DEVICE FOR BUILDING INTEGRATED PHOTOVOLTAIC DEVICE - The present invention is premised upon a connector device and method that can more easily electrically connect a plurality of PV devices or photovoltaic system components and/or locate these devices/components upon a building structure. It also may optionally provide some additional sub-components (e.g. at least one bypass diode and/or an indicator means) and may enhance the serviceability of the device. | 2015-03-12 |
20150072542 | Board Connector - A board connector includes: a connector body housing a terminal fitting; and a connector receiving member attached to a circuit board and engagingly locking a tip end surface of the connector body in a state where the tip end surface is butted against a surface of the circuit board. The connector body includes: an inner housing which engagingly locks the terminal fitting so that a tip end surface of the terminal fitting is projected from the tip end surface of the connector body; an outer housing which supports the inner housing so that the inner housing is slidable in a fitting direction; and a housing urging spring which urges the inner housing. The tip end surface of the terminal fitting is pressingly contacted with the contact pattern, thereby causing the terminal fitting to be electrically connected to the contact pattern. | 2015-03-12 |
20150072543 | STEPPED SPRING CONTACT - In an embodiment, a stepped spring contact may have a first portion, a transition portion, and a second portion. The first portion may include a plurality of windings whose pitch may vary. The second portion may include a plurality of windings that are closely wound. A pitch of the windings contained in the second portion may be, for example, constant. The transition portion may include a winding that may make mechanical and electrical contact with a first electrical conductor (e.g., a pad contained on a printed circuit board (PCB)). The first portion may include a tip. The tip may be, for example, flat shaped or conically shaped. The tip may make electrical contact with a second electrical conductor (e.g., a terminal connector). In operation, the stepped spring contact may provide electrical continuity between the first electrical conductor and the second electrical conductor. | 2015-03-12 |
20150072544 | COAXIAL CONNECTOR - A coaxial connector for a mating device to be inserted therein, includes an insulating body having a sustaining portion, a static terminal having a first contact portion, and a movable terminal having a second contact portion for contacting the first contact portion. The sustaining portion and an object below have a gap therebetween. The static terminal and the movable terminal are fixed to the insulating body. An elastic arm is formed by extending from the second contact portion. The sustaining portion engages the elastic arm. When the mating device is inserted into the coaxial connector, the mating device presses the elastic arm downwards, the second contact portion moves downwards to be separated from the first contact portion, and the elastic arm drives the sustaining portion to move downwards together, such that the sustaining portion butts against the object below to prevent the movable terminal from moving downwards excessively. | 2015-03-12 |