11th week of 2015 patent applcation highlights part 22 |
Patent application number | Title | Published |
20150070044 | RADIO FREQUENCY CHARACTERISTICS MEASUREMENT JIG DEVICE - A radio frequency characteristics measurement jig device includes: a ground conductor part; a first coplanar line; a connection substrate; and a holding part. The first coplanar line includes a first dielectric layer, a first center conductive layer and first ground conductive layers. The connection substrate includes a second dielectric layer, a second center conductive layer, second ground conductive layers, and a third ground conductive layer. The holding part is configured to press the connection substrate to the first coplanar line and the signal terminal so as to allow electrical continuity between the first center conductive layer and the second center conductive layer on the first region, to allow electrical continuity between the first ground conductive layer and the second ground conductive layer, and to allow electrical continuity between the second center conductive layer on the second region and the signal terminal. | 2015-03-12 |
20150070045 | ULTRA FAST TRANSISTOR THRESHOLD VOLTAGE EXTRACTION - A method for performing a semiconductor parametric test comprising performing a full voltage sweep for a first component on a first semiconductor wafer to determine a first value of an electrical characterization parameter for the first component, wherein the full voltage sweep comprises a range between about a minimum input voltage level of the first component and about a maximum input voltage level of the first component, determining a smart sensing window (SSW) for a plurality of subsequent components on the first semiconductor wafer according to the first value, wherein the SSW comprises a range comprising a portion of the full voltage sweep range, performing a partial voltage sweep in the SSW for each of the subsequent components to determine a second value of the electrical characterization parameter for each of the subsequent semiconductor components, and adapting the SSW for at least some of the subsequent components. | 2015-03-12 |
20150070046 | SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING THE SAME - According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire. | 2015-03-12 |
20150070047 | DIAGNOSTICS FOR SYSTEMS INCLUDING VARIABLE FREQUENCY MOTOR DRIVES - One embodiment is a diagnostic method for a system including setting a first diagnostic code based upon a condition of a DC bus of a variable frequency drive during a first drive state, setting at least one additional diagnostic code based upon a condition of at least one motor phase current during a second drive state, outputting first diagnostic information indicating a malfunction of the variable frequency drive if the first diagnostic code indicates a first error, and outputting second diagnostic information indicating a malfunction of a motor or a connector coupling the motor and the drive if the at least one additional diagnostic code indicates a second error. | 2015-03-12 |
20150070048 | VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES - Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit. | 2015-03-12 |
20150070049 | APPARATUS AND METHODS FOR LEAKAGE CURRENT REDUCTION IN INTEGRATED CIRCUITS - This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit. | 2015-03-12 |
20150070050 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages. | 2015-03-12 |
20150070051 | HIGH SPEED PHASE SELECTOR WITH A GLITCHLESS OUTPUT USED IN PHASE LOCKED LOOP APPLICATIONS - A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown. | 2015-03-12 |
20150070052 | REFERENCE VOLTAGE GENERATOR FOR SINGLE-ENDED COMMUNICATION SYSTEMS - An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system. | 2015-03-12 |
20150070053 | INTERNAL VOLTAGE GENERATION CIRCUITS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - An internal voltage generation circuit including a voltage generator and a detection voltage generator. The voltage generator generates a temperature reference voltage signal whose level depends on an internal temperature, a division reference voltage signal whose level is constant regardless of the internal temperature, and a selection reference voltage signal obtained by detecting a level of an internal voltage signal. The detection voltage generator compares the division reference voltage signal and the selection reference voltage signal in response to the temperature reference voltage signal to generate a detection voltage signal controlling a pumping operation of the internal voltage signal. | 2015-03-12 |
20150070054 | SYNCHRONIZATION SYSTEM AND FREQUENCY DIVIDER CIRCUIT - In a synchronization system, a frequency divider circuit generates a divided clock by dividing a reference clock in a first division ratio. First and second devices operate in synchronization with the reference clock and the divided clock. A division ratio detection circuit, for each period of the divided clock, detects a division ratio of the divided clock based on a count value counted in synchronization with the reference clock and output the division ratio as a second division ratio. A decoder generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio. The first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal. | 2015-03-12 |
20150070055 | RECEIVER - A received is disclosed that is capable of improving reception sensitivity while avoiding an increase in circuit scale. The receiver includes: a multi-phase local oscillation signal generating section that generates a plurality of local oscillation signals of different phases; a phase selection signal generating section that generates a phase selection signal used to select a baseband signal of a predetermined phase based on a detection result of a reception level of a high-frequency signal; and a frequency converter that frequency-converts the high-frequency signal based on the plurality of local oscillation signals, that generates a plurality of baseband signals of different phases, and that selects a baseband signal from among the plurality of baseband signals based on the phase selection signal. | 2015-03-12 |
20150070056 | APPARATUSES AND RELATED METHODS FOR STAGGERING POWER-UP OF A STACK OF SEMICONDUCTOR DIES - An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time. | 2015-03-12 |
20150070057 | Multiple Power Domain Electronic Device and Related Method - An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit. | 2015-03-12 |
20150070058 | Logarithmic Detector Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion - A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency. | 2015-03-12 |
20150070059 | PHASE LOCKED LOOP CIRCUIT, PHASE LOCKED LOOP MODULE, AND PHASE LOCKED LOOP METHOD - Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply. | 2015-03-12 |
20150070060 | MULTI-OUTPUT PHASE DETECTOR - Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. | 2015-03-12 |
20150070061 | DUAL-PORT NEGATIVE LEVEL SENSITIVE RESET PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 2015-03-12 |
20150070062 | Filtered Radiation Hardened Flip Flop with Reduced Power Consumption - A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters. | 2015-03-12 |
20150070063 | LOW POWER CLOCK GATED FLIP-FLOPS - A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output. | 2015-03-12 |
20150070064 | INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE - An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop. | 2015-03-12 |
20150070065 | SIGNAL-ALIGNMENT CIRCUITRY AND METHODS - Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship. | 2015-03-12 |
20150070066 | CIRCUITRY USEFUL FOR CLOCK GENERATION AND DISTRIBUTION - An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase. | 2015-03-12 |
20150070067 | 3D CLOCK DISTRIBUTION CIRCUITS AND METHODS - An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via. | 2015-03-12 |
20150070068 | INTERNAL VOLTAGE GENERATOR AND METHOD OF GENERATING INTERNAL VOLTAGE - An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock. | 2015-03-12 |
20150070069 | LEVEL SHIFTER WITH BUILT-IN LOGIC FUNCTION FOR REDUCED DELAY - A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs. | 2015-03-12 |
20150070070 | Multiple Voltage Input Buffer and Related Method - A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad. The switch has an input terminal electrically connected to an input terminal of the first level shifter, and an output terminal electrically connected to an output terminal of the first level shifter. The control circuit is electrically connected to a control terminal of the switch. | 2015-03-12 |
20150070071 | HARMONIC REJECTION MIXER ARRANGEMENT - It is disclosed a mixer arrangement for complex signal mixing comprising a first harmonic rejection mixer, and a second harmonic rejection mixer. Each of the harmonic rejection mixers comprises mixer unit cells wherein each mixer unit cell comprises a differential input, transconductance elements corresponding to the differential input, and a switching network arranged to switch signals from the transconductance elements to a differential output, and the first and the second harmonic rejection mixers have mutual quadrature phase relationship. The first and the second rejection mixer share a plurality of mixer unit cell, each comprising an input for receiving a signal to be mixed, an input for receiving control signals derived from a local oscillator signal, and one output for each of the first and second harmonic rejection mixers. A radio circuit comprising such a mixer arrangement and a communication apparatus comprising such a radio circuit are also disclosed. | 2015-03-12 |
20150070072 | HARMONIC MIXER - A harmonic mixer includes first through third field effect transistors. A gate electrode of the first field effect transistor is supplied with a positive-phase signal of a first signal. A gate electrode of the second field effect transistor is supplied with a negative-phase signal of the first signal. A source electrode of the second field effect transistor is short-circuited with a source electrode of the first field effect transistor and is grounded. A source electrode of the third field effect transistor is connected to a terminal at which drain electrodes of the first field effect transistor and the second field effect transistor are short-circuited. A gate electrode of the third field effect transistor is supplied with a second signal. A drain electrode of the third field effect transistor outputs a signal. | 2015-03-12 |
20150070073 | SINGLE-CHIP MULTI-DOMAIN GALVANIC ISOLATION DEVICE AND METHOD - An integrated circuit, including:
| 2015-03-12 |
20150070074 | CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY - Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node. | 2015-03-12 |
20150070075 | RADIO FREQUENCY SWITCH WITH IMPROVED LINEARITY - A Radio Frequency (RF) switch element is described. The RF switch element comprises a primary transistor element for facilitating switching an RF signal between circuit nodes. A pair of secondary transistor elements are also provided. The pair of secondary transistor elements are co-operable with the primary transistor element and provide respective signal paths which have a lower impedance level than an intrinsic element associated with the primary transistor element. | 2015-03-12 |
20150070076 | BRIDGE CIRCUITS AND THEIR COMPONENTS - A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor. | 2015-03-12 |
20150070077 | SIGNAL DISTRIBUTION CIRCUITRY - Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines. | 2015-03-12 |
20150070078 | CIRCUIT AND METHOD FOR CONDUCTING SOFT TURN-OFF OF A DRIVING CIRCUIT OF SEMICONDUCTOR SWITCHING DEVICE - A circuit for conducting soft turn-off includes a semiconductor switching device, a resistor and a sink pin. The second semiconductor switching device has a current inflow terminal connected to a current control terminal of a first semiconductor switching device, and a current outflow terminal connected to a ground. The resistor has a first terminal connected to the current inflow terminal of the second semiconductor switching device, and a second terminal connected to a current control terminal of the first semiconductor switching device. The sink pin applies a value lower than a previous applied value (i.e., a low value) to the current control terminal of the second semiconductor switching device. | 2015-03-12 |
20150070079 | Capacitive Sensing Array Having Electrical Isolation - A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed. | 2015-03-12 |
20150070080 | SYSTEM AND METHOD FOR DISTRIBUTED REGULATION OF CHARGE PUMPS - A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control circuit to generate a control signal for each of the charge pumps. The control signal causes each of the charge pumps to be enabled, partially enabled, or disabled, and controls at least one of the charge pumps independently of the other charge pumps. | 2015-03-12 |
20150070081 | SYSTEM AND METHOD FOR REDUCTION OF BOTTOM PLATE PARASITIC CAPACITANCE IN CHARGE PUMPS - A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high. | 2015-03-12 |
20150070082 | CHARGE PUMP CIRCUIT - A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes. | 2015-03-12 |
20150070083 | BOOSTING CIRCUIT OF CHARGE PUMP TYPE AND BOOSTING METHOD - A boosting circuit of charge pump type includes: charging portion for applying an input voltage to a first capacitor; double boosting portion for applying the input voltage to a second capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor in a first predetermined period after start of a boosting operation; and triple boosting portion for repeating in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor. | 2015-03-12 |
20150070084 | SEMICONDUCTOR DEVICE - A semiconductor device includes an input-part receiving a first voltage and an output-part outputing a second voltage. A current mirror part receives the first voltage. A reference voltage is supplied to a gate of a reference transistor. The reference transistor is electrically connected between the current-mirror part and a ground voltage. A monitor transistor includes a gate electrically connected to the second power-supply voltage, and is electrically connected between the current-mirror part and the ground voltage. A voltage-generation transistor includes a gate electrically connected to both the current-mirror part and the reference transistor. The voltage-generation transistor is electrically connected between the input-part and the output-part. A first capacitor including one end electrically connected to the output-part, and the other end electrically connected to both the current-mirror part and the reference transistor. | 2015-03-12 |
20150070085 | REDUCTION IN ON-RESISTANCE IN PASS DEVICE - A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device. | 2015-03-12 |
20150070086 | REGULATOR CIRCUITRY CAPABLE OF TRACKING REFERENCE VOLTAGES - An integrated circuit having a regulator circuit capable of tracking reference voltages is provided. The integrated circuit includes shunt regulator circuitry. The shunt regulator circuitry includes a shunt regulator circuit and a voltage tracking circuit. The shunt regulator circuit has an output on which a regulated voltage is provided. The shunt regulator circuit also provides electrical current to the output when the regulated voltage is outside of a voltage range bounded by first and second reference voltages. The voltage tracking circuit may be coupled to the shunt regulator circuit. The voltage tracking circuit may generate the first and second reference voltages. In one instance, the first voltage is greater than the regulated voltage and the second voltage is less than the regulated voltage. | 2015-03-12 |
20150070087 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first power supply line to which an input power supply voltage is to be applied, a second power supply line configured to supply a bias voltage to a load circuit, a MOS transistor having a source-drain current path connected between the first and second power supply lines, an NMOS transistor having a source-drain current path connected between the first and second power supply lines, and a control circuit configured to generate a first control signal that is supplied to a gate electrode of the PMOS transistor at a first point in time, and a second control signal that is boosted to have a voltage level higher than the input power supply voltage and then supplied to a gate electrode of the NMOS transistor at a second point in time point that is after the first point in time. | 2015-03-12 |
20150070088 | Circuits And Methods For Cancelling Nonlinear Distortions In Pulse Width Modulated Sequences - A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input signal is generated. The first signal has quantized levels representing the input signal. A pulse width modulated (PWM) sequence that is representative of the first signal is generated. A second signal that is the PWM sequence mixed with a carrier signal is generated. An error signal is generated in response to the first signal and modeled from the second signal. The error signal is added to the input signal. | 2015-03-12 |
20150070089 | ADAPTIVE NONLINEAR MODEL LEARNING - In accordance with an example implementation of this disclosure, a receiver may comprise a signal reconstruction circuit and a nonlinearity modeling circuit. The nonlinearity modeling circuit may be operable to generate a look-up table (LUT)-based model of nonlinear distortion present in a received signal. An entry of the LUT may comprise a signal power parameter value and a distortion parameter value. The signal reconstruction circuit may be operable to generate one or more candidates for a transmitted signal corresponding to the received signal. The signal reconstruction circuit may be operable to distort the one or more candidates according to the model, the distortion resulting in one or more reconstructed signals. The signal reconstruction circuit may be operable to decide a best one of the candidates based on the one or more reconstructed signals. | 2015-03-12 |
20150070090 | SUSPEND MODE IN CHARGE PUMP - A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load. | 2015-03-12 |
20150070091 | ANALOG AMPLIFIERS AND COMPARATORS - An innovative analog circuit design using digital components is disclosed. Embodiments of the present invention includes, but not limited to analog amplifiers and comparators. An amplifier of an embodiment of the present invention includes an inverter, a plurality of switches, offset capacitor and flying capacitor. The one terminal of the offset capacitor is connected to the input of the inverter. During setup phase of clock signals, the switches are configured to connect input and output of the inverter and to connect the flying capacitor to input terminals of the amplifier, respectively, for storing a differential input voltage. Then, during the enable phase of the clock signals, the switches are configured to connect the first terminal of the second capacitor and the first terminal of the first capacitor, and to connect the second terminal of the second capacitor to the output of the inverter. | 2015-03-12 |
20150070092 | POWER AMPLIFIER MODULE - A power amplifier module includes a first amplification transistor that amplifies and outputs a radio frequency signal, a second amplification transistor that is connected in parallel to the first amplification transistor and that has a smaller size than the first amplification transistor, a bias circuit that supplies a bias voltage or a bias current to the first and second amplification transistors, a current detector circuit that detects a current flowing in the second amplification transistor, and a bias control circuit that controls the bias voltage or the bias current supplied from the bias circuit to the first and second amplification transistors depending on the detection result of the current detector circuit. | 2015-03-12 |
20150070093 | Logarithmic Detector Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion - A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency. | 2015-03-12 |
20150070094 | DOHERTY POWER AMPLIFIER WITH COUPLING MECHANISM INDEPENDENT OF DEVICE RATIOS - A method and system for design and implementation of symmetric and asymmetric Doherty power amplifiers are disclosed. Quarter wave transmission lines are interposed between the main and peak power amplifiers of a Doherty power amplifier system and a 3 dB hybrid coupler. The impedances of the quarter wavelength transmission lines are chosen based on a ratio of the power ratings of the main and peak power amplifiers such that the impedances seen by the main and peak power amplifiers is independent of the impedance of the 3 dB coupler. | 2015-03-12 |
20150070095 | WIDEBAND BIAS CIRCUITS AND METHODS - The present disclosure includes circuits and methods for wideband biasing. In one embodiment, an amplifiers includes a cascode transistor between an input and an output of the amplifier. The cascode transistor receives a bias from a bias circuit comprising a resistor between the power supply and a first node, a resistor between the first node and a reference voltage, and a capacitor between the power supply and the first node. The power supply may be a modulated power supply, which is coupled through the bias circuit to a capacitance at the control terminal of the cascode transistor. An inductor is configured between a terminal of the cascode transistor and the power supply. The inductor may isolate the output from the modulated supply signal. | 2015-03-12 |
20150070096 | POWER AMPLIFIER - A power amplifier is smaller in size and limits input noise having a differential frequency. A power amplifier has an input terminal, an amplifying transistor, a bias circuit, a filter circuit, and an impedance matching circuit. The bias circuit supplies a bias to the signal input side of the amplifying transistor. The filter circuit removes noise at the signal input side of the amplifying transistor. The filter circuit has a matching resistor, a chip inductor, and a chip capacitor. Each of the chip inductor and the chip capacitor is a surface mount device. The matching resistor is located on a semiconductor substrate, has a first end connected to a connection point of two MIM capacitors, and a second end connected to a connection point of one of the MIM capacitors and the signal input side of the amplifying transistor. | 2015-03-12 |
20150070097 | CONFIGURABLE MULTIMODE MULTIBAND INTEGRATED DISTRIBUTED POWER AMPLIFIER - A novel and useful configurable radio frequency (RF) power amplifier (PA) and related front end module (FEM) circuit that enables manipulation of the operating point of the power amplifier resulting in configurability, multimode and multiband operating capability. The configurable PA also provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configurable power amplifier is made up of one or more configurable sub-amplifiers having each constructed to have several orders of freedom (i.e. biasing points). Each sub-amplifier and its combiner path include active and passive elements. Manipulating one or more biasing points of each sub-amplifier, and therefore of the aggregate power amplifier as well, achieves multimode and multiband operation. Biasing points include, for example, the gain and saturation point, frequency response, linearity level and EVM. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provides efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers. | 2015-03-12 |
20150070098 | RF AMPLIFICATION DEVICE WITH POWER PROTECTION DURING HIGH SUPPLY VOLTAGE CONDITIONS - Radio frequency (RF) amplification devices are disclosed along with methods of providing power to an RF signal. In one embodiment, an RF amplification device includes an RF amplification circuit and a voltage regulation circuit. The RF amplification circuit includes a plurality of RF amplifier stages coupled in cascade. The voltage regulation circuit is coupled to provide a regulated voltage to a driver RF amplifier stage. The voltage regulation circuit is configured to generate the regulated voltage so that the maximum output power of the RF amplification circuit is provided approximately at a first power level while the supply voltage is above a threshold voltage level. The first power level should be within the physical capabilities of the RF amplification circuit, and thus, the RF amplification circuit is prevented from being damaged once the supply voltage is above the threshold voltage level. | 2015-03-12 |
20150070099 | SYSTEM TO LINEARIZE A FREQUENCY SWEEP VERSUS TIME - A system for generating a variable frequency is provided. The system includes a voltage controlled oscillator (VCO) and an integrator. The VCO is configured to output a frequency signal with a frequency value dependent on a voltage value of a control signal. The integrator is configured to vary the control signal provided to the VCO. The ramp rate of the integrator is varied so the frequency value changes at a substantially constant frequency rate over a period of time, i.e. is linearized. In one configuration, the ramp rate of the integrator is based on an input value of an input signal to the integrator determined by a digital to analog convertor (DAC). | 2015-03-12 |
20150070100 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OSCILLATION SYSTEM - The semiconductor integrated circuit includes an inverting amplifier that generates an oscillation signal with an input connected to the first terminal and an output connected to the second terminal, the inverting amplifier fluctuating in gain in response to a gain control signal. The semiconductor integrated circuit includes a waveform shaping circuit that shapes a waveform of the oscillation signal and outputs a clock signal to a clock signal output terminal. The semiconductor integrated circuit includes an edge detecting circuit that detects an edge of the clock signal and outputs the gain control signal at a time of the edge. | 2015-03-12 |
20150070101 | NON-RECIPROCAL CIRCUIT ELEMENT - In a non-reciprocal circuit element, first to third center conductors intersect one another in an insulated state around a microwave magnetic body, and first ends of the first to third center conductors define first to third ports. A first capacitance element is connected to the first center conductor in parallel and a second capacitance element is connected to the second center conductor in parallel, and the other ends of the first to third center conductors are connected to one another and are grounded via a first inductance element and a third capacitance element that are connected in series. A second inductance element is connected to one end of the center conductor in parallel, and the other end of the second inductance element is grounded. A fourth capacitance element is connected to a connection point between the one end of the center conductor and the second inductance element, and the other end of the fourth capacitance element is connected to a third terminal. | 2015-03-12 |
20150070102 | Transmission Line and Filtering Module Thereof - A transmission line includes a signal terminal for inputting a first signal and a second signal, a first wire coupled to the signal terminal for transmitting the first signal, a second wire coupled to the signal terminal for transmitting the second signal, a filtering module coupled to the first and second wires for receiving the first and second signals to filter out noises of the first and second signal, a third wire coupled to the filtering module for transmitting the first signal, and a fourth wire coupled to the filtering module for transmitting the second signal. | 2015-03-12 |
20150070103 | NON-RECIPROCAL CIRCUIT ELEMENT - A non-reciprocal circuit element includes a permanent magnet, a microwave magnetic body to which a direct current magnetic field is applied by the permanent magnet, a first center electrode that is wrapped around the microwave magnetic body, is connected at one end to an input port, and is connected at another end to an output port, a second center electrode that is wrapped around the microwave magnetic body while intersecting with the first center electrode so as to be insulated from the first center electrode, is connected at one end to the output port, and is connected at another end to a ground port, a first matching capacitance connected between the input port and the output port in parallel with the first center electrode, a terminating resistance connected between the input port and the output port in parallel with the first center electrode, and a second matching capacitance connected between the output port and the ground port. A sub-center electrode is connected in parallel to a portion of the second center electrode. | 2015-03-12 |
20150070104 | COMPONENTS AND CIRCUITS FOR OUTPUT TERMINATION - A lossy electrical-signal transmission line having first and second ends, the transmission line being configured such that: its characteristic impedance at the first end has a first value; its characteristic impedance at the second end has a second value, lower than the first value; and its series resistance measured from its first end to its second end is within a given range of the difference between said first and second values. | 2015-03-12 |
20150070105 | SIGNAL OUTPUT DEVICE, COMMUNICATION SYSTEM, SIGNAL OUTPUT METHOD, AND COMMUNICATION METHOD - A signal output device, in a signal level non-transition period, matches an output impedance of an output section to a characteristic impedance of an output transmission path, and also matches the output impedance of the output section to the characteristic impedance of the output transmission path in a signal level transition period in a case in which a second bit of output-target data is a first value, and generates a mismatch between the output impedance of the output section and the characteristic impedance of the output transmission path in the signal level transition period in a case in which the second bit of the output-target data is a second value, so as to cause generation of a change in waveform in an output signal in the signal level transition period such that an absolute value of a signal level of the output signal exceeds a preset threshold value. | 2015-03-12 |
20150070106 | FILTER AND LAYOUT STRUCTURE THEREOF - A circuit structure is disclosed, wherein the circuit structure comprises: a substrate comprising a top surface, a bottom surface and lateral surfaces connecting the top surface and the bottom surface; a plurality of conductive layers disposed over the top surface of the substrate, wherein a dielectric layer is disposed between each two adjacent conductive layers, wherein at least one capacitor is formed by a first portion of the plurality of conductive layers with the dielectric layers therebetween, and wherein at least one first inductor is formed by a second portion of the plurality of conductive layers; and at least one conductive pattern layer disposed over at least one of the lateral surface to form at least one second inductor, wherein a third portion of the plurality of conductive layers electrically connects with said at least one capacitor, said at least one first inductor and said at least one second inductor. | 2015-03-12 |
20150070107 | HIGH FREQUENCY MODULE - Provided is a high frequency module capable of reducing size and cost. A high frequency module includes an LC filter having an inductor formed through a thin film process and a capacitor also formed through a thin film process, and a piezoelectric resonator that is connected in series to the LC filter and serves as a trap filter having a resonant frequency at the outside of a passing band of the LC filter. | 2015-03-12 |
20150070108 | ELASTIC WAVE FILTER - An elastic wave filter includes a piezoelectric substrate, an input side IDT electrode, an output side IDT electrode, and a reflector. At least one IDT electrode among the input side IDT electrode and the output side IDT electrode is weighted only with a main lobe among an apodized weighting method such that the intersection length becomes short from a part at which one electrode finger is opposed to another electrode finger adjacent to the one electrode finger toward an end portion of the at least one IDT electrode in a propagation direction of an elastic wave. A part with the largest intersection length in the at least one IDT electrode is shifted to any one of one side and another side in the propagation direction of the elastic wave from a center position at the at least one IDT electrode in the propagation direction of the elastic wave. | 2015-03-12 |
20150070109 | ISOTHERMAL TERMINATOR AND METHOD FOR DETERMINING SHAPE OF ISOTHERMAL TERMINATOR - An isothermal terminator system is provided. The isothermal terminator includes a waveguide formed to define a propagation channel through which electro-magnetic (EM) radiation is directed and a terminator including a body having an exterior surface and an interior surface opposite the exterior surface. The terminator is disposed in the propagation channel such that the EM radiation is incident on the exterior surface to raise a temperature of the body. The body is substantially isothermal with the EM radiation incident on the exterior surface. | 2015-03-12 |
20150070110 | SLOW-WAVE RADIOFREQUENCY PROPAGATION LINE - The instant disclosure describes a radiofrequency propagation line including a conducting strip connected to a conducting plane parallel to the plane of the conducting strip, wherein the conducting plane includes a network of nanowires made of an electrically conductive, non-magnetic material extending orthogonally to the plane of the conducting strip, in the direction of said conducting strip. | 2015-03-12 |
20150070111 | SYSTEM FOR TRANSMITTING INFORMATION BETWEEN CIRCUITS - A system for transferring information from a first circuit to a second circuit includes first and second isolation elements coupled between the first circuit and the second circuit. A first transient filter is located on the second circuit and coupled to the first isolation element. A second transient filter is located on the second circuit and coupled to the second isolation element. A first ground is located on the first circuit, and a second ground is located on the second circuit. The first ground electrically floats relative to the second ground. | 2015-03-12 |
20150070112 | RIGID RF COAXIAL TRANSMISSION LINE WITH CONNECTOR HAVING ELECTRICALLY CONDUCTIVE LINER AND RELATED METHODS - A rigid RF coaxial transmission line is positioned within a wellbore in a subterranean formation. The rigid RF coaxial transmission line includes a series of rigid coaxial sections coupled together in end-to-end relation and to be positioned within the wellbore of the subterranean formation. Each rigid coaxial section includes an inner conductor, a rigid outer conductor surrounding the inner conductor, and a dielectric therebetween. Each of the rigid outer conductors has threaded ends. The rigid RF coaxial transmission line includes a respective connector between adjacent ones of the series of rigid coaxial sections, each connector having a rigid outer layer threadingly secured to respective threaded ends of adjacent rigid outer conductors, and an electrically conductive liner carried by the rigid outer layer and defining an electrical joint between the adjacent rigid outer conductors. | 2015-03-12 |
20150070113 | TRIPPING MECHANISMS FOR TWO-POLE CIRCUIT BREAKERS - A two-pole circuit breaker is provided that includes an electronic pole disposed between a first mechanical pole and a second mechanical pole. The first mechanical pole includes a first armature, and the second mechanical pole includes a second armature. The first and second armatures each are adapted to rotate in a first plane. The electronic pole includes a trip mechanism having a first trip arm disposed adjacent the first armature and a second trip arm disposed adjacent the second armature. The first trip arm and the second trip arm are each adapted to rotate in a second plane substantially orthogonal to the first plane. Numerous other aspects are provided. | 2015-03-12 |
20150070114 | Remote Operated Circuit Breaker With Manual Reset - A circuit breaker having a movable contact arm for opening and closing the circuit which is controlled separately by a circuit breaker mechanism for circuit protection and by a switch lever mechanism which does not require actuation of the circuit breaker mechanism to function. The switch lever may also be activated remotely by a remote actuator, for example, a solenoid. A manual reset mechanism is provided so that, actuation of which, when power has been lost to the remote actuator when the remote actuator is in the off position, moves the remote actuator to the on position, thereby resetting the circuit to the closed state. | 2015-03-12 |
20150070115 | RETENTION MECHANISM, DRIVING APPARATUS, AND BLUR CORRECTION APPARATUS - A retention mechanism according to an embodiment includes a fixed part including a magnet, and a movable part opposed to the fixed part. A plurality of rolling elements are provided between the fixed part and the movable part, and the movable part is movable in a plane direction. A magnetic material which forms, in combination with the magnet, a magnetic spring is provided on the movable part. The magnetic spring generates a magnetic attraction force which attracts the movable part to the fixed part. The magnetic material is extended along a direction in which magnetic poles of the magnet are arrayed. | 2015-03-12 |
20150070116 | SOLENOID INCLUDING A DUAL COIL ARRANGEMENT TO CONTROL LEAKAGE FLUX - A solenoid includes a magnetic frame, a bobbin having a length, a hold coil, a pick up coil having a length, a fixed pole, a movable armature having a length, and a return spring biasing the armature away from the pole. The solenoid includes a pick up state when the armature and the pole are separated by a magnetic gap, and a holding state when the armature and the pole are proximate each other. The pick up coil is wound around the bobbin for a portion of the length of the bobbin and the hold coil is wound around the bobbin for a remaining portion of the length of the bobbin. The length of the pick up coil is about the same as the length of the armature and is less than the length of the bobbin. | 2015-03-12 |
20150070117 | ELIMINATING ANHYSTERETIC MAGNETISM IN FERROMAGNETIC BODIES - The aim is to improve the demagnetisation of ferromagnetic components by means of simple enhancements of a demagnetising device in such a manner that, in spite of the demagnetisation at approximately room temperature, ferromagnetic components with vanishingly low residual magnetism, as was previously only achievable by means of thermal demagnetisation, are achieved. This is achieved in that a chamber with walls made from magnetically highly-permeable ferromagnetic material for shielding from external interference fields, for example the magnetic field of the Earth, is used in the demagnetising coil of a demagnetising device, whereby an interference-field-free chamber interior is pushed with a reduction of the interference field strength in the chamber interior to such a small magnetic interference field, that the residual magnetism at the treated objects has a lower value after demagnetisation than the interference field outside of the chamber space. | 2015-03-12 |
20150070118 | Electronic Apparatus Combined with Magnetic Attraction Force - An electronic apparatus combined with magnetic attraction force includes a first body and a second body. The first body includes at least one first magnetic element; the second body includes at least one receiving groove, at least one moving assembly, and at least one assistant magnetic element. Each moving assembly is movably disposed in each receiving groove, and each moving assembly includes a second magnetic element. Each assistant magnetic element is fixed in the receiving groove, and the magnetic attraction force between the assistant magnetic element and the second magnetic element is smaller than that between the first magnetic element and the second magnetic element. When the second body is combined with the first body, each second magnetic element is attracted by each first magnetic element such that each moving assembly is driven to move toward the first body. | 2015-03-12 |
20150070119 | Switchable Magnetic Lock - This document describes techniques using, and apparatuses including, switchable magnetic locks. These techniques and apparatuses can enable low or no power consumption and a seamless design for locking and unlocking of devices one to the other, such as computing devices and peripherals. | 2015-03-12 |
20150070120 | COIL COMPONENT, METHOD FOR MANUFACTURING THE SAME, AND COIL ELECTRONIC COMPONENT - A coil component has a wound coil, a coil magnetic body, and an exterior body. The coil magnetic body has a magnetic core inside winding of the wound coil. The exterior body covers a surface of the coil magnetic body. This coil component has a mount surface, and a thermal conductivity in a direction parallel to a surface of the exterior body is greater than a thermal conductivity in a direction perpendicular to the surface of the exterior body. | 2015-03-12 |
20150070121 | COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME - There are provided a coil component and a method of manufacturing the same. The coil component includes a core; at least one bobbin coupled to the core and having a coil wound therearound; and a base having the core seated therein and including an external connection terminal, wherein one side of the core is seated in the bobbin and the other side thereof is exposed to the outside of the base. | 2015-03-12 |
20150070122 | Three Piece Transformer Core - A three piece transformer core includes a top having a pair of top lateral faces, namely a top left lateral face and a top right lateral face. The top left lateral face has a lower edge bounded at a top lower left face. The top right lateral face has a lower edge bounded at a top lower right face. A core left side section has a core left side section first leg and a core left side section second leg. The core left side section has a left lateral upper face configured to abut the top lower left face of the top. A core right side section has a core right side section first leg and a core right side section second leg. The core right side section has a right lateral upper face configured to abut the top lower right face of the top. | 2015-03-12 |
20150070123 | METHODS FOR FORMING CHIP-SCALE ELECTRICAL COMPONENTS - A method of forming a planar, low loss electrical component such as an inductor or transmission line is provided. A channel can be formed on a top surface of a substrate. A threading plate can be positioned on an upper surface of the channel. A wire or fiber can be introduced through the substrate, the channel, and the threading plate. The wire or fiber can then be guided into the channel using the threading plate. The substrate and the threading plate can then be removed. | 2015-03-12 |
20150070124 | SOFT MAGNETIC CORE WITH POSITION-DEPENDENT PERMEABILITY - Soft magnetic core, in which permeabilities that occur at least two different locations of the core are different. | 2015-03-12 |
20150070125 | INTEGRAL INDUCTOR ARRANGEMENT - The disclosure relates to an integral inductor arrangement with at least three magnetic loops arranged side by side to each other in a row and at least one winding associated with each of the magnetic loops. The magnetic loops are formed by individual core elements, each of which being part of one of the magnetic loops, and shared core elements, each of which being part of two adjacent of the magnetic loops. The shared core elements are separated from the individual core elements by magnetic gaps and each of the at least one winding is arranged around one of the individual core elements. The disclosure further relates to a use of such integral inductor arrangement within a 3-phase AC-filter for a power inverter for feeding electrical power into a power grid. | 2015-03-12 |
20150070126 | THERMAL FUSE DEVICE - A thermal fuse device has an essentially annular frame made of electrically insulating material. First and second contact strips of electrically conductive material extend through opposite portions of the frame and have respective first ends extending inside the internal region of the frame, where they at least partially face each other, and respective second ends extending outside the frame for connection to an electrical or electronic circuit. The first end of the first contact strip is joined to the first end of the second contact strip by a quantity of heat-meltable material, in a condition where the first contact strip is resiliently pre-stressed so that, when the joint is broken, the first end of the first contact strip moves away from the first end of the second contact strip. | 2015-03-12 |
20150070127 | NTC THERMISTOR ELEMENT AND METHOD AND METHOD FOR PRODUCING THE SAME - A NTC thermistor element that includes a substrate composed of a ceramic material containing Mn, Ni, Fe and Ti; and a pair of external electrodes on the substrate. When the molar amount of Mn in the substrate is a [mol %] and the molar amount of Ni in the substrate is b [mol %], a and b satisfy a+b=100, 44.90≦a≦65.27 and 34.73≦b≦55.10. When the molar amount of Fe is c [mol %] and the molar amount of Ti is d [mol %], c and d satisfy 24.22≦c≦39.57 and 5.04≦d≦10.18 based on a+b=100. | 2015-03-12 |
20150070128 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetoresistive element comprises a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, a second nonmagnetic layer, and a third magnetic layer. The first magnetic layer has a variable magnetization direction. The second magnetic layer has an invariable magnetization direction and includes a nonmagnetic material film and a magnetic material film. The first nonmagnetic layer is arranged between the first magnetic layer and the second magnetic layer. The second nonmagnetic layer is arranged on a surface of the second magnetic layer. The third magnetic layer is arranged on a surface of the second nonmagnetic layer. The second nonmagnetic layer is in contact with the nonmagnetic material film included in the second magnetic layer. | 2015-03-12 |
20150070129 | METHODS AND SYSTEMS FOR PROVIDING NAVIGATION ASSISTANCE TO A USER - Methods and systems for providing navigation assistance to a user are disclosed. A method for providing navigation assistance to a user includes defining at least one virtual wall along at least a portion of a path for navigation through an environment. The at least one virtual wall is offset from the path by an offset distance. The method further includes determining a location of the user and providing tactile feedback to the user, automatically by a processor, when the location of the user is within a threshold distance of the at least one virtual wall. | 2015-03-12 |
20150070130 | SECURITY SYSTEM WITH POINT BUS ABSTRACTION AND PARTITIONING - Security systems and methods of operating the same. One security system includes a plurality of point devices positioned in a premises, a plurality of interim devices, and a control panel. The system also includes a first communication bus connecting the control panel and each of the plurality of interim devices and a plurality of second communication buses. Each of the plurality of second communication buses connects one of the plurality of interim devices with at least one of the plurality of point devices. The control panel is also configured to address a message for one of the plurality of point device based on an identifier of the one of the plurality of point devices and an identifier of at least one of the plurality of interim devices connected to the point device over one of the plurality of second communication buses. | 2015-03-12 |
20150070131 | METHOD AND APPARATUS FOR DETECTING BOARDING OF A MEANS OF TRANSPORT - An approach is provided for detecting when a user has boarded a means of transport. The sensor platform may determine sensor information associated with at least one device, wherein the sensor information is collected from one or more sensors that do not include one or more satellite-based location sensors. Then, the sensor platform may process and/or facilitate a processing of the sensor information to determine at least one entry or at least one exit of the at least one device with respect to at least one structure, at least one supporting structure associated with the at least one structure, or a combination thereof associated with one or more transport means. | 2015-03-12 |
20150070132 | SECURE REMOTE CONTROL FOR OPERATING CLOSURES SUCH AS GARAGE DOORS - Actuation of an access closure such as a garage door may be initiated by a remote control (RC) if a correct authentication code is received by the RC and/or if a designated authorization device such as a mobile phone is within near field communication transceiver range of the RC. | 2015-03-12 |
20150070133 | IDENTIFICATION SENSOR FOR GATE IDENTIFICATION OF A PERSON - The invention relates to an identification sensor ( | 2015-03-12 |
20150070134 | AUTHENTICATION SYSTEM USING WEARABLE DEVICE - A wearable device (“WD”) stores a token after its wearer completes a successful strong authentication on a primary protected device (“primary PD”). Other protected devices (“secondary PDs”) recognize the stored token as representing a strong authentication and grant the user access while the user continues to wear the WD within a “digital leash-length” proximity. The WD constantly monitors whether the user continues to wear the device. Upon sensing that the user has removed the WD, the WD deletes, disables, or invalidates the token, The user must then repeat the strong authentication to gain further access to the protected devices. | 2015-03-12 |
20150070135 | SECURITY SYSTEM AND DEVICE THEREFOR - A security system and security devices, optionally for a vehicle. The security system comprising a control unit, a locking system, a primary key and a secondary key, the primary key and the secondary key each normally operable to activate and deactivate the locking system and upon operation of the secondary key to activate the locking system, at least some or all of the functionality of the primary key is caused to be disabled and/or the control unit is caused to temporarily ignore command signals transmitted by the primary key. | 2015-03-12 |
20150070136 | KEYLESS ENTRY SYSTEM - A keyless entry system including multiple portable devices and an in-vehicle device controlling smart lock and smart unlock of a vehicle door is disclosed. The in-vehicle device includes an vehicle-cabin-inside portable determination section, which when locking the vehicle door by the auto-lock function, determines whether or not there is the portable device located inside the vehicle cabin, and a disabled state release section that releases the disabled states of all of the portable devices when the vehicle-cabin-inside portable determination section determines that there is no portable device located inside the vehicle cabin. | 2015-03-12 |
20150070137 | FINGER BIOMETRIC SENSOR INCLUDING CIRCUITRY FOR ACQUIRING FINGER BIOMETRIC DATA BASED UPON FINGER STABILITY AND RELATED METHODS - A finger biometric sensor may include an array of finger biometric sensing pixels and processing circuitry coupled to the array of finger biometric sensing pixels. The processing circuitry may be capable of acquiring finger stability biometric data from a subset of the array, and determining whether a finger is stable relative to the array of finger biometric sensing pixels based upon the finger stability biometric data. The processing circuitry may also be capable of acquiring finger biometric data from the array of finger biometric sensing pixels when the finger is stable. | 2015-03-12 |
20150070138 | DETECTION OF BURIED ASSETS USING CURRENT LOCATION AND KNOWN BUFFER ZONES - A method on a mobile computing device for locating a buried asset is provided. The method includes receiving a data structure that represents a two dimensional area comprising a buffer zone at an above-surface location, wherein the buffer zone corresponds to a particular buried asset sought by an operator of the device and iteratively executing the following steps: a) calculating an above-surface location of the device; b) determining whether the above-surface location of the device is located within the two dimensional area; c) if the above-surface location is not located within the two dimensional area, displaying a first graphic in a display of the mobile computing device; d) if the above-surface location is located within the area, displaying a second graphic in the display. | 2015-03-12 |
20150070139 | System and Method for External Equipment Monitoring - The present invention is a system and method for external equipment monitoring. The presenting invention uses a network of sensor-devices that constitute a system that provides information about entities within a facility, where entities may mean industrial equipment, personnel, parts, raw materials, etc. The invention allows the entities to be tracked; monitored and optimized without input from a user of what type of entity or what type of entity it is (e.g., users, rooms, etc. can be monitored. The present invention uses devices that do not require an electronic connection to the entity and with the ability for one entity to monitor the activity of another entity. | 2015-03-12 |
20150070140 | RFID SKIER MONITORING SYSTEMS AND METHODS - A system and method monitor skier behavior. An identifier is read from a lift access product when the lift access product is in the vicinity of a lift boarding area and a scan record containing the identifier, location information of the lift boarding area and a time stamp if generated. The scan record is processed to generate a location event record that is stored within a location database. The location database is processed to determine skier behavior based upon the location event records. | 2015-03-12 |
20150070141 | WIRELESS CONTROL SYSTEM AND METHOD OF SETTING THE CONTROL SYSTEM - A wireless control system for controlling a plurality of electric elements, includes a control signal generator, at least a converting device, and a plurality of controlling devices. The control signal generator generates a Wi-Fi control signal and sends it to the converting device. The converting device converts the Wi-Fi control signal into a radio frequency control signal, and sends the radio frequency control signal to the controlling devices. The controlling devices are connected to the electric elements respectively to receive the radio frequency control signal from the converting device and control the electric elements accordingly. | 2015-03-12 |
20150070142 | REMOTE CONTROL SYSTEM, METHOD FOR CONFIGURING REMOTE CONTROL SYSTEM, COMMUNICATION TERMINAL DEVICE, ELECTRONIC DEVICE, AND SERVER DEVICE - In a case where a registration process of registering a second mode is carried out, (i) a communication terminal device ( | 2015-03-12 |
20150070143 | Novelty Door Knocker with Audio Playback - A novelty door knocker having an electronic sound effect or effects, the door knocker with mechanical arm, plate, switch or proximity sensor enabled to trigger a sound effect, and a battery-powered circuit for controlling and coordinating the acoustics with the trigger. The door knocker may be decorated with or shaped as a cartoon figure for use on a child's bedroom door, for example. | 2015-03-12 |