11th week of 2009 patent applcation highlights part 29 |
Patent application number | Title | Published |
20090067187 | Removable tubular variable lighting system for a skateboard - A multiple tube, multiple lights effects neon or fluorescent lighting system for a skateboard produces a variety of controlled light effects and combinations. A pair of high strength colored protective transparent elongated casings house the light tubes. The casings are removably attached in a highly visible position on the side edges of a skateboard or under the skateboard adjacent to the side edges. The casings are secured by industrial strength mating hook and loop fasteners. | 2009-03-12 |
20090067188 | LIGHT SOURCE - A first optical waveguide guides a pumping light emitted from a semiconductor laser. A second optical waveguide absorbs the pumping light and emits a spontaneous emission light having a wavelength longer than that of the pumping light. A third optical waveguide guides a light output from the second optical waveguide to outside. A wavelength selecting element is provided between the second optical waveguide and the third optical waveguide, across which a resonator is formed between the semiconductor laser side and an output side to outside. A wavelength of a laser light emitted from the resonator is set by controlling length of the second optical waveguide. | 2009-03-12 |
20090067189 | CONTRA-ANGLE ROTATING HANDPIECE HAVING TACTILE-FEEDBACK TIP FERRULE - An illumination device is described containing optical fibers that transmit electromagnetic energy from a source to a target. Additional optical fibers return reflected electromagnetic energy from the target. High-level electromagnetic energy can be used for cutting, reforming, or treating a surface. Low-level electromagnetic energy illuminates the surface. | 2009-03-12 |
20090067190 | Optical Film and Backlight Unit Using the Same - An optical film enhances provide brightness in the frontal direction and light diffusing without using a prism sheet or a lens sheet. | 2009-03-12 |
20090067191 | LED Lighting System - A lighting system is provided having a light source with a housing, an LED engine, a controller, a heat sink, a connection device, and a power cable opening. The LED engine, controller and heat sink can be enclosed by the housing and sealed from atmosphere. The heat sink can be in thermal communication with the LED engine. The controller can be connected to a power cable inserted through the power cable opening. The controller can control at least one of power to the LED engine and a light output generated by the LED engine. A fiber optic cable can be connected to the LED engine by the connection device. The LED engine can communicate the light output through the fiber optic cable. | 2009-03-12 |
20090067192 | LOGO DISPLAY - A logo display includes a light guide plate including a light emitting surface, a plurality of light emitting diodes (LEDs) optically coupled to the light guide plate, and a light-transmissive layer disposed on the light emitting surface of the light guide plate. A light-transmissive colored pattern is formed on the light-transmissive layer. The light-transmissive colored pattern is configured for filtering out a color component of the light incident on the light-transmissive layer same as a color of the light-transmissive colored pattern. | 2009-03-12 |
20090067193 | Back light unit and manufacturing method thereof - A back light unit and a manufacturing method thereof capable of improving efficiency of a manufacturing process are disclosed. The back light unit includes a light source, a light guiding plate which uniformly transmits a light beam generated by the light source, and a cover portion which forms an external appearance and fixes the light guiding plate, wherein a resin material is charged between the light guiding plate and the cover portion to couple the light guiding plate and the cover portion. | 2009-03-12 |
20090067194 | Light guide with imprinted phosphor - A light guide includes a transparent sheet exhibiting total internal reflection in at least one direction and phosphor printed on the transparent sheet. The phosphor extracts light from the transparent sheet when the sheet is edge-lit and converts the light from one wavelength to another wavelength. The phosphor is pressed into the surface of the sheet after heating the surface to its softening temperature. | 2009-03-12 |
20090067195 | BACKLIGHT REFLECTION PLATE AND BACKLIGHT MODULE - Disclosed is a backlight reflection plate and a backlight module using the reflection plate. The reflection plate encloses a light source. The reflection plate comprises a reflection substrate with a surface facing the light source. The reflection plate comprises a first region close to one end of the light source with a higher brightness and a second region close to the other end of the light source with a lower brightness. The reflectivity of the first region is smaller than that of the second region. | 2009-03-12 |
20090067196 | SURFACE LUMINOUS BODY - A surface luminous body comprises a light guiding body, a coating layer formed by applying a binder paint where a reflecting material is mixed into and dispersed in a binder onto a surface of the light guiding body, and a reflecting layer made of a pigment layer which is formed by applying a pigment containing binder paint where a pigment is mixed into and dispersed in a binder onto the coating layer, wherein the average particle diameter of the mixed beads is 1 μm to 80 μm, and the pigment is opaque and made of a light reflecting material. | 2009-03-12 |
20090067197 | Decorative Lamp - The present invention relates to a lamp string, particularly to a decorative lamp. The decorative lamp includes a flowered shell, a soft core, and a soft head. The flowered shell is defined in the top of the soft core. The soft head is defined in the bottom of the soft core. The fitting place of the flowered shell and the soft core is integrally formed by injection molding. The present invention has the following advantages; the first is that the integrative structure of the fitting place of the flowered shell and the soft core can prevent the leakage of rain; the second is the extension of the service life and the reduction of the using cost; the third is the convenience of the replacement; the fourth is the reasonable idea, the novel design and the market potential. | 2009-03-12 |
20090067198 | CONTACTLESS POWER SUPPLY - A system includes a first device configured to receive a first wireless power associated with a first electromagnetic wave from a wireless power source. The first device is configured to convert the first wireless power to a first DC power, store the first DC power, and convert the first DC power stored in the first device to a second wireless power associated with a second electromagnetic wave. The system includes a second device configured to receive the second wireless power from the first device. The second device is configured to convert the second wireless power to a second DC power. The first device can receive the first wireless power at a first location and can convert the first DC power stored in the first device to the second wireless power at a second location different from the first location. | 2009-03-12 |
20090067199 | SWITCHED MODE POWER SUPPLY - A switched mode power supply assembly ( | 2009-03-12 |
20090067200 | Device and method for equalizing the charges of individual, series-connected cells of an energy storage device - A device and a method for compensating charges of serially connected individual cells of an energy storage device includes a DC/DC converter which taps power from the energy storage device or an additional energy source, charges a capacitor of an intermediate circuit by way of the tapped power, inverts the voltage thereof in a DC/AC converter, converts the alternating voltage into an intermittent direct current via an AC bus and a double capacitor by way of a rectifier, and charges the cell with the intermittent direct current at the lowest cell voltage. | 2009-03-12 |
20090067201 | Isolated Switched-mode Power Supply With Output Regulation From Primary Side - Embodiments disclosed herein describe an isolated switched-mode power supply with its output regulated from the primary side, by generating a sensing current using a sensing element coupled to the output of the power supply, and measuring a scaled version of the sensing current which depends on the output voltage, and calculating an estimate voltage representing the output voltage, and regulating the output of the isolated switched-mode power supply based on the estimate voltage. | 2009-03-12 |
20090067202 | Power Supply System And Vehicle Including The Same - A converter ECU ( | 2009-03-12 |
20090067203 | THREE PHASE INVERTER WITH IMPROVED LOSS DISTRIBUTION - An inverter circuit couples a DC voltage source having a primary side and a reference side to an electric motor or other AC machine having multiple electrical phases. An inverter circuit includes switches, diodes and a controller. For each of the electrical phases, a first switch couples the electrical phase to the primary side of the DC voltage source and a second switch couples the electrical phase with the reference side of the DC voltage source. For each of the first and second switches, an associated anti-parallel diode is configured to provide an electrical path when the switch associated with the diode is inactive. The controller is coupled to the switching inputs of each of the first and second switches and is configured to provide a control signal thereto, wherein the control signal provided to each switch comprises, in a low frequency mode, a first portion and a second portion, wherein the first portion comprises a first pulse width modulation scheme and the second portion comprises a second pulse width modulation scheme different from the first modulation scheme. | 2009-03-12 |
20090067204 | SYSTEM AND METHOD FOR PROVIDING CONTROL FOR SWITCH-MODE POWER SUPPLY - System and method for providing control for switch-mode power supply. According to an embodiment, the present invention provides a system for regulating a power converter. The system comprises a signal processing component that is configured to receive a first voltage and a second voltage, to process information associated with the first voltage and the second voltage, to determine a signal based on at least information associated with the first voltage and the second voltage, and to send the signal to a switch for a power converter. The switch is regulated based on at least information associated with the signal. The signal processing component is further configured to determine the signal to be associated a first mode, if the first voltage is higher than a first threshold. | 2009-03-12 |
20090067205 | Power Controller and Vehicle Equipped with Power Controller - An ECU detects an effective value and phase of a voltage from a commercial power supply, based on a voltage from a voltage sensor. Further, ECU generates a command current, which is a command value of current caused to flow through power lines and in-phase with the voltage of the commercial power supply, based on the detected effective value and the phase and on a charge/discharge power command value for a power storage device. Then, ECU controls zero-phase voltage of inverters based on the generated command current. | 2009-03-12 |
20090067206 | Rectifier Circuit and Three-Phase Rectifier Device - Choppers are provided respectively in the output stages of two diode bridges, and their output sides are connected in parallel to a smoothing capacitor. By controlling the operations of the two choppers, the currents which are allowed to be inputted to the diode bridges are made triangular waves of mutually opposite phases, or middle-phase waveforms of three phases. | 2009-03-12 |
20090067207 | Secondary-side power receiving circuit of noncontact power supplying equipment - A plurality of pickup coils | 2009-03-12 |
20090067208 | METHOD AND APPARATUS FOR PROVIDING POWER - An apparatus includes a first converter module, a second converter module, and a sensor module. The first converter module converts a wireless power associated with an electromagnetic wave to a first DC voltage. The first converter module can include, for example, a Villiard cascade voltage multiplier, a precision rectifier, or a full-wave bridge rectifier. The sensor module monitors the first DC voltage. The second converter module converts the first DC voltage to a second DC voltage that is larger than the first DC voltage. The second converter module is enabled by the sensor module when the first DC voltage is above a first threshold voltage. The second converter module is disabled by the sensor module when the first DC voltage is below a second threshold voltage that is lower than the first threshold voltage. The second converter module provides power to a load based on the second DC voltage. | 2009-03-12 |
20090067209 | Low-Power Content-Addressable-Memory Device - A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence. | 2009-03-12 |
20090067210 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-03-12 |
20090067211 | Electronic Fuse System and Methods - An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words with at least one word of the plurality of words containing security bits associated with a respective block. An electronic fuse controller is in communication with the fuse ROM and one or more external devices that are configured to request one or more words that reside in the fuse ROM from the electronic fuse controller. At least one security register includes indication bits that provide an indication whether security bits have been obtained for a respective block of memory of the fuse ROM after a power down and power up cycle. The electronic fuse controller provides the requested word if an indication bit associated with the block of memory is set. | 2009-03-12 |
20090067212 | MAGNETIC RANDOM ACCESS MEMORY AND DATA READ METHOD OF THE SAME - A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element, a second reference element making a pair with the first reference element, and having a third fixed layer, a third recording layer, and a third nonmagnetic layer, parallel data being written in the second reference element, and a current source which, when a read operation is performed, supplies a current from the second fixed layer to the second recording layer in the first reference element, and supplies the current from the third recording layer to the third fixed layer in the second reference element. | 2009-03-12 |
20090067213 | Method of forming controllably conductive oxide - In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer. | 2009-03-12 |
20090067214 | Electric element, memory device, and semiconductor integrated circuit - An electric element includes a first terminal ( | 2009-03-12 |
20090067215 | Electric element, memory device, and semiconductor integrated circuit - An electric element comprises: a first electrode ( | 2009-03-12 |
20090067216 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS - A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation. | 2009-03-12 |
20090067217 | Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same - In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode. | 2009-03-12 |
20090067218 | Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same - An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) and (ii) sense amplifier circuitry, coupled to the memory cell array, to sense a data state stored in one of the memory cells during a sense phase of operation. In one embodiment, the sense amplifier circuitry includes first and second capacitors, a first input electrically coupled to (i) the memory cell to receive a signal which is representative of the data state stored therein and (ii) a first terminal of the first capacitor, and a second input electrically coupled to (i) a first predetermined voltage and (ii) a first terminal of the second capacitor. The sense amplifier circuitry further includes a current source and a transistor wherein the gate of the transistor is electrically coupled to the second terminals of the first and second capacitors, and a first region of the transistor is electrically coupled to the current source. | 2009-03-12 |
20090067219 | Semiconductor memory device including SRAM cell having well power potential supply region provided therein - A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer transistor and the drive transistor being coupled in series between a bit line and a power source line, and a first diffusion region of the first conductivity type arranged between the drive transistor of the first SRAM cell and the drive transistor of the second SRAM cell, to apply a first well potential to the first well. | 2009-03-12 |
20090067220 | Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor provided between the output terminal of the first inverter and one line of a bit line pair, a transmission transistor provided between the output terminal of the second inverter and the other line of the bit line pair; and an isolation transistor for isolating the drive transistor and the transmission transistor. The transmission transistor, the transmission transistor, the drive transistor, and the isolation transistor are formed in a continuous active region and the isolation transistor is provided between the drive transistor and the transmission transistor. | 2009-03-12 |
20090067221 | HIGH DENSITY 45NM SRAM USING SMALL-SIGNAL NON-STROBED REGENERATIVE SENSING - A memory device includes a plurality of cells comprising CMOS structures. A non-strobed regenerative sense-amplifier (NSR-SA) is coupled to the cells and employs offset compensation and avoids strobe timing uncertainty to increase read-access speeds. | 2009-03-12 |
20090067222 | SEMICONDUCTOR MEMORY DEVICE - SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor. | 2009-03-12 |
20090067223 | COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters. | 2009-03-12 |
20090067224 | MAGNETORESISTIVE ELEMENT, PARTICULARLY MEMORY ELEMENT OR LOGIC ELEMENT, AND METHOD FOR WRITING INFORMATION TO SUCH AN ELEMENT - A magnetoresistive element, in particular a memory element or a logic element and a method for writing information to such an element are disclosed. The element comprises a first contact of ferromagnetic material and a corresponding layer of magnetoelectric or ferromagnetic material, whereby the first contact is magnetically polarized, depending on an antiferromagnetic boundary surface polarization of the first layer. Said magnetic polarization forms binary information. | 2009-03-12 |
20090067225 | MODULAR MAGNETORESISTIVE MEMORY - A magnetoresistive memory element has a read module with a first pinned layer that has a magnetoresistance that is readable by a read current received from an external circuit. The element has a write module that receives a write current from the external circuit. A coupling module adjacent both the write module and the read module has a free layer that functions as a shared storage layer for both the read module and the write module. The shared storage layer receives spin torque from both the read module and the write module and has a magnetization that is rotatable by the write current. | 2009-03-12 |
20090067226 | INTEGRATED CIRCUIT WITH PHASE-CHANGE MEMORY CELLS AND METHOD FOR ADDRESSING PHASE-CHANGE MEMORY CELLS - The present invention relates to integrated circuit comprising a plurality of bitlines (b | 2009-03-12 |
20090067227 | PHASE CHANGE MEMORY DEVICE HAVING A PLURALITY OF REFERENCE CURRENTS AND OPERATING METHOD THEREOF - A phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A plurality of sense amplifiers sense and amplify data of the phase change resistance cell selected using a plurality of reference currents. A plurality of comparing units compare an output signal of the corresponding sense amplifier with that of the neighboring sense amplifier so as to output a flag enable signal. | 2009-03-12 |
20090067228 | PHASE CHANGE MEMORY DEVICE, MANUFACTURING METHOD THEREOF AND OPERATING METHOD THEREOF - A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity. | 2009-03-12 |
20090067229 | SEMICONDUCTOR MEMORY DEVICE FOR WRITING DATA TO MULTIPLE CELLS SIMULTANEOUSLY AND REFRESH METHOD THEREOF - A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines. | 2009-03-12 |
20090067230 | Multi-level memory devices and methods of operating the same - The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value. | 2009-03-12 |
20090067231 | MAGNETIC MEMORY CELL BASED ON A MAGNETIC TUNNEL JUNCTION(MTJ) WITH INDEPENDENT STORAGE AND READ LAYERS - Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a first free layer optimized for reading; and a second free layer separate from the MTJ and optimized for writing. | 2009-03-12 |
20090067232 | Multiple Magneto-Resistance Devices Based on Doped Magnesium Oxide - The present invention provides a low resistance high magnetoresistance (MR) device comprised of a junction of two magnetic elements separated by a magnesium oxide (MgO) layer doped with such metals as Al and Li. Such device can be used as a sensor of magnetic field in magnetic recording or as a storage element in magnetic random access memory (MRAM). The invention provides a high-MR device possessing a diode function, comprised of a double junction of two outer magnetic elements separated by two MgO insulating layer and a center MgO layer doped with such metals as Al and Li. Such device provides design advantages when used as a storage element in MRAM. The invention with MR wherein a gate electrode is placed in electrical or physical contact to the center layer of the double tunnel junction. | 2009-03-12 |
20090067233 | Magnetic random access memory and method of reading data from the same - A magnetic random access memory (MRAM) includes a memory cell having a first transistor and a first magnetic tunneling junction (MTJ) layer, and a reference cell operable as a basis when reading data stored in the memory cell, the reference cell including second and third MTJ layers arranged in parallel to each other, and a second transistor connected in series to each of the second and third MTJ layers, the second transistor having a driving capability corresponding to twice a driving capability of the first transistor of the memory cell. | 2009-03-12 |
20090067234 | Flash Memory Device and Fabrication Method Thereof - The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation. | 2009-03-12 |
20090067235 | Test circuit and method for multilevel cell flash memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 2009-03-12 |
20090067236 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential. | 2009-03-12 |
20090067237 | MULTI-BIT DATA MEMORY SYSTEM AND READ OPERATION - Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data. | 2009-03-12 |
20090067238 | NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION - The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations. | 2009-03-12 |
20090067239 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 2009-03-12 |
20090067240 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 2009-03-12 |
20090067241 | DATA PROTECTION FOR WRITE ABORT - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period. | 2009-03-12 |
20090067242 | PROGRAMMING METHOD OF FLASH MEMORY DEVICE - A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines. | 2009-03-12 |
20090067243 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to respectively correspond to the bit lines and reading data stored in the memory cells; and bit line drivers provided to the bit lines and operating the bit lines when data is written to the memory cells, wherein the bit line drivers access the memory cells adjacent to a first memory cell diagonally with respect to the form of the lattice for writing the data to the adjacent memory cells during a data write operation without changing data stored in the memory cells adjacent to the first memory cell in the first and the second directions. | 2009-03-12 |
20090067244 | NONVOLATILE MEMORY AND METHOD FOR ON-CHIP PSEUDO-RANDOMIZATION OF DATA WITHIN A PAGE AND BETWEEN PAGES - Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip. | 2009-03-12 |
20090067245 | SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD OF NAND FLASH MEMORY - A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second voltages to the bit lines connected to the memory cell transistors in which the “0” data and “1” data is to be programmed respectively, when the selection transistor is turned on, in a write operation. The page buffer is adopted to put the bit line into electrically floating after the first voltage and the second voltage are applied. The row decoder is adopted to apply a third voltage to a semiconductor layer on which the memory cell transistors are formed, and apply a program voltage to the selected word line when the bit line is in the electrically floating. | 2009-03-12 |
20090067246 | Methods to Prevent Program Disturb in Nonvolatile Memory - Methods are provided to be used individually or in any combination that reduce program disturb in a non-volatile memory consisting of dual-gate memory cells. These methods counteract the effect of a leakage current in reducing a boosted voltage in a non-selected dual-gate memory string. According to one approach, a voltage applied to the gate electrode of an access device of a dual-gate memory cell is increased during a programming event. According to a second approach, the gate electrodes of an access device of a dual-gate memory cell is applied a series of electrical pulses synchronously with programming the memory device of the dual-gate memory cell by a second series of electrical pulses. According to a third approach, multiple dual-gate select devices are provided between a string of dual-gate memory devices and either a source line or a bit line, or both. | 2009-03-12 |
20090067247 | Method of programming nonvolatile memory device - A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage. | 2009-03-12 |
20090067248 | PROGRAM METHOD OF FLASH MEMORY DEVICE - In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented. | 2009-03-12 |
20090067249 | MEMORY WITH MULTI-PAGE READ - A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data. | 2009-03-12 |
20090067250 | MEMORY DEVICES WITH PAGE BUFFER HAVING DUAL REGISTERS AND METHOD OF USING THE SAME - A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed. | 2009-03-12 |
20090067251 | REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage. | 2009-03-12 |
20090067252 | FUSE DATA ACQUISITION - One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit. | 2009-03-12 |
20090067253 | Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles. | 2009-03-12 |
20090067254 | NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING A MULTI LEVEL CELL IN THE SAME - A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 2009-03-12 |
20090067255 | NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL FOR STORING MULTILEVEL DATA HAVING TWO OR MORE VALUES - A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage. | 2009-03-12 |
20090067256 | Thin gate stack structure for non-volatile memory cells and methods for forming the same - Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over the tunnel dielectric material to store electrical charge. The storage medium is disposed between a first interface material and a second interface material, each interface material provides a smoother interface between the storage medium and surrounding dielectric materials. A charge blocking material is formed over the storage medium, followed by a control gate material. | 2009-03-12 |
20090067257 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number of operation cycle). Even if a level of the threshold voltage is changed to a level which differs from that of the target voltage by an increase of the accumulated number of operation cycle regardless of the programming operation (or the erasing operation) being normally performed, the reliability of the reading operation can be enhanced to prevent a malfunction of the memory cell from being generated. | 2009-03-12 |
20090067258 | SEMICONDUCTOR MEMORY DEVICE HAVING A CURRENT CONSUMPTION REDUCTION IN A DATA WRITE PATH - The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a particular mode is transferred in correspondence with a prescribed pad. A routing controller allows the representative data to be routed over a transfer path corresponding to any other pads in the particular mode and prevents the general data from being routed over the transfer path in modes other than the particular mode. The semiconductor memory device can reduce current consumption caused by unnecessary toggling of the data through utilization of the routing controller. | 2009-03-12 |
20090067259 | SEMICONDUCTOR MEMORY DEVICE CONFIGURED TO REDUCE CURRENT CONSUMPTION ASSOCIATED WITH CRITICAL EVALUATING OF DATA WRITE OPERATIONS - A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific operational mode and upon deviating from the mode, interrupting the routing of the general data to the transfer pass. | 2009-03-12 |
20090067260 | Buffer control circuit of memory device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller. | 2009-03-12 |
20090067261 | Multi-port memory device - A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group. | 2009-03-12 |
20090067262 | VOLTAGE GENERATING UNIT OF SEMICONDUCTOR MEMORY DEVICE - A voltage generating unit of a semiconductor memory device makes it possible to reduce a peak current value when generating a high voltage. The voltage generating unit of the semiconductor memory device includes a detecting unit configured to detect a voltage level of a high voltage by comparing a reference voltage with a fed-back high voltage, an oscillating unit configured to generate a plurality of clock signals with different operation time points on the basis of an output signal of the detecting unit, and a plurality of pumping units configured to generate the high voltage according to pumping control signals based on the clock signals. | 2009-03-12 |
20090067263 | CORE VOLTAGE DISCHARGE DRIVER - A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal for controlling discharge of the core voltage, and an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit. | 2009-03-12 |
20090067264 | SEMICONDUCTOR MEMORY DEVICE WITH NORMAL AND OVER-DRIVE OPERATIONS - A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and then subsequently normally drives the drive signal with the normal drive voltage. The semiconductor memory device also includes a drive voltage adjuster that detects a level of the over-drive voltage and compensates for a change in the voltage level of the normal drive voltage in response to the detected level of the over-drive voltage. | 2009-03-12 |
20090067265 | SEMICONDUCTOR STORAGE DEVICE - A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell. The plurality of step-down circuits are connected to the bit line, and the plurality of step-down circuits are controlled by step-down control signals different to each other. | 2009-03-12 |
20090067266 | MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE - Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read. | 2009-03-12 |
20090067267 | MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY - A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active. | 2009-03-12 |
20090067268 | APPARATUS AND METHOD FOR CONTROLLING DATA STROBE SIGNAL - Provided are an apparatus and method for controlling a data strobe signal. The apparatus includes a period measurement unit measuring a period of an input clock signal or data strobe signal; a controller determining a read delay time, a setup margin delay time, and a hold margin delay time of the data strobe signal on the basis of the period; a delay circuit unit outputting signals generated by delaying the data strobe signal by the read delay time, the setup margin delay time, and the hold margin delay time; a flip-flop unit latching and outputting input data by using the signals output from the delay circuit unit; and a comparator comparing outputs from the flip-flop unit and feeding a result of the comparison back to the controller. Accordingly, it is possible to stably read data recorded in a memory. | 2009-03-12 |
20090067269 | MEMORY COLUMN REDUNDANCY SCHEME - A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage. | 2009-03-12 |
20090067270 | STRUCTURE FOR IMPROVED MEMORY COLUMN REDUNDANCY SCHEME - A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage. | 2009-03-12 |
20090067271 | SEMICONDUCTOR DEVICE - A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is precharged. A state in a simultaneous access operation is reproduced by activating the word line WLB during a time period of activating the word line WLA regardless of a delay difference of the clock signal and maintaining Vds of an access transistor of A port at a constant value. | 2009-03-12 |
20090067272 | MEMORY COMPILER REDUNDANCY - An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit. Means are provided in the memory instances for comparing incoming memory addresses to address bits for defective memory subunits stored in each memory-instance register. | 2009-03-12 |
20090067273 | SEMICONDUCTOR STORAGE DEVICE - A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply. | 2009-03-12 |
20090067274 | MEMORY DEVICE HAVING AN EVALUATION CIRCUIT - A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch. | 2009-03-12 |
20090067275 | PROJECTION DISPLAY APPARATUS - A projector | 2009-03-12 |
20090067276 | Storing Operational Information in an Array of Memory Cells - The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a column scramble to shift the order of the data units. The method includes storing the data units in memory cells of at least one row of a second block of memory cells, wherein an order of the data units stored in the at least one row of the second block is different than an order of the data units stored in memory cells of the at least one row of the first block. | 2009-03-12 |
20090067277 | Memory device command decoding system and memory device and processor-based system using same - Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode. | 2009-03-12 |
20090067278 | DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal. | 2009-03-12 |
20090067279 | Stand mixer with electronic controls - There is provided a stand mixer comprising a housing ( | 2009-03-12 |
20090067280 | Method for Agitating the Contents of A Reaction Receptacle Within A Temperature-Controlled Environment - An automated analyzer for performing multiple diagnostic assays simultaneously includes multiple stations, or modules, in which discrete aspects of the assay are performed on fluid samples contained in reaction receptacles. The analyzer includes stations for automatically preparing a specimen sample, incubating the sample at prescribed temperatures for prescribed periods, performing an analyte isolation procedure, and ascertaining the presence of a target analyte. An automated receptacle transporting system moves the reaction receptacles from one station to the next. The analyzer further includes devices for carrying a plurality of specimen tubes and disposable pipette tips in a machine-accessible manner, a device for agitating containers of target capture reagents comprising suspensions of solid support material and for presenting the containers for machine access thereto, and a device for holding containers of reagents in a temperature controlled environment and presenting the containers for machine access thereto. A method for performing an automated diagnostic assay includes an automated process for isolating and amplifying a target analyte. The process is performed by automatically moving each of a plurality of reaction receptacles containing a solid support material and a fluid sample between stations for incubating the contents of the reaction receptacle and for separating the target analyte bound to the solid support from the fluid sample. An amplification reagent is added to the separated analyte after the analyte separation step and before a final incubation step. | 2009-03-12 |
20090067281 | COCKTAIL SHAKER - A cocktail shaker uses a motor to cause a container to be shaken. The shaker includes a following member coupled to a following device that is engaged in a directional mechanism, such as a slot or rod. The directional mechanism defines the path and angle of the motion imparted to the container. The throw is defined by the mechanism that transforms rotational motion of a motor to a shaking motion of the container. A mechanism for transforming rotational motion to a shaking motion may include a rotational member and an attachment member pivotally coupled to the rotational member on one end and coupled to the device holding the container on the other end. A combination of throw, path, and motor speed are capable of providing a mechanism for shaking the container that is similar to shaking the container by hand. For example, the motor speed and duration of shaking may be continuously variable or discretely selectable, which may be selected by the user. | 2009-03-12 |
20090067282 | PRECONDITIONER HAVING INDEPENDENTLY DRIVEN HIGH-SPEED MIXER SHAFTS - An improved, dual-shaft preconditioner ( | 2009-03-12 |
20090067283 | VERTICAL MIXER WITH MOVEABLE FLOOR - A vertical mixer assembly for mixing a bulk material is disclosed. The vertical mixer assembly comprises a floor having an upper surface; at least one wall extending from the floor and having an interior surface and an upper edge; the floor and the at least one wall defining an open topped mixing chamber having a general tub-shape suitable for receiving the bulk material; at least one vertical auger positioned in the mixing chamber for mixing the bulk material, the auger having a flight suitable for mixing the bulk material upon operation of the auger; an opening in the mixing chamber for allowing egress of the bulk material, the opening having a wall portion and a floor portion; and a door assembly. The door assembly allows for more consistent unloading of the mixed bulk material and for quicker unloading of the mixed bulk material. The door assembly comprises a side door moveable between a closed position covering the wall portion of the opening and an open position exposing the wall portion of the opening; and a floor section moveable between a closed position covering the floor portion of the opening and an open position exposing the floor portion of the opening. | 2009-03-12 |
20090067284 | TWISTED STATIC PASTE MIXER WITH A DYNAMIC PREMIXING CHAMBER - A device for mixing two paste components, such as a dental impression substance and a catalyst, comprising a tubular housing, two inlet openings for the two paste components to be mixed, and an outlet opening for delivering the mixed paste, is presented. The housing consists of a premixing chamber at the front end and a tubular mixing chamber at the rear end. The two paste components are mixed first in the premixing chamber by a dynamic rotor and then mixed in the tubular mixing chamber by a twisted static shaft, resulting in a well mixed, bubble-free paste at the outlet opening of the housing. | 2009-03-12 |
20090067285 | 3D DEGHOSTING OF MULTICOMPONENT OR OVER / UNDER STREAMER RECORDINGS USING CROSS-LINE WAVENUMBER SPECTRA OF HYDROPHONE DATA - A technique includes obtaining pressure data that was acquired by seismic sensors towed as part of a three-dimensional spread of streamers and obtaining particle motion data, which are indicative of particle motion at locations of the sensors. The technique includes estimating cross-line spectra of the pressure data based at least in part on the pressure data, and the technique includes deghosting the particle motion data based at least in part on the estimated cross-line spectra. | 2009-03-12 |
20090067286 | DISPERSION EXTRACTION FOR ACOUSTIC DATA USING TIME FREQUENCY ANALYSIS - This invention pertains to the extraction of the slowness dispersion characteristics of acoustic waves received by an array of two or more sensors by the application of a continuous wavelet transform on the received array waveforms (data). This produces a time-frequency map of the data for each sensor that facilitates the separation of the propagating components thereon. Two different methods are described to achieve the dispersion extraction by exploiting the time frequency localization of the propagating mode and the continuity of the dispersion curve as a function of frequency. The first method uses some features on the modulus map such as the peak to determine the time locus of the energy of each mode as a function of frequency. The second method uses a new modified Radon transform applied to the coefficients of the time frequency representation of the waveform traces received by the aforementioned sensors. Both methods are appropriate for automated extraction of the dispersion estimates from the data without the need for expert user input or supervision | 2009-03-12 |