11th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090065786 | PROCESS FOR PRODUCING THIN NITRIDE FILM ON SAPPHIRE SUBSTRATE AND THIN NITRIDE FILM PRODUCING APPARATUS - A method for growing a nitride thin film on a sapphire substrate, in which using no resists, miniaturization can be accomplished while relieving vexatious complication of the process; and a relevant device using nitride thin film. There is provided a method for growing a nitride thin film on a sapphire substrate, comprising irradiating a sapphire substrate having undergone high temperature hydrogen treatment with electron beams and depositing a nitride thin film on the substrate having undergone the electron beam irradiation by using the metal-organic chemical vapor deposition technique to thereby accomplish patterning of nitride thin film. | 2009-03-12 |
20090065787 | COMPOUND SEMICONDUCTOR STRUCTURE - A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×10 | 2009-03-12 |
20090065788 | Semiconductor substrate with islands of diamond and resulting devices - Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed. | 2009-03-12 |
20090065789 | LED chip package structure with high-efficiency light-emitting effect and method of packing the same - An LED chip package structure with high-efficiency light-emitting effect includes a substrate unit, a light-emitting unit, and a package colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace respectively formed on the substrate body. The light-emitting unit has a plurality of LED chips arranged on the substrate body. Each LED chip has a positive electrode side and a negative electrode side respectively and electrically connected with the positive electrode trace and the negative electrode trace of the substrate unit. The package colloid unit has a plurality of package colloids respectively covered on the LED chips. Each package colloid has a colloid cambered surface and a colloid light-emitting surface respectively formed on a top surface and a front surface thereof. | 2009-03-12 |
20090065790 | LED chips having fluorescent substrates with microholes and methods for fabricating - Methods for fabricating semiconductor devices such as LED chips at the wafer level, and LED chips and LED chip wafers fabricated using the methods. An LED chip wafer according to the present invention comprises a plurality of LEDs on a wafer and a plurality of pedestals, each of which is on one of the LEDs. A fluorescent substrate or preform (“preform”) is provided covering at least some of the LEDs, the preform comprising holes with the pedestals arranged within the holes. During operation of the covered ones of said LEDs at least some light from the LEDs passes through the preform and is converted. LED chips are provided that are singulated from this LED chip wafer. One embodiment of a method for fabricating LED chips from a wafer comprises depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. Pedestals are formed on the LEDs and a fluorescent preform is formed with holes. The fluorescent preform is bonded over at least some of the plurality of LEDs so that at least some light from the covered ones of said LEDs passes through the preform and is converted. The pedestals are arranged in the holes so that an electrical signal is applied to the LEDs through the pedestals. | 2009-03-12 |
20090065791 | WHITE LIGHT LED WITH MULTIPLE ENCAPSULATION LAYERS - Light-emitting semiconductor devices with multiple encapsulation layers having more uniform white light when compared to conventional light-emitting devices and methods for producing the same are provided. The uniformity of the emitted white light may be quantified by comparing correlated color temperature (CCT) variations between devices, where embodiments of the present invention have a lower CCT variation when compared to conventional devices over a substantial range of light emission angles. | 2009-03-12 |
20090065792 | METHOD OF MAKING AN LED DEVICE HAVING A DOME LENS - A method of making a light emitting device is disclosed herein. The method includes providing an LED die and dispensing a photopolymerizable composition to form a photopolymerizable dome lens, wherein the photopolymerizable composition is optically coupled to the LED die. The photopolymerizable dome lens may be formed by the photopolymerizable composition using a single drop or a plurality of drops. In one embodiment, the photopolymerizable composition comprises a metal-containing catalyst and a silicon-containing resin comprising silicon-bonded hydrogen and aliphatic unsaturation. The photopolymerizable dome is polymerized to form a polymerized dome lens. Light emitting devices prepared according to the methods are also described. | 2009-03-12 |
20090065793 | LIGHT EMITTING DEVICE - A light emitting device is disclosed herein. An embodiment of the light emitting device comprises a substrate and a reflector extending from the substrate. The reflector forms a cavity in conjunction with the substrate. A light emitter is located in the cavity. At least one first recessed portion is located in the reflector, the at least one first recessed portion extends substantially axially around the reflector. | 2009-03-12 |
20090065794 | Light emitting diode device and manufacturing method therof - A light-emitting diode (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first type conductivity semiconductor layer, an active layer, a second type conductivity semiconductor layer, a transparent conductive oxide stack structure, a first electrode, and a second electrode. The first semiconductor layer on the substrate has a first portion and a second portion. The active layer and the second semiconductor layer are subsequently set on the first portion. The transparent conductive oxide stack structure on the second semiconductor layer has at least two resistant interfaces. The first electrode is above the second portion, and the second electrode is above the transparent conductive oxide stack structure. | 2009-03-12 |
20090065795 | TRANSPARENT CONDUCTIVE FILM ON P-TYPE LAYER FOR GAN-BASED LED AND METHOD FOR FABRICATING THE SAME - The present disclosure provides a transparent conductive film on P-type layer of GaN-based LED and a fabricating method thereof. The transparent conductive film is fabricated by Ni/ITO, Al/ITO or NiO/ITO. In one embodiment, the thickness of the Ni layer is 5 Å to 30 Å. The thickness of the Al layer is 5 Å to 30 Å. The thickness of the NiO layer is 5 Å to 40 Å. The thickness of the ITO layer is 1000 Å to 3000 Å. In one embodiment, the fabricating method comprises steps of evaporating one of Ni, Al and NiO layers on a P-type GaN layer, heat-treating a wafer on which the Ni or Al layer is evaporated, then evaporating an ITO layer on the surface of Ni, Al or NiO layer, and heat-treating the wafer on which Ni/ITO, Al/ITO or NiO/ITO layers are evaporated. The transparent conductive film can have high light transmittance within the range of visible light and low specific contact resistance. | 2009-03-12 |
20090065796 | SURFACE MOUNT LIGHT EMITTING APPARATUS - A surface mount LED apparatus is provided which can prevent separation of the surface of an LED chip from a sealing resin portion. Patterned circuits on a substrate are provided with a device mounting region and a wire bond region, and an increased-thickness portion having a thickness 1.6 times or more than the greater of the thickness of the device mounting region and the thickness of the wire bond region. When the apparatus is heated, this configuration allows for inducing interfacial separation between the increased-thickness portion and the sealing resin portion earlier than interfacial separation is induced between the LED chip and the sealing resin portion. This configuration can prevent interfacial separation between the LED chip and the sealing resin portion. | 2009-03-12 |
20090065797 | Light emitting unit and liquid crystal display device using the same - A light emitting unit capable of widely adjusting brightness or size, and a liquid crystal display device using the same are disclosed. The light emitting unit includes a circuit board including circuit lines having a plurality of connecting members, and a plurality of unit module connected to the connecting members of the circuit board. The unit module is coupled with at least one light emitting device. | 2009-03-12 |
20090065798 | PACKAGING TECHNIQUE FOR THE FABRICATION OF POLARIZED LIGHT EMITTING DIODES - A polarized light emitting diode (LED) includes a marker indicating a polarization direction. A package for the LED also includes a marker indicating the polarization direction. The markers on the LED and package are used for mutual alignment, wherein the LED is attached in a favorable orientation with respect to a package, so that the polarization direction of emitted light from the package is apparent. The marker is placed on the LED before die separation and the marker is placed on the package before alignment. The marker on the LED comprises a photolithographic pattern, an asymmetric die shape, a notch on the die, or a scratch on the die, while the marker on the package comprises an electrode shape or pattern, an asymmetric package shape, a notch on the package, or a scratch on the package. Finally, the LED or package may be installed in an external circuit or system that also indicates the polarization direction. | 2009-03-12 |
20090065799 | LIGHT EMITTING DIODE PACKAGE - The present invention relates to a light emitting diode package, and provides a light emitting diode package employing a thermoelectric element therein. The light emitting diode package of the present invention is constructed such that the thermoelectric element is coupled to a housing or formed of a substrate itself so as to directly dissipate heat generated from a light emitting chip. Thus, the heat generated from the light emitting chip can be efficiently dissipated from the interior of the package to the outside, without an additional heat dissipation means. In addition, an external heat sink may be coupled to the thermoelectric element to more efficiently dissipate the heat from the light emitting chip. | 2009-03-12 |
20090065800 | OPTOELECTRONIC COMPONENT, DEVICE COMPRISING A PLURALITY OF OPTOELECTRONIC COMPONENTS, AND METHOD FOR THE PRODUCTION OF AN OPTOELECTRONIC COMPONENT - Disclosed is an optoelectronic component ( | 2009-03-12 |
20090065801 | Surface plasmon polariton actuated transistors - A surface plasmon polaritron activated semiconductor device uses a surface plasmon wire that functions as an optical waveguide for fast communication of a signal and functions as a energy translator using a wire tip for translating the optical signal passing through the waveguide into plasmon-polaritron energy at a connection of the semiconductor device, such as a transistor, to activate the transistor for improved speed of communications and switching for preferred use in digital systems. | 2009-03-12 |
20090065802 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: an element forming region of a semiconductor substrate isolated by an element isolating region formed in the semiconductor substrate; an insulating film formed on the semiconductor substrate; an opening portion formed in the insulating film to include a region to be selectively epitaxially grown in the element forming region; and a semiconductor layer formed by selective epitaxial growth of the element forming region of the semiconductor substrate in the opening portion. | 2009-03-12 |
20090065803 | Space-Charge-Free Semiconductor and Method - A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at T | 2009-03-12 |
20090065804 | BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME - Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap. | 2009-03-12 |
20090065805 | Method and structure using a pure silicon dioxide hardmask for gate pattering for strained silicon MOS transistors - A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region. | 2009-03-12 |
20090065806 | MOS TRANSISTOR AND FABRICATION METHOD THEREOF - A MOS transistor and a fabrication method thereof are disclosed. The mobility of electrons or holes serving as charge carriers of the MOS transistor can be improved by forming a lattice stress-causing material in source/drain regions of a MOS transistor or by forming a gapping layer having a tensile stress in the MOS transistor. As a result, a driving current of the MOS transistor may be reduced. | 2009-03-12 |
20090065807 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a first MIS transistor formed on a first region of a first conductivity type in a semiconductor substrate; and a second MIS transistor formed on a second region of a second conductivity type in the semiconductor substrate. The first MIS transistor has a first gate insulating film and a first gate electrode formed on the first region, first sidewalls formed on the side faces of the first gate electrode, and first source/drain regions made of silicon formed in portions of the first region. The second MIS transistor has a second gate insulating film and a second gate electrode formed on the second region, second sidewalls formed on the side faces of the second gate electrode, and second source/drain regions including silicon germanium formed in portions of the second region. The second sidewalls are smaller in height than the first sidewalls. | 2009-03-12 |
20090065808 | SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL - A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases I | 2009-03-12 |
20090065809 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided in which a stress can be effectively applied from a semiconductor layer having a different lattice constant from a semiconductor substrate to a channel part, whereby carrier mobility can be improved and higher functionality can be achieved. In a semiconductor device | 2009-03-12 |
20090065810 | III-NITRIDE BIDIRECTIONAL SWITCHES - Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical contact with a drain of the second transistor. In some embodiments, the two transistors share a drift region and the switch is free of a drain contact between the two transistors. Matrix converters can be formed from the bidirectional switches. | 2009-03-12 |
20090065811 | Semiconductor Device with OHMIC Contact and Method of Making the Same - A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped semiconductor contact layer, forming an adhesive contact portion over the platinum contact portion, forming a barrier contact portion over the adhesive contact portion, and forming a gold contact portion over the barrier contact portion. The method further comprises annealing the semiconductor structure to alloy the platinum contact portion with the N-type doped semiconductor contact layer to form a platinum/semiconductor alloyed diffusion contact barrier substantially disposed within the N-type doped semiconductor contact layer. | 2009-03-12 |
20090065812 | COMPOUND SEMICONDUCTOR SUBSTRATE - Provides is a compound semiconductor substrate about which the thickness of its nitride semiconductor single crystal layer can be made large while the generation of cracks, crystal defects or the like is restrained in the nitride semiconductor single crystal layer. The substrate has a first intermediate layer | 2009-03-12 |
20090065813 | CONFIGURING STRUCTURED ASIC FABRIC USING TWO NON-ADJACENT VIA LAYERS - An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells. | 2009-03-12 |
20090065814 | MOS device with schottky barrier controlling layer - A semiconductor device is formed on a semiconductor substrate. The semiconductor device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and the body into the drain, an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain form a Schottky diode, and a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench. | 2009-03-12 |
20090065815 | Solid-state imaging device and imaging apparatus - A solid-state imaging device includes a semiconductor substrate and a plurality of photoelectric conversion elements provided in the semiconductor substrate, wherein the plurality of photoelectric conversion elements include: effective photoelectric conversion elements which are photoelectric conversion elements for obtaining an imaging signal corresponding to light from a subject; and OB photoelectric conversion elements which are photoelectric conversion elements for obtaining a reference signal of an optical black level, and the solid-state imaging device further includes a first shielding layer provided at least over the effective pixel area as defined herein and having an opening provided at least over a part of the effective photoelectric conversion elements, and a second shielding layer provided over the OB pixel area as defined herein and electrically separated from the first shielding layer. | 2009-03-12 |
20090065816 | MODULATING THE STRESS OF POLY-CRYSTALINE SILICON FILMS AND SURROUNDING LAYERS THROUGH THE USE OF DOPANTS AND MULTI-LAYER SILICON FILMS WITH CONTROLLED CRYSTAL STRUCTURE - In certain embodiments a method of forming a multi-layer silicon film is provided. A substrate is placed in a process chamber. An amorphous silicon film is formed on the substrate by flowing into the process chamber a first process gas comprising a silicon source gas. A polysilicon film is formed on the amorphous silicon film by flowing into the deposition chamber a first process gas mix comprising a silicon source gas and a first dilution gas mix comprising H | 2009-03-12 |
20090065817 | DIELECTRIC SPACER REMOVAL - The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate. | 2009-03-12 |
20090065818 | STRUCTURE FOR IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 2009-03-12 |
20090065819 | APPARATUS AND METHOD OF MANUFACTURE FOR AN IMAGER STARTING MATERIAL - An imager apparatus and associated starting material are provided. Such starting material includes a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Further included is a first doped layer disposed adjacent to the oxide layer with a first doping, and a second doped layer disposed adjacent to the first doped layer with, a second doping that is less than the first doping layer. | 2009-03-12 |
20090065820 | Method and structure for simultaneously fabricating selective film and spacer - The present invention provides a method for simultaneously fabricating a selective film and a spacer. First, a semiconductor substrate is provided and a first device area and a second device area are defined on the semiconductor substrate. At least a gate is formed on the semiconductor substrate in the second device area. Subsequently, at least a dielectric material is formed on the semiconductor substrate and the dielectric material covers the first device area and the second device area. A patterned mask is then formed on a portion of the dielectric material. Subsequently, an etching process is carried out to remove the dielectric material not covered by the patterned mask, thereby a selective film is formed in the first device area and simultaneously spacers are formed on the sidewalls of the gate in the second device area. Finally, the patterned mask is removed. | 2009-03-12 |
20090065821 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - An image sensor and fabricating method thereof for preventing cross-talk between neighboring pixels by providing at least three light-shield walls combining to extend vertically above a lateral periphery of a photodiode for deflecting light from a microlens array towards the photodiode. | 2009-03-12 |
20090065822 | Image Sensor and Method for Manufacturing an Image Sensor - Provided are methods for manufacturing an image sensor. A method for manufacturing an image sensor can include: forming a readout circuitry on a substrate; forming an electrical junction region in the substrate; forming an interconnection connected to the electrical junction region; and forming an image sensing device on the interconnection. The readout circuitry can be formed on a first substrate. The electrical junction region can be formed in the first substrate to electrically connect the image sensing device with the readout circuitry. The image sensing device can be formed using a second substrate that is then bonded on the interconnection. | 2009-03-12 |
20090065823 | Image Sensor and Method for Manufacturing an Image Sensor - Provided is an image sensor. The image sensor can include a readout circuitry on a first substrate, an electrical junction region in the first substrate electrically connected with the readout circuitry, and an interconnection on the first substrate. The interconnection can be formed for connection to the electrical junction region. An image sensing device can be formed on the interconnection. | 2009-03-12 |
20090065824 | Image Sensor and Manufacturing Method Thereof - An image sensor can be formed of a first substrate having a readout circuitry, an interlayer dielectric, and lower lines, and a second substrate having a photodiode. The first substrate comprises a pixel portion and a peripheral portion. The readout circuitry is formed on the pixel portion. The interlayer dielectric is formed on the pixel portion and the peripheral portion. The lower lines pass through the interlayer dielectric to electrically connect with the readout circuitry and the peripheral portion. The photodiode is bonded to the first substrate and etched to correspond to the pixel portion. A transparent electrode is formed on the interlayer dielectric on which the photodiode is formed such that the transparent electrode can be connected with the photodiode and the lower line in the peripheral portion. A first passivation layer can be formed on the transparent electrode. In one embodiment, the first passivation layer includes a trench exposing a portion of the transparent electrode. Then, an upper line can be formed on the peripheral portion and in the trench to shield a lateral side of the photodiode. | 2009-03-12 |
20090065825 | Image Sensor and Manufacturing Method Thereof - Provided is an image sensor. The image sensor comprises an interlayer dielectric, lines, and a crystalline semiconductor layer including photodiodes and a device isolation region. The interlayer dielectric can be formed on a first substrate comprising a readout circuitry. The lines pass through the interlayer dielectric to connect with the readout circuitry, and each line is formed according to unit pixel. The crystalline semiconductor layer can be bonded on the interlayer dielectric including the lines. The photodiodes, formed inside the crystalline semiconductor layer, are electrically connected with the lines. The device isolation region comprises conductive impurities and is formed inside the crystalline semiconductor layer so that the photodiodes can be separated according to unit pixels. | 2009-03-12 |
20090065826 | Image Sensor and Method for Manufacturing the Same - Provided is an image sensor. The image sensor can include a first substrate, an image sensing device and a light shielding layer. The first substrate includes a readout circuitry and an interconnection. The image sensing device is formed on the interconnection. The light shielding layer is formed in portions of the image sensing device on a boundary between pixels. | 2009-03-12 |
20090065827 | Image Sensor and Manufacturing Method Thereof - Provided is an image sensor. The image sensor can include a readout circuitry on a first substrate. An interlayer dielectric is formed on the first substrate, and comprises a lower line therein. A crystalline semiconductor layer is bonded to the interlayer dielectric. A photodiode can be formed in the crystalline semiconductor layer, and comprises a first impurity region and a second impurity region. A via hole can be formed passing through the crystalline semiconductor layer and the interlayer dielectric to expose the lower line. A plug is formed inside the first via hole to connect with only the lower line and the first impurity region. A device isolation region can be formed in the crystalline semiconductor layer to separate the photodiode according to unit pixel. | 2009-03-12 |
20090065828 | Image Sensor and Manufacturing Method Thereof - Provided is an image sensor. The image sensor can include a first substrate comprising a pixel portion in which a readout circuitry is provided and a peripheral portion in which a peripheral circuitry is provided. An interlayer dielectric including lines can be formed on the first substrate to connect with the readout circuitry and the peripheral circuitry. A crystalline semiconductor layer can be provided on a portion of the interlayer dielectric corresponding to the pixel portion through a bonding process. The crystalline semiconductor layer can include a first photodiode and second photodiode. The first and second photodiodes can be defined by device isolation trenches in the crystalline semiconductor layer. A device isolation layer can be formed on the crystalline semiconductor layer comprising the device isolation trenches. An upper electrode layer passes through the device isolation layer to connect with a portion of the first photodiode. An expose portion can be formed in the upper electrode layer to selectively expose an upper region of the first photodiode. A passivation layer can be formed on the first substrate on which the expose portion is provided. | 2009-03-12 |
20090065829 | Image Sensor and Method for Manufacturing the Same - Provided are image sensors and a method of manufacturing the same. The image sensor can include a semiconductor substrate having a metal line and a readout circuitry formed thereon; a photodiode on the semiconductor substrate, the photodiode including a first impurity region and a second impurity region horizontally arranged in a crystalline region; and a first contact and a second contact penetrating the photodiode. The first contact can penetrate the first impurity region of the photodiode, and the second contact can penetrate the second impurity region to connect with the metal line. | 2009-03-12 |
20090065830 | Image Sensor and a Method for Manufacturing the Same - An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a center region and an edge region, each with a gate. A first impurity region and a second impurity region can be provided in the semiconductor substrate to a first side of each gate. A floating diffusion region can be provided to a second side of teach gate. A third impurity region can be provided in the semiconductor substrate to the first side of the gate in the edge region. | 2009-03-12 |
20090065831 | Image Sensor and Method for Manufacturing the Same - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate including a CMOS circuit, a dielectric layer including a metal interconnection on the semiconductor substrate, a bottom electrode on the metal interconnection, in which the bottom electrode has at least one protrusion, a photodiode on the dielectric layer and the bottom electrode, and a top electrode on the photodiode. | 2009-03-12 |
20090065832 | SOLID-STATE IMAGING DEVICE - It is an object of the present invention to provide an image sensor having a high ratio of a surface area of a light receiving element to a surface area of one pixel. The above-described object is achieved by an inventive solid-state imaging device unit comprising solid-state imaging devices arranged on a substrate according to the present invention. The solid-state imaging device comprises a signal line formed on the substrate, an island shaped semiconductor placed over the signal line, and a pixel selection line connected to an upper portion of the island shaped semiconductor. The island shaped semiconductor comprises a first semiconductor layer disposed in a lower portion of the island shaped semiconductor and connected to the signal line, a second semiconductor layer disposed adjacent to an upper side of the first semiconductor layer, a gate connected to the second semiconductor layer via an insulating film, an electric charge accumulator comprising a third semiconductor layer connected to the second semiconductor layer and carrying a quantity of electric charges which varies in response to a light reception, and a fourth semiconductor layer disposed adjacent to an upper side of the second semiconductor layer and the third semiconductor layer and connected to the pixel selection line. The solid-state imaging devices are arranged on the substrate in a honeycomb configuration. | 2009-03-12 |
20090065833 | CMOS IMAGE SENSOR - A CMOS image sensor is described, based on a substrate and including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, a photodiode and a floating node structure. The substrate includes a floating node area between the transfer transistor and the reset transistor. The floating node structure includes a P-well in the substrate within the floating node area, an N-well in the substrate outside of the floating node region, a lightly N-doped region having a portion in the P-well and another portion connected with the N-well, a heavily N-doped region in the N-well, and a contact plug for coupling the heavily N-doped region to the source follower transistor. | 2009-03-12 |
20090065834 | IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 2009-03-12 |
20090065835 | Capacitorless DRAM and methods of manufacturing and operating the same - Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer. | 2009-03-12 |
20090065836 | SEMICONDUCTOR DEVICE HAVING MIM CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having an MIM capacitor and a method of manufacturing the same. In one example embodiment, a semiconductor device having an MIM capacitor includes a lower electrode including a pair of metal patterns spaced apart from each other, a dielectric formed so as to cover the surfaces of the spaced-apart metal patterns of the lower electrode, a metal plug formed on the dielectric, and an upper electrode made of a metal and formed on the metal plug. | 2009-03-12 |
20090065837 | SEMICONDUCTOR MEMORY DEVICE HAVING CAPACITOR FOR PERIPHERAL CIRCUIT - Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line. | 2009-03-12 |
20090065838 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - An improved semiconductor memory device having a silicon on insulator (SOI) structure. Exemplary devices provide improved charge injection into the device's floating gate electrode. Exemplary devices may include a semiconductor substrate including a transistor forming region and a capacitor forming region; a MOSFET; a MOS capacitor; a projection formed within a periphery of the capacitor electrode of the MOS capacitor; and a floating gate electrode extending from the channel region of the MOSFET to overlap the projection of the capacitor electrode, with a gate insulating film interposed therebetween. The projection may include an inclined surface which may have a concave shape and/or the projection may extend above a capacitor groove having a undercut portion beneath the projection. | 2009-03-12 |
20090065839 | Driver for Driving a Load Using a Charge Pump Circuit - A charge pump circuit includes MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a multiplicity of first electrodes formed in one region of the substrate, insulating layers formed on/above respective substrate regions between neighboring first electrodes, each layer covering at least the respective substrate region, and a multiplicity of second electrodes formed on/above the respective insulating layers. The MOS capacitors have improved frequency response. | 2009-03-12 |
20090065840 | FLASH MEMORY AND MANUFACTURING METHOD OF THE SAME - A flash memory and a manufacturing method of the same includes a shallow trench isolation and an active region formed at a substrate, a plurality of stacked gates formed on and/or over the active region, a deep implant region formed at a lower portion of the shallow trench isolation and the active region between the stacked gates and a shallow implant region formed at a surface of the active region between the stacked gates. | 2009-03-12 |
20090065841 | SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS - An improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM). SiON (silicon oxy-nitride) may be used in lieu of SiN (silicon nitride), for the CESL. Or, the CESL may be processed to be discontinuous, to reduce stress effects, using either conventional SiN (silicon nitride) or SiON. Or, the CESL layer may be eliminated entirely, to reduce stress effects. | 2009-03-12 |
20090065842 | Ta-lined tungsten plugs for transistor-local hydrogen gathering - The present electronic device includes a dielectric body having an opening therein. A tantalum layer is provided in the opening of the dielectric body, the layer having the characteristic of absorbing hydrogen with decrease in temperature, and releasing hydrogen with increase in temperature. A conductive tungsten plug is provided on the layer in the opening. | 2009-03-12 |
20090065843 | Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Flash Memory Structures - Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the bottom of the photoresist mask sidewalls and remove at least the majority of the foot regions. In some embodiments, trenches may be formed adjacent the photoresist mask sidewalls in a material that is beneath the photoresist mask. Another material may be formed to have projections extending into the trenches. Such projections may assist in anchoring said other material to the material that is beneath the photoresist mask. In some embodiments, the photoresist mask is utilized for patterning flash memory structures. Some embodiments include semiconductor constructions having materials anchored to underlying materials through fang-like projections. | 2009-03-12 |
20090065844 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells each having a double-layered gate structure in which a floating gate and a control gate formed of a nickel silicide film are laminated, a first contact plug formed on a substrate contact portion of a surface of the semiconductor substrate, the first contact plug having a lower layer formed of a semiconductor film and an upper layer formed of a nickel silicide film, and second contact plugs formed on the control gates and first contact plug. | 2009-03-12 |
20090065845 | Embedded semiconductor device and method of manufacturing an embedded semiconductor device - Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance. | 2009-03-12 |
20090065846 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure. | 2009-03-12 |
20090065847 | FLASH MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate. | 2009-03-12 |
20090065848 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atoms or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film. | 2009-03-12 |
20090065849 | Semiconductor device and method for manufacturing the same - To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having a low concentration of hydrogen and a lower region having a high concentration of hydrogen. Such a silicon nitride film is formed in such a manner that a silicon nitride film including 15 atomic % or more hydrogen is formed by a chemical vapor deposition method and an upper portion of the silicon nitride film is nitrided. The nitridation treatment is performed by nitriding the silicon nitride film by nitrogen radicals produced in plasma of a nitrogen gas. | 2009-03-12 |
20090065850 | NON-VOLATILE MEMORY DEVICES - According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability. | 2009-03-12 |
20090065851 | OPERATING METHOD OF NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN to tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased. | 2009-03-12 |
20090065852 | NONVOLATILE MEMORY DEVICE WITH NANOWIRE CHANNEL AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished. | 2009-03-12 |
20090065853 | FIN FIELD EFFECT TRANSISTOR - Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si | 2009-03-12 |
20090065854 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes second-conductive-type drift areas formed in a first-conductive-type well of a semiconductor substrate while being spaced apart from each other a vertical area protruding from the drift areas, and a second-conductive-type source/drain area formed on the vertical area. The vertical area can provide an extended drift area for a current path | 2009-03-12 |
20090065855 | MOS device with integrated schottky diode in active region contact trench - A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench. | 2009-03-12 |
20090065856 | Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device - In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode | 2009-03-12 |
20090065857 | RAISED VERTICAL CHANNEL TRANSISTOR DEVICE - A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices. | 2009-03-12 |
20090065858 | DMOS TRANSISTOR AND FABRICATION METHOD THEREOF - In one example embodiment, a method of fabricating a DMOS transistor includes various steps. First, a P-type well or an N-type well is formed on a semiconductor substrate by an impurity injection. Next, a drift region is formed on the portion of the semiconductor substrate in which the well region is formed by injecting conductive impurities reverse to those of the well region. Then, a trench for forming a gate on the semiconductor substrate is formed within the drift region. Next, a gate oxide and a gate electrode are formed in the trench. Finally, source/drain regions are formed by injecting the same conductive impurities as those of the drift region at both sides of the gate electrode. | 2009-03-12 |
20090065859 | TRENCH TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A trench transistor and a manufacturing method for the same are disclosed. The manufacturing method includes preparing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a gate oxide layer over an inner wall of the trench, forming a gate having a first conductivity type by embedding polysilicon in the trench, the gate including a protruding portion protruding over a surface of the semiconductor substrate, forming a barrier layer by implanting second conductivity type ions in the protruding portion, and forming a second conductivity type source region over the surface of the semiconductor substrate. | 2009-03-12 |
20090065860 | Semiconductor device and method for manufacturing the same - An exemplary object of the invention is to simultaneously achieve, in a semiconductor device which includes a trench gate structure formed by recessing a portion of a diffusion layer and an inter-diffusion-layer isolation insulating film which are formed on the a semiconductor substrate, good embeddability of the inter-diffusion-layer isolation insulating film and a reduction in channel resistance. In an exemplary embodiment, the diffusion layer which comprises a projecting structure is formed by selectively wet-etching the inter-diffusion-layer isolation insulating film with respect to the diffusion layer in the trench, and an overhanging structure is formed at a projecting portion of the diffusion layer further by selectively epitaxially growing the projecting structure of the diffusion layer. | 2009-03-12 |
20090065861 | MOS device with low injection diode - A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and into the body, an active region contact electrode disposed within the active region contact trench, wherein a thin layer of body region separating the active region contact electrode from the drain. | 2009-03-12 |
20090065862 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer. | 2009-03-12 |
20090065863 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - In one example embodiment, an LDMOS device includes a first n-type well formed on a p-type substrate, a plurality of isolation layers formed in the first n-type well, a p-type ion implantation region formed on a surface of each of the isolation layers, and a gate selectively formed on the first n-type well and the isolation layers. | 2009-03-12 |
20090065864 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device and a method of fabricating the same are provided. The semiconductor device can include a buried conductive layer in a semiconductor substrate, an epitaxial layer on the buried conductive layer, and a plug passing through the epitaxial layer. The plug can be electrically connected to the buried conductive layer and can have an insulating layer around it, isolating the plug from an adjacent active area. | 2009-03-12 |
20090065865 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and source/drain regions provided on the transistor structure. Accordingly, transistor operations can utilize the current path above and below the gate electrode. | 2009-03-12 |
20090065866 | Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie - Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric. | 2009-03-12 |
20090065867 | ORIENTATION-OPTIMIZED PFETS IN CMOS DEVICES EMPLOYING DUAL STRESS LINERS - A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 | 2009-03-12 |
20090065868 | Electronic Circuit and Method of Manufacturing an Electronic Circuit - An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected. | 2009-03-12 |
20090065869 | SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1. | 2009-03-12 |
20090065870 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material. | 2009-03-12 |
20090065871 | SEMICONDUCTOR CHIP AND PROCESS FOR FORMING THE SAME - A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures. | 2009-03-12 |
20090065872 | FULL SILICIDE GATE FOR CMOS - A method is provided for fabricating an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”) in which the NFET and PFET are formed after which a protective hard mask layer, e.g., a dielectric stressor layer is formed to overlie edges of gates, source regions and drain regions of the PFET and NFET. Sputter etching can be used to remove a portion of the protective hard mask layer to expose the gates of the PFET and NFET. The semiconductor elements can be etched selectively with respect to the protective hard mask layer to reduce a thickness of the semiconductor elements. A metal may then be deposited and caused to react with the reduced thickness semiconductor element to form silicide elements of the gates. | 2009-03-12 |
20090065873 | Semiconductor device and method of fabricating metal gate of the same - Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low. | 2009-03-12 |
20090065874 | SEMICONDUCTOR MEMORY DEVICE HAVING LAYOUT AREA REDUCED - A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell. | 2009-03-12 |
20090065875 | METAL-OXIDE-SEMICONDUCTOR DEVICE WITH A DOPED TITANATE BODY - A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate ( | 2009-03-12 |
20090065876 | Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer. | 2009-03-12 |
20090065877 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed on the first insulating film; a first sidewall insulating film formed at side portions of the first gate electrode; a first single-crystal silicon layer formed on each of the first source and drain regions, and having at least an upper-face made of a {111} plane; a first NiSi layer formed at least on the first single-crystal silicon layer, and having a portion whose interface with the first single-crystal silicon is on the {111} plane of the first single-crystal silicon layer and a part of the portion of the first NiSi layer being in contact with the first sidewall insulating film; and a first TiN film being in contact with the portion of the first NiSi layer on the {111} plane of the first single-crystal silicon. | 2009-03-12 |
20090065878 | DIKETOPYRROLOPYRROLE-BASED DERIVATIVES FOR THIN FILM TRANSISTORS - A thin film transistor device includes a semiconductor layer. The semiconductor layer includes a compound comprising a chemical structure represented by: | 2009-03-12 |
20090065879 | HIGH VOLTAGE DEVICE AND METHOD OF FABRICATING THE SAME - A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer. | 2009-03-12 |
20090065880 | Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region - In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal. | 2009-03-12 |
20090065881 | Electric Field Concentration Minimization for MEMS - A method and resulting device for reducing an electrical field at an isolation gap in a capacitive actuator includes providing a bottom electrode layer and forming a pattern in the bottom electrode layer having an isolation gap between center and outer electrode components of the patterned electrode. A spacing material is deposited in the isolation gap, the spacing material having a greater height than a remainder of the patterned electrode, and a sacrificial material is deposited conformably on a surface of the patterned electrode and spacing material. The method also includes applying a deformable electrode to a surface of the sacrificial material, whereby removal of the sacrificial and spacing materials results in a greater spacing between the deformable electrode and the electrode layer at a region of the isolation gap than over a remainder of the spacing between the patterned electrode layer and deformable surface. | 2009-03-12 |
20090065882 | Semiconductor device, lead frame, and microphone package therefor - A semiconductor device is constituted of a mold sheet for mounting a sensor chip and a cover having a box-like shape, both of which are combined together so as to form a cavity therebetween. The mold sheet includes a stage having a rectangular shape in a plan view, a plurality of cutouts formed in the periphery of the stage, and a plurality of lead terminals arranged inside of the cutouts. The lead terminals include a plurality of connection portions electrically connected to the sensor chip and a plurality of support leads which are externally extended from the periphery of the stage. The stage and the lead terminals are sealed with a mold resin, by which they are electrically insulated from each other. The recesses of the support leads are sealed with the insulating resin mold relative to the surface of the mold sheet so as to mount the opening end of the cover. | 2009-03-12 |
20090065883 | MRAM Device with Continuous MTJ Tunnel Layers - A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units. | 2009-03-12 |
20090065884 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device is provided and includes: a semiconductor substrate; a plurality of photoelectric conversion elements arranged in a two-dimensional array in a surface portion of the semiconductor substrate; a conductive light shielding film above the surface portion, the conductive light shielding film having openings at a light-incident side of the respective photoelectric conversion elements; a connection pad formed in the semiconductor substrate and to be applied with a voltage from outside the solid-state imaging device; and a wiring that connects the connection pad and the conductive light shielding film, wherein the wiring has a wiring structure having a time constant smaller than that of one linear wiring. | 2009-03-12 |
20090065885 | Image Sensor and Method for Manufacturing the Same - Provided is an image sensor and method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and a circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline semiconductor layer and electrically connected with the lower metal line. A light shielding layer is formed in regions of the photodiode. | 2009-03-12 |