10th week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120056237 | SEMICONDUCTOR COMPOUND STRUCTURE AND METHOD OF FABRICATING THE SAME USING GRAPHENE OR CARBON NANOTUBES, AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR COMPOUND STRUCTURE - A semiconductor compound structure and a method of fabricating the semiconductor compound structure using graphene or carbon nanotubes, and a semiconductor device including the semiconductor compound structure. The semiconductor compound structure includes a substrate; a buffer layer disposed on the substrate, and formed of a material including carbons having hexagonal crystal structures; and a semiconductor compound layer grown and formed on the buffer layer. | 2012-03-08 |
20120056238 | BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - A bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss. | 2012-03-08 |
20120056239 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is coupled between a first power line and a second power line and comprises a P-type well, a first N-type doped region, a first P-type doped region, a second P-type doped region and a second N-type doped region. The first N-type doped region is formed in the P-type well. The first P-type doped region is formed in the first N-type doped region. The second P-type doped region comprises a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. The second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT). | 2012-03-08 |
20120056240 | SEMICONDUCTOR DEVICE - A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate. | 2012-03-08 |
20120056241 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion. | 2012-03-08 |
20120056242 | SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE BIPOLAR TRANSISTOR AND DIODE - A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions. | 2012-03-08 |
20120056243 | PHOTODETECTOR AND METHOD FOR MANUFACTURING PHOTODETECTOR - A photodetector | 2012-03-08 |
20120056244 | Growth of multi-layer group III-nitride buffers on large-area silicon Substrates and other substrates - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 2012-03-08 |
20120056245 | SEMICONDUCTOR DEVICES INCLUDING SILICIDE REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy | 2012-03-08 |
20120056246 | INSULATED GATE FIELD EFFECT TRANSISTORS - An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced. | 2012-03-08 |
20120056247 | PSEUDO BURIED LAYER AND MANUFACTURING METHOD OF THE SAME, DEEP HOLE CONTACT AND BIPOLAR TRANSISTOR - The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices. | 2012-03-08 |
20120056248 | ONE-TRANSISTOR PIXEL ARRAY - To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. | 2012-03-08 |
20120056249 | INTERLAYER FOR ELECTRONIC DEVICES - Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as interlayers applied to fluoropolymer layers used in the fabrication of electronic devices, the electronic devices that encompass such polycycloolefin interlayers and processes for preparing such polycycloolefin interlayers and electronic devices. | 2012-03-08 |
20120056250 | DYNAMIC SCHOTTKY BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE - A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance. | 2012-03-08 |
20120056251 | SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS - A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate. | 2012-03-08 |
20120056252 | ELECTRONIC DEVICE - An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire. | 2012-03-08 |
20120056253 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a select transistor, a lower electrode, a magnetic tunnel junction element, a first protection film, an upper electrode, and a second protection film. The select transistor is formed on the semiconductor substrate. The lower electrode is electrically connected to one diffusion layer of the select transistor. The magnetic tunnel junction element is provided on the lower electrode. The first protection film is provided on a side surface of the magnetic tunnel junction element. The upper electrode is provided on the magnetic tunnel junction element and the first protection film. The second protection film is provided on side surfaces of the upper electrode, the first protection film, and the lower electrode. | 2012-03-08 |
20120056254 | SPIN INJECTION ELECTRODE STRUCTURE, SPIN TRANSPORT ELEMENT, AND SPIN TRANSPORT DEVICE - The present invention provides a spin injection electrode structure, a spin transport element, and a spin transport device which enable effective spin injection in a silicon channel layer at room temperature. A spin injection electrode structure IE comprises a silicon channel layer | 2012-03-08 |
20120056255 | Semiconductor device and method of fabricating the same - A semiconductor device includes a device formation region including a plurality of unit regions arranged in series to each other, each unit region comprising first and second active regions alternately arranged in series to each other. The first active region extends in a first direction. The second active region extends obliquely to the first direction. A plurality of first semiconductor pillars is arranged in the first direction and in each of the first active regions. A second semiconductor pillar is in each of the second active regions. A first bit line includes a first diffusion layer in the device formation region. The first diffusion layer extends under the plurality of first semiconductor pillars and the second semiconductor pillar. The first bit line connects the plurality of first semiconductor pillars and the second semiconductor pillar. A second bit line is electrically connected to the second semiconductor pillar. | 2012-03-08 |
20120056256 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a first semiconductor pillar, a second semiconductor pillar, and a first wiring. The first semiconductor pillar includes a first diffusion region. The second semiconductor pillar is adjacent to the first semiconductor pillar. The first wiring is positioned between the first and second semiconductor pillars. The first wiring has a first metal surface. The first metal surface has an ohmic contact with the first diffusion region. | 2012-03-08 |
20120056257 | Non-Volatile Memory System with Modified Memory Cells - A method and system in which an embedded memory is fabricated in accordance with a conventional logic process includes one or more non-volatile memory cells, each having an access transistor and a capacitor, which share a common floating gate electrode. The coupling capacitor is provided with a dielectric layer having a thickness greater than the dielectric layer of the access transistor. Regions under the capacitor are implanted with a high dose implant to form an electrically shorted doped area in the channel region of the capacitor. The high dose implant improves the coupling ratio of the capacitor and enhances the uniformity of the capacitor's oxide layer. | 2012-03-08 |
20120056258 | ELECTRICAL SWITCH USING GATED RESISTOR STRUCTURES AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING THE SAME - An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration. | 2012-03-08 |
20120056259 | MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL - A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region. | 2012-03-08 |
20120056260 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 2012-03-08 |
20120056261 | BI-DIRECTIONAL, REVERSE BLOCKING BATTERY SWITCH - Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package. | 2012-03-08 |
20120056262 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, an embedded electrode, a control electrode, a fourth semiconductor layer of the second conductivity type, a first main electrode, and a second main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The embedded electrode is provided in a first trench via a first insulating film. The first trench penetrates through the second semiconductor layer from a surface of the third semiconductor layer to reach the first semiconductor layer. The control electrode is provided above the embedded electrode via a second insulating film in the first trench. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench. The second trench penetrates through the second semiconductor layer from the surface of the third semiconductor layer to reach the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is provided in the second trench and connected to the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer. The embedded electrode is electrically connected to one of the second main electrode and the control electrode. A Schottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench. | 2012-03-08 |
20120056263 | SEMICONDUCTOR TRENCH ISOLATION INCLUDING POLYSILICON AND NITRIDE LAYERS - A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed. | 2012-03-08 |
20120056264 | METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET - A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator. | 2012-03-08 |
20120056265 | SEMINCONDUCTOR DEVICE AND FABRICATIONS THEREOF - A semiconductor device is disclosed, including a substrate, a fin type semiconductor layer disposed on the substrate, a gate dielectric layer disposed on a top and sidewalls of the fin type semiconductor layer, a metal nitride layer disposed on the gate dielectric layer, and an aluminum doped metal nitride layer disposed on the metal nitride layer. In an embodiment of the invention, the metal nitride layer is a titanium nitride layer and the aluminum doped metal nitride layer is an aluminum doped titanium nitride layer. | 2012-03-08 |
20120056266 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of gate insulating films formed on a semiconductor substrate. Of the plurality of gate insulating films, the gate insulating film having a smallest thickness in an HP transistor formation region is a silicon oxide film, and each of the remaining gate insulating films in an I/O transistor formation region and an LP transistor formation region is a silicon oxynitride film. | 2012-03-08 |
20120056267 | HYBRID CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A hybrid channel semiconductor device and a method for forming the same are provided. The method includes: providing a first semiconductor layer, the first semiconductor layer including an NMOS area and a PMOS area, a surface of the first semiconductor layer being covered by a second semiconductor layer, wherein electrons have higher mobility than holes in one of the first semiconductor layer and the second semiconductor layer, and holes have higher mobility than electrons in the other; forming a first dummy gate structure, and a first source region and a first drain region on respective sides of the first dummy gate structure on the second semiconductor layer in the NMOS area, forming a second dummy gate structure, and a second source region and a second drain region on respective sides of the second dummy gate structure on the second semiconductor layer in the PMOS area; forming an interlayer dielectric layer on the second semiconductor layer and performing planarization; removing the first dummy gate structure and the second dummy gate structure to form a first opening and a second opening; and forming a first gate structure on the one of the first semiconductor layer and the second semiconductor layer in which electrons have higher mobility in the first opening, and forming a second gate structure on the other semiconductor layer in the second opening. The invention can reduce defects in the channel region. | 2012-03-08 |
20120056268 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used. | 2012-03-08 |
20120056269 | NOVEL DEVICE SCHEME OF HMKG GATE-LAST PROCESS - The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate. | 2012-03-08 |
20120056270 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an NMIS transistor including a first gate insulating film containing a high-k dielectric and a first gate electrode provided on the first gate insulating film and containing a metal material and a PMIS transistor including a second gate insulating film containing a high-k dielectric and a second gate electrode provided on the second gate insulating film and containing a metal material. A side surface of the first gate insulating film is located at an inner side of a side surface of the first gate electrode. A ratio of a length of the first gate insulating film along a gate length direction to a length of the first gate electrode along the gate length direction is lower than a ratio of a length of the second gate insulating film along the gate length direction to a length of the second gate electrode along the gate length direction. | 2012-03-08 |
20120056271 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first, second, and third MIS transistors of a first conductivity type respectively including a first, second, and third gate electrodes on a first, second, and third active regions of a semiconductor substrate with a first, second, and third gate insulating films interposed therebetween. The first gate insulating film is formed of a first silicon oxide film and a first high-k insulating film on the first silicon oxide film. The second gate insulating film is formed of a second silicon oxide film and a second high-k insulating film on the second silicon oxide film. The third gate insulating film is formed of a third silicon oxide film and a third high-k insulating film on the third silicon oxide film. The second silicon oxide film has a same thickness as the first silicon oxide film, and a greater thickness than the third silicon oxide film. | 2012-03-08 |
20120056272 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor having a first conductivity type; and a second transistor having the first conductivity type and having a higher threshold voltage than the first transistor. The first transistor includes a first channel region having a second conductivity type, a first gate insulating film, a first gate electrode, and a first extension region having the first conductivity type. The second transistor includes a second channel region having the second conductivity type, a second gate insulating film, a second gate electrode, and a second extension region having the first conductivity type. The second extension region contains impurities for shallower junction. A junction depth of the second extension region is shallower than a junction depth of the first extension region. | 2012-03-08 |
20120056273 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first transistor formed on a semiconductor substrate; and a second transistor formed above the semiconductor substrate with an insulation film interposed therebetween. The first transistor includes a first body region formed on a surface of the semiconductor substrate, and a first source region and a first drain region formed so as to sandwich the first body region, the second transistor includes a semiconductor layer formed on the insulation film, a second body region formed in a part of the semiconductor layer, a second source region and a second drain region formed so as to sandwich the second body region in the semiconductor layer, agate insulation film formed on the body region of the semiconductor layer, and agate electrode formed on the gate insulation film, and the second drain region is disposed on the first body region. | 2012-03-08 |
20120056274 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: transistor Tr | 2012-03-08 |
20120056275 | HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE - A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer. | 2012-03-08 |
20120056276 | STRAINED ASYMMETRIC SOURCE/DRAIN - The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed. | 2012-03-08 |
20120056277 | SEMICONDUCTOR DEVICE INTEGRATED WITH CONVERTER AND PACKAGE STRUCTURE THEREOF - The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device. | 2012-03-08 |
20120056278 | Method for Manufacturing Contacts for a Semiconductor Device, and Semiconductor Device Having Such Contacts - A manufacturing method for contacts for a semiconductor device and a semiconductor device having said contacts, said method forms contact structures whose lower part consists of a plurality of contact holes and whose upper part consists of a trench contact, said contact holes having relatively smaller diameters, and the trench contacts having relatively larger contact areas. Thus contact holes with smaller diameters and trench contacts having larger contact areas can be easily connected to the metal layer above them, thereby improving the electrical conductivity of the contacts and improving the overall performances of the device. | 2012-03-08 |
20120056279 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element includes: a packaging substrate having first and second wiring layers on two surfaces thereof and a chip embedded therein; a first dielectric layer disposed on the packaging substrate and the chip; a third wiring layer disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and the third wiring layer and having a recessed portion; a lid disposed in the recessed portion and on the top surface of the second dielectric layer around the periphery of the recessed portion, wherein the portion of the lid on the top surface of the second dielectric layer is formed into a lid frame on which an adhering material is disposed to allow a substrate having an MEMS element to be attached to the packaging substrate with the MEMS element corresponding in position to the recessed portion, thereby providing a package structure of reduced size and costs with better electrical properties. | 2012-03-08 |
20120056280 | MEMS Sensor Package - A MEMS sensor package includes a support and a MEMS sensor chip having a mounting side adhered on the support by a point-shaped adhesive or a linear-shaped adhesive in such a way that the MEMS sensor chip has a free side opposite to the mounting and suspended above the support. Because the MEMS sensor chip has the free side that is not restrained on the support, the stress due to deformation of the support will not affect the accuracy of the MEMS sensor chip. | 2012-03-08 |
20120056281 | HIGH ASPECT RATIO CAPACITIVELY COUPLED MEMS DEVICES - A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode. | 2012-03-08 |
20120056282 | MEMS Transducer for an Audio Device - A MEMS transducer ( | 2012-03-08 |
20120056283 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face and becomes a reference for the information stored in the memory layer; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer and is formed of a non-magnetic layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure having the memory layer, the insulating layer, and the magnetization-fixed layer, and thereby the magnetization direction varies and a recording of information is performed with respect to the memory layer, and a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer. | 2012-03-08 |
20120056284 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element which includes a layered structure. The layered structure includes a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer having magnetization perpendicular to the film face; an insulating layer provided between the memory layer and the magnetization-fixed layer; and a cap layer provided at a face side, which is opposite to the insulating layer-side face, of the memory layer, in which an electron that is spin-polarized is injected in a lamination direction of the layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and at least a face, which comes into contact with the memory layer, of the cap layer is formed of a Ta film. | 2012-03-08 |
20120056285 | MEMORY ELEMENT AND MEMORY DEVICE - There is provided a memory element including a memory layer that has magnetization perpendicular to a film face; a magnetization-fixed layer that has magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, the insulating layer is formed of an oxide film, and the memory layer is formed of Co—Fe—B, a concentration of B is low in the vicinity of an interface with the insulating layer, and the concentration of B increases as it recedes from the insulating layer. | 2012-03-08 |
20120056286 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a layered structure including a memory layer that has magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of the layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and the memory layer and the magnetization-fixed layer have a film thickness in such a manner that an interface magnetic anisotropy energy becomes larger than a diamagnetic energy. | 2012-03-08 |
20120056287 | DISPOSITIF DE DETECTION DE RAYONNEMENT ET PROCEDE DE FABRICATION - A method for manufacturing an ionizing radiation detection device having a block of a semiconductor material adapted to undergo local separations of charges between positive and negative charges under the effect of ionizing radiation. The device including a first series of at least two collecting electrodes formed on the surface of the semiconductor block, and a second series of at least two non-collecting electrodes formed on a support and separated from the semiconductor block by an insulating layer. During processing, after forming the insulating layer on the support so as to cover the non-collecting electrodes, the block of semiconductor material bearing the collecting electrodes and the support bearing the non-collecting electrodes and the insulating layer are assembled. | 2012-03-08 |
20120056288 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC APPARATUS - A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer. | 2012-03-08 |
20120056289 | MATERIALS, SYSTEMS AND METHODS FOR OPTOELECTRONIC DEVICES - A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer. | 2012-03-08 |
20120056290 | THIN-FILM SOLAR FABRICATION PROCESS, DEPOSITION METHOD FOR SOLAR CELL PRECURSOR LAYER STACK, AND SOLAR CELL PRECURSOR LAYER STACK - A method of manufacturing a layer stack adapted for a thin-film solar cell and a precursor for a solar cell are described. The method includes depositing a TCO layer over a transparent substrate, depositing a first conductive-type layer, wherein the depositing includes: providing for a first SiOx-containing anti-reflection layer by chemical vapor deposition. The method further includes depositing a first intrinsic-type layer and depositing a further conductive-type layer with a conductivity opposite to the first conductive-type layer. | 2012-03-08 |
20120056291 | IMAGING DEVICE, IMAGING MODULE AND METHOD FOR MANUFACTURING IMAGING DEVICE - According to one embodiment, an imaging device includes a substrate, a photodetecting portion, a circuit portion and a through interconnect. The substrate has a first major surface, a second major surface on a side opposite to the first major surface, a recess portion provided on the first major surface and retreated in a first direction going from the first major surface to the second major surface, and a through hole communicating with the first major surface and the second major surface and extending in the first direction. The photodetecting portion is provided above the recess portion and away from the substrate. The circuit portion is electrically connected to the photodetecting portion and provided on the first major surface. The through interconnect is electrically connected to the circuit portion and provided inside the through hole. The recess portion has a first inclined surface. The through hole has a second inclined surface. | 2012-03-08 |
20120056292 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR A SEMICONDUCTOR PACKAGE AS WELL AS OPTICAL MODULE - A semiconductor package includes: a supporting substrate; a functioning element and a first joining element formed on a first principal surface of the supporting substrate; a sealing substrate disposed in an opposing relationship to the supporting substrate with the functioning element and the first joining element interposed therebetween; a second joining element provided on a second principal surface of the supporting substrate; a through-electrode provided in and extending through the supporting substrate and adapted to electrically connect the first and second joining elements; and a first electromagnetic shield film coated in an overall area of a side face of the supporting substrate which extends perpendicularly to the first and second principal surfaces. | 2012-03-08 |
20120056293 | SEMICONDUCTOR OPTICAL ELEMENT - A semiconductor optical element has an active layer including quantum dots. The density of quantum dots in the resonator direction in a portion of the active layer in which the density of photons is relatively high is increased relative to the density of quantum dots in a portion of the active layer in which the density of photons is relatively low. | 2012-03-08 |
20120056294 | SCHOTTKY DIODES WITH DUAL GUARD RING REGIONS AND ASSOCIATED METHODS - The present invention discloses a Schottky diode. The Schottky diode comprises a cathode region, an anode region and a guard ring region. The anode region may comprise a metal Schottky contact. The guard ring region may comprise an outer guard ring and a plurality of inner guard stripes inside the outer guard ring. And wherein the inner guard stripe has a shallower junction depth than the outer guard ring. | 2012-03-08 |
20120056295 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 2012-03-08 |
20120056296 | SEMICONDUCTOR DEVICE AND METHOD OF BLOWING FUSE THEREOF - A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region. | 2012-03-08 |
20120056297 | BALUNS FOR RF SIGNAL CONVERSION AND IMPEDANCE MATCHING - A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance. | 2012-03-08 |
20120056298 | Semiconductor Device - A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals. | 2012-03-08 |
20120056299 | Integrated Capacitor Comprising an Electrically Insulating Layer Made of an Amorphous Perovskite-Type Material and Manufacturing Process - An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided. | 2012-03-08 |
20120056300 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME - Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm. | 2012-03-08 |
20120056301 | STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates. | 2012-03-08 |
20120056302 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor. | 2012-03-08 |
20120056303 | Resistor Array And Semiconductor Device Including The Same - A resistor array includes a semiconductor substrate, a plurality of isolation regions, a plurality of dummy active regions and a plurality of unit resistors. The plurality of isolation regions are formed in the semiconductor substrate. The plurality of dummy active regions are formed in the semiconductor substrate between the plurality of isolation regions. The plurality of unit resistors are formed on the plurality of dummy active regions. | 2012-03-08 |
20120056304 | Wafer, Fabricating Method Of The Same, And Semiconductor Substrate - A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface. | 2012-03-08 |
20120056305 | SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width. | 2012-03-08 |
20120056306 | MULTI-STACK SEMICONDUCTOR DEVICE - A multi-stack semiconductor device comprises: a substrate; a first conductive layer, a first group of the semiconductor material layers and a second group of the semiconductor material layers. The first conductive layer is formed on the substrate scribed by laser on the bottom of the first conductive layer to form a plurality of the first scribe lines. The first group of the semiconductor material layers is formed on the first conductive layer, and the second group of the semiconductor material layers is formed on the first group of the semiconductor material layers. The first group of the semiconductor material layers and the second group of the semiconductor material layers are simultaneously scribed by laser on bottom of the first group of the semiconductor material layers to form a plurality of the second scribe lines. Each second scribe line is comprised of a plurality of the second pores. The second conductive layer is formed on the second group of the semiconductor material layers and is scribe by laser on the bottom of the first group of the semiconductor material layers to form a plurality of the third scribe lines. The second pores are shortened for shortening the horizontal distance of the first scribe lines and the second scribe lines and/or the horizontal distance of the second scribe lines and the third scribe lines. | 2012-03-08 |
20120056307 | EPITAXIAL SILICON WAFER AND PRODUCTION METHOD THEREOF - Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression. | 2012-03-08 |
20120056308 | METHOD OF FORMING AN ELECTROMECHANICAL TRANSDUCER DEVICE - A method of forming an electromechanical transducer device comprises forming on a fixed structure a movable structure and an actuating structure of the electromechanical transducer device, wherein the movable structure is arranged in operation of the electromechanical transducer device to be movable in relation to the fixed structure in response to actuation of the actuating structure. The method further comprises providing a stress trimming layer on at least part of the movable structure, after providing the stress trimming layer, releasing the movable structure from the fixed structure to provide a released electromechanical transducer device, and after releasing the movable structure changing stress in the stress trimming layer of the released electromechanical transducer device such that the movable structure is deflected a predetermined amount relative to the fixed structure when the electromechanical transducer device is in an off state. | 2012-03-08 |
20120056309 | SEMICONDUCTOR DEVICE WITH REDUCED HEAT-INDUCED LOSS - A semiconductor device which is capable of reducing a heat-induced loss includes a substrate and a circuit element disposed on the substrate. The substrate is of a rectangular shape with beveled surfaces on four corners thereof. | 2012-03-08 |
20120056310 | SEMICONDUCTOR DEVICE AND METHOD FOR INCREASING SEMICONDUCTOR DEVICE EFFECTIVE OPERATION AERA - A method for increasing semiconductor device effective operation area, comprising following steps: depositing first conductive layer on the substrate; using laser for scribing a plurality of the first scribe lines on the first conductive layer, where the scribe lines are scribed on the bottom of the first conductive layer; depositing a plurality of the semiconductor material layers on the first conductive layer and in the plurality of the first scribe lines; using laser for scribing a plurality of the second scribe lines on the semiconductor material layer, where the scribe lines are scribed on the bottom of the semiconductor material layer, each second scribe line is comprised of a plurality of the second pores; depositing a second conductive layer on the semiconductor material layer and in the plurality of the first scribe lines and the plurality of the second scribe lines; using laser for scribing a plurality of the third scribe lines on the second conductive layer, where the scribe lines are scribed on the bottom of the semiconductor material layer; wherein the second pores are shortened for shortening the distance between the first scribe line and second scribe line and the distance between the third scribe line and second scribe line. | 2012-03-08 |
20120056311 | LEADFRAME FOR SEMICONDUCTOR DEVICE - A lead frame for a semiconductor device has a die pad with a first major surface for receiving an semiconductor die and a connection bar that encircles the die pad. First lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the first lead fingers lie in a first plane. Second lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the second lead fingers lie in a second plane that is parallel and spaced from the first plane. An isolation frame is disposed between the proximal ends of the first and second lead fingers. The isolation frame separates but supports the proximal ends of the first and second lead fingers. | 2012-03-08 |
20120056312 | Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die - A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die. | 2012-03-08 |
20120056313 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars. | 2012-03-08 |
20120056314 | Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die - A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die. | 2012-03-08 |
20120056315 | Alignment Marks in Substrate Having Through-Substrate Via (TSV) - A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. | 2012-03-08 |
20120056316 | Semiconductor Device and Method of Forming Different Height Conductive Pillars to Electrically Interconnect Stacked Laterally Offset Semiconductor Die - A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures. | 2012-03-08 |
20120056317 | CHIP - A chip includes a body, a number of pins, and conductive pieces. The body includes a top surface and a bottom surface. The pins are arranged on the bottom surface. The conductive pieces are arranged on the top surface. The number of the conductive pieces equals to the number of the pins. Each pin is electrically connected to one conductive piece. | 2012-03-08 |
20120056318 | SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a semiconductor element, an electrode pad of the semiconductor element, a buffer coat film, and a micro-bump. The buffer coat film has an opening corresponding to the electrode pad. The micro-bump is electrically connected to the electrode pad through the opening. A contact area between the micro-bump and side surfaces of the opening is larger than a contact area between the micro-bump and a bottom surface of the opening. | 2012-03-08 |
20120056319 | EMBEDDED PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An embedded package includes a first semiconductor chip having a first conductive line which has a first sunken area, a second semiconductor chip having a second conductive line which has a second sunken area, wherein the first semiconductor chip and the second semiconductor chip are arranged facing each other, and wherein the first sunken area and the second sunken area are arranged facing each other, a core layer surrounding the first semiconductor chip and the second semiconductor chip, wherein the core layer has a first circuit pattern coupled to an external terminal; and a bump formed in the first and second sunken areas, wherein the bump is coupled to the first circuit pattern. | 2012-03-08 |
20120056320 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer. | 2012-03-08 |
20120056321 | Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers - A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate. | 2012-03-08 |
20120056322 | SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY - A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film. | 2012-03-08 |
20120056323 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a semiconductor substrate comprising a first surface and a second surface opposite to each other; and a silicon via formed through the semiconductor substrate, wherein the silicon via comprises a first via formed through the first surface; and a second via formed through the second surface and electrically connected with the first via, wherein the first and second vias are formed individually. Embodiments of the invention are applicable to the manufacture of a 3D integrated circuit. | 2012-03-08 |
20120056324 | SUBSTRATE FOR A MICROELECTRONIC PACKAGE AND METHOD OF FABRICATING THEREOF - Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density. | 2012-03-08 |
20120056325 | METHODS OF FABRICATING ELECTRONIC DEVICES USING DIRECT COPPER PLATING - The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention. | 2012-03-08 |
20120056326 | TITANIUM NITRIDE FILMS - The use of a monolayer or partial monolayer sequencing process to form conductive titanium nitride produces a reliable structure for use in a variety of electronic devices. In an embodiment, a structure can be formed by using ammonia and carbon monoxide reactant materials with respect to a titanium-containing precursor exposed to a substrate. Such a TiN layer has a number of uses including, but not limited to, use as a diffusion barrier underneath another conductor or use as an electro-migration preventing layer on top of a conductor. Such deposited TiN material may have characteristics associated with a low resistivity, a smooth topology, high deposition rates, excellent step coverage, and electrical continuity. | 2012-03-08 |
20120056327 | RAMP-STACK CHIP PACKAGE WITH STATIC BENDS - A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication. | 2012-03-08 |
20120056328 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 2012-03-08 |
20120056329 | Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect - A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame. | 2012-03-08 |
20120056330 | SEMICONDUCTOR DEVICE - A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug. | 2012-03-08 |
20120056331 | METHODS OF FORMING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FORMED BY THE SAME - Provided are a method of forming a semiconductor device including a via and a semiconductor device formed by the same. In the method, by forming an unseeded layer that covers a seed layer disposed on a substrate and at a side wall of a via hole, exposes the seed layer disposed at a bottom of the via hole, and cannot serve as a seed, a plated layer configuring the via is formed upward from the seed layer in a bottom-up growth process, and thus, a void is not formed. Also, an inlet of the via hole is not blocked by using the bottom-up growth process, and thus, an electroplating speed can increase, thereby shortening a time taken in filling the via hole with a metal. | 2012-03-08 |
20120056332 | COMPLIANT PRINTED CIRCUIT WAFER LEVEL SEMICONDUCTOR PACKAGE - A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices. | 2012-03-08 |
20120056333 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion. | 2012-03-08 |
20120056334 | Semiconductor Device and Method of Forming Pre-Molded Substrate to Reduce Warpage During Die Mounting - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting. | 2012-03-08 |
20120056335 | MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING - A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed. | 2012-03-08 |
20120056336 | SEMICONDUCTOR PACKAGE FOR CONTROLLING WARPAGE - A semiconductor structure having a ring. The semiconductor structure includes a substrate, at least one chip, and the ring. The substrate has a first surface. The chip is located on the first surface of the substrate and electrically connected to the substrate. The ring has a first portion and a second portion. In various embodiments, the first and second portions different coefficients of thermal expansion (CTE), and or different cross-sectional widths. In another embodiment, the ring includes a third portion having a CTE different from both the first and second CTEs. | 2012-03-08 |