10th week of 2009 patent applcation highlights part 78 |
Patent application number | Title | Published |
20090063706 | Combined Layer 2 Virtual MAC Address with Layer 3 IP Address Routing - Inbound packets received by a physical network adapter of a processing device are routed by evaluating an inbound frame to determine if an inbound frame destination MAC address is associated with the processing device and determining whether the inbound frame should be routed to a corresponding logical interface or to drop the inbound frame if the inbound frame destination MAC address is equal to a virtual MAC address supported by the processing device. If it is determined that the inbound frame should be routed to the corresponding logical interface, then any necessary layer 3 functions are performed and the inbound frame is routed to the corresponding logical interface, thereby combining both layer 2 and layer 3 routing into a single logical function. | 2009-03-05 |
20090063707 | Shared Resource Support for Internet Protocols - Creating a unique identification for each stack in partitions of a host data computer such that a plurality of partitions may share a single adapter card during an Input/Output operation wherein the adapter card is exchanging data between the host and a Local Area Network. The adapter card includes a unique identifier pool for maintaining values of unique identifiers which are available for identifying the stacks. A deleted unique identifier for a stack may be reused by newly created stacks and may be reassigned to a recreated stack, if still available, when the stack had previously been deleted by the operating system, but is then recreated. | 2009-03-05 |
20090063708 | Load Distribution and Redundancy Using Tree Aggregation - A network comprising a plurality of trees each comprising at least one ingress leaf node, at least one interior node, and at least one egress leaf node, wherein at least some of the ingress leaf nodes and the egress leaf nodes are common to the trees, and wherein the ingress leaf node is configured to transport data to the egress leaf node using any of the trees is disclosed. Also disclosed is a network component comprising a processor configured to implement a method comprising selecting one of a plurality of trees associated with information contained within a frame, directing the frame to the selected tree, and maintaining a filtering database (FDB) entry in an interior node in the unselected tree or trees. | 2009-03-05 |
20090063709 | Method for Loading and Maintaining Executable Code Extensions in Instruments - A synthetic instrument and method for operating the same is disclosed. The synthetic instrument includes a plurality of component modules and a controller. Each component module includes signal processing circuitry that processes input signals thereto to provide output signals that are coupled to a device external to that component module. Each module also includes a memory for storing information specifying the manner in which the input signals are processed to provide the output signals and a network interface that connects the component module to a network within the apparatus. A component download manager within that module loads information into the memory in response to messages received on the network, the component module executing a function that is specified by that information. The controller generates messages on the network specifying data that is to be loaded into at least one of the component modules. | 2009-03-05 |
20090063710 | CAPABILITY-BASED CONTROL OF A COMPUTER PERIPHERAL DEVICE - In an embodiment, a computer-implemented method comprises sending, to a computer peripheral device, a request to obtain capabilities of the computer peripheral device; receiving a first capability description from the computer peripheral device, wherein the first capability description describes one or more capabilities, features or functions of the device at the time of the request; creating one or more graphical user interface (GUI) elements based upon the first capability description and causing displaying the GUI elements; receiving user input representing one or more selections of the GUI elements; creating job ticket data that describes a job for the computer peripheral device to perform, based on the GUI elements that were selected as represented in the user input; sending the job ticket data to the peripheral device; wherein the job ticket data describes one or more device settings that the computer peripheral device can transform to device commands. | 2009-03-05 |
20090063711 | PREVENTION OF INADVERTENT DATA SYNCHRONIZATION TO AND FROM REMOVABLE MEMORY SOURCES ON A HANDHELD CONNECTED DEVICE - A method is disclosed for continuously synchronizing data to and from a removable memory source connected to a user's handheld device. When the memory source is inserted into the handheld device, the device queries the memory source to determine whether the memory source is associated with the device or with an online service associated with the device. Upon determining that the memory source is associated with the device, the device exposes the memory source to the online service and allows read and write access to the online service. Upon determining that the memory source is not associated with the device, the device further checks to determine whether the user seeks to associate the memory source with the device. If the user chooses not to do so, the user is allowed to view and modify the contents of the memory source without synchronizing data to and from the online service. | 2009-03-05 |
20090063712 | KVM SWITCH IDENTIFYING PERIPHERAL FOR COMPUTER AND METHOD THEREOF - Disclosed is a KVM switch identifying a peripheral for at least one computer coupled thereto. The KVM switch comprises a memory and a KVM control module. The memory stores identification data responded by the peripheral while the peripheral is being initialized by the KVM switch and stores an initializing command generated by the computer when the computer requests the identification data. The KVM control module sends the initializing command stored in the memory to the peripheral to request the identification data when the peripheral is connected to the KVM switch and replies to the computer with the identification data stored in the memory when the computer requests the identification data for identifying the peripheral. The KVM control module also updates the initializing command stored in the memory if a new initializing command is generated by the computer. | 2009-03-05 |
20090063713 | System for Generating a Data Logout in a Computing Environment - A method and system are disclosed for generating a data logout in a computing environment having a processor and an input/output subsystem for receiving data from and sending data to the processor. The method comprises the steps of the input/output subsystem maintaining a defined set of data; at defined time, the processor issuing a data logout command; and sending said data logout command to the input/output subsystem. In response to receiving said data logout command, the input/output subsystem sends said defined set of data to a specified location. In a preferred implementation, the input/output subsystem includes a channel subsystem and a plurality of input/output devices, and the data logout command is sent to one of the input/output devices. Also, in the preferred embodiment, the channel subsystem includes a channel control unit function and the data logout command is sent to the channel control unit function. | 2009-03-05 |
20090063714 | Method for Generating a Data Logout in a Computing Environment - A method and system are disclosed for generating a data logout in a computing environment having a processor and an input/output subsystem for receiving data from and sending data to the processor. The method comprises the steps of the input/output subsystem maintaining a defined set of data; at defined time, the processor issuing a data logout command; and sending said data logout command to the input/output subsystem. In response to receiving said data logout command, the input/output subsystem sends said defined set of data to a specified location. In a preferred implementation, the input/output subsystem includes a channel subsystem and a plurality of input/output devices, and the data logout command is sent to one of the input/output devices. Also, in the preferred embodiment, the channel subsystem includes a channel control unit function and the data logout command is sent to the channel control unit function. | 2009-03-05 |
20090063715 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 2009-03-05 |
20090063716 | Prioritising Data Processing Operations - The invention relates to a system and method for prioritising one or more data processing operations in a computer storage system, the computer storage system including a plurality of modules, the method comprising receiving a command indicating one or more data processing operations to which priority is to be assigned and interfacing with each of the modules so as to prioritise the one or more data processing operations over other data processing operations. | 2009-03-05 |
20090063717 | Rate Adaptation for Support of Full-Speed USB Transactions Over a High-Speed USB Interface - A USB communications interface (USBCI) may enable communication between a high-speed USB device, e.g. a High-Speed-Inter-Chip (HSIC) USB device, and a non high-speed USB host, e.g. a full-speed USB host. The USBCI may receive first data from the USB host via a non high-speed transaction, and buffer the first data. The USBCI may also initiate a high-speed transaction corresponding to the non high-speed transaction to the USB device, and transmit at least a portion of the buffered first data to the USB device via the high-speed transaction. The USBCI may subsequently receive second data from the USB device via the high-speed transaction, and buffer the second data. The USBCI may also transmit at least a portion of the buffered second data to the USB host via the non high-speed transaction, and complete the non high-speed transaction upon the high-speed transaction completing. | 2009-03-05 |
20090063718 | AUTOMATICALLY GENERATING CAPABILITY-BASED COMPUTER PERIPHERAL DEVICE DRIVERS - In an embodiment, a data processing system comprises device driver generation logic that is encoded in one or more computer-readable storage media for execution and which when executed is operable to perform receiving a first capability description from a computer peripheral device, wherein the first capability description describes one or more capabilities of the computer peripheral device; receiving a generic device driver file; receiving configuration data; automatically generating a device driver for the computer peripheral device and for a computer operating system based on the first capability description, the generic device driver file and the configuration data; device job processing logic that is configured to receive a request to use the computer peripheral device, to request and receive current first capability description from the computer peripheral device at the time of the request, to generate based on the current first capability description and send to the computer peripheral device job ticket data that describes a job for the computer peripheral device to perform, and to provide job data formatted in a page description language to the computer peripheral device. | 2009-03-05 |
20090063719 | RELAY DEVICE, RELAY METHOD AND RELAY CONTROL PROGRAM - A relay device having a plurality of physical ports connecting with a storage medium and relaying data between a higher level device storing configuration information of a storage device and the storage medium, the relay device including a notification unit for issuing a status change notification reporting that a status of the storage medium connected with said physical port changes to said higher level device when the status change of the storage medium is detected, a monitor of status change notification frequency for monitoring whether the frequency of the status change notification informed via said physical port exceeds a specific threshold, and an invalidation unit for invalidating a function of said physical port when said monitor of status change notification frequency detects that the frequency of the status change notification informed via said physical port exceeds the specific threshold. | 2009-03-05 |
20090063720 | Systems and Methods for Controlling HDA System Capabilities - Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware. | 2009-03-05 |
20090063721 | DEVICE AND FILE TRANSFER SYSTEM - A device is connectable to a computer through USB interface. The device includes a mode switching section configured to switch the device to one of a first mode and a second mode in which an access from the computer to a USB storage device is permitted and prohibited, respectively. When a standard data string is received and the device is in the first mode, the device accesses the physical storage area of the data storage section. When the standard data string is received and the device is in the second mode, the device transmits a pseudo response to the computer, the pseudo response indicating that no storage medium is mounted to the data storage section. When a particular data string is received, the device accesses a file through a file system provided in the device. | 2009-03-05 |
20090063722 | DEVICE AND FILE TRANSFER SYSTEM - A device is connectable to a computer and recognized by the computer as a USB multi function device capable of functioning as a USB storage device and an additional device. The device includes a mode switching section configured to switch the device to one of a first mode and a second mode in which an access from the computer to a USB storage device is permitted and prohibited, respectively. When the device is in the first mode, the device accesses the physical storage area of the data storage section. When the device is in the second mode, the device transmits a pseudo response to the computer. The pseudo response indicates that no storage medium is mounted to the data storage section. When a particular data string different from the standard data string is received, the device accesses a file through a file system provided in the device. | 2009-03-05 |
20090063723 | STORAGE APPARATUS, AND METHOD OF STOPPING OPERATION OF ADD-ON STORAGE DEVICE WHICH IS IN OPERATION WITHIN THE STORAGE APPARATUS - A storage apparatus and method are provided. The storage apparatus including includes a basic storage device having a control unit and an add-on storage device configured to be connected to the basic storage device. The add-on storage device including a first request receiving unit receiving a first operation stop request output from the basic storage device to the add-on storage device second request receiving unit receiving a second operation stop request different from the first operation stop request, communication monitoring unit monitoring communication from the basic storage device, and operation stop processing unit performing processing for stopping the operation of the add-on storage device. The operation stop processing unit determines the validity of the second operation stop request on the basis of a monitoring result obtained by the communication monitoring unit, and stops the operation of the add-on storage device. | 2009-03-05 |
20090063724 | System core for transferring data between an external device and memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 2009-03-05 |
20090063725 | Direct memory access system - A direct memory access (DMA) system is disclosed herein. The DMA system includes a controller and an interrupt processing unit. The controller is coupled to a first module and a second module for controlling transferring data between the first module and the second module. The data is modulated into a plurality of data blocks. The interrupt processing unit is coupled to the controller for receiving an interrupt from the first module indicative of transferring a data block of the plurality of data blocks, and for generating a drive signal to the controller indicative of transferring the data block of the plurality of data blocks. The plurality of data blocks are transferred between the first module and the second module in sequence according to a parameter value stored in the controller. | 2009-03-05 |
20090063726 | IMPLEMENTING BUFFERLESS DIRECT MEMORY ACCESS (DMA) CONTROLLERS USING SPLIT TRANSACTIONS - According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller directed to a source unit, the read command including an identifier which matches the identifier in the write command, the source unit transmitting read data on a split transaction bus, the read data including the identifier of the read command, and receiving the read data at the destination unit via the split transaction bus if the identifier of the read data matches the identifier of the write command. | 2009-03-05 |
20090063727 | STREAM DATA CONTROL SERVER, STREAM DATA CONTROL METHOD, AND STREAM DATA CONTROLLING PROGRAM - A stream data control server includes: a processable flow rate managing unit which manages a processable flow rate corresponding to an amount of data per unit time, which can be processed in each of storage units serving as storing destinations; a classified data flow rate managing unit which manages a data flow rate corresponding to an amount of data processed per unit time for each class of data to which a data priority is attached; and a storing destination control unit which controls the storing destinations of respective data based upon the processable flow rate of each of the storage units and the data flow rate for each class in such a manner that the data having higher data priorities are stored in the storage units having higher priorities within a range of the processable flow rate of each of the storage units. | 2009-03-05 |
20090063728 | System and Method for Direct/Indirect Transmission of Information Using a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link. | 2009-03-05 |
20090063729 | System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel - A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data. | 2009-03-05 |
20090063730 | System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel - A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount. | 2009-03-05 |
20090063731 | Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel - A method is provided that supports partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel. In a memory hub controller integrated in the memory module determines an amount of data to be transmitted to or from a set of memory devices of the memory module, in responsive to an access request. The memory hub controller generates a burst length field corresponding to the amount of data. The memory controller controls the amount of data that is transmitted to or from the memory devices using the burst length field. The amount of data is equal to or less than a standard data burst amount of data for the set of memory devices. | 2009-03-05 |
20090063732 | KVM switch and method for controlling the same - A KVM switch connected between a plurality of consoles including a plurality of monitors, and a plurality of information processing apparatuses, comprises a setting portion that sets a part or all of the plurality of consoles to each information processing apparatus as one group, wherein the plurality of monitors included in the plurality of consoles which are set as one group by the setting portion display information from an information processing apparatus corresponding to the group. | 2009-03-05 |
20090063733 | INPUT/OUTPUT PORT SWITCH STRUCTURE OF ELECTRONIC DEVICE - The invention provides an input/output port (I/O port) switch structure of an electronic device. The electronic device comprises a motherboard, and an opening is installed on a predetermined position of the electronic device. The switch structure is installed on the motherboard of the electronic device and a corresponding opening is installed on a side of the electronic device. The I/O port switch structure comprises a base and an operation unit, wherein the base is electrically connected to the motherboard and is used for installing a plurality of I/O ports with different functions. The operation portion is connected to the base to let the base perform a rotating motion at a predetermined angle, and the user can therefore switch and use the required I/O port by operating switch elements. | 2009-03-05 |
20090063734 | BUS CONTROLLER - A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush. | 2009-03-05 |
20090063735 | Method and Apparatus for Operating an Age Queue for Memory Request Operations in a Processor of an Information Handling System - A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. The age queue stores ID tags in respective age queue slots. Each ID tag in the age queue corresponds to a respective address of a load instruction in the request queue. In one embodiment, ID tags propagate through the age queue at a fixed rate of two at a time from a tail of the age queue to a head of the age queue. Arbitration control circuitry generates an enable bit vector that identifies the oldest ID tag in the age queue corresponding to the oldest load request in the request queue. The arbitration circuitry selects the identified oldest instruction in the request queue as the next to dispatch. In one embodiment, the core interface unit exhibits an input frequency that is a multiple of an internal operating frequency of the core interface unit. | 2009-03-05 |
20090063736 | LOW POWER DIGITAL INTERFACE - This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided. | 2009-03-05 |
20090063737 | Portable amplified stethoscope with recording capability - The present invention relates to an improved design for a stethoscope. The invention is a stethoscope with a built-in amplifier and a memory stick to digitally record sounds as well as patient information. The present invention will be able to digitally record the sounds from the stethoscope through the use of an electronic amplification system and a built in memory stick. This system will also have a USB Port that allows the invention to communicate with a computer system. The medical practitioner will also be able to digitally hear the patient sounds with a set of head-phones or through the use of a Bluetooth system. | 2009-03-05 |
20090063738 | Systems and Methods for Overriding Hardwired Responses in an HDA Codec - Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses. | 2009-03-05 |
20090063739 | Systems, and/or Devices to Control the Synchronization of Diagnostic Cycles and Data Conversion for Redundant I/O Applications - Certain exemplary embodiments can provide a first analog input module adapted to, via a sent synchronization signal, automatically terminate a diagnostic cycle of a second analog input module. The synchronization signal can be adapted to cause an initiation of a data conversion cycle at the second analog input module. | 2009-03-05 |
20090063740 | METHOD AND APPARATUS FOR ARBITRATION IN A WIRELESS DEVICE - A method and apparatus for traffic arbitration in a system are provided. In the system, a first module operating in a first protocol and a second module operating in a second protocol share one communication channel. An arbitration circuit schedules medium accesses thereof, in which a quota table maintains a utilization value updated in accordance with the amount of time slots consumed by a particular traffic type, and a time counter periodically resets the utilization value to a default value. When the arbitration circuit receives a request for medium access of the particular traffic type, the arbitration circuit grants the request according to the utilization value, such that the first module or the second module are not activated at the same time. | 2009-03-05 |
20090063741 | METHOD FOR DYNAMICALLY ALLOCATING LINK WIDTH OF RISER CARD - A method for dynamically allocating link width of a riser card is disclosed. The method is suitable for a system including a riser card. In the present method, the number and the positions of cards inserted in the slots and functioning normally are detected so as to decide the link widths allocated for each of the cards. Next, a link width retraining procedure is executed so as to provide a proper link width for each the card to use. In this way, the present invention is able to achieve the optimization of allocating link widths without being limited by the types and the number of the cards disposed on the riser card, which is advantageous in saving the design cost of the riser card and enhancing the convenience to use and handle with the riser card. | 2009-03-05 |
20090063742 | HOST APPARATUS FOR CONTROLLING MEMORY CARDS - A host controller can divide a preliminary process for writing to a memory card, or the like, into a plurality of unit processes for execution. While writing or the like is being performed with respect to a memory card (card | 2009-03-05 |
20090063743 | Card-type peripheral device - A card-type peripheral device includes an electronic component including a memory disposed in a case, a terminal part including connection terminals connectable with a to-be-connected device, and a switch for disabling writing to the memory. The card-type peripheral device further includes a signal terminal capable of transmitting a signal indicating the status of the switch to the to-be-connected device. | 2009-03-05 |
20090063744 | SMART DOCK FOR CHAINING ACCESSORIES - A system for communicating between an accessory and an electronic device includes a first interface, a second interface, and a docking station. The first interface is configured to communicate with the electronic device. The second interface is configured to communicate with the accessory. The docking station is coupled to the first interface and the second interface. The docking station is configured to receive a set of preferences from the accessory and forward the set of preferences to the electronic device. | 2009-03-05 |
20090063745 | DETACHABLE INTERFACE DEVICE FOR POWERING PORTABLE DATA PROCESSING SYSTEM USING A VEHICLE DIAGNOSTIC PORT - A interface device for powering a data processing system using an output of a vehicle diagnostic port, such as an OBD II connector, that outputs self-diagnostic information. The vehicle diagnostic port is disposed on, and an integral part of, a vehicle. The interface device includes a first connector, a second connector and a power converter. The first connector is configured to detachably couple to the vehicle diagnostic port to receive output signals therefrom. The output signals of the vehicle diagnostic port include a vehicle power output and a diagnostic output including self-diagnostic information. The second connector is configured to detachably couple to a docking connector of the data processing system. The power converter, coupled to the first connector and the second connector, is configured to generate a regulated voltage based on the vehicle power output of the vehicle diagnostic port. The regulated voltage is provided to power the data processing system. | 2009-03-05 |
20090063746 | Integral SATA Interface - An interface couples a host device and a peripheral device. The interface includes at least one tab integrally formed and extending from a main body of a printed circuit board. The at least one tab has a plurality of contact pads. The interface also includes at least one keying feature integrally formed with an enclosure of the peripheral device. The at least one keying feature configured to guide a receptacle connector of the host device into connection with the plurality of contact pads on the at least one tab. | 2009-03-05 |
20090063747 | APPLICATION NETWORK APPLIANCES WITH INTER-MODULE COMMUNICATIONS USING A UNIVERSAL SERIAL BUS - An application network appliance having inter-module communication using a universal serial bus (USB) is described herein. According to one embodiment, a network element includes a lossless data transport fabric (LDTF), multiple service modules coupled to each other over the LDTF, and a service control module (SCM) coupled to each of the service modules over the LDTF for routing network data between the SCM and the service modules. The SCM is also coupled to each of the service modules via a universal serial bus (USB) for managing the service modules, where the network element operates as a security gateway to a datacenter having multiple servers. Other methods and apparatuses are also described. | 2009-03-05 |
20090063748 | Method and Apparatus for Providing Continuous Access to Shared Tape Drives from Multiple Virtual Tape Servers Within a Data Storage System - A method for providing continuous access to shared tape drives from two virtual tape server (VTS) nodes is disclosed. A group of tape drives are connected to two VTS nodes via a set of switches. Both VTS nodes can concurrently process requests to mount physical tape cartridges to separate tape drives. The selection of a tape drive to fulfill a volume mount request on a physical volume begins by locking down any access to a tape drive table having a composite view of all the tape drives shared between the two VTS nodes. An available tape drive is then selected to mount the physical volume, and an entry in the tape drive table is updated to claim ownership of the tape drive. A reservation command is sent to the tape drive to lock down any access to the tape drive, and the lock to the tape drive table is released. Having claimed ownership to the tape drive, the VTS node can now perform the volume mount request. | 2009-03-05 |
20090063749 | TRACKING DATA UPDATES DURING MEMORY MIGRATION - Methods, systems, and computer program products for tracking updates during memory migration. The method includes computer instructions for establishing communication from a source virtual machine to a target virtual machine, the source virtual machine including a memory. Contents of the memory on the source virtual machine are transmitted to the target virtual machine. The contents include a plurality of pages. Pages in the memory that are modified subsequent to being transmitted to the target virtual machine are tracked. The tracking includes creating a data structure having a plurality of bits corresponding to the pages in the memory, the bits indicating if the corresponding pages have been modified subsequent to being transmitted to the target virtual machine. The data structure also includes a first bit location index to identify the location of the first bit in the data structure that corresponds to a modified page. Bits in the data structure are updated in response to detecting that the corresponding pages have been modified subsequent to being transmitted to the target virtual machine. The data structure is scanned starting at the first bit location index to identify pages that have been modified subsequent to being transmitted to the target virtual machine. The identified pages are transmitted to the target virtual machine. | 2009-03-05 |
20090063750 | MIGRATING CONTENTS OF A MEMORY ON A VIRTUAL MACHINE - A system and computer program product for migrating contents of a memory on a virtual machine. The system includes a source virtual machine executing on a host system, the source virtual machine including a memory. The system also includes a hypervisor executing on the host system. The hypervisor is in communication with the source virtual machine and includes instructions. The instructions facilitate establishing communication from the source virtual machine to a target virtual machine, the source virtual machine including a memory. The contents of the memory on the source virtual machine are transmitted to the target virtual machine. The contents of the memory on the source virtual machine include a plurality of pages. It is determined if all or a subset of the pages have been modified on the source virtual machine subsequent to being transmitted to the target virtual machine. If it is determined that all or a subset of the pages have been modified, then the modified pages, including a page location and page content for each of the modified pages, are transmitted to the target virtual machine. The determining and transmitting the modified pages continues until the number of remaining pages that have been modified is less than a threshold. The virtual machine is then paused the remaining pages are transmitted to the target virtual machine. | 2009-03-05 |
20090063751 | METHOD FOR MIGRATING CONTENTS OF A MEMORY ON A VIRTUAL MACHINE - A method for migrating contents of a memory on a virtual machine. The method includes computer instructions for establishing communication from a source virtual machine to a target virtual machine, the source virtual machine including a memory. The contents of the memory on the source virtual machine are transmitted to the target virtual machine. The contents of the memory on the source virtual machine include a plurality of pages. It is determined if all or a subset of the pages have been modified on the source virtual machine subsequent to being transmitted to the target virtual machine. If it is determined that all or a subset of the pages have been modified, then the modified pages, including a page location and page content for each of the modified pages, are transmitted to the target virtual machine. The determining and transmitting the modified pages continues until the number of remaining pages that have been modified is less than a threshold. The virtual machine is then paused the remaining pages are transmitted to the target virtual machine. | 2009-03-05 |
20090063752 | UTILIZING DATA ACCESS PATTERNS TO DETERMINE A DATA MIGRATION ORDER - Systems and computer program products for utilizing data access patterns to determine a data migration order. A system includes a source virtual machine executing on a host system, the source virtual machine including a memory. The system also includes a hypervisor executing on the host system, the hypervisor in communication with the source virtual machine and executing instructions. The instructions facilitate establishing communication with a target virtual machine. Access information for pages in the memory is collected and utilized to determine an order of migration for pages in the memory. The pages in the memory are transmitted to the target virtual machine in the order of migration. | 2009-03-05 |
20090063753 | METHOD FOR UTILIZING DATA ACCESS PATTERNS TO DETERMINE A DATA MIGRATION ORDER - A method for utilizing data access patterns to determine a data migration order. The method includes computer instructions for establishing communication from a source virtual machine to a target virtual machine, the source virtual machine including a memory. The access information for pages in the memory is collected and utilized to determine an order of migration for pages in the memory. The pages in the memory are transmitted to the target virtual machine in the order of migration. | 2009-03-05 |
20090063754 | COMBINED PARALLEL/SERIAL STATUS REGISTER READ - Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command. | 2009-03-05 |
20090063755 | PAPER-SHAPED NON-VOLATILE STORAGE DEVICE - A paper-shaped non-volatile storage device includes a top paper layer, a bottom paper layer and a flexible printed circuit board packaged between the top paper layer and the bottom paper layer. The flexible printed circuit board comprises a data-transmitting interface, a non-volatile memory controller and at least one non-volatile memory disposed thereon. Therefore, the paper-shaped non-volatile storage device features as both of traditional paper and traditional non-volatile storage devices, such as instantly writing, manually binding, and outwardly visible content as provided by the traditional paper sheets, and digital information storage, repeatable editing and rapid search capability as provided by the traditional non-volatile storage devices. | 2009-03-05 |
20090063756 | USING FLASH STORAGE DEVICE TO PREVENT UNAUTHORIZED USE OF SOFTWARE - A flash storage device and a method for using the flash storage device to prevent unauthorized use of a software application are provided. An identifier may be encoded within specific sectors of the flash storage device. One bits of the identifier may be encoded as unusable ones of the specific sectors and zero bits of the identifier may be encoded as usable one of the specific sectors. Alternatively, the zero bits of the identifier may be encoded as the unusable ones of the specific sectors and the one bits of the identifier may be encoded as the usable ones of the specific sectors. The software application may be permitted to execute on a processing device connected to the flash storage device only when the identifier is encoded within the flash storage device. | 2009-03-05 |
20090063757 | Memory emulation in an electronic organizer - An electronic organizer using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the electronic organizer. At least one of the memory arrays may be in the form of a removable memory card. | 2009-03-05 |
20090063758 | PROGRAM AND READ METHOD AND PROGRAM APPARATUS OF NAND FLASH MEMORY - A program method, a read method, and a program apparatus of a NAND flash memory are disclosed. The program method and apparatus of the NAND flash memory provided by the present invention can reduce the programming time of each page and increase the programming speed of the entire NAND flash memory when the data to be programmed in a single operation is less than the storage capacity of all the data storage areas in the page. In addition, the read method of the NAND flash memory provided by the present invention can reduce the number of reading each page and accordingly the number of reading the entire NAND flash memory when the data to be read in a single operation is less than the storage capacity of all the data storage areas in the page. | 2009-03-05 |
20090063759 | SYSTEM AND METHOD FOR PROVIDING CONSTRAINED TRANSMISSION AND STORAGE IN A RANDOM ACCESS MEMORY - A system and method for providing constrained transmission and storage in a random access memory. A system includes a memory device for providing constrained transmission and storage. The memory device includes an interface to a data bus, the data bus having a previous state. The memory device also includes an interface to an address and command bus for receiving a request to read data at an address, and a mechanism for initiating a programmable mode. The programmable mode facilitates retrieving data at the address, and executing an exclusive or (XOR) using the retrieved data and the previous state of the data bus as input. The result of the XOR operation is transmitted to the requester via the data bus. | 2009-03-05 |
20090063760 | Systems, devices, and/or methods to access synchronous RAM in an asynchronous manner - Certain exemplary embodiments can provide a method, which can comprise, via a state machine implemented as an application specific integrated circuit, responsive to an automatically detected asynchronous RAM interface signal, automatically transmitting a corresponding synchronous RAM interface signal. The state machine can be communicatively coupled to a programmable logic controller. | 2009-03-05 |
20090063761 | Buffered Memory Module Supporting Two Independent Memory Channels - A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module. | 2009-03-05 |
20090063762 | Content-Addressable Memories and State Machines for Performing Three-Byte Matches and for Providing Error Protection - A method and system for detecting matching strings in a string of characters utilizing content addressable memory is disclosed. | 2009-03-05 |
20090063763 | CONTROLLING WRITING TO MAGNETIC TAPE - A method for controlling writing for a tape recorder that is connected to a host and sequentially records, as a transaction, a plurality of records that are transferred from the host and stored in a buffer is provided, including receiving a synchronous command for a first transaction from the host; in response to the synchronous command, sequentially writing the plurality of records stored in the buffer to a tape as the first transaction; receiving the size of a second transaction following the first transaction from the host; calculating time for a backhitch associated with an operation of the synchronous command for the first transaction on the basis of the size; and performing the backhitch on the basis of the time for the backhitch. | 2009-03-05 |
20090063764 | Designed roughness and surface treatments for capillary buffer of fluid dynamic bearings - A contoured region is disposed within a capillary buffer of a Fluid Dynamic Bearing. In one embodiment, the contoured region comprises at least one defined edge for arresting the displacement of a lubricant within the capillary buffer. | 2009-03-05 |
20090063765 | PARALLEL ACCESS VIRTUAL TAPE LIBRARY AND DRIVES - A system and method described herein allows a virtual tape library (VTL) to perform multiple simultaneous or parallel read/write or access sessions with disk drives or other storage media, particularly when subject to a sequential SCSI-compliant layer or traditional limitations of VTLs. In one embodiment, a virtualizing or transaction layer can establish multiple sessions with one or more clients to concurrently satisfy the read/write requests of those clients for physical storage resources. A table or other data structure tracks or maps the sessions associated with each client and the location of data on the physical storage devices. | 2009-03-05 |
20090063766 | STORAGE CONTROLLER AND FIRMWARE UPDATING METHOD - A storage controller and method are provided. The storage controller includes control sections including storage sections into which data transmitted from a host unit is cached, one of the control sections being a main control section which controls firmware update in the control sections. The main control section includes an instruction updater sending an update instruction to a sub control section in the control sections in which firmware is to be updated, and an area instructor requesting the sub control section to transmit area information, the sub control section including an area information obtainer obtaining, according to the instruction from the area instructor and an area information transmitter transmitting to the area instructor; and an area setter setting the location of the cache area in the storage section on the basis of the instruction. | 2009-03-05 |
20090063767 | Method for Automatically Configuring Additional Component to a Storage Subsystem - A method for automatically configuring a newly added component to a storage subsystem is disclosed. In response to a new component being connected to a storage subsystem, a determination is made whether or not the new component is a host computer or a disk drive. If the new component is a host computer, the new component is added to the storage subsystem as a host computer when the number of computer systems that can be supported by the storage subsystem has not yet been exceeded. If the new component is a disk drive, the new component is allocated to a pool of storage devices within the storage subsystem, wherein some of the pool of storage devices are held in reserve while some of the pool of storage devices are allocated to a host computer based on policy rules. | 2009-03-05 |
20090063768 | ALLOCATION OF HETEROGENEOUS STORAGE DEVICES TO SPARES AND STORAGE ARRAYS - A plurality of storage devices of a plurality of types is provided. A plurality of criteria is associated for each of the plurality of storage devices, based on characteristics of the plurality of storage devices, wherein the plurality of criteria can be used to determine whether a selected storage device is a compatibility spare for a storage device in a storage device array, and whether the selected storage device is an availability spare for the storage device in the storage device array. A determination is made by a spare management application, based on at least the plurality of criteria and at least one optimality condition, of a first set of storage devices selected from the plurality of storage devices to be allocated to a plurality of storage device arrays, and of a second set of storage devices selected from the plurality of storage devices to be allocated as spares for the plurality of storage device arrays. An allocation is made of the first set of storage devices to the plurality of storage device arrays. An allocation made of the second set of storage devices as spares for the plurality of storage device array. | 2009-03-05 |
20090063769 | RAID APPARATUS, CONTROLLER OF RAID APPARATUS AND WRITE-BACK CONTROL METHOD OF THE RAID APPARATUS - A RAID apparatus includes a plurality of recording devices, a first adaptor connected to a first interface which is connected to a high-level apparatus, a controller for controlling processing of data transmitted by the high-level apparatus, and a second adaptor that connects to a second interface connected to a plurality of recording devices. The controller has a first memory area in which said data are stored, a second memory area used for a write-back of the data in said plurality of recording devices, a write-back information control unit controlling a write-back type of data stored in the first memory area and a usage state of the second memory area, a write-back data determination unit for determination of data to be written-back based on the write-back information, and a write-back execution unit for executing a write-back of the data to be written back on the plurality of recording devices. | 2009-03-05 |
20090063770 | STORAGE CONTROL APPARATUS, STORAGE CONTROL PROGRAM, AND STORAGE CONTROL METHOD - A storage control apparatus controls a logical volume using a plurality of recording media. The storage control apparatus includes: a management database that manages information of the recording media, type of the logical volume using the recording media, and state of the logical volume, and a control section that sets, when receiving a first instruction of changing a non-mirrored volume set in advance in the management database to a mirrored volume, the non-mirrored volume as a mirrored volume in a non-redundant state which is a state where only one of recording media constituting a mirroring pair exists, in the management database and performs rebuild processing of the mirrored volume in the non-redundant state. | 2009-03-05 |
20090063771 | STRUCTURE FOR REDUCING COHERENCE ENFORCEMENT BY SELECTIVE DIRECTORY UPDATE ON REPLACEMENT OF UNMODIFIED CACHE BLOCKS IN A DIRECTORY-BASED COHERENT MULTIPROCESSOR - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design structure may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors. | 2009-03-05 |
20090063772 | Methods and apparatus for controlling hierarchical cache memory - Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory. | 2009-03-05 |
20090063773 | Technique to enable store forwarding during long latency instruction execution - A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold store operations in program order while independent load instructions are satisfied during a time in which a high-latency instruction is being processed. After the high-latency instruction is processed, the store operations can be restored in program order without searching the storage structure. | 2009-03-05 |
20090063774 | High Performance Pseudo Dynamic 36 Bit Compare - A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output. | 2009-03-05 |
20090063775 | INSTRUMENT, A SYSTEM AND A CONTAINER FOR PROVISIONING A DEVICE FOR PERSONAL CARE TREATMENT, AND A DEVICE FOR PERSONAL CARE TREATMENT WITH SUCH A CONTAINER - The present invention provides a system and a method for a cache partitioning technique for application tasks based on the scheduling information in multiprocessors. Cache partitioning is performed dynamically based on the information of the pattern of task scheduling provided by the task scheduler ( | 2009-03-05 |
20090063776 | SECOND CHANCE REPLACEMENT MECHANISM FOR A HIGHLY ASSOCIATIVE CACHE MEMORY OF A PROCESSOR - A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed. | 2009-03-05 |
20090063777 | CACHE SYSTEM - A cache system includes a tag memory having a tag indicating whether data is obtained by prefetch access, a prefetch reliability storage unit having prefetch reliability of each processor, and a tag comparator configured to compare the tag with an access address, instruct the prefetch reliability storage unit to decrease the prefetch reliability if cache miss occurs for the tag indicating the prefetch access, and erase information indicating the prefetch access and instruct the prefetch reliability storage unit to increase the prefetch reliability if cache hit occurs for the tag indicating the prefetch access. | 2009-03-05 |
20090063778 | Storage System and Storage System Control Method - A storage system of the present invention improves the response performance of sequential access to data, the data arrangement of which is expected to be sequential. Data to be transmitted via streaming delivery is stored in a storage section. A host sends data read out from the storage section to respective user machines. A prefetch section reads out from the storage section ahead of time the data to be read out by the host, and stores it in a cache memory. A fragmentation detector detects the extent of fragmentation of the data arrangement in accordance with the cache hit rate. The greater the extent of the fragmentation, the smaller the prefetch quantity calculated by a prefetch quantity calculator. A prefetch operation controller halts a prefetch operation when the extent of data arrangement fragmentation is great, and restarts a prefetch operation when the extent of fragmentation decreases. | 2009-03-05 |
20090063779 | CACHE MEMORY AND A METHOD FOR SERVICING ACCESS REQUESTS - A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages. | 2009-03-05 |
20090063780 | DATA PROCESSING SYSTEM AND METHOD FOR MONITORING THE CACHE COHERENCE OF PROCESSING UNITS - The present invention relates to a data processing system with a plurality of processing units (PU), a shared memory (M) for storing data from said processing units (PU) and an interconnect means (IM) for coupling the memory (M) and the plurality of processing units (PU). At least one of the processing units (PU) comprises a cache memory (C). Furthermore, a transition buffer (STB) is provided for buffering at least some of the state transitions of the cache memories (C) of said at least one of said plurality of processing units (PU). A monitoring means (MM) is provided for monitoring the cache coherence of the caches (C) of said plurality of processing units (PU) based on the data of the transition buffer (STB), in order to determine any cache coherence violations. | 2009-03-05 |
20090063781 | CACHE ACCESS MECHANISM - Techniques for improving cache accesses in an object-relational mapping space are described herein. In one embodiment, in response to a first cache request received at a first cache API associated with a transaction for updating a data entry of the relational database, the updated data of the data entry is stored in a local cache, where the local cache is one of members of a cache cluster, and an invalidation message is sent to remaining members of the cache cluster to invalidate corresponding cache entries of the remaining members. In response to a second cache request received at a second cache API associated with a transaction for loading data from a data entry of the relational database, the loaded data is stored in the local cache without sending an invalidation message to the remaining members of the cache cluster. Other methods and apparatuses are also described. | 2009-03-05 |
20090063782 | Method for Reducing Coherence Enforcement by Selective Directory Update on Replacement of Unmodified Cache Blocks in a Directory-Based Coherent Multiprocessor - Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors. | 2009-03-05 |
20090063783 | METHOD AND APPARTAUS TO TRIGGER SYNCHRONIZATION AND VALIDATION ACTIONS UPON MEMORY ACCESS - A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class. | 2009-03-05 |
20090063784 | System for Enhancing the Memory Bandwidth Available Through a Memory Module - A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces. | 2009-03-05 |
20090063785 | Buffered Memory Module Supporting Double the Memory Device Data Width in the Same Physical Space as a Conventional Memory Module - A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices. | 2009-03-05 |
20090063786 | Daisy-chain memory configuration and usage - Daisy-chain memory configuration and usage is disclosed. According to one configuration, a memory system includes a controller and corresponding string of multiple successive memory devices coupled in a daisy-chain manner. The controller communicates commands over the serial control link to configure a first memory device to write a block of data to a second memory device in the chain. For example, the controller initiates copying a block of data by communicating over the daisy-chain control link to configure a first memory device of the multiple memory devices to be a source for outputting data, communicating over the daisy-chain control link to configure a second memory device to be a destination for receiving data, and communicating over the daisy-chain control link to initiate a transfer of the data from the first memory device to the second memory device. | 2009-03-05 |
20090063787 | Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity - A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at least one memory hub device integrated in the memory module. In the memory system, each memory hub device in the memory module comprises a first memory device data interface that communicates with a first set of memory devices and a second memory device data interface that communicates with a second set of memory devices. In the memory system, the first set of memory devices which are separate from the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces. | 2009-03-05 |
20090063788 | Techniques For Storing System Images In Slices On Data Storage Devices - A data storage device has a data storage medium. A data storage capacity of the data storage device is divided into slices. Each slice has a set of sectors. Data storage device firmware is configured to store copies of a system image in the slices on the data storage device. Each of the slices stores a different copy of the system image. | 2009-03-05 |
20090063789 | ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS - Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units. | 2009-03-05 |
20090063790 | Method and apparatus for managing configuration memory of reconfigurable hardware - Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking. | 2009-03-05 |
20090063791 | COMPUTER SYSTEM, CONTROL METHOD THEREOF AND DATA PROCESSING APPARATUS - A computer system and a method of controlling a computer system, the computer system including: a first memory corresponding to a first channel and a second memory corresponding to a second channel; a data processor to process the data of the first and second channels in a time division manner; and a controller to inactivate the second channel if an amount of the data processed by the data processor is less than or equal to a predetermined value. | 2009-03-05 |
20090063792 | Memory control circuit, semiconductor integrated circuit, and verification method of nonvolatile memory - A memory control circuit includes a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting the individual bit that is once again read out from the memory cell, which is previously determined to be successfully storing an expectation value, to a corresponding expectation value expected to be stored in the memory cell, and a determination circuit determining a result of a write processing to write parallel expectation value data to the nonvolatile memory, based on the parallel readout bit data converted by the conversion circuit and the parallel expectation value data. | 2009-03-05 |
20090063793 | STORAGE SYSTEM, DATA MANAGEMENT APPARATUS AND MANAGEMENT ALLOCATION METHOD THEREOF - Provided are a storage system, a data management apparatus, and a data management method capable of facilitating the add-on procedures of data management apparatuses for managing data groups such as directory groups. In a storage system comprising a plurality of data management apparatuses for managing storage destination management information of a data group stored in a storage extent of a prescribed storage controller, at least one of the data management apparatuses decides the respective data management apparatuses to newly manage the data group for each of the data groups based on the importance of each of the data groups or the loaded condition of each of the data management apparatuses, and migrates storage destination management information containing information regarding the storage destination of the data group to the data management apparatus to newly manage the data group based on the decision as necessary. | 2009-03-05 |
20090063794 | METHOD AND SYSTEM FOR ENHANCED DATA STORAGE MANAGEMENT - A method and system for implementing enhanced data storage management are provided. The method includes compiling a list of all online disks for a data storage environment. For each disk in the list, the method includes querying a backup control database to obtain statistical information for the disk which includes a backup status of the disk. Responsive to the query, the method includes generating a first report that includes the statistical information of each of the disks in which a backup has been performed, and generating a second report for each of the disks in which no backup has been performed. The method further includes using the second report to determine whether to add the disks from the second report to a list of disks scheduled for backup based upon predefined criteria, and adding those disks from the second report to the list of disks scheduled for backup when the results of the determination match the predefined criteria. | 2009-03-05 |
20090063795 | DE-DUPLICATION IN A VIRTUALIZED STORAGE ENVIRONMENT - A data de-duplication application de-duplicates redundant data in the pooled storage capacity of a virtualized storage environment. The virtualized storage environment includes a plurality of storage devices and a virtualization or abstraction layer that aggregates all or a portion of the storage capacity of each storage device into a single pool of storage capacity, all or portions of which can be allocated to one or more host systems. For each host system, the virtualization layer presents a representation of at least a portion of the pooled storage capacity wherein the corresponding host system can read and write data. The data de-duplication application identifies redundant data in the pooled storage capacity and replaces it with one or more pointers pointing to a single instance of the data. The de-duplication application can operate on fixed or variable size blocks of data and can de-duplicate data either post-process or in-line. | 2009-03-05 |
20090063796 | Buddy replication - A method and apparatus for replicating instances of cache nodes in a cluster is described. In one embodiment, the number of available cache nodes in the cluster is determined. Available cache nodes from the cluster are selected based on a parameter. An instance of a cache node is replicated to only one of the selected cache nodes in the cluster. | 2009-03-05 |
20090063797 | BACKUP DATA ERASURE METHOD - A computer system comprises a storage subsystem, a host computer and a management computer, and stores catalogue information containing correspondence between a first volume for data reading or writing and a second volume for storing a copy of the data stored in the first volume. The management computer requests the storage subsystem to erase the data stored in the first volume upon reception of an erasure request of the data stored in the first volume. The storage subsystem erases the data stored in the first volume. The management computer specifies a second volume for storing the copy of the data stored in the first volume based on the catalogue information. The storage subsystem erases data stored in the specified second volume. Thus, security risks are reduced by erasing data regarding the data when the data stored in the volume is erased. | 2009-03-05 |
20090063798 | Data processing system having a plurality of storage systems - It is an object of the present invention to conduct data transfer or data copying between a plurality of storage systems, without affecting the host computer of the storage systems. Two or more auxiliary storage systems | 2009-03-05 |
20090063799 | Memory Protection For Embedded Controllers - System and method for protecting data in a system including a main processor, an embedded controller, and a memory. In response to a power-on-reset (POR), access to the memory is enabled, e.g., access by the embedded controller. First data is read from the memory (e.g., by the embedded controller) in response to the enabling, where the first data are usable to perform security operations for the system prior to boot-up of the main processor. The first data are used, e.g., by the embedded controller, to perform one or more security operations for the system, then access to the memory, e.g., by the embedded controller, is disabled, where after the disabling the memory is not accessible, e.g., until the next POR initiates enablement. | 2009-03-05 |
20090063800 | ARRANGEMENTS HAVING SECURITY PROTECTION - Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise. | 2009-03-05 |
20090063801 | Write Protection Of Subroutine Return Addresses - Exemplary methods, systems, and products are described that operate generally by moving subroutine return address protection to the processor itself, in effect proving atomic locks for subroutine return addresses stored in a stack, subject to application control. More particularly, exemplary methods, systems, and products are described that write protect subroutine return addresses by calling a subroutine, including storing in a stack memory address a subroutine return address and locking, by a computer processor, the stack memory address against write access. Calling a subroutine may include receiving in the computer processor an instruction to lock the stack memory address. Locking the stack memory address may be carried out by storing the stack memory address in a protected memory lockword. A protected memory lockword may be implemented as a portion of a protected content addressable memory. | 2009-03-05 |
20090063802 | DATA SECURITY SYSTEM - A data security system [ | 2009-03-05 |
20090063803 | CIRCUIT FOR INITIALIZING A PIPE LATCH UNIT IN A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation. | 2009-03-05 |
20090063804 | DYNAMIC A-MSDU ENABLING - A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the 802.11 | 2009-03-05 |
20090063805 | DATA ACQUISITION MESSAGING USING SPECIAL PURPOSE REGISTERS - A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the data acquisition operation has been identified, data corresponding to the configuration information is written to a data register. The data in the data register and the configuration information in the configuration register are formatted into the data acquisition message. The data acquisition message is sent to the external port of the data processing system. | 2009-03-05 |