09th week of 2011 patent applcation highlights part 57 |
Patent application number | Title | Published |
20110053273 | METHODS FOR CLONING AND MANIPULATING GENOMES - Compositions and methods are disclosed herein for cloning a synthetic or a semi-synthetic donor genome in a heterologous host cell. In one embodiment, the donor genome can be further modified within a host cell. Modified or unmodified genomes can be further isolated from the host cell and transferred to a recipient cell. Methods disclosed herein can be used to alter donor genomes from intractable donor cells in more tractable host cells. | 2011-03-03 |
20110053274 | LAC EXPRESSION SYSTEM - Provided herein is a nucleic acid comprising a mutant lac operator operably linked to a gene of interest, a host cell comprising the nucleic acid, and a method of using the host cell to express the gene of interest. Also provided is a recA-mediated cloning method. | 2011-03-03 |
20110053275 | Corrosion Detection Product and Method - A corrosion detection product is a coating including a film forming material and a complexing agent, the complexing agent forming a complex when it comes into contact with a corrosion byproduct produced by corrosion of a substrate on which the coating is applied, the complex being detectably different from the complexing agent when the coating is exposed to radiation in order to detect the corrosion, the complexing agent being immobilized in the coating to reduce leaching of the complexing agent or the complex from the coating. | 2011-03-03 |
20110053276 | MOLECULAR INDICATOR AND PROCESS OF SYNTHESIZING - A molecular indicator for detecting primary diamines includes an indicator structure coupled to (a) a bis-crown ether structure or (b) a structure having a bis-crown ether-like functionality. A package for detecting an analyte emitted by a packaged object includes a packaging material for the object. The package further includes a molecular indicator included with the packaging material for detecting the analyte. The molecular indicator includes an indicator structure coupled to a trapping structure for trapping the analyte. The molecular indicator is highly specific for the analyte, and the trapping of the analyte by the molecular indicator avoids reactive chemistry by-products. The molecular indicator can be synthesized by several different process schemes. | 2011-03-03 |
20110053277 | ANALYZING APPARATUS AND CONTROL METHOD FOR THE SAME - A specimen analyzing apparatus for measuring a specimen by using a reagent which has a dispensing mechanism which includes a dispensing tube for suctioning and discharging liquid; a reagent container holder from which a reagent container is removable when the reagent container is in a container removal area; a receiving section for receiving a replacement command for a replacement of the reagent; and a controller for controlling the dispensing mechanism so as to retreat the dispensing tube from the container removal area when the replacement command has been received by the receiving section. Also, a control method for a specimen analyzing apparatus. | 2011-03-03 |
20110053278 | SYSTEMS AND METHODS FOR ENHANCING FLUORESCENT DETECTION OF TARGET MOLECULES IN A TEST SAMPLE - Systems and methods for enhancing fluorescent detection of target molecules in a test sample are for use with an irradiating device. First fluorophores are provided for absorption of EMF radiation, and emission of a first signal. Second fluorophores are provided for partial absorption of the first signal, and emission of a second signal distinguishable from the first signal. The fluorophores are combined with the test sample, and secured to the target molecules and relative to one another. After the first fluorophores receive the EMF radiation from the irradiating device, the first signal is detected, together with the second spectral signal if the target molecules are present in the test sample. | 2011-03-03 |
20110053279 | DETECTION METHODS OF PROTEINS ON POLYACRYLAMIDE GELS USING GEL BACKGROUND STAINING AND ORGANIC DYE COMPOSITIONS FOR THE SAME - Disclosed are a method for detecting proteins on a polyacrylamide gel by background staining method using an organic dye composition containing eosin Y or phloxine B, and the organic dye composition for use in the method, which enables the rapid and simple detection of the protein on the polyacrylamide gel with a high sensitivity. | 2011-03-03 |
20110053280 | Detection of Post-Translationally Modified Peptides with Liquid Crystals - A method for differentiating between a post-translationally modified peptide and a peptide contained in a sample, comprising: (a) contacting the sample with a peptide attachment surface to create a peptidized surface, wherein the sample includes at least one functional group; (b) contacting the peptidized surface with a recognition reagent that selectively binds or forms a complex with the post-translationally modified peptide in the sample to provide an incubated surface; and (c) contacting a liquid crystal with the incubated surface and detecting presence of post-translationally modified peptide in the sample with the liquid crystal. | 2011-03-03 |
20110053281 | Genetic variants on CHR 11Q and 6Q as markers for prostate and colorectal cancer predisposition - It has been discovered that certain polymorphic markers on chromosome 6 and chromosome 11 are indicative of a susceptibility to prostate cancer and colon cancer. The invention describes diagnostic applications for determining a susceptibility to cancer using such markers, as well as kits for use in such applications. | 2011-03-03 |
20110053282 | Methods and Kits Using Extended Rhodamine Dyes - Extended rhodamine compounds exhibiting favorable fluorescence characteristics having the structure | 2011-03-03 |
20110053283 | Beverage Immersate with detection capability - Methods and systems described herein include beverage immersates and methods of their use. Systems include: at least one beverage immersate, wherein the at least one beverage immersate includes at least one sensor configured to detect at least one analyte in a fluid within a personal use beverage container; and at least one signal transmitter configured to transmit a signal responsive to the at least one beverage immersate. Methods include: detecting one or more analyte in fluid within a personal use beverage container with at least one sensor integral to at least one beverage immersate; and communicating data from the at least one beverage immersate to at least one device external to the beverage immersate. | 2011-03-03 |
20110053284 | CHEMICAL FUNCTIONALIZATION OF SOLID-STATE NANOPORES AND NANOPORE ARRAYS AND APPLICATIONS THEREOF - Chemical functionalization of solid-state nanopores and nanopore arrays and applications thereof. Nanopores are extremely sensitive single-molecule sensors. Recently, electron beams have been used to fabricate synthetic nanopores in thin solid-state membranes with sub-nanometer resolution. A new class of chemically modified nanopore sensors are provided with two approaches for monolayer coating of nanopores by: (1) self-assembly from solution, in which nanopores −10 nm diameter can be reproducibly coated, and (2) self-assembly under voltage-driven electrolyte flow, in which 5 nm nanopores may be coated. Applications of chemically modified nanopore are provided including: the detection of biopolymers such as DNA and RNA; immobilizing enzymes or other proteins for detection or for generating chemical gradients; and localized pH sensing. | 2011-03-03 |
20110053285 | SENSOR USING MASS ENHANCEMENT OF NANOPARTICLES - Provided herein is a method of detecting a biomolecule, which enhances a mass of the target biomolecule by irradiating light to a photocatalytic nanoparticle binding to the target biomolecule. Accordingly, the method can effectively detect a change in mass, and provide economical and rapid detection using a low-priced photocatalyst. | 2011-03-03 |
20110053286 | METHOD AND APPARATUS FOR MOVING STAGE DETECTION OF SINGLE MOLECULAR EVENTS - An apparatus and method based on the apparatus is disclosed for detecting and monitoring chemical and/or bio-chemical reactions or interactions at the single molecule level, where detection and monitoring is improved by moving the viewing field of the detector in a controlled manner. The motion of the moving frame is accomplished either through software in the detector system or is accomplished by moving the reacting system. The motion is controlled and is either linear, circular or elliptical. The motion provides for improved site identification or mapping, improved event detection and monitoring, improved signal recognition and improved noise reduction. | 2011-03-03 |
20110053287 | METHODS FOR THE DIAGNOSIS, RISK ASSESSMENT, AND MONITORING OF AUTISM SPECTRUM DISORDERS - Methods for the diagnosis, risk assessment, and monitoring of Autism Spectrum Disorder (ASD) are disclosed. More specifically the present invention relates to the measurement of small molecules (metabolites) in human plasma that are found to have different abundances between persons with a clinical manifestation of ASD and subjects not expressing symptoms of ASD. Further, this invention relates to the monitoring of putative therapeutic strategies designed to ameliorate the biochemical abnormalities associated with ASD. | 2011-03-03 |
20110053288 | SYSTEMS AND METHODS FOR COLLECTION AND ANALYSIS OF ANALYTES - Systems and methods are provided for collecting and analyzing analytes. One embodiment of the invention includes a system for collecting analyte. The system comprises a sampling section disposed on a collection platform and an air source that provides an analyte to be sorbed by the sampling section. The sampling section can be formed of a low pressure drop configuration of sorbent material | 2011-03-03 |
20110053289 | Assay Device and Method - An assay method and device can perform at least one (e.g., at least two) assays on a single aliquot of a sample liquid. The device can mix a sample liquid with assay reagents including magnetically susceptible particles. The device is configured to create a sample liquid-air interface with the sample liquid. The magnetically susceptible particles can be located (via an applied magnetic field) at the liquid-air interface when a second liquid contacts the interface to form a liquid-liquid interface. The magnetic particles travel across the liquid-liquid interface to the second liquid. The magnetically susceptible particles are configured to trans-port an analyte across the interface into the second liquid. An assay for the analyte is performed in the second liquid. An assay for another analyte can also be performed in the sample liquid. | 2011-03-03 |
20110053290 | LIGHT ADDRESSING BIOSENSOR CHIP AND METHOD OF DRIVING THE SAME - Provided is a biosensor chip. The biosensor chip includes a plurality of biosensor cells that are arranged in a matrix and selectively generate and output a sensed signal by addressing of external light, at least one sensing line that is simultaneously connected with the plurality of biosensor cells and transmits the sensed signal from one selected from the biosensor cells, and an output terminal that receives the sensed signal from the sensing line and outputs the sensed signal to an external reader. Thus, the biosensor cells are set in array in the biosensor chip without a separate driving unit, so that a process of manufacturing the biosensor chip is simplified. The biosensor cell to be sensed is selectively addressed through the external light, so that it is possible to reduce a price of the biosensor chip used as a disposable chip. | 2011-03-03 |
20110053291 | METHOD FOR ANALYZING SAMPLE SOLUTION AND APPARATUS FOR ANALYZING SAMPLE SOLUTION - Disclosed is a method for analyzing a sample solution, including introducing a sample solution | 2011-03-03 |
20110053292 | SIGNAL AMPLIFICATION TECHNIQUE FOR MASS ANALYSIS - There is provided a novel method for amplifying mass spectrometric signals. More particularly, a novel method for detecting signals of a target molecule includes: i) allowing a test sample, in which it is required to determine whether or not a target molecule is present, to be contact with a gold particle whose surface is modified to selectively bind to the target molecule, ii) allowing a low molecular molecule engrafted to the gold particle to generate mass spectrometric signals after the interaction, such as binding, between the gold particle and the target molecule, and iii) amplifying the mass spectrometric signals by generating a great deal of mass spectrometric signals of the low molecular molecule even in the presence of a trace of the target molecule. Also, the assay system using the method and the gold particle prepared in the method are provided. The method may be useful to specifically amplify signals of the target molecule without any pretreatment of a test sample, which makes it possible to measure the target molecule simply and precisely. | 2011-03-03 |
20110053293 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively. | 2011-03-03 |
20110053294 | UV IRRADIANCE MONITORING IN SEMICONDUCTOR PROCESSING USING A TEMPERATURE DEPENDENT SIGNAL - In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished. | 2011-03-03 |
20110053295 | RESIN APPLICATION APPARATUS, OPTICAL PROPERTY CORRECTION APPARATUS AND METHOD, AND METHOD FOR MANUFACTURING LED PACKAGE - A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit. | 2011-03-03 |
20110053296 | THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - A thin film deposition apparatus and a method of manufacturing an organic light-emitting display device by using the same, and more particularly, to a thin film deposition apparatus that can remove a deposition material deposited on a patterning slit sheet without performing an additional cleaning process, and a method of manufacturing an organic light-emitting display device by using the thin film deposition apparatus. | 2011-03-03 |
20110053297 | SUBMOUNTS FOR SEMICONDUCTOR LIGHT EMITTING DEVICES AND METHODS OF FORMING PACKAGED LIGHT EMITTING DEVICES INCLUDING DISPENSED ENCAPSULANTS - A submount for mounting an LED chip includes a substrate, a die attach pad configured to receive an LED chip on an upper surface of the substrate, a first meniscus control feature on the substrate surrounding the die attach pad and defining a first encapsulant region of the upper surface of the substrate, and a second meniscus control feature on the substrate surrounding the first encapsulant region and defining a second encapsulant region of the upper surface of the substrate. The first and second meniscus control features may be substantially coplanar with the die attach pad. A packaged LED includes a submount as described above and further includes an LED chip on the die attach pad, a first encapsulant on the substrate within the first encapsulant region, and a second encapsulant on the substrate within the second encapsulant region and covering the first encapsulant. Method embodiments are also disclosed. | 2011-03-03 |
20110053298 | VERTICAL NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat. | 2011-03-03 |
20110053299 | LIGHT EMITTING DEVICE AND DISPLAY - A method for manufacturing a light emitting device comprises: preparing a light emitting component having an active layer of a semiconductor, the active layer comprising a gallium nitride based semiconductor containing indium and being capable of emitting a blue color light; preparing a phosphor capable of absorbing a part of the blue color light emitted from the light emitting component and emitting a yellow color light, wherein selection of the phosphor is controlled based on an emission wavelength of the light emitting component; and combining the light emitting component and the phosphor so that the blue color light from the light emitting component and the yellow color light from the phosphor are mixed to make a white color light. | 2011-03-03 |
20110053300 | THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - A thin film deposition apparatus that can be applied to manufacture large-sized display devices on a mass scale and that improves manufacturing yield, and a method of manufacturing an organic light-emitting display device by using the thin film deposition apparatus. | 2011-03-03 |
20110053301 | THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - A thin film deposition apparatus that is suitable for production of large-sized substrates with fine patterns includes: an electrostatic chuck including a body that contacts a substrate that constitutes a deposition target and including a supporting surface supporting the substrate, an electrode installed in the body to generate an electrostatic force on the supporting surface, and a battery that is electrically connected to the electrode in the body; a plurality of chambers that are maintained in vacuum states; at least one thin film deposition assembly disposed in one of the plurality of chambers, separated by a predetermined distance from the substrate, and forming a thin film on the substrate supported by the electrostatic chuck; and a carrier moving the electrostatic chuck through the chambers. | 2011-03-03 |
20110053302 | METHOD OF FABRICATING LIGHT EMITTING DIODE USING LASER LIFT-OFF TECHNIQUE AND LASER LIFT-OFF APPARATUS HAVING HEATER - Disclosed is a method of fabricating a light emitting diode using a laser lift-off apparatus. The method includes growing an epitaxial layer including a first conductive-type compound semiconductor layer, an active layer and a second conductive-type compound semiconductor layer on a first substrate, bonding a second substrate, having a different thermal expansion coefficient from that of the first substrate, to the epitaxial layers at a first temperature of the first substrate higher than a room temperature, and separating the first substrate from the epitaxial layer by irradiating a laser beam through the first substrate at a second temperature of the first substrate higher than the room temperature but not more than the first temperature. Thus, during a laser lift-off process, focusing of the laser beam can be easily achieved and the epitaxial layers are prevented from cracking or fracture. The laser lift-off process is performed by a laser lift-off apparatus including a heater. | 2011-03-03 |
20110053303 | Method of fabricating semiconductor substrate and method of fabricating light emitting device - The present invention provides a method of fabricating a semiconductor substrate and a method of fabricating a light emitting device. The method includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a void is formed in a first portion of the first semiconductor layer under the metallic material layer during formation of the second semiconductor layer, and separating the substrate from the second semiconductor layer by etching at least a second portion of the first semiconductor layer using a chemical solution. | 2011-03-03 |
20110053304 | METHOD OF MAKING AN ELECTRONIC DEVICE WITH A CURVED BACKPLATE - A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modulator includes providing a transparent substrate and manufacturing an interferometric modulator array on a backside of the substrate. A back plate includes a curved portion relative to the substrate. The curved portion is substantially throughout the back plate. The back plate is sealed to the backside of the substrate with a back seal in ambient conditions, thereby forming a package. | 2011-03-03 |
20110053305 | SOLID-STATE IMAGING DEVICE, CAMERA AND METHOD OF PRODUCING THE SOLID-STAE IMAGING DEVICE - Producing a solid-state imaging device by (1) forming a structure including (a) a substrate having a first impurity with a first concentration, (b) a first conductive type Si layer and (c) a first conductive type impurity layer stacked on one another in that order, the first conductive type Si layer being formed on the substrate, the first conductive type impurity layer being formed in a boundary region including a boundary of the substrate and the Si layer, and a part of the substrate facing the boundary and a part of the first conductive type Si layer facing the boundary having a second impurity; and (2) forming in the Si layer a second conductive type region capable of storing in the Si layer a charge generated by a photoelectric conversion; and forming an interconnection layer on the Si layer. | 2011-03-03 |
20110053306 | Photovoltaic Lead Manufacture - An improved lead foil operation procedure for photovoltaic module manufacture is disclosed. The procedure includes lift, cut, and fold lead foil. | 2011-03-03 |
20110053307 | REPATTERNING OF POLYVINYL BUTYRAL SHEETS FOR USE IN SOLAR PANELS - Embodiments of the invention provide a method of forming a composite solar cell structure that includes preparing a device substrate, wherein the device substrate includes a glass substrate, a transparent conductive layer deposited over the glass substrate, one or more silicon layers deposited over the transparent conductive layer, a back contact layer deposited over the one or more silicon layers, and one or more internal electrical connections disposed on the back contact layer. The method also includes forming a mating pattern on a bonding material to match a topography of an exposed surface of the device substrate, the exposed surface comprising the back contact layer and the one or more internal electrical connections. The method also includes positioning the bonding material over the exposed surface, disposing a back glass substrate over the bonding material to form a composite structure, and compressing the composite structure. Embodiments of the present invention also include methods of preparing a pre-patterned bonding material for a solar cell assembly. | 2011-03-03 |
20110053308 | Method for the Production of an Optoelectronic Component using Thin-Film Technology - On an epitaxy substrate ( | 2011-03-03 |
20110053309 | METHOD FOR FABRICATING IMAGE SENSOR - A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array. | 2011-03-03 |
20110053310 | PHOTOVOLTAIC DEVICE AND MANUFACTURING METHOD THEREOF - The manufacturing method includes: forming a P-type silicon substrate and a high-concentration N-type diffusion layer, in which an N-type impurity is diffused in a first concentration, on an entire surface at a light-incident surface side; forming an etching resistance film on the high-concentration N-type diffusion layer and forming fine pores at a predetermined position within a recess forming regions on the etching resistance film; forming recesses by etching the silicon substrate around a forming position of the fine pores, so as not to leave the high-concentration N-type diffusion layer within the recess forming region; forming the low-concentration N-type diffusion layer, in which an N-type impurity is diffused in a second concentration that is lower than the first concentration, on a surface on which the recesses are formed; and forming a grid electrode in an electrode forming region at a light-incident surface side of the silicon substrate. | 2011-03-03 |
20110053311 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - Provided is a technique for manufacturing a photoelectric conversion element using a dense crystalline semiconductor film without a cavity between crystal grains. A method of manufacturing a photoelectric conversion device having a first electrode, a unit cell, and a second electrode over a substrate includes the steps of: forming a plasma region between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a chamber of a plasma CVD apparatus is set to from 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to from 1 mm to 20 mm, preferably, 4 mm to 16 mm; forming deposition precursors including a crystalline semiconductor in a gas phase including the plasma region; forming a crystal nucleus having a grain size of from 5 nm to 15 nm by depositing the deposition precursors; and forming a semiconductor film having a first conductivity type, a semiconductor film effective in photoelectric conversion, or a semiconductor film having a first conductivity type in the unit cell, by growing a crystal from the crystal nucleus. | 2011-03-03 |
20110053312 | METHOD FOR THE CONTACT SEPARATION OF ELECTRICALLY-CONDUCTING LAYERS ON THE BACK CONTACTS OF SOLAR CELLS AND CORRESPONDING SOLAR CELL - A method for fabricating a solar cell comprising a semiconductor substrate is proposed where electrical contacting is made on the back side of the semiconductor substrate. The back side of the semiconductor substrate has locally doped regions. The adjacent regions exhibit different doping from the region. The two regions are initially coated with electrically conductive material over the entire area. So that the conductive material does not short-circuit the solar cell, the two regions are covered with a thin electrically insulating layer at least at the region boundaries. | 2011-03-03 |
20110053313 | MANUFACTURING METHOD OF ORGANIC SEMICONDUCTOR DEVICE - The present invention provides a manufacturing method of an organic semiconductor device comprising a step of transferring an organic semiconductor layer to a gate insulation layer by a thermal transfer at a liquid crystal phase transition temperature of a liquid crystalline organic semiconductor material, and the step uses: an organic semiconductor layer-transferring substrate comprising a parting substrate having parting properties, and the organic semiconductor layer formed on the parting substrate and containing the liquid crystalline organic semiconductor material; and a substrate for forming an organic semiconductor device comprising a substrate, a gate electrode formed on the substrate, and the gate insulation layer formed to cover the gate electrode and having alignment properties which are capable of aligning the liquid crystalline organic semiconductor material on a surface of the gate insulation layer. | 2011-03-03 |
20110053314 | Method of Fabricating Top Gate Organic Semiconductor Transistors - The present invention provides a method of fabricating a top-gate organic semiconductor transistor comprising: providing a substrate; depositing a source and drain electrode over the substrate; depositing an organic semiconductor material in a channel between the source and drain electrode and over at least a portion of the source and drain electrodes; depositing a dielectric material over the organic semiconductor material; depositing a gate electrode over the dielectric material and organic semiconductor material in the channel; removing a portion of the dielectric material and organic semiconductor material, wherein the gate electrode acts as a mask to shield the underlying organic semiconductor material and dielectric material during the step of removing. | 2011-03-03 |
20110053315 | ORGANIC THIN FILM TRANSISTOR SUBSTRATE AND FABRICATION METHOD THEREFOR - An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer. | 2011-03-03 |
20110053316 | Organic Thin Film Transistor With Tunneling Barrier Layer and Method for Manufacturing the Same - An organic thin film transistor includes a buffer layer on a substrate, a source and drain electrodes on the buffer layer, wherein each of the source and drain electrodes is in an island shape, a tunneling barrier layer on the source and drain electrodes, an organic semiconductor layer on the tunneling barrier layer, a gate insulation layer on the organic semiconductor layer, and a gate electrode overlapping both edges of the source and drain electrodes, and formed on the gate insulation layer. | 2011-03-03 |
20110053317 | PHASE CHANGE RAM DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a phase change RAM device and a method for fabricating a phase change RAM device, which can efficiently lower intensity of current required for changing a phase of a phase change layer. The method includes the steps of providing a semiconductor substrate formed with an insulating interlayer including a tungsten plug, forming a first oxide layer on the semiconductor substrate, forming a pad-type bottom electrode, which makes contact with the tungsten plug, in the first oxide layer, forming a second oxide layer on the first oxide layer including the bottom electrode, and forming a porous polystyrene pattern on the second oxide layer such that a predetermined portion of the second oxide layer corresponding to a center portion of the bottom electrode is covered with the porous polystyrene pattern. | 2011-03-03 |
20110053318 | FABRICATION METHOD OF PACKAGE STRUCTURE - Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other. In the fabrication process, the alignment error between packaging substrate units in each packaging substrate block can be reduced by cutting the packaging substrate into packaging substrate blocks of appropriate size, thereby increasing the yield, and also the packaging of the semiconductor chips can be performed at the same time on all packaging substrate units in each substrate block so as to integrate fabrication of substrates with the packaging of semiconductor chips to simplify fabrication steps, thus increasing the productivity and reducing fabrication costs. | 2011-03-03 |
20110053319 | Method for Fabricating a Circuit Substrate Assembly and a Power Electronics Module Comprising an Anchoring Structure for Producing a Changing Temperature-Stable Solder Bond - A power semiconductor module is fabricated by providing a circuit substrate with a metal surface and an insulating substrate comprising an insulation carrier featuring a bottom side provided with a bottom metallization layer. An anchoring structure is provided comprising a plurality of oblong pillars each featuring a first end facing away from the insulation carrier, at least a subset of the pillars being distributed over the anchoring structure in its entirety, it applying for each of the pillars of the subset that from a sidewall thereof no or a maximum of three elongated bonding webs each extend to a sidewall of another pillar where they are bonded thereto. The anchoring structure is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom metallization layer and anchoring structure by means of a solder packing all interstices between the metal surface and bottom metallization layer with the solder. | 2011-03-03 |
20110053320 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming a debonding layer constituted with a thermoplastic resin on a supporting material, and forming an insulating layer constituted with a thermosetting resin including a solvent dissolving the thermoplastic resin on the debonding layer. | 2011-03-03 |
20110053321 | METHOD OF FABRICATING AND ENCAPSULATING MEMS DEVICES - A method of fabricating and encapsulating MEMS devices is disclosed, using least two carbon films as the dual sacrificial layers sandwiching a MEMS structural film which is anchored onto a substrate and covered by an encapsulating film containing a plurality of thru-film sacrificial release holes. The dual sacrificial carbon films are selectively removed via plasma-enhanced oxygen or nitrogen ashing through the thru-film sacrificial release holes for releasing the MEMS structural film inside a cavity formed between the encapsulating film and the substrate. The thru-film sacrificial release holes, preferably with a relative high asperity ratio, are then sealed off by depositing a hole-sealing film in a physical vapor deposition process or a chemical vapor deposition process or combination. | 2011-03-03 |
20110053322 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (which is for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. Besides impurities such as moisture existing in the oxide semiconductor film, heat treatment causes reduction of impurities such as moisture existing in the gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor film and are in contact with the oxide semiconductor film. | 2011-03-03 |
20110053323 | PHOTOMASK AND METHOD FOR FABRICATING SOURCE/DRAIN ELECTRODE OF THIN FILM TRANSISTOR - A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed. | 2011-03-03 |
20110053324 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions. | 2011-03-03 |
20110053325 | Method for producing semiconductor device - The invention provides a method for producing a semiconductor device that can reduce the number of mask steps. In a CMOS production process, gate electrodes are formed in regions for forming an NMOS and a PMOS at the same time with a common mask pattern, and after the gate electrodes have been formed, a well, and source and drain regions are formed by impurity ion implantations with a common mask pattern in each region of the NMOS and the PMOS, using the gate electrode as a mask, whereby the number of mask steps is reduced. | 2011-03-03 |
20110053326 | SUPER JUNCTION TRENCH POWER MOSFET DEVICE FABRICATION - Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant. | 2011-03-03 |
20110053327 | METHOD OF FORMING RECESS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE SAME - Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer. | 2011-03-03 |
20110053328 | METHOD FOR MANUFACTURING MEMORY CELL - In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type. | 2011-03-03 |
20110053329 | Semiconductor device including a gate electrode of lower electrial resistance and method of manufacturing the same - A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented. | 2011-03-03 |
20110053330 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - When transistors having different gate lengths are formed on one substrate and an ESD structure is applied to at least a transistor having longer gate length, a method including: depositing a gate insulating film and a gate electrode material layer on the substrate; forming a first gate electrode having a longer gate length in a first region; forming a first insulating film on a whole surface; forming a second gate electrode including the first insulating film and having a shorter gate length in a second region; forming a second insulating film on a whole surface; forming second sidewalls made of the second insulating film on sidewalls of the second gate electrode; forming first sidewalls made of the first and second insulating films on sidewalls of the first gate electrode; forming a selectively epitaxially grown layer on at least exposed substrate of the first region and implanting ions into the substrate via the selectively epitaxially grown layer, thereby forming an ESD structure. | 2011-03-03 |
20110053331 | BIPOLAR TRANSISTOR FINFET TECHNOLOGY - This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus. | 2011-03-03 |
20110053332 | SEMICONDUCTOR CIRCUIT - A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device. | 2011-03-03 |
20110053333 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer. | 2011-03-03 |
20110053334 | PHASE CHANGE MEMORY DEVICE WITH HEATER ELECTRODES HAVING FINE CONTACT AREA AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode. | 2011-03-03 |
20110053335 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE - A method of forming a semiconductor device includes the following processes. A heater electrode film is formed in a first inter-layer insulating film that is over a semiconductor substrate. A mask is formed over the heater electrode film. The first inter-layer insulating film is selectively removed using the mask to expose a side surface of an upper portion of the heater electrode film. The exposed side surface of the heater electrode film is subjected to an anisotropic etching process using the mask, to selectively remove the heater electrode film to form a heater electrode which is tapered to its top. The mask is removed. A phase change recording layer is formed, which contacts the top of the heater electrode. | 2011-03-03 |
20110053336 | METHOD FOR SELECTIVE DEPOSITION OF DIELECTRIC LAYERS ON SEMICONDUCTOR STRUCTURES - A method for forming a capacitor and a transistor device on different surface portions of a semiconductor structure includes forming a passivation dielectric layer for the device; forming a bottom electrode for the capacitor; forming a removable layer extending over the bottom electrode and over the passivation dielectric layer with a window therein, such window exposing said bottom electrode; depositing a capacitor dielectric layer of the same or different material as the passivation dielectric layer over the removable layer with first portions passing through the window onto the exposed bottom electrode and second portions being over the removable layer, the thickness of the deposited layer being different from the thickness of the passivation layer; removing the removable layer with the second portions thereon while leaving said first portions on the bottom electrode; and forming a top electrode for the capacitor on the second portions remaining on the bottom electrode. | 2011-03-03 |
20110053337 | SELF-ALIGNMENT METHOD FOR RECESS CHANNEL DYNAMIC RANDOM ACCESS MEMORY - A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer. | 2011-03-03 |
20110053338 | FLASH MEMORY AND METHOD OF FABRICATING THE SAME - In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer. | 2011-03-03 |
20110053339 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method for manufacturing a semiconductor device includes forming a first conductor layer on a surface of a semiconductor layer via a tunnel insulating film. The method includes forming an isolation trench extending from a surface of the first conductor layer to the semiconductor layer to form a plurality of conductive plates on the tunnel insulating film. The method includes filling the isolation trench with an element insulation insulating film from bottom of the isolation trench to an intermediate portion of a side surface of each of the conductive plates. The method includes forming a silicon nitride film on an exposed surface of the each of the conductive plates not covered with the element insulation insulating film. In addition, the method includes filling an upper portion of the isolation trench by forming a second conductor layer above the conductive plates and the element insulation insulating film. | 2011-03-03 |
20110053340 | METHOD OF FORMING A TRENCH ISOLATION - A method of forming a trench isolation, comprising the steps of:
| 2011-03-03 |
20110053341 | INTEGRATED CIRCUIT ARRANGEMENT COMPRISING ISOLATING TRENCHES AND A FIELD EFFECT TRANSISTOR AND ASSOCIATED PRODUCTION METHOD - A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array. | 2011-03-03 |
20110053342 | SEMICONDUCTOR SUBSTRATE SURFACE PREPARATION METHOD - The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface. | 2011-03-03 |
20110053343 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device. | 2011-03-03 |
20110053344 | SEMICONDUCTOR ON INSULATOR AND METHODS OF FORMING SAME USING TEMPERATURE GRADIENT IN AN ANODIC BONDING PROCESS - Methods and apparatus for producing a semiconductor on glass (SOG) structure include: bringing a first surface of a glass substrate into direct or indirect contact with a semiconductor wafer; heating at least one of the glass substrate and the semiconductor wafer such that a second surface of the glass substrate, opposite to the first surface thereof, is at a lower temperature than the first surface; applying a voltage potential across the glass substrate and the semiconductor wafer; and maintaining the contact, heating and voltage to induce an anodic bond between the semiconductor wafer and the glass substrate via electrolysis. | 2011-03-03 |
20110053345 | METHOD FOR REPROCESSING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING REPROCESSED SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SOI SUBSTRATE - An object is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; and etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left. | 2011-03-03 |
20110053346 | DICING/DIE BONDING FILM - A dicing die-bonding film comprising a dicing film having a pressure-sensitive adhesive layer on a base material, and a die-bonding film formed on the dicing film, wherein the pressure-sensitive adhesive layer contains a polymer obtained by the addition reaction of an acrylic polymer containing 10 to 40 mol % of a hydroxyl group-containing monomer with 70 to 90 mol % of an isocyanate compound having a radical reactive carbon-carbon double bond based on the hydroxyl group-containing monomer, and 2 to 20 parts by weight of a crosslinking agent including in the molecule two or more functional groups having reactivity with a hydroxyl group based on 100 parts by weight of the polymer, and the pressure-sensitive adhesive layer is also cured by irradiation with ultraviolet rays under predetermined conditions, and wherein the die-bonding film comprises an epoxy resin, and is also bonded on the pressure-sensitive adhesive layer after irradiation with ultraviolet rays. | 2011-03-03 |
20110053347 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a method for manufacturing an SOI substrate in which reduction in yield can be suppressed while impurity diffusion into a semiconductor film is suppressed. A semiconductor substrate provided with an oxide film is formed by thermally oxidizing the surface of the semiconductor substrate. Plasma is generated under an atmosphere of a gas containing nitrogen atoms and plasma nitridation is performed on part of the oxide film, so that a semiconductor substrate in which an insulating film containing nitrogen atoms is formed over the oxide film is obtained. After bonding the insulating film containing nitrogen atoms and a glass substrate to each other, the semiconductor substrate is split, whereby an SOI substrate in which the insulating film containing nitrogen atoms, the oxide film, a thin semiconductor film are stacked in this order is formed. | 2011-03-03 |
20110053348 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved. | 2011-03-03 |
20110053349 | APPLICATION OF MILLISECOND HEATING SOURCE FOR SURFACE TREATMENT - A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second. | 2011-03-03 |
20110053350 | SILICON WAFER - A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas. | 2011-03-03 |
20110053351 | Solar Cell Defect Passivation Method - The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency. | 2011-03-03 |
20110053352 | Method of forming a passivated densified nanoparticle thin film on a substrate - A method for forming a passivated densified nanoparticle thin film on a substrate in a chamber is disclosed. The method includes depositing a nanoparticle ink on a first region on the substrate, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 400° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes flowing an oxidizer gas into the chamber; and heating the porous compact to a second temperature between about 600° C. and about 1000° C., and for a second time period of between about 5 seconds and about 1 hour; wherein the passivated densified nanoparticle thin film is formed. | 2011-03-03 |
20110053353 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed. | 2011-03-03 |
20110053354 | METHOD OF MANUFACTURING LAYER-STACKED WIRING - A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film. | 2011-03-03 |
20110053355 | Plasma apparatus and method of fabricating nano-crystalline silicon thin film - A plasma apparatus having a chamber, a set of arc electrodes and a substrate holder is provided. The set of arc electrodes disposed within the chamber has an anode and a cathode, wherein an arc forming space is formed between the anode and the cathode. The anode and the cathode respectively have a crystallized silicon target. The crystallized silicon target of the anode is disposed on an end facing to that of the cathode, wherein the resistance of the crystallized silicon targets is smaller than 0.01 Ω·cm. The substrate holder is disposed within the chamber and has a carrying surface, wherein the carrying surface is face to the arc forming space. Besides, a method of fabricating nano-crystalline silicon thin film is also provided. By using the plasma apparatus, a nano-crystalline silicon thin film with high quality is formed. | 2011-03-03 |
20110053356 | GAS MIXING METHOD REALIZED BY BACK DIFFUSION IN A PECVD SYSTEM WITH SHOWERHEAD - Embodiments of the present invention generally relate to methods of forming a microcrystalline silicon layer on a substrate in a deposition chamber. In, one embodiment, the method includes flowing a processing gas into a diffuser region between a backing plate and a showerhead of the deposition chamber, flowing the processing gas through a plurality of holes in the showerhead and into a process volume between the showerhead and a substrate support in the deposition chamber, igniting a plasma in the process volume, back-flowing gas ions formed in the plasma through the plurality of holes in the showerhead and into the diffuser region, mixing the gas ions and the processing gas in the diffuser region, re-flowing the gas ions and processing gas through the plurality of holes in the showerhead and into the process volume, and depositing a microcrystalline silicon layer on the substrate. | 2011-03-03 |
20110053357 | PLASMA CVD APPARATUS, METHOD FOR FORMING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A structure of a plasma CVD apparatus for forming a dense semiconductor film is provided. Further, a technique for forming a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains is provided. An electrode supplied with electric power for generating plasma is included in a reaction chamber of the plasma CVD apparatus. This electrode has a common plane on a surface opposite to a substrate, and the common plane is provided with depressed openings. Gas supply ports are provided on the bottom of the depressed openings or on the common plane of the electrode. The depressed openings are provided in isolation from one another. | 2011-03-03 |
20110053358 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus. | 2011-03-03 |
20110053359 | METHODS OF MANUFACTURING QUANTUM WELL MATERIALS - Processes for economical large scale commercial production of blocks of quantum well particles, platelets, or continuous sheets of material imparting minimal or essentially no parasitic substrate loss in quantum well devices such as thermoelectric generators in which the blocks are embodied involve roll to roll processing, i.e., deposition and crystallization of alternating layers of quantum well materials, on an elongate and continuous base layer of appreciable width. Blocks of quantum well materials having no attached base layer are produced on decomposable or release treated base layers. | 2011-03-03 |
20110053360 | PLASMA IMMERSED ION IMPLANTATION PROCESS USING BALANCED ETCH-DEPOSITION PROCESS - Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, generating a plasma from a gas mixture including a reacting gas and a etching gas in the chamber, adjusting the ratio between the reacting gas and the etching gas in the supplied gas mixture and implanting ions from the plasma into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a halogen containing reducing gas into the chamber, forming a plasma from the gas mixture, gradually increasing the ratio of the etching gas in the gas mixture, and implanting ions from the gas mixture into the substrate. | 2011-03-03 |
20110053361 | FinFET Formation with a Thermal Oxide Spacer Hard Mask Formed from Crystalline Silicon Layer - A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer ( | 2011-03-03 |
20110053362 | METHOD OF FORMING A MASK PATTERN, METHOD OF FORMING A MINUTE PATTERN, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns. | 2011-03-03 |
20110053363 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell. | 2011-03-03 |
20110053364 | Method of manufacturing semiconductor device - A layer to be etched is first formed in a substrate. Then, a mask pattern is formed over the layer to be etched. Then, the layer to be etched is wet-etched using the mask pattern as a mask. In the procedure of performing wet etching, the substrate is dipped into an etching bath with the mask pattern downward. | 2011-03-03 |
20110053365 | METHOD OF MANUFACTURING GATE STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE SAME - In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution. | 2011-03-03 |
20110053366 | METHODS OF FABRICATING MEMORY DEVICES - Methods of fabricating a memory device can include forming a plurality of wordlines on a semiconductor substrate. A ground select line can be formed on a first side of the wordlines. A string select line can be formed on a second side of the wordlines. The wordlines can extend between the ground select line and the string select line. First spacers may be formed between the wordlines, between the ground select line and an adjacent one of the wordlines and between the string select line and an adjacent one of the wordlines. Second spacers can be formed on sidewalls of the ground select line and the string select line displaced from the first spacers. The second spacers can be formed from a different material than the first spacers. | 2011-03-03 |
20110053367 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode. | 2011-03-03 |
20110053368 | Arrangement for solder bump formation on wafers - An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon. | 2011-03-03 |
20110053369 | Methods of manufacturing a semiconductor memory device - Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer. | 2011-03-03 |
20110053370 | METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME - A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WN | 2011-03-03 |
20110053371 | SEMICONDUCTOR PROCESS - A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein. | 2011-03-03 |
20110053372 | Low Temperature Surface Preparation for Removal of Organometallic Polymers in the Manufacture of Integrated Circuits - A method of removing photoresist from a surface during the manufacture of an integrated circuit. Organometallic polymers and monomers are formed during the etch of a hard mask material defining the locations of a metal-bearing film, such as tantalum nitride, when photoresist is used to mask the hard mask etch. These organometallic polymers and monomers as formed are not fully cross-linked. A liquid phase solution of sulfuric acid and hydrogen peroxide used to remove the photoresist also removes these not-fully-cross-linked organometallic polymers and monomers, thus preventing the formation of stubborn contaminants during subsequent high temperature processing. | 2011-03-03 |