09th week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140054609 | LARGE HIGH-QUALITY EPITAXIAL WAFERS - Large high-quality epitaxial wafers are disclosed. Embodiments of the invention provide silicon carbide epitaxial wafers with low basal plane dislocation (BPD) densities. In some embodiments, these wafers are of the 4H polytype. These wafers can be at least about 100 mm in diameter and have an epitaxial layer from about 1 micron to about | 2014-02-27 |
20140054610 | SEMICONDUCTOR DEVICE AND METHOD FOR GROWING SEMICONDUCTOR CRYSTAL - A semiconductor device comprises a base substrate, a pattern on the base substrate, a buffer layer on the base substrate, and an epitaxial layer on the buffer. The pattern is a self-assembled pattern. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled pattern on the silicon carbide substrate, forming a buffer layer on the silicon carbide substrate, and forming an epitaxial layer on the buffer layer. A semiconductor device comprises a base substrate comprising a pattern groove and an epitaxial layer on the base substrate. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled projection on the silicon carbide substrate, forming a pattern groove in the silicon carbide, and forming an epitaxial layer on the silicon carbide. | 2014-02-27 |
20140054611 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches. | 2014-02-27 |
20140054612 | BIPOLAR JUNCTION TRANSISTOR IN SILICON CARBIDE WITH IMPROVED BREAKDOWN VOLTAGE - A silicon carbide (SiC) bipolar junction transistor (BJT) including a collector region and a base region having an extrinsic part. The SiC BJT including an emitter region and a surface passivation layer deposited on the extrinsic part between an emitter contact contacting the emitter region and a base contact contacting the base region. The SiC BJT also including a surface gate at the surface passivation layer. | 2014-02-27 |
20140054613 | Light-Emitting Transistors with Improved Performance - Disclosed are light-emitting transistors having novel structures that can lead to enhanced device brightness, specifically, via incorporation of additional electrically insulating components that can favor charge localization and in turn, carrier recombination and exciton formation. | 2014-02-27 |
20140054614 | SEMICONDUCTOR DEVICE HAVING OPTICALLY-COUPLED ELEMENT - According to one embodiment, a semiconductor device includes a light-emitting element, a light-receiving element, a primary side lead electrically connected to the light-emitting element, a secondary side lead electrically connected to the light-receiving element and a molded body. The molded body includes an internal resin, an external resin and a light shielding layer. The internal resin covers a portion fixed with the light-emitting element of the primary side lead and a portion fixed with the light-receiving element of the secondary side lead. The external resin covers the internal resin, and shields external light to which the light-receiving element is sensitive. The light shielding layer is provided at a position closer to the second surface than any of the light-emitting element, the light-receiving element, the primary side lead, and the secondary side lead, and shielding the external light. | 2014-02-27 |
20140054615 | CHIP WITH SEMICONDUCTOR ELECTRICITY CONVERSION STRUCTURE - A semiconductor electricity conversion structure is provided. The semiconductor electricity conversion structure includes: a substrate; and at least one semiconductor electricity conversion structure formed on the substrate, the at least one semiconductor electricity conversion structure including: at least one semiconductor electricity-to-light conversion unit for converting an input electric energy into a light energy, and at least one semiconductor light-to-electricity conversion unit for converting the light energy back into an output electric energy, in which a number of the semiconductor electricity-to-light conversion unit is in proportion to a number of the semiconductor light-to-electricity conversion unit to realize an electricity conversion, and an emitting spectrum of the semiconductor electricity-to-light conversion unit and an absorption spectrum of the semiconductor light-to-electricity conversion unit are matched with each other. | 2014-02-27 |
20140054616 | Method and Apparatus for Fabricating Phosphor-Coated LED Dies - The present disclosure involves a method of packaging a light-emitting diode (LED). According to the method, a group of metal pads and a group of LEDs are provided. The group of LEDs is attached to the group of metal pads, for example through a bonding process. After the LEDs are attached to the metal pads, each LED is spaced apart from adjacent LEDs. Also according to the method, a phosphor film is coated around the group of LEDs collectively. The phosphor film is coated on top and side surfaces of each LED and between adjacent LEDs. A dicing process is then performed to slice through portions of the phosphor film located between adjacent LEDs. The dicing process divides the group of LEDs into a plurality of individual phosphor-coated LEDs. | 2014-02-27 |
20140054617 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - Embodiments of the present invention provide an array substrate, comprising: a base substrate; a gate line and a data line formed on the base substrate, the gate line and the data line crossing with each other to define a pixel region; a thin film transistor and a pixel electrode, disposed in the pixel region; a strip-like common electrode, disposed above the pixel electrode and the data line, the common electrode comprising a first common electrode which covers above the data line and has a width greater than that of the data line; and a second common electrode, disposed above the pixel electrode; an insulating layer, disposed between the common electrode and the pixel electrode as well as between the common electrode and the data line, wherein a region of the first common electrode corresponding to the data line is hollowed out. | 2014-02-27 |
20140054618 | LIGHT-EMITTING DIODE DEVICES - An LED device includes an LED chip having a sapphire substrate, a first-type semiconductor layer on the substrate, a second-type semiconductor layer disposed on the first-type semiconductor layer, a first via hole passing through the sapphire substrate and the first-type semiconductor layer, a second via hole passing through the sapphire substrate, and an insulation layer coated on an inner wall of the first via hole; a transparent conductive layer made of electrically conductive material and formed on the second-type semiconductor layer; a cover layer formed on the transparent conductive layer; electrical conductors, each disposed within one of the via holes, wherein the electrical conductor in the first via hole is electrically connected to the second-type semiconductor layer and the electrical conductor in the second via hole is electrically connected to the first-type semiconductor layer; and two linkers for connection to external circuitry, formed on a surface of the sapphire. | 2014-02-27 |
20140054619 | Method and Apparatus for Packaging Phosphor-Coated LEDS - The present disclosure involves a method of packaging light-emitting diodes (LEDs). According to the method, a plurality of LEDs is provided over an adhesive tape. The adhesive tape is disposed on a substrate. In some embodiments, the substrate may be a glass substrate, a silicon substrate, a ceramic substrate, and a gallium nitride substrate. A phosphor layer is coated over the plurality of LEDs. The phosphor layer is then cured. The tape and the substrate are removed after the curing of the phosphor layer. A replacement tape is then attached to the plurality of LEDs. A dicing process is then performed to the plurality of LEDs after the substrate has been removed. The removed substrate may then be reused for a future LED packaging process. | 2014-02-27 |
20140054620 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - Embodiments of the present invention provide an array substrate, a method for manufacturing the same and a display device. The method for manufacturing a thin film transistor array substrate comprises: forming a passivation layer and a resin layer on a substrate in sequence; removing a part of the resin layer through a patterning process, so as to form a resin-layer via hole passing through the resin layer; etching the passivation layer under the resin-layer via hole, so as to form a via hole passing through the resin layer and the passivation layer; treating the via hole with an etching process, so that a sidewall at the resin layer and a sidewall at the passivation layer for the via hole smoothly adjoin. | 2014-02-27 |
20140054621 | SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING TRANSPARENT PLATE WITH SLANTED SIDE SURFACE - In a semiconductor light-emitting device including a substrate, a semiconductor light-emitting element mounted on a top surface of the substrate, a transparent plate adapted to cover a top surface of the semiconductor light-emitting element, a wavelength-converting layer formed between a top surface of the semiconductor light-emitting element and a bottom surface of the transparent plate, and a reflective material layer surrounding all side surfaces of the semiconductor light-emitting element, the wavelength-converting layer and the transparent plate, at least one of the side surfaces of the transparent plate is slanted in an inward direction at the bottom surface of the transparent plate. | 2014-02-27 |
20140054622 | LIGHT EMITTING PACKAGE - The present invention discloses a light emitting package, including: a base; a light emitting device on the base; an electrical circuit layer electrically connected to the light emitting device; a screen member having an opening and disposed on the base adjacent to the light emitting device; and a lens covering the light emitting device, wherein a width of a cross-sectional shape of the screen member is larger than a height of the cross sectional shape of the screen member, wherein the lens is disposed on the screen member, and wherein the lens is connected to an uppermost surface of the screen member. | 2014-02-27 |
20140054623 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes: a semiconductor chip having a nonpolar plane as a growth surface and configured to emit polarized light; and a reflector having a reflective surface. When a plane forming an angle of 45° relative to a direction of polarization of the polarized light is a plane L | 2014-02-27 |
20140054624 | DISPLAY PANEL - A display device includes a plurality of pixel units. Each of the pixel units at least includes three sub-pixels for displaying different colors. The three sub-pixels are electrically connected to three different gate lines, and at least two of the three sub-pixels are electrically connected to the same data line. | 2014-02-27 |
20140054625 | VERTICAL LIGHT EMITTING DIODES - A tunable colour LED module comprises at least two sub-modules, each comprising an LED, a wavelength converting element (WCE) and a reflector cup. The total light emitted by the module comprises light generated from each LED and WCE and the module is configured to emit a total light having a predefined colour chromaticity when activation properties of the LEDs are managed appropriately. The total light may have a broad white emission spectrum. The module combines the benefits of a low cost with uniform chromaticity properties in the far field, and offers long and controlled lifetime at the same time as flexibility and intelligence of tunable colour chromaticity, Colour Rendering Index (CRI) and intensity, either at manufacture or in an end user lighting application. A controlled LED module system comprises a control system for the managing activation properties of the LEDs in the sub-modules. Also described is a method of manufacture. | 2014-02-27 |
20140054626 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS - The present disclosure relates to an array substrate and the manufacturing method thereof, and a display apparatus. The manufacturing method of the array substrate comprises following step. A gate insulating layer and an active layer is formed on the substrate with said gate electrode and said common electrode formed thereon. A source drain layer is formed on the substrate with said gate insulating layer and said active layer formed thereon. A passivation layer is formed on the substrate with said source drain layer formed thereon, and a through hole is formed in the passivation layer; a pixel electrode is formed on the substrate with said passivation layer formed thereon with said through hole. The pixel electrode is connected to the drain electrode in the source drain layer through said through hole. The process for forming the pixel electrode comprises first etching, ashing and second etching. | 2014-02-27 |
20140054627 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a circuit board with a layout layer and a die bonding area. At least one positive endpoint, negative endpoint and function endpoint are disposed on the layout layer. At least one semiconductor light-emitting chip is disposed within the die bonding area, and is electrically coupled to the positive endpoint, the negative endpoint and the function endpoint to facilitate various connection configurations. | 2014-02-27 |
20140054628 | SUBSTRATE, LIGHT-EMITTING DEVICE, AND LIGHTING APPARATUS - A substrate on which LEDs are to be mounted to form an element row and which includes a first line and a second line disposed such that the element row is interposed therebetween. The first line includes a first main line portion extending mainly in the row direction of the element row, and a first connecting portion including a portion for connecting to the LEDs. The second line includes a second main line portion extending mainly in the row direction of the element row, and a second connecting portion including a portion for connecting to the LEDs. The gap between the first main line portion and the second main line portion is larger at LED mounting positions than at positions other than the LED mounting positions. | 2014-02-27 |
20140054629 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM HAVING THE SAME - Disclosed are light emitting device and a lighting system including the same. The light emitting device includes a body including first and second sidewalls having a first length and corresponding to each other, third and fourth sidewalls close to the first and second sidewalls and having a second length shorter than the first length, and a concave portion having an open upper portion; a first lead frame disposed in the concave portion of the body and including a first cavity having a depth lower than a bottom of the concave portion; a second lead frame disposed in the concave portion of the body and including a second cavity having a depth lower than the bottom of the concave portion; a gap part between the first and second lead frames; a first light emitting chip in the first cavity; and a second light emitting chip in the second cavity. | 2014-02-27 |
20140054630 | TFT-LCD Array Substrate And Display Device - A TFT-LCD array substrate and a display device. The TFT-LCD array substrate comprises a pixel area the pixel area comprising a plurality of pixel units arranged in an array, and each of the pixel units comprising a first electrode and a second electrode generating a horizontal electric field with the first electrode. The second electrode comprises strip electrodes, and the strip electrodes constitute a radial pattern of a regular triangle, a regular polygon or a circle in each of the pixel units. | 2014-02-27 |
20140054631 | LED ARRAY - An LED array having N light-emitting diode units (N≧3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer. | 2014-02-27 |
20140054632 | SILICONE COATED LIGHT-EMITTING DIODE - A silicone protective coating for an electronic light source and a method for applying the coating over an exposed or outer surface of the electronic light source assembled as part of or mounted to a circuit board or other substrate. | 2014-02-27 |
20140054633 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate and a light emitting structure including a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer provided in a first direction on the substrate. A first electrode layer is provided over the first conductive type semiconductor layer, and a second electrode layer is provided in a second direction over the second conductive type semiconductor layer. The second electrode layer has an energy band gap wider than an energy band gap of the active layer. | 2014-02-27 |
20140054634 | SILICATE PHOSPHOR EXHIBITING HIGH LIGHT EMISSION CHARACTERISTICS AND MOISTURE RESISTANCE, AND LIGHT EMITTING DEVICE - A silicate phosphor having a coating layer comprising a fluorine-containing compound on its surface which is obtained by a method of heating a mixture of 100 weight parts of a silicate phosphor and 0.5-15 weight parts of ammonium fluoride at a temperature in the range of 200 to 600° C. exhibits high light emission intensity and high moisture resistance. | 2014-02-27 |
20140054635 | CARRIER FOR AN OPTOELECTRONIC STRUCTURE AND OPTOELECTRONIC SEMICONDUCTOR CHIP COMPRISING SUCH A CARRIER - A carrier ( | 2014-02-27 |
20140054636 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR FABRICATING THE SAME - This nitride-based semiconductor light-emitting element includes: a nitride-based semiconductor multilayer structure including a p-type semiconductor region, the nitride-based semiconductor multilayer structure having a growing plane which is an m-plane; and an electrode which is arranged on an Al | 2014-02-27 |
20140054637 | Omnidirectional Reflector - A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the efficiency of the distributed Bragg reflector. A first contact layer, an active layer, and a second contact layer are preferably either formed over the photonic crystal layer or alternatively attached to the photonic crystal layer. | 2014-02-27 |
20140054638 | LIGHT EMITTING DEVICES HAVING SHIELDED SILICON SUBSTRATES - Light emitting devices comprise a light emitting component, such as a GaN LED having active material layers supported by a Silicon substrate, which can be a growth substrate, or attached. Phosphor(s) can be disposed relative to the light emitting component to absorb a primary emission, and produce a secondary emission that can be relatively tuned or selected so that their combination produces light of a desired spectrum, such as light appearing white. The Silicon substrate has exposed sidewalls, which can be angled, with respect to planar surfaces of the substrate, and a light reflecting material, such as a diffusely reflective material coats the sidewalls. The reflective material can be opaque to the primary and secondary emissions. If other exposed portions of the Silicon substrate exist and are exposed to primary or secondary light, these other exposed portions can be coated with such light reflecting material. | 2014-02-27 |
20140054639 | METHOD OF FABRICATING VERTICAL STRUCTURE LEDS - A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out. | 2014-02-27 |
20140054640 | DISTRIBUTED CURRENT BLOCKING STRUCTURES FOR LIGHT EMITTING DIODES - An LED device includes a strip-shaped electrode, a strip-shaped current blocking structure and a plurality of distributed current blocking structures. The current blocking structures are formed of an insulating material such as silicon dioxide. The strip-shaped current blocking structure is located directly underneath the strip-shaped electrode. The plurality of current blocking structures may be disc shaped portions disposed in rows adjacent the strip-shaped current blocking structure. Distribution of the current blocking structures is such that current is prevented from concentrating in regions immediately adjacent the electrode, thereby facilitating uniform current flow into the active layer and facilitating uniform light generation in areas not underneath the electrode. In another aspect, current blocking structures are created by damaging regions of a p-GaN layer to form resistive regions. In yet another aspect, current blocking structures are created by etching away highly doped contact regions to form regions of resistive contact between conductive layers. | 2014-02-27 |
20140054641 | INTEGRATING A TRENCH-GATED THYRISTOR WITH A TRENCH-GATED RECTIFIER - An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode. | 2014-02-27 |
20140054642 | ESD PROTECTION DEVICE WITH IMPROVED BIPOLAR GAIN USING CUTOUT IN THE BODY WELL - An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor. | 2014-02-27 |
20140054643 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - The invention discloses an ESD protection circuit, including a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively. | 2014-02-27 |
20140054644 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n | 2014-02-27 |
20140054645 | INSULATED-GATE BIPOLAR TRANSISTOR - In an IGBT, a trench extending in a bent shape to have a corner is formed in an upper surface of a semiconductor substrate. The inside of the trench is covered with an insulating film. A gate is placed inside the trench. An emitter and a collector are formed on an upper surface and a lower surface of the semiconductor substrate, respectively. An emitter region, a body region, a drift region, and a collector region are formed in the semiconductor substrate. The emitter region is formed of an n-type semiconductor, is in contact with the insulating film, and is in ohmic contact with the emitter electrode. The body region is formed of a p-type semiconductor, is in contact with the insulating film below the emitter region, is in contact with the insulating film of an inner corner portion of the trench, and is in ohmic contact with the emitter electrode. | 2014-02-27 |
20140054646 | Apparatus and Method for Multiple Gate Transistors - An apparatus comprises a substrate having a first crystal orientation and an active region, wherein an upper portion of the active region is of a second crystal orientation and the upper portion of the active region is wrapped by a gate structure around two sides. The apparatus further comprises a trench surrounded by isolation regions, wherein the upper portion of the active region is over top surfaces of the isolation regions. | 2014-02-27 |
20140054647 | HIGH ELECTRON MOBILITY BIPOLAR TRANSISTOR - A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×10 | 2014-02-27 |
20140054648 | NEEDLE-SHAPED PROFILE FINFET DEVICE - Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel. | 2014-02-27 |
20140054649 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES INCLUDING A RETROGRADE WELL - Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon. | 2014-02-27 |
20140054650 | Method for Increasing Fin Density - The present disclosure is directed to a method of manufacturing a FinFET structure in which at least one initial set of fin structures is formed by photolithographic processes, followed by forming an additional fin structure by epitaxial growth of a semiconductor material between the initial set of fin structures. The method allows for formation of FinFET structures having increased fin density. | 2014-02-27 |
20140054651 | RELIABLE NANOFET BIOSENSOR PROCESS WITH HIGH-K DIELECTRIC - Provided are semiconductor field effect sensors including a high-k thin film gate dielectric. The semiconductor field effect sensors described herein exhibit high detection sensitivity and enhanced reliability when placed in contact with liquids. Also disclosed are semiconductor field effect sensors having optimized fluid gate electrode voltages and/or back gate electrode voltages for improved detection sensitivity. | 2014-02-27 |
20140054652 | STIMULATED PHONON EMISSION DEVICE AND OSCILLATOR, FREQUENCY FILTER, COOLING DEVICE, LIGHT-RECEIVING DEVICE, AND LIGHT-EMITTING DEVICE COMPRISING THE STIMULATED PHONON EMISSION DEVICE - A stimulated phonon emission device of an embodiment is provided with a first electroconductive type of semiconductor substrate of an indirect transition type semiconductor crystal, a second electroconductive type of well region provided in the semiconductor substrate, an element isolation region deeper than the well region, an element region surrounded by the element isolation region, and a field-effect transistor having a plurality of gate electrodes which are formed in the well region in the element region, are parallel to each other, and are arranged at a constant pitch and first electroconductive type of source region and drain region provided in the element regions on the both sides of the gate electrode. | 2014-02-27 |
20140054653 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel. | 2014-02-27 |
20140054654 | MOS TRANSISTOR AND PROCESS THEREOF - A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor. | 2014-02-27 |
20140054655 | SEMICONDUCTOR GATE STRUCTURE AND METHOD OF FABRICATING THEREOF - A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure. | 2014-02-27 |
20140054656 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure. | 2014-02-27 |
20140054657 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer. | 2014-02-27 |
20140054658 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved. | 2014-02-27 |
20140054659 | SEMICONDUCTOR DEVICES AND METHODS FABRICATING SAME - Disclosed are semiconductor devices and methods of forming the same. According to the semiconductor device, gate structures are provided to be buried in a substrate and first dopant regions and second dopant regions are provided at both ends of the gate structures. Conductive lines cross the gate structures and are connected to the first dopant regions. Contact structures are respectively provided in contact holes which are provided between the conductive lines and expose the second dopant regions. The contact structures are in contact with the second dopant regions, respectively. Each of the contact structures includes a pad pattern extending along a sidewall of the contact hole. | 2014-02-27 |
20140054660 | FILM FORMATION METHOD AND NONVOLATILE MEMORY DEVICE - According to one embodiment, a film formation method can include irradiating a layer to be processed provided on an underlayer with an ionized gas cluster containing any one of oxygen and nitrogen to modify at least part of the layer. | 2014-02-27 |
20140054661 | NANOWIRE PHOTO-DETECTOR GROWN ON A BACK-SIDE ILLUMINATED IMAGE SENSOR - An embodiment relates to a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. | 2014-02-27 |
20140054662 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE - The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate | 2014-02-27 |
20140054663 | SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM - At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise. | 2014-02-27 |
20140054664 | POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH - A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer. | 2014-02-27 |
20140054665 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a tunnel insulating layer formed on an active region defined by an isolation layer, a polysilicon pattern including a first portion formed on the tunnel insulating layer on the active region and a second portion protruding from the first portion beyond the isolation layer, wherein the second portion has a narrower width than the first portion, and a doped region formed near a surface of the polysilicon pattern and including p-type dopants. | 2014-02-27 |
20140054666 | VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY - Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed. | 2014-02-27 |
20140054667 | Split-Gate Memory Cell With Depletion-Mode Floating Gate Channel, And Method Of Making Same - A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type. | 2014-02-27 |
20140054668 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer. | 2014-02-27 |
20140054669 | Structures and Methods for Making NAND Flash Memory - A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices. | 2014-02-27 |
20140054670 | Method of Making a Three-Dimensional Memory Array with Etch Stop - A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes. | 2014-02-27 |
20140054671 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode. | 2014-02-27 |
20140054672 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode. | 2014-02-27 |
20140054673 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and metal silicide layers configured to be in contact with the pipe connection gate electrode. The electric resistance of the pipe connection gate electrode may be greatly reduced without deteriorating the characteristics of the memory layers by forming the metal silicide layers coming in contact with the pipe connection gate electrode. | 2014-02-27 |
20140054674 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height. | 2014-02-27 |
20140054675 | VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a vertical type semiconductor device includes a pillar structure on a substrate. The pillar structure includes a semiconductor pattern and a channel pattern. The semiconductor pattern includes an impurity region. A first word line structure faces the channel pattern and is horizontally extended while surrounding the pillar structure. A second word line structure has one side facing the impurity region of the semiconductor pattern and another side facing the substrate. A common source line is provided at a substrate portion adjacent to a sidewall end portion of the second word line structure. | 2014-02-27 |
20140054676 | VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS - A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps. | 2014-02-27 |
20140054677 | Arrays Comprising Vertically-Oriented Transistors, Integrated Circuitry Comprising A Conductive Line Buried In Silicon-Comprising Semiconductor Material, Methods Of Forming A Plurality Of Conductive Lines Buried In Silicon-Comprising Semiconductor Material, And Methods Of Forming An Array Comprising Vertically-Oriented Transistors - An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed. | 2014-02-27 |
20140054678 | N-type Field Effect Transistors, Arrays Comprising N-type Vertically-Oriented Transistors, Methods Of Forming An N-type Field Effect Transistor, And Methods Of Forming An Array Comprising Vertically-Oriented N-type Transistors - An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed. | 2014-02-27 |
20140054679 | DOPING A NON-PLANAR SEMICONDUCTOR DEVICE - In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle. | 2014-02-27 |
20140054680 | METHOD OF FORMING GROUP III NITRIDE SEMICONDUCTOR, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, GROUP III NITRIDE SEMICONDUCTOR DEVICE, METHOD OF PERFORMING THERMAL TREATMENT - A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively. | 2014-02-27 |
20140054681 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes. | 2014-02-27 |
20140054682 | BIDIRECTIONAL FIELD EFFECT TRANSISTOR AND METHOD - In one embodiment, a structure for a semiconductor device has trench shield electrodes formed above and below a gate electrode. The structure can be configured to function as a bidirectional power field effect transistor. | 2014-02-27 |
20140054683 | TRENCH DEVICES HAVING IMPROVED BREAKDOWN VOLTAGES AND METHOD FOR MANUFACTURING SAME - In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field, region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to dispose an electric field. | 2014-02-27 |
20140054684 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 2014-02-27 |
20140054685 | SEMICONDUCTOR DEVICE WITH IMPROVED LINEAR AND SWITCHING OPERATING MODES - A semiconductor device that includes a semiconductor body, having a front side and a back side opposite to one another in a first direction of extension; a drift region, which extends in the semiconductor body, faces the front side, and has a first type of conductivity and a first value of doping; a body region, which has a second type of conductivity opposite to the first type of conductivity, extends in the drift region, and faces the front side of the semiconductor body; a first control terminal, which extends on the front side of the semiconductor body, at least partially overlapping, in the first direction of extension, the body region; and a second control terminal, which extends to a first depth in the semiconductor body, inside the body region, and is staggered with respect to the first control terminal. | 2014-02-27 |
20140054686 | DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE - N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate). | 2014-02-27 |
20140054687 | MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact trench wall; and an epitaxial enhancement portion disposed below the contact trench and in contact with the implant. | 2014-02-27 |
20140054688 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: | 2014-02-27 |
20140054689 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate with a cell region, a second pad region, and a first pad region between the second pad region and the cell region, a first buried gate buried in a trench of the semiconductor substrate, and extended from the cell region to the second pad region, and a second buried gate buried in the trench of the semiconductor substrate, disposed over and spaced apart from an upper part of the first buried gate, and extended from the cell region to the first pad region. | 2014-02-27 |
20140054690 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a fabricating method thereof are provided, in which the semiconductor device includes a semiconductor substrate with a trench formed therein, a bottom electrode placed at a lower inner portion of the trench, the bottom electrode having an uneven upper surface, an insulating layer formed on an upper portion of the bottom electrode and on a sidewall of the trench, and a top electrode placed at an upper portion of the bottom electrode inside the trench, the top electrode having a top electrode which is uneven, in which the top electrode is so configured that the top electrode is inclined toward a center portion. | 2014-02-27 |
20140054691 | FIELD EFFECT TRANSISTOR WITH GATED AND NON-GATED TRENCHES - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 2014-02-27 |
20140054692 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them. | 2014-02-27 |
20140054693 | SEMICONDUCTOR DEVICE - According to one embodiment, a first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between an edge of the second insulating film on an inner peripheral side of the second semiconductor layer and an edge of the third semiconductor layer on an outer peripheral side of the second semiconductor layer. The second distance in the first region is shorter than the second distance in the second region. | 2014-02-27 |
20140054694 | Semiconductor Device with HCI Protection Region - A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate. | 2014-02-27 |
20140054695 | High Side Gate Driver Device - The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region. | 2014-02-27 |
20140054696 | NOVEL LATCH-UP IMMUNITY NLDMOS - An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region. | 2014-02-27 |
20140054697 | SEMICONDUCTOR DEVICE WITH FIELD ELECTRODE AND METHOD - A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction. | 2014-02-27 |
20140054698 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 2014-02-27 |
20140054699 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM OXIDE LINER AND UPPER NITRIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 2014-02-27 |
20140054700 | Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer - Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers. | 2014-02-27 |
20140054701 | METHOD OF MANUFACTURING TRANSISTOR, TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE - Embodiments of the present invention provide a method for manufacturing a transistor, a transistor, an array substrate and a display device. The method comprises: forming a first source/drain metal layer on a substrate; forming an insulating layer above the first source/drain metal layer; forming a gate metal layer on the insulating layer; forming a gate insulating layer on the gate metal layer; forming a semiconductor layer above the gate insulating layer; forming an etching blocking layer on the semiconductor layer; forming a second source/drain metal layer above the etching blocking layer; forming an insulating layer above the second source/drain metal layer. | 2014-02-27 |
20140054702 | TFT, MASK FOR MANUFACTURING THE TFT, ARRAY SUBSTRATE AND DISPLAY DEVICE - Embodiments of the invention relate to a TFT, a mask for manufacturing the TFT, an array substrate and a display device. A channel of the TFT is formed by using a single slit mask. The channel of the TFT has a bent portion and extension portions provided on both sides of the bent portion, and a channel width of the bent portion is larger than a channel width of the extension portion. | 2014-02-27 |
20140054703 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - Embodiments of the invention provide an array substrate comprising a plurality of pixel units, each of the pixel units including a first display electrode, a second display electrode and an insulating portion, wherein, the insulating portion comprises a plurality of first via holes; the first display electrode is disposed at a surface of the insulating portion, and the second display electrode is disposed at bottom surfaces of the first via holes. Embodiments of the invention further provide a method for manufacturing the array substrate. | 2014-02-27 |
20140054704 | SEMICONDUCTOR DEVICE INCLUDING AN ACTIVE REGION AND TWO LAYERS HAVING DIFFERENT STRESS CHARACTERISTICS - An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type. | 2014-02-27 |
20140054705 | SILICON GERMANIUM CHANNEL WITH SILICON BUFFER REGIONS FOR FIN FIELD EFFECT TRANSISTOR DEVICE - A fin field effect transistor (finFET) device includes a substrate; first and second source/drain regions located on the substrate; and a fin located on the substrate between the first and second source/drain regions. The fin includes a silicon germanium channel region and first and second silicon buffer regions located in the fin adjacent to and on either side of the silicon germanium channel region. The first silicon buffer region is located between the first source/drain region and the silicon germanium channel region and the second silicon buffer region is located between the second source/drain region and the silicon germanium channel region. | 2014-02-27 |
20140054706 | MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS - A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof. | 2014-02-27 |
20140054707 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one. | 2014-02-27 |
20140054708 | Stacked and Tunable Power Fuse - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 2014-02-27 |