07th week of 2016 patent applcation highlights part 44 |
Patent application number | Title | Published |
20160049165 | Integrated Head for Heat Assisted Magnetic Recording - A magnetic recording apparatus includes a write element and an optical device for heating a portion of a magnetic medium. The optical device and the write element are arranged to generally prevent the write element from affecting the optical fields generated by the optical device. | 2016-02-18 |
20160049166 | MINISKIRT TAPE HEAD HAVING QUASI-STATICALLY TILTED TRANSDUCER ARRAYS - In one general embodiment, an apparatus includes a magnetic head. The magnetic head has a first portion and a second portion, the first portion and the second portion together providing a tape bearing surface. The first portion has an opening at least partially encircling the second portion. The second portion has two modules, each module having at least one array of transducers. Each module has a first outermost edge oriented orthogonally to an intended direction of tape travel thereacross, and a second outermost edge opposite the first edge, the second edge being oriented at an angle between 0.2° and about 10° relative to a line oriented orthogonally to the intended direction of tape travel thereacross. | 2016-02-18 |
20160049167 | MAGNETIC HEAD AND SYSTEM HAVING OFFSET ARRAYS - In one embodiment, an apparatus includes at least first and second modules, a mechanism for orienting the modules to control a transducer pitch presented to a tape, and a controller physically configured to determine a state of expansion of the tape based on a readback signal from the tape. Each of the modules have an array of transducers. The first and second modules are fixed relative to each other. The transducers of the first module are about aligned with the transducers of the second module in an intended direction of tape travel thereacross when longitudinal axes of the arrays are oriented at an angle greater than 0.2° relative to a line oriented perpendicular to the intended direction of tape travel. The controller is physically configured to control the mechanism for altering the angle of the modules away from the nominal angle based on the state of expansion of the tape. | 2016-02-18 |
20160049168 | Methods and Apparatus for Improved Pattern Detection - Improved pattern detection is provided for a predefined pattern in data. A detection threshold employed by a Euclidean detector to detect a pattern (such as a Servo Address Mark) may be adjusted based upon data gathered that corresponds to an indication of a detected pattern by one of a plurality of pattern detectors. | 2016-02-18 |
20160049169 | SERVO PARAMETERIZATION FOR MULTI-SENSOR READER - A storage media includes a plurality of servo sectors with embedded servo patterns characterized by one or more servo pattern parameters. Each of the servo sectors has a servo pattern parameter based on a separation between read sensors of a transducer head reading the servo sector. | 2016-02-18 |
20160049170 | OPTICAL INFORMATION RECORDING AND RECONSTRUCTING DEVICE - During reconstruction, the hologram cannot be reconstructed at high speed. In the present invention, the distance between the optical system base point, which is associated with a recording medium address during recording, and the recording medium is measured, and said distance is recorded in a memory. During reconstruction, distance information, which is the distance of the recording medium from the memory that is associated with a recording medium reconstruction address, is read, and the position of an aperture filter is adjusted at high speed in the optical axis direction on the basis of the read distance information and a distance measurement result for the optical system base point during reconstruction and the recording medium. Thus, the relative positions of the hologram within the recorded medium associated with the optical system during reconstruction and during recording can be matched. | 2016-02-18 |
20160049171 | LOAD BALANCING AND SPACE EFFICIENT BIG DATA TAPE MANAGEMENT - A tool for space efficient tape management. The tool retrieves one or more tapes from one or more tape library frames in a first tape library. The tool inserts the one or more tapes into the one or more tape library frames in the first tape library. The tool transfers the one or more tapes from the one or more tape library frames in the first tape library to one or more tape library frames in a second tape library. | 2016-02-18 |
20160049172 | ENERGY TRANSFER BETWEEN DATA STORAGE DEVICES WITH MOVING PARTS - A system that includes a first data storage element actuated by a first electric motor. The system also includes a second data storage element actuated by a second electric motor. An electrical connector assembly transfers electrical energy from a back electromotive force generated in the first electric motor, by movement of the first data storage element, to the second electric motor to thereby energize the second electric motor. | 2016-02-18 |
20160049173 | TECHNIQUES AND APPARATUS FOR EDITING VIDEO - An apparatus may include a memory to store a recorded video. The apparatus may further include an interface to receive at least one set of sensor information based on sensor data that is recorded concurrently with the recorded video and a video clip creation module to identify a sensor event from the at least one set of sensor information and to generate a video clip based upon the sensor event, the video clip comprising video content from the recorded video that is synchronized to the sensor event. | 2016-02-18 |
20160049174 | DISTRIBUTED LOGICAL TRACK LAYOUT IN OPTICAL STORAGE TAPE - An optical data storage tape includes more than one segment, with each segment divided into multiple zones, which include multiple data tracks. The layout of the logical zones in one segment is in a different order than those of another segment. In an example, the tape includes at least N physical segments, at least M physical zones in each segment, at least M logical zones assigned to the M physical zones, and wherein logical zones of adjacent physical segments are in a different order than an adjacent physical segment. | 2016-02-18 |
20160049175 | SYSTEMS AND METHODS FOR CATALOGUING AUDIO-VISUAL DATA - A method for cataloguing audio-visual data including indexing a plurality of audio-visual segments by specifying a storage location and recording time of each segment. A segment hierarchy is created based on the locations and times of each recording. The plurality of audio-visual segments can be recorded with a mobile digital video recorder onto a removable medium located within a vehicle such that the mobile digital video recorder can identify the vehicle in which the removable medium is located in while recording each segment. | 2016-02-18 |
20160049176 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed. | 2016-02-18 |
20160049177 | MEMORY SYSTEM, STORAGE SYSTEM - According to one embodiment, a memory system includes a power supply circuit. The power supply circuit includes a first capacitor circuit which applies a voltage to a nonvolatile memory and a memory controller, and a second capacitor circuit which adds a further voltage to the voltage applied by the first capacitor circuit, when the voltage applied by the first capacitor circuit is less than a set value. | 2016-02-18 |
20160049178 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 2016-02-18 |
20160049179 | LOW-POWER SENSE AMPLIFIER - A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state. | 2016-02-18 |
20160049180 | SEMICONDUCTOR DEVICE INCLUDING INPUT/OUTPUT CIRCUIT - Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers. | 2016-02-18 |
20160049181 | VIRTUAL MEMORY MAPPING FOR IMPROVED DRAM PAGE LOCALITY - Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages. | 2016-02-18 |
20160049182 | MEMORY ARCHITECTURE - A memory macro includes a plurality of columns and a plurality of switching circuits. A column of the plurality of columns has a plurality of voltage supply nodes corresponding to a plurality of memory cells in the column. A switching circuit of the plurality of switching circuits corresponds to a column of the plurality of columns and is configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes. The first voltage value and the second voltage value differ by a predetermined voltage value. | 2016-02-18 |
20160049183 | STROBE GATING ADAPTION AND TRAINING IN A MEMORY CONTROLLER - A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal. | 2016-02-18 |
20160049184 | HIGH CAPACIY LOW COST MULTI-STATE MAGNETIC MEMORY - One embodiment of the present invention includes a multi-state current-switching magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states. | 2016-02-18 |
20160049185 | DIFFERENTIAL MAGNETIC TUNNEL JUNCTION PAIR INCLUDING A SENSE LAYER WITH A HIGH COERCIVITY PORTION - An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion. | 2016-02-18 |
20160049186 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, nonvolatile semiconductor memory device comprises: a memory mat including a memory cell having a variable resistance element; a write driver which applies a write current to the memory cell in one of a first direction and a second direction opposite to the first direction in write; and a read driver which applies a verify read current to the memory cell in one of the first direction and the second direction in verify read after write. | 2016-02-18 |
20160049187 | SEMICONDUCTOR DEVICE - In one embodiment, gate conductors include a pair of first portions and a pair of second portions. First and second load transistors each includes source and drain regions having different conductivity types and sandwiching one or the other of the first portions, a diffusion region of a first conductivity type corresponding to the drain region being between the first portions. First and second driver transistors each includes source and drain regions having different conductivity types and sandwiching the one or the other of the first portions, a diffusion region of the first conductivity type corresponding to the source region being between the first portions. First and second transfer transistors each includes source and drain regions having different conductivity types and sandwiching one or the other of the second portions, a diffusion region of the first conductivity type corresponding to the source region being between the second portions. | 2016-02-18 |
20160049188 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW | 2016-02-18 |
20160049189 | METHOD OF MINIMIZING THE OPERATING VOLTAGE OF AN SRAM CELL - An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively. | 2016-02-18 |
20160049190 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. | 2016-02-18 |
20160049191 | Integrated Circuit for Storing Data - An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC | 2016-02-18 |
20160049192 | VSL-BASED VT-COMPENSATION AND ANALOG PROGRAM SCHEME FOR NAND ARRAY WITHOUT CSL - A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual V | 2016-02-18 |
20160049193 | METHOD FOR DYNAMICALLY ACCESSING AND PROGRAMMING RESISTIVE CHANGE ELEMENT ARRAYS - Methods for dynamically programming and dynamically reading one or more resistive change elements within a resistive change element array are disclosed. These methods include first pre-charging all of the array lines within a resistive change element array simultaneously and then grounding certain array lines while allowing other array lines to float in order to direct discharge currents through only selected cells. In this way, resistive change elements within resistive change element arrays made up of 1-R cells—that is, cells without in situ selection circuitry—can be reliably and rapidly accessed and programmed. | 2016-02-18 |
20160049194 | APPARTUSES AND METHODS FOR SENSING USING AN INTEGRATION COMPONENT - The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided. | 2016-02-18 |
20160049195 | RESISTIVE CROSS-POINT ARCHITECTURE FOR ROBUST DATA REPRESENTATION WITH ARBITRARY PRECISION - This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network. | 2016-02-18 |
20160049196 | Memory with specific driving mechanism applied on source line - An embodiment of the invention provides a memory. The memory includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a memory cell array. The memory cell array has a plurality of memory cells disposed at the intersections of the word and bit lines to form a matrix of rows and columns, wherein each memory cell comprises a resistive memory device and a transistor. The source lines are each disposed between two word lines, wherein each source line is coupled to source terminals of the transistors. When a RESET operation is applied to a selected memory cell, the voltage level of the source line is pulled up to a first voltage level, and when another operation is applied to the selected memory cell, the source line is grounded. | 2016-02-18 |
20160049197 | Memory Devices Including a Plurality of Layers and Related Systems - A memory device is provided including a cell region including at least one cell layer, each cell layer including multiple first lines and multiple second lines; and a control region including at least one control layer. The at least one control layer includes multiple circuit regions for performing a memory operation on the cell region. The multiple first lines include at least one first signal line through which a first signal from a first circuit region of the control layer is transmitted to a second circuit region of the control layer. | 2016-02-18 |
20160049198 | CONTENT ADDRESSABLE MEMORY CELL AND ARRAY - A content addressable memory (CAM) cell system is provided. The CAM cell system includes a first memory cell, a first logic circuitry and a first compare circuitry. The first logic circuit includes a first n-FET, a first p-FET, and a first input terminal. A gate of the first n-FET and a gate of the first p-FET are galvanically coupled to the first input terminal. The first compare circuitry is communicatively coupled to the first memory cell via a first coupling, and to the first input terminal via a second coupling. The first compare circuitry is configured to receive first data stored in the first memory cell via the first coupling, receive first match data, transmit a first binary logical value to the first input terminal via the second coupling in response to the first data not matching the first match data, and transmit a second binary logical value to the first input terminal via the second coupling in response to the first data matching the first match data. | 2016-02-18 |
20160049199 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string. | 2016-02-18 |
20160049200 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively. | 2016-02-18 |
20160049201 | SUB-BLOCK ERASE - A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines. | 2016-02-18 |
20160049202 | VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION - A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array. | 2016-02-18 |
20160049203 | SYSTEM AND METHOD OF USING MULTIPLE READ OPERATIONS - Systems and methods are described for reading a storage element of a memory. In a particular embodiment, a method, in a data storage device including a controller and a non-volatile memory, where the non-volatile memory includes a plurality of storage elements, includes performing multiple read operations at a storage element of the non-volatile memory. Each read operation of the multiple read operations is performed using the same reading voltage. The method further includes determining a read value of the storage element based on the multiple read operations. | 2016-02-18 |
20160049204 | MEMORY SYSTEM AND METHOD OF CONTROLLING NON-VOLATILE MEMORY - According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading. | 2016-02-18 |
20160049205 | RANK DETERMINATION - Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information. | 2016-02-18 |
20160049206 | High Voltage Step Down Regulator with Breakdown Protection - A high voltage step regulator, such as would be used to provide a regulated low voltage (on the order of a few volts) from a high voltage external supply (e.g. 12V), is presented. To protect the output transistor, through which the output is provided from the input, from breakdown, a depletion type device is connected between the supply and the output transistor. The control gate of the depletion device is then connected to the output level of the regulator. This reduces the voltage drop across the output transistor, helping to avoid violating design rules (EDR) on how great a voltage differential can be placed across the output transistor. Examples of applications for such a circuit are for various operating voltages on a non-volatile memory chip operating with a high voltage power supply. | 2016-02-18 |
20160049207 | CONFIGURATION FUSE DATA MANAGEMENT IN A PARTIAL POWER-ON STATE - In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode. | 2016-02-18 |
20160049208 | GATE DRIVING CIRCUIT AND DISPLAY APPARATUS - The present disclosure provides a gate driving circuit and a display apparatus, wherein the gate driving circuit comprises a shift register ( | 2016-02-18 |
20160049209 | THRESHOLD VOLTAGE EXPANSION - Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed. | 2016-02-18 |
20160049210 | MODULAR TRANSPORTABLE NUCLEAR GENERATOR - The present invention relates generally to electric power and process heat generation using a modular, compact, transportable, hardened nuclear generator rapidly deployable and retrievable, comprising power conversion and electric generation equipment fully integrated within a single pressure vessel housing a nuclear core. The resulting transportable nuclear generator does not require costly site-preparation, and can be transported fully operational. The transportable nuclear generator requires an emergency evacuation area substantially reduced with respect to other nuclear generators as it may be configured for operation with a melt-proof conductive ceramic core which allows decay heat removal even under total loss of coolant scenarios. | 2016-02-18 |
20160049211 | SILICON CARBIDE MULTILAYERED CLADDING AND NUCLEAR REACTOR FUEL ELEMENT FOR USE IN WATER-COOLED NUCLEAR POWER REACTORS - A nuclear fuel element for use in water-cooled nuclear power reactors and an improved multilayered silicon carbide tube for use in water-cooled nuclear power reactors and other high temperature, high strength thermal tubing applications including solar energy collectors. The fuel element includes a multilayered silicon carbide cladding tube. The multilayered silicon carbide cladding tube includes (i) an inner layer; (ii) a central layer; and (iii) a crack propagation prevention layer between the inner layer and the central layer. A stack of individual fissionable fuel pellets may be located within the cladding tube. In addition, a thermally conductive layer may be deposited within the cladding tube between the inner layer of the cladding tube and the stack of fuel pellets. The multilayered silicon carbide cladding tube may also be adapted for other high temperature, high strength thermal tubing applications including solar energy collectors. | 2016-02-18 |
20160049212 | Method for In-Core Instrumentation Withdrawal From the Core of a Pressurized Water Reactor - A method of removing the upper internals assembly from a nuclear reactor pressure vessel for refueling that simultaneously disconnects two or more of the in-core instrument thimble assemblies from the reactor vessel penetrations through which their signal cables extend. The signal cables are connected to the penetrations with an electrical connector that supports the two or more in-core instrumentation thimble assembly signal leads. Before the electrical connector is disconnected, water in the vessel is lowered below the connection so that the process is performed in a dry environment. | 2016-02-18 |
20160049213 | Neutron Absorber Members, Insertion Apparatus, And Neutron Absorber Member Retainers - Neutron absorber members for a control rod guide tube of a spent fuel assembly are provided as a tube split throughout a length thereof. In further examples, an insertion apparatus for inserting a neutron absorber member into a control rod guide tube of a spent fuel assembly includes an insertion tool base and an insertion tool rod. The insertion tool rod is removably secured within and extending from the insertion tool base according to a position of the control rod guide tube into which the neutron absorber is to be inserted. In further examples, a neutron absorber member retainer for a top nozzle of a spent fuel assembly is provided. The retainer includes a plate configured to inhibit a neutron absorber member inserted in a control rod guide tube from removal. | 2016-02-18 |
20160049214 | COUPLING BETWEEN NANOSTRUCTURES AND OPTICAL FIBERS - Technologies are generally provided for enhancing optical coupling between nanostructures, such as a nanowire, and an optical element, such as an optical fiber, for example in order to enable effective optical communication. A nanostructure may be automatically aligned with an optical fiber by suspending the nanowire within a fluid and causing the nanowire to align itself with a tip of the optical fiber also suspended within the fluid. Light may be directed through the optical fiber to induce an optical gradient in the fluid near the optical fiber tip. The optical gradient may attract the nanowire to the tip of the optical fiber, and may cause to align with the optical fiber. Post-alignment, the nanowire may be permanently coupled with the optical fiber to form a nanowire-optical fiber assembly to couple light between the optical fiber and a nanophotonic circuit integrated with the nanowire. | 2016-02-18 |
20160049215 | METHOD AND STRUCTURE FOR PLASMONIC OPTICAL TRAPPING OF NANO-SCALE PARTICLES - Methods and article for optically trapping nano-sized objects by illuminating a coaxial plasmonic aperture are disclosed. | 2016-02-18 |
20160049216 | Method and Apparatus for Ion Beam Bragg Peak Measurement - A system and method for recording in real-time the duration, position, and energy of ion beams as delivered by a proton or heavy ion cancer treatment system for the purpose of calibrating the radiological system and verifying the treatment plans for various lesions. The energy of the ion beam is calculated from the beam ion depth penetration through a phantom as recorded on a two-dimensional scintillator surface which is viewed by a sensitive visible-light camera mounted in a darkened enclosure. The energy of the beam is degraded by a novel multi-step dual-slope chevron wedge phantom which creates, at a minimum, two bright spots in the camera's field of view. The distance between the centers of these two spots along with the dimensions and density of the multi-step dual-slope chevron wedge are used to calculate the Bragg Peak penetration depth of the ion beam. A computer connected to the camera measures the location and intensity of these spots during treatment delivery and archives the original beam image, spot parameters, timing, and computed beam energies to memory. Software algorithms reconstruct a mathematical description of each treatment beam. The operator can then determine discrepancies between the measured dosimetric pattern and the intended treatment or calibration pattern. | 2016-02-18 |
20160049217 | SEAL-HEALING COMPOSITES AND APPLICATIONS THEREOF - A battery electrode includes an electrochemically active material and a binder covering the electrochemically active material. The binder includes a self-healing polymer and conductive additives dispersed in the self-healing polymer to provide an electrical pathway across at least a portion of the binder. | 2016-02-18 |
20160049218 | MIXED SOLID INSULATION MATERIAL FOR A TRANSMISSION SYSTEM - A transmission system includes an electrical conductor and an insulation layer circumferentially covering the conductor. The layer includes at least two layer sections including a plurality of sublayers concentrically orientated, whereby each sublayer comprises one or more strips arranged beside each other in a circumferential direction. Gaps are formed between adjacent edges of strips and each gap is covered by a strip of an adjacent sublayer. Each of the strips includes one or more sheets arranged beside each other in a radial direction. Each sheet includes an insulation material including cellulose paper and polymer. At least one sublayer includes at least one sheet of said cellulose paper, and at least one sublayer including at least one sheet of said polymer, and whereby the insulation layer is impregnated. | 2016-02-18 |
20160049219 | DIELECTRIC HEAT-TRANSFER FLUID - Provided is a use of a vegetable oil high in monounsaturates as dielectric and heat-transfer fluid in a device for the generation, storage, conversion and/or distribution of electrical energy. | 2016-02-18 |
20160049220 | SHIELDED ELECTRICAL CABLE - A shielded electrical cable includes conductor sets extending along a length of the cable and spaced apart from each other along a width of the cable. First and second shielding films are disposed on opposite sides of the cable and include cover portions and pinched portions arranged such that, in transverse cross section, the cover portions of the films in combination substantially surround each conductor set. An adhesive layer bonds the shielding films together in the pinched portions of the cable. A transverse bending of the cable at a cable location of no more than 180 degrees over an inner radius of at most 2 mm causes a cable impedance of the selected insulated conductor proximate the cable location to vary by no more than 2 percent from an initial cable impedance measured at the cable location in an unbent configuration. | 2016-02-18 |
20160049221 | RADIATION AND HEAT RESISTANT CABLES - A cable intended for use in a nuclear environment includes one or more conductors, a longitudinally applied corrugated shield surrounding the one or more conductors, and a cross-linked polyolefin jacket layer surrounding the longitudinally applied corrugated shield. The cable conducts about 5,000 volts to about 68,000 volts in use and is radiation resistant and heat resistant. The cable comprises a life span of about 40 years or more when measured in accordance with IEEE 323. Methods for making a cable and a nuclear reactor utilizing such a cable are also provided. | 2016-02-18 |
20160049222 | Flexible Transmission Line Assembly - A flexible transmission line assembly, which is connected between two relatively moving means that are movable relative to each other, comprises an abrasion-resistant flexible film and a plurality of transmission lines. The abrasion-resistant flexible film inner surface is surrounded to form a receiving space and is provided with an adhesive. The plurality of transmission lines is provided within the receiving space in a way each transmission line is adjacent to one another in a single row in width directions of the transmission lines, and the adjacent transmission lines being closely contacted with each other. The plurality of transmission lines is adhered with the inner surface of the abrasion-resistant flexible film by means of the adhesive, and the plurality of transmission lines at both ends in a longitudinal direction thereof is formed with a connecting element. | 2016-02-18 |
20160049223 | READILY STRIPPABLE CABLE - A readily-strippable cable is herein described having at least two wires encapsulated by a continuous electrically insulating layer wherein each encapsulated wire is connected to an adjacent wire by a relatively thinner portion of the insulating layer, the insulating layer having at least one relatively weak portion per encapsulated wire that extends along the length of the cable and is substantially uniform in position and strength along the length of the cable; and wherein the weak portion is configured to allow the insulating layer to split along the relatively weak portion and down the length of the cable upon separation of the encapsulated wires by application of force against the relatively thinner portion of insulating layer in a direction substantially perpendicular to the length of the cable, thereby exposing the wire without the use of a secondary operation. | 2016-02-18 |
20160049224 | TELECOMMUNICATIONS WIRE HAVING A CHANNELED DIELECTRIC INSULATOR AND METHODS FOR MANUFACTURING THE SAME - The present disclosure relates generally to a telecommunications wire including an electrical conductor and a dielectric insulator surrounding the electrical conductor. The dielectric insulator defines a plurality of channels defining void space containing a material having a low dielectric constant such as air. The channels each run along a length of the electrical conductor. The channels are configured to lower an overall dielectric constant of the dielectric insulator while maintaining desirable mechanical properties such as crush resistance. | 2016-02-18 |
20160049225 | QUENCH PROTECTED STRUCTURED SUPERCONDUCTING CABLE - Quench protected structured (QPS) superconducting cables, methods of fabricating the same, and methods of bending the same are disclosed. The methods of bending the QPS superconducting cables can be employed to produce windings. The QPS superconducting cables can rapidly drive a distributed quench to a normal conducting state in a superconducting cable if a region of the cable spontaneously quenches during high current operation. | 2016-02-18 |
20160049226 | CONJUGATED POLYMER COATINGS AND METHODS FOR ATMOSPHERIC PLASMA DEPOSITION THEREOF - A method providing conductive coatings is provided. A dopant layer with a plasma deposited conjugated polymer is provided. Conductive, conjugated polymer coatings are also provided. | 2016-02-18 |
20160049227 | METHOD OF PRODUCING CONDUCTIVE PATTERNS OF NANOPARTICLES AND DEVICES MADE THEREOF - A method of processing a liquid material. The method includes mixing a liquid material with a solvent, wherein the solvent has a constituent capable of coating the particles of the material. The liquid material mixed with the solvent is then particlized, deposited on a substrate and activated to form a pre-defined electrically conductive pattern. Particlization methods include sonication and the deposition methods include ink-jet printing. Activation methods include applying mechanical pressure. The method can be used to produce electronic devices. The electronic devices made by the method include strain gauges. The substrates utilized for making the electronic devices utilizing the method can be wearable or stretchable or both. | 2016-02-18 |
20160049228 | Method for energizing a superconducting magnet arrangement - A method for charging a magnet arrangement having a superconducting tape conductor with a first transition temperature in a cryostat device. The magnet arrangement is temperature-controlled to a first pre-operating temperature between the first transition temperature and the operating temperature, a first pre-operating current is excited, the magnet arrangement is cooled to operating temperature and a first operating current is excited. The magnet arrangement has a second magnet winding composed of a second superconductor material with a second transition temperature above the operating temperature and at least 15 K below the first transition temperature, wherein a second operating current in the second magnet winding is excited at the latest after cooling of the magnet arrangement to the operating temperature, and with the second operating current the second magnet winding generates a second operating magnetic field in the volume of the first magnet winding. | 2016-02-18 |
20160049229 | Light-Weight, Efficient Superconducting Magnetic Energy Storage - Novel configurations to improve the performance of superconducting magnetic energy storage system are described. The use of poloidal grading of the conductor, enabled by the use of 2 | 2016-02-18 |
20160049230 | MAGNETIC ARMATURE - A magnetic armature for a torque motor is provided, comprising a pivot portion and at least one arm portion extending from said pivot portion, wherein the smallest cross-sectional area of said armature at said pivot portion is at least 60% of the smallest cross-sectional area of said armature at said at least one arm portion. | 2016-02-18 |
20160049231 | SPRINGLESS ELECTROMAGNET ACTUATOR HAVING A MODE SELECTABLE MAGNETIC ARMATURE - A standard solenoid body and coils are combined with a non-magnetic armature tube containing a permanent magnet, preferably neodymium. The magnet is located in one of three positions within the armature. When biased toward the stop end of the solenoid, it may be configured to act as a push solenoid. When biased toward the collar end of the solenoid, it may be configured to act as a pull solenoid. In either case, no spring is required to return the armature to its de-energized position. Positioning the magnet in the middle of the armature defines a dual-latching solenoid requiring no power to hold it in a given state. A positive coil pulse moves the armature toward the stop end, whereas a negative coil pulse moves the armature toward the collar end. The armature will remain at the end to which it was directed until another pulse of opposite polarity comes along. | 2016-02-18 |
20160049232 | ELECTROMAGNETIC FIELD CONFINEMENT - The present application invention relates to the control of electromagnetic fields. It has particular relevance to magnetic flux coupling apparatus such as inductive power transfer pads for wireless power transfer systems. There is provided a magnetic flux coupling apparatus comprising a coil for generating or receiving magnetic coupling flux and a leakage flux element comprising material of a relatively high magnetic permeability. The leakage flux element is separated from the coil by a region of relatively low magnetic permeability and positioned to provide a controlled path for leakage flux independent of coupling flux. There is provided an electromagnetic wave absorber comprising a high permeability magnetic material arranged in a first layer; and a conductive or low permeability material arranged in a second layer. | 2016-02-18 |
20160049233 | DOOR CHIME ASSEMBLY - A door chime assembly with a transformer assembly mounted within an electrical box and proximately to a chime. The transformer assembly including a transformer operably coupled to a bracket. The transformer being insertable into the electrical box such that the bracket and electrical box cooperate to electrically isolate the transformer from the chime. The electrical box having mounting features for securing the door chime assembly in existing and/or new construction. | 2016-02-18 |
20160049234 | COMMON MODE NOISE FILTER AND MANUFACTURING METHOD THEREOF - A common mode noise filter includes: a laminated body; and a first and second coil conductors that are formed inside the laminated body and face each other in a first direction, wherein the first coil conductor has a first surface facing the second coil conductor; the second coil conductor has a second surface facing the first surface; a distance between ends of the first and second surfaces in the first direction is longer than a distance between centers of the first and second surfaces in the first direction; the first and second surfaces have corners each formed into an arcuate shape in a cross section; and a relationship between a height h in the first direction and a width w in a second direction perpendicular to the first direction is h≧w in a cross section of each of the first and second coil conductors. | 2016-02-18 |
20160049235 | EMBEDDED MAGNETIC COMPONENT DEVICE - An embedded magnetic component device includes a magnetic core located in a cavity extending into an insulating substrate. The cavity and magnetic core are coved with a cover layer. Through holes extend through the cover layer and the insulating substrate, and are plated to define conductive vias. Metallic traces are provided at exterior surfaces of the cover layer and the insulating substrate to define upper and lower winding layers. The metallic traces and conductive vias define the respective primary and secondary side windings for an embedded transformer. At least a first isolation barrier is provided on the cover layer, and at least a third insulating layer is provided on the substrate. The second and third insulating layers provide additional insulation for the device, and define and function as a circuit board for surface mounted power electronics. | 2016-02-18 |
20160049236 | EMBEDDED MAGNETIC COMPONENT DEVICE - An embedded magnetic component device includes a magnetic core located in a cavity in an insulating substrate. An electrical winding includes inner and outer conductive connectors. An inner solid bonded joint boundary is located between first and second portions of the insulating substrate and extends between the cavity and the inner conductive connectors. An outer solid bonded joint boundary is located between the first and the second portions of the insulating substrate extends between the cavity and the outer conductive connectors. The minimum distance of the inner solid bonded joint boundary between any of the inner conductive connectors and the inner interior wall of the cavity is defined as D1, and the minimum distance of the outer solid bonded joint boundary between any of the outer conductive connectors and the outer interior wall of the cavity is defined as D2. D1 and D2 are about 0.4 mm or more. | 2016-02-18 |
20160049237 | ELECTRONIC COMPONENT - An electronic component includes a multilayer body including insulating layers stacked in a stacking direction, first and second linear conductors having different line widths and provided on a respective one of the insulating layers, and third and fourth linear conductors having different line widths and provided on a respective one of the insulating layers. The insulating layer(s) supporting the third and fourth linear conductors is/are at one side in the stacking direction of the insulating layer(s) supporting the first and the second linear conductors. In a planar view from the stacking direction, the first and the fourth linear conductors overlap each other, and the second and the third linear conductors overlap each other. The first, the second, the third and the fourth linear conductors are electrically connected to define a coil. | 2016-02-18 |
20160049238 | MAGNETIC COMPONENT FOR A SWITCHING POWER SUPPLY AND A METHOD OF MANUFACTURING A MAGNETIC COMPONENT - The present application relates to magnetic components employed in switching power supplies. The application provides a gapped magnetic core ( | 2016-02-18 |
20160049239 | COIL MANUFACTURING APPARATUS - A coil manufacturing apparatus 10 includes: a nozzle configured to feed a wire; a take-up jig configured to take up, through rotation, the wire fed from the nozzle; a cylindrical inner cutter tube that is provided coaxially with the take-up jig and is configured to rotate together with the take-up jig, the cylindrical inner cutter tube comprising a first slit that is formed so as to extend in an axial direction, the first slit being configured that the wire is inserted through; and an immovable outer cutter tube that is provided so as to be superimposed on an outside of the cylindrical inner cutter tube, the immovable outer cutter tube comprising a second slit that is formed so as to extend in the axial direction, the second slit being configured that the wire is inserted through. | 2016-02-18 |
20160049240 | FLEXIBLE CABLE AND ELECTRONIC DEVICE - A flexible cable includes an elongated flexible substrate including first and second surfaces on opposite sides thereof, a first capacitor electrode provided on the first surface side of the flexible substrate, the first capacitor electrode extending from a first end of the flexible substrate toward a second end of the flexible substrate, a second capacitor electrode provided on the second surface side of the flexible substrate, the second capacitor electrode extending from the second end of the flexible substrate toward the first end of the flexible substrate, a first connection portion provided at an end of the first capacitor electrode located at the first end of the flexible substrate, and a second connection portion provided at an end of the second capacitor electrode located at the second end of the flexible substrate. | 2016-02-18 |
20160049241 | MULTILAYER CERAMIC ELECTRONIC COMPONENT INCLUDING A PAIR OF SIDE OUTER ELECTRODES AND A CENTER ELECTRODE - A multilayer ceramic electronic component includes a multilayer ceramic element, a center outer electrode at a center portion of a surface of the multilayer ceramic element, side outer electrodes interposing the center outer electrode therebetween, first inner electrodes inside the multilayer ceramic element and electrically connected to the outer electrode via center extending portions, and second inner electrodes electrically connected to the side outer electrodes via first and second-side extending portions. Exposed ends of the first-side extending portions of the second inner electrodes near a center layer of the multilayer ceramic element are spaced from an end surface of the multilayer ceramic element by a distance C. Exposed ends of the first-side extending portions of the second inner electrodes disposed near an outermost layer of the multilayer portion are spaced from the end surface of the multilayer ceramic element by a distance D greater than the distance C. | 2016-02-18 |
20160049242 | MULTILAYER CERAMIC ELECTRONIC COMPONENT INCLUDING A PAIR OF SIDE OUTER ELECTRODES AND A CENTER ELECTRODE - A multilayer ceramic electronic component includes a multilayer ceramic element with first through sixth surfaces, a center outer electrode located between a first-side outer electrode and a second-side outer electrode on the multilayer ceramic element. A first plated film is provided on the center outer electrode, second plated films are provided on the first-side outer electrode and the second-side outer electrode, respectively, and a thickness of each of the second plated films is greater than a thickness of the first plated film. | 2016-02-18 |
20160049243 | MULTILAYER CAPACITOR AND INSTALLATION STRUCTURE OF MULTILAYER CAPACITOR - In a multilayer capacitor, a multilayer capacitor main body includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction. The second main surface is depressed in a portion extending from opposite ends of the second main surface toward a center of the second main surface in the length direction. | 2016-02-18 |
20160049244 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, and length-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A Si content ratio is higher in a boundary portion between the outer portion and the inner portion. A relationship expressed by T | 2016-02-18 |
20160049245 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, length-direction first and second outer layer sections, and width-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A boundary portion between the outer portion and the inner portion has a larger Si content than the outer portion. The inner portion has a higher composition ratio of Mn to Ti than the outer portion. Each of minimum dimensions in the length direction of the length-direction first and second outer layer sections is greater than both dimensions in the width direction of the width-direction first and second outer layer sections. | 2016-02-18 |
20160049246 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, and length-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A Si content ratio is higher in a boundary portion between the outer portion and the inner portion. The inner portion has a higher composition ratio of Mn to Ti than the outer portion. Both of minimum dimensions in the length direction of the length-direction first and second outer layer sections are greater than a dimension in the thickness direction of the thickness-direction first outer layer section. | 2016-02-18 |
20160049247 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, and width-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A Si content ratio is higher in a boundary portion between the outer portion and the inner portion. A relationship expressed by T | 2016-02-18 |
20160049248 | DIELECTRIC CERAMIC COMPOSITION AND DIELECTRIC ELEMENT - The present invention relates to a dielectric ceramic composition which is complex oxides represented by the following formula (1), {[(Bi | 2016-02-18 |
20160049249 | MULTILAYER CAPACITOR AND INSTALLATION STRUCTURE OF MULTILAYER CAPACITOR - In a multilayer capacitor, both a dimension in a thickness direction of a first terminal electrode on the first end surface and a dimension in the thickness direction of a second terminal electrode on the second end surface are greater than a minimum distance in the thickness direction between a first effective portion of a first inner electrode and a second main surface and a minimum distance in the thickness direction between a second effective portion of a second inner electrode and the second main surface. | 2016-02-18 |
20160049250 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more. | 2016-02-18 |
20160049251 | FOLDING TYPE CAPACITOR COMPRISING THROUGH HOLE - A folding type capacitor includes a metal substrate wherein a through hole penetrates an inside thereof; at least one dielectric layer formed on a surface of the metal substrate and an inner peripheral surface of the through hole; and an electrode layer formed on the at least one dielectric layer, wherein the metal substrate has bending portions whose surfaces are facing each other. Thus, manufacturing process is more simplified since Al | 2016-02-18 |
20160049252 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes external electrodes disposed on both end surfaces of a ceramic body and a mounting surface to be spaced apart from each other in a width direction, respectively, first internal electrodes connected to the left and right external electrodes, second internal electrodes having lead-out portions to be connected to the external electrodes disposed on the mounting surface. The ceramic body includes a first region positioned in a center portion thereof in the width direction and second regions positioned in both side portions in the width direction, with the first region therebetween, the plurality of first internal electrodes are disposed in the first region, and the first and second internal electrodes are alternately disposed in the second regions. | 2016-02-18 |
20160049253 | MULTILAYER CAPACITOR AND INSTALLATION STRUCTURE OF MULTILAYER CAPACITOR - In a multilayer capacitor, both a minimum distance in a thickness direction between a first effective portion of a first inner electrode and a second main surface and a minimum distance in the thickness direction between a second effective portion of a second inner electrode and the second main surface are shorter than any of a dimension in the thickness direction of a first extending portion of the first inner electrode, a dimension in the thickness direction of a second extending portion of the first inner electrode and a dimension in the thickness direction of the third extending portion of the second inner electrode. | 2016-02-18 |
20160049254 | MULTILAYER CERAMIC CAPACITOR - A multilayer body includes an inner layer portion having a dimension in a stacking direction greater than a dimension of the inner layer portion in a width direction, a second outer layer portion including an outer portion including a second principle surface and an inner portion disposed adjacent to both of the outer portion and the inner layer portion, a dimension of the outer portion in the stacking direction being greater than a dimension of the inner portion, and a composition ratio of Si relative to Ti in the outer portion is greater than that in the inner portion. | 2016-02-18 |
20160049255 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface. | 2016-02-18 |
20160049256 | MULTILAYER CERAMIC CAPACITOR, MULTILAYER CERAMIC CAPACITOR SERIES INCLUDING THE SAME, AND MULTILAYER CERAMIC CAPACITOR MOUNT BODY INCLUDING THE SAME - A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion. | 2016-02-18 |
20160049257 | ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT - An electronic component comprises an element body and an outer electrode. The element body has a pair of end faces opposing each other, a pair of main faces opposing each other while extending so as to connect the pair of end faces to each other, and a pair of side faces opposing each other while extending so as to connect the pair of main faces to each other. The outer electrode is formed on the end face side of the element body and covers a portion of the main and side faces adjacent to the end face. At least a surface of an electrode portion of the outer electrode located on the side face side thereof is covered with an insulating layer. | 2016-02-18 |
20160049258 | ELECTRICITY STORAGE DEVICE, PROCESS FOR PRODUCING THE SAME, AND DEVICE FOR PRODUCING THE SAME - An electricity storage device constituted by a stack of a plurality of electricity storage elements superposed on each other and two external electrodes formed on respective opposite side surfaces of the stack, wherein each of the plurality of electricity storage elements has a basic unit obtained by alternately superposing at least one electricity storage film and a plurality of internal electrode films on each other, and two protective films which have an electrical insulation property and which are superposed on respective opposite surfaces of the basic unit as seen in a direction of superposition of the at least one electricity storage film and the plurality of internal electrode films, and the two external electrodes are formed so as to bridge corresponding side surfaces of adjacent ones of the plurality of electricity storage elements. | 2016-02-18 |
20160049259 | SOLID ELECTROLYTIC CAPACITOR, AND PRODUCTION METHOD THEREOF - A production method efficiently produces a box sealed type solid electrolytic capacitor in which a capacitor element is accommodated in a box-shaped case. The method includes a step of preparing a bottom wall substrate having bottom walls. A step forms cathode anode circuit patterns on the bottom wall substrate. A step prepares a peripheral side wall substrate having peripheral side walls. A step prepares a peripheral side wall substrate in which a plurality of through-holes are provided that correspond to plurality of bottom wall structural portions. A step fixes a capacitor element to each bottom wall structural portion of the bottom wall substrate. A step obtains a capacitor continuous member in which a plurality of capacitor structural portions structuring a solid electrolytic capacitor by attaching an upper lid substrate on the peripheral side wall substrate. A step obtains a plurality of solid electrolytic capacitors by cutting the capacitor continuous member. | 2016-02-18 |
20160049260 | DYE-SENSITIZED SOLAR-CELL ELEMENT - A dye-sensitized solar cell element including a semiconductor electrode that includes an electrode substrate, and a metal oxide semiconductor porous film that is provided on the electrode substrate and supports a dye, a counter electrode that is disposed opposite to the semiconductor electrode, and an electrolyte layer that is provided between the semiconductor electrode and the counter electrode, the counter electrode including a nano-carbon material, and the electrolyte layer including a polyether compound that has a specific onium-structure repeating unit. The present invention makes it possible to provide a dye-sensitized solar cell element that exhibits high photoelectric conversion efficiency as compared with a known dye-sensitized solar cell element. | 2016-02-18 |
20160049261 | SUPERCAPACITOR - Embodiments provide a hybrid supercapacitor exhibiting high energy and power densities enabled by a high-performance lithium-alloy anode coupled with a porous carbon cathode in an electrolyte containing lithium salt. Embodiments include a size reduced silicon oxide anode, a boron-doped silicon oxide anode, and/or a carbon coated silicon oxide anode, which may improve cycling stability and rate performance. Further embodiments include a hybrid supercapacitor system using a Li-active anode in an electrolyte including LiPF6 in a mixture of ethylene carbonate, diethyl carbonate, and dimethyl carbonate (EC:DEC:DMC, 2:1:2 by vol.) and 10 wt % fluoroethylene carbonate (FEC), which may reduce the self-discharge rate. | 2016-02-18 |
20160049262 | Melanins as Active Components in Energy Storage Materials - In one aspect, an energy storage device comprises one or more organic electrodes comprising one or more melanin-based energy storage materials and cations, with the one or more melanin-based energy storage materials reversibly binding the cations while the biocompatible energy storage device is in an inactive state, and the one or more melanin-based energy storage materials releasing the cations to provide energy while the energy storage device is in an active state. | 2016-02-18 |
20160049263 | CIRCUIT BREAKERS WITH HANDLE BEARING PINS - Circuit breakers with handles having at least one handle bearing pin that contacts an upper end portion of a moving arm and allows the arm to rotate to “OFF”, “ON” and “TRIP” positions, typically about 90 degrees of rotation. | 2016-02-18 |
20160049264 | KEY STEM FOR A KEY MODULE OF A KEY FOR A KEYBOARD, KEY MODULE OF A KEY FOR A KEYBOARD, AND METHOD FOR MANUFACTURING A KEY MODULE FOR A KEY FOR A KEYBOARD - A key stem for a key module of a key for a keyboard is proposed. The key stem has a coupling section for coupling a key button thereto, and a guidance section for guiding a key stem into a receiving section of the key module when the key stem is actuated between a standby position and an actuation position. The key stem includes at least one elastically deformable end stop element, which is disposed on the guidance section and is designed to bear against at least one end stop section of the key module when the key stem is actuated into the actuation position. The key stem also includes at least one elastically deformable return stop element, which is disposed on the guidance section and is designed to bear against at least one return stop section of the key module when the key stem has been actuated back into the standby position. | 2016-02-18 |