06th week of 2011 patent applcation highlights part 39 |
Patent application number | Title | Published |
20110033921 | BARDET-BIEDL SUSCEPTIBILITY GENE AND USES THEREOF - The present invention relates to the identification of a gene, now designated negevin (ngvn), that is involved in the genetic disease Bardet Biedl Syndrome (BBS), which is characterized by such diverse symptoms as obesity, diabetes, hypertension, mental retardation, renal cancer and other abnormalities, retinopathy and hypogonadism. The human NGVN protein disclosed herein is 731 amino acids in length and is coded for by a gene spanning 17 exons. Homologs have been identified in mouse, rat, zebrafish. Methods of use for the gene, for example in diagnosis and therapy of BBS and in drug screening, also are described. | 2011-02-10 |
20110033922 | MICROCHIP-BASED ACOUSTIC TRAPPING OR CAPTURE OF CELLS FOR FORENSIC ANALYSIS AND RELATED METHOD THEREOF - The present invention provides a method and apparatus for separating by size a mixture of different size particles using ultrasound. The apparatus contains a microchannel having an acoustic transducer thereon. As a mixture of cells having different sizes flows down the microchannel, the ultrasonic radiation traps cells of desired sizes focused at nodes of a standing pressure wave in the microchannel. | 2011-02-10 |
20110033923 | MARKER FOR STEM CELLS AND ITS USE - A marker for mesenchymal stem cells (MSC) is provided, comprising an integrin alpha10 chain and/or an integrin alpha11 chain expressed on the cell surface of or intracellular in a MSC. The marker is used in methods for identification of mammalian MSC and in methods for isolation of MSC. Also included are isolated cellular populations of mammalian MSC and a cellular composition comprising the latter. Moreover, uses of said marker for isolation, modulation and identification of mammalian MSC are provided. | 2011-02-10 |
20110033924 | Apparatus and Method for Filtering Biological Material - A method and apparatus for harvesting cells from a fluid so as to preserve the integrity of the cells when used in the diagnosis of cancer. The apparatus comprises a filter adapted to collect cells of a predetermined size, a fluid pathway arranged to transmit fluid to and from the filter, a pump which provide a positive pressure which urges the fluid to the filter along the fluid pathway and a negative pressure which draws the fluid from the filter along the fluid pathway and which operates to pass the sample through the filter in a first direction to collect cells on the filter. A second pump operates to pass a cell preservative fluid through the filter in a second direction to remove cells from the filter for collection. A controller is provided to regulate the flow of fluid along the fluid pathway. The method and apparatus provides a gentle pressure gradient which minimises damage to the cells during the process of filtration and collection. | 2011-02-10 |
20110033925 | Cell Separation Method and Apparatus - Disclosed herein are apparatus and methods for isolating a fraction of interest from a physiological fluid sample. | 2011-02-10 |
20110033926 | Production Of Viral Vectors - The present invention relates to methods and compositions for the production of viral vectors. In particular, the present invention provides methods and compositions for faster, higher titer and higher purity production of viral vectors (e.g. adenoviral vectors). In some embodiments, the present invention provides gutted and helper viruses with identical or similar termini. In other embodiments, the present invention provides terminal protein linked adenoviral DNA. In certain embodiments, the present invention provides template extended adenoviral DNA. | 2011-02-10 |
20110033927 | METHODS OF GENERATING SMALL-DIAMETER TISSUE ENGINEERED BLOOD VESSELS - Methods for generating small diameter tissue engineered blood vessels through direct cell seeding onto tubular templates or mandrels, such as fibrin microthreads or collagen-coated silicon tubes, are described. | 2011-02-10 |
20110033928 | METHODS AND COMPOSITIONS FOR GROWTH OF CELLS AND EMBRYONIC TISSUE ON A SYNTHETIC POLYMER MATRIX - The present invention provides methods and compositions for establishing and maintaining growth of cells and embryonic tissue on a synthetic polymer matrix. For example, the present invention provides synthetic growth matrices for stem cells, gametes, mature differentiated cells, and embryonic tissue (e.g., blastomeres, embryos, and embryoid bodies). In certain embodiments, the cells are capable of going through multiple passages while remaining in an undifferentiated state as a result of the synthetic polymer matrix. | 2011-02-10 |
20110033929 | USES OF ANTIBODIES TO MAMMALIAN DC LANGERHANS CELL ANTIGEN - The present invention relates to purified mammalian DC cell surface protein, designated Langerin, nucleic acids encoding Langerin, and antibodies which specifically bind Langerin. | 2011-02-10 |
20110033930 | METHOD FOR OBTAINING NGN3-EXPRESSING CELLS AND INSULIN PRODUCING-BETA CELLS - The present invention relates to a method for obtaining Ngn3-expressing cells and insulin producing-beta cells by contacting a Pdx1-expressing pancreas explant with an amount of at least one histone deacetylase inhibitor (HDACi). The inventive methods have the advantage of being simple and quick, and of providing large amounts of Ngn3-expressing cells and insulin producing-beta cells, that are useful therapeutic tools. The invention also relates to a pharmaceutical composition for the treatment of diabetes which comprises an amount of at least one HDACi. | 2011-02-10 |
20110033931 | DE-DIFFERENTIATION OF HUMAN CELLS - Methods of de-differentiating somatic cells to an embryonic stem cell state comprising direct delivery of a protein into the somatic cell, wherein the protein effects de-differentiation of the somatic cell to an embryonic stem cell phenotype. | 2011-02-10 |
20110033932 | SUBSTRATE FOR CELL ADHESION OR CULTURE AND METHOD FOR PRODUCING THE SAME - A substrate for cell adhesion or culture of the invention comprises: a base material; a cell adhesion layer arranged to cover a predetermined region on this base material; and a non-cell adhesion layer arranged on the base material to cover a region other than the predetermined region. An exposed surface of the cell adhesion layer is a cell adhesion surface. The non-cell adhesion layer has a light transmission characteristic, and an exposed surface of the non-cell adhesion layer is a non-cell adhesion surface. | 2011-02-10 |
20110033933 | METHOD APPLYING HEMODYNAMIC FORCING AND KLF2 TO INITIATE THE GROWTH AND DEVELOPMENT OF CARDIAC VALVES - A method for forming a cardiovascular structure in culture is provided. The method includes applying mechanical force to a cell population in culture such that a cardiovascular structure is formed. In some embodiments, the mechanical force is produced in culture medium by a pulsatile liquid flow with a retrograde component. The cell population can include stem cells or differentiated cells, or combinations of both. In particular embodiments, a cardiovascular valve is formed. Scaffolds for the support and growth of the cell population, and bioreactors including the scaffolds, are also provided. | 2011-02-10 |
20110033934 | Transcriptome Transfer Produces Cellular Phenotype Conversion - The present invention includes methods for effecting phenotype conversion in a cell by transfecting the cell with phenotype-converting nucleic acid. Expression of the nucleic acids results in a phenotype conversion in the transfected cell. Preferably the phenotype-converting nucleic acid is a transcriptome, and more preferably an mRNA transcriptome. | 2011-02-10 |
20110033935 | RATIONALLY-DESIGNED MEGANUCLEASES WITH RECOGNITION SEQUENCES FOUND IN DNASE HYPERSENSITIVE REGIONS OF THE HUMAN GENOME - Rationally-designed LAGLIDADG meganucleases and methods of making such meganucleases are provided. In addition, methods are provided for using the meganucleases to generate recombinant cells and organisms having a desired DNA sequence inserted into a limited number of loci within the genome, as well as methods of gene therapy, for treatment of pathogenic infections, and for in vitro applications in diagnostics and research. | 2011-02-10 |
20110033936 | CANINE iPS CELLS AND METHOD OF PRODUCING SAME - Provided are a method of producing canine iPS cells, comprising (a) the step of bringing into contact with each other a canine somatic cell and a nuclear reprogramming factor, and (b) the step of culturing the cell in a medium containing at least one substance selected from the group consisting of a mitogen-activated protein kinase kinase inhibitor, an activin receptor-like kinase inhibitor, a glycogen synthase kinase inhibitor, a L-type calcium channel agonist and a DNA methylation inhibitor, and a leukemia inhibitory factor, and canine iPS cells that can be obtained by the method. | 2011-02-10 |
20110033937 | DOWN-REGULATION OF GENE EXPRESSION USING ARTIFICIAL MICRORNAS - Isolated nucleic acid fragments comprising precursor miRNA, and artificial miRNAs and their use in down-regulating gene expression are described. | 2011-02-10 |
20110033938 | SYSTEM FOR INDUCIBLE GENE EXPRESSION IN CHLAMYDOMONAS - The unicellular green alga | 2011-02-10 |
20110033939 | METHOD OF MEASURING LIPOARABINOMANNAN AND APPLICATION THEREOF - A method for measuring LAM and a method for detecting an acid-fast bacterium, which comprise at least a step of allowing a | 2011-02-10 |
20110033940 | CLICK CHEMISTRY, MOLECULAR TRANSPORT JUNCTIONS, AND COLORIMETRIC DETECTION OF COPPER - Click chemistry is used to construct molecular transport junctions (MTJs) through assembly of a molecular wire across a nanogap formed between two electrodes. Also disclosed are methods of using click chemistry and oligonucleotide-modified nanoparticles to detect the presence of copper in a sample. | 2011-02-10 |
20110033941 | RISK ANALYSIS IN PATIENTS WITH AND WITHOUT METABOLIC SYNDROME - The present invention relates to a method for identifying a subject being susceptible to a metabolic syndrome related therapy based on determining the amounts of adiponectin, retinol binding protein 4, and proinsulin in a sample of a subject, and comparing the thus determined amounts to suitable reference amounts. Moreover, the present invention relates to a method for predicting the risk of developing a metabolic syndrome in an apparently healthy subject based on determining the aforementioned markers in a sample from the subject. Also encompassed by the present invention are kits and devices adapted to carry out the methods of the present invention. | 2011-02-10 |
20110033942 | PREDICTING RENAL FAILURE IN DIABETES PATIENTS BASED ON PLACENTAL GROWTH FACTOR AND SOLUBLE FLT-1 - Disclosed is a method for predicting the risk of developing renal failure or mortality for a subject suffering from diabetes mellitus. More specifically, a method is disclosed for predicting the risk of developing renal failure for a subject suffering from diabetes mellitus, the method including the steps of determining the amounts of PLGF and sFlt-1 in a sample of a subject suffering from diabetes mellitus and comparing the amounts of PLGF and sFlt-1 determined with reference amounts of PLGF and sFlt-1, whereby the risk of developing renal failure is predicted. Also disclosed are diagnostic devices and kits for carrying out the aforementioned methods. | 2011-02-10 |
20110033943 | HYDROGEN SULPHIDE SAMPLING METHOD - The invention relates to a method for sampling a sulphur-containing solid product including supplying a gas flow comprising hydrogen sulphide, bringing the gas flow into contact with a solid reagent and reacting the solid reagent with the hydrogen sulphide contained in the gas flow, the reaction fixing the sulphur of the hydrogen sulphide by forming a sulphur-containing solid product which is different in colour from the solid reagent, and recovering the sulphur-containing solid product. The invention also relates to a device suitable for the implementation of this method. | 2011-02-10 |
20110033944 | METHOD FOR MEASURING HYPOCHLORITE ION - A method for measuring hypochlorite ion, which comprises the steps of: | 2011-02-10 |
20110033945 | COLORIMETRIC ASSAY FOR PYRETHROID INSECTICIDES - The invention relates to an assay to test for pyrethroids in a sample. The assay is particularly useful for testing material treated with pyrethroids, such as bed netting and the like. | 2011-02-10 |
20110033946 | DETECTION OF SHORT-CHAIN FATTY ACIDS IN BIOLOGICAL SAMPLES - Described herein is a method of detecting and/or quantifying analytes, such as short-chain fatty acids. Analysis for the presence and/or quantity of the small molecule can be performed on a biological sample from a subject. In some embodiments, a liquid chromatography/mass spectrometry (LC-MS/MS) instrumentation is combined with a solid-phase extraction (SPE). Methods of derivatization can also be incorporated with LC-MS/MS and SPE instrumentation to detect and quantify target analytes. In addition to derivation, methods of reconstituting derivatized molecules can also be incorporated with LC-MS/MS and SPE instrumentation to detect and quantify target analytes. | 2011-02-10 |
20110033947 | METHOD OF DETECTING TARGET SUBSTANCE AND TARGET-SUBSTANCE DETECTION KIT - Provided is a detection method for a target substance capable of enhancing detection sensitivity and quantitative property of a magnetic biosensor, while keeping monodispersity and dispersion stability of magnetic markers, including the steps of: reacting the target substance in a sample solution with a first target substance trapping member immobilized on a sensing element and with a second target substance trapping member immobilized on a gel particle to hold the gel particle on the sensing element; adjusting a magnetic marker precursor including the gel particle and a magnetic material precursor existing in the gel particle by bringing the magnetic material precursor into contact with the gel particle; synthesizing a magnetic material from the magnetic material precursor held on the gel particle, thereby adjusting the magnetic markers; and detecting the magnetic markers with the sensing element. | 2011-02-10 |
20110033948 | METHOD OF READING ENCODED PARTICLES - Microparticles | 2011-02-10 |
20110033949 | TEFLON CONTAINER FOR SAMPLE DECOMPOSITION USING GAS CONDENSATION BY AIR COOLING - When an atomic absorption spectrophotometer (AAS) or inductively coupled plasma (ICP) is used, samples must be introduced in a liquid state. Thus, sample decomposition by acids must be performed. Methods for decomposing samples using beakers or microwaves have caused several problems such as loss of volatile elements, excessive use of acids, emission of harmful gases, limitation of sample capacity and amount, and inconvenience of cleaning up. However, the present invention can treat many samples with one acid injection through gas condensation by both heating of a reaction container and air cooling of a collection pipe, wherein the reaction container is made of fluororesin (Teflon) or quartz. Also, if there are many samples, the samples can be treated at once. Furthermore, since the present invention can treat the samples with a conventional heating plate, the invention can be used at inexpensive costs. Additionally, since harmful gases or volatile elements generated in decomposition are condensed in an absorption pipe, anticorrosive effects and accurate data can be obtained. Also, the invention can reduce reagents and prevent both contamination of samples caused by concentration of reagents and air pollution caused by harmful gases generated during decomposition. | 2011-02-10 |
20110033950 | TURBIDIMETRIC IMMUNOASSAY FOR ASSESSING HUMAN CYSTATIN C - There is a demand for improved turbidimetric immunoassays for human Cystatin C in biological samples, especially in human clinical samples of body fluids. The present invention provides a turbidimetric immunoassay method and reagent set enabling measurement of human Cystatin C by turbidimetric methods, resulting in a surprisingly stronger and faster turbidimetric signal than in the present state of the art. The increased and faster signal is accomplished by the use of new reagents and compositions, and enables shorter assay times and kinetic reading with a stronger signal, improving overall assay speed and quality. Improved robustness to lipid interference and improved linearity is achieved. | 2011-02-10 |
20110033951 | ASSAY METHOD AND KIT FOR NUCLEIC ACID BINDING PROTEIN - An object of the present invention is to provide a method of detecting a nucleic acid binding protein and a method of screening for a binding inhibitor or promoter for a nucleic acid binding protein. According to the present invention, there is provided a method of detecting binding between a nucleic acid and a nucleic acid binding protein, comprising determining the degree of structural change in a nucleic acid complex having at least two nucleic acid duplex moieties. | 2011-02-10 |
20110033952 | Sensor for Biomolecules - A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies. | 2011-02-10 |
20110033953 | CHARACTERIZATION OF REACTION VARIABLES - A microscale method for the characterization of one or more reaction variables that influence the formation or dissociation of an affinity complex comprising a ligand and a binder, which have mutual affinity for each other. The method is characterized in comprising the steps of: (i) providing a microfluidic device comprising a microchannel structures that are under a common flow control, each microchannel structure comprising a reaction microactivity; (ii) performing essentially in parallel an experiment in each of two or more of the plurality of microchannel structures, the experiment in these two or more microchannel structures comprising either a) formation of an immobilized form of the complex and retaining under flow conditions said form within the reaction microactivity, or b) dissociating, preferably under flow condition, an immobilized form of the complex which has been included in the microfluidic device provided in step (i), at least one reaction variable varies or is uncharacterized for said two or more microchannel structures while the remaining reaction variables are kept essentially constant; (iii) measuring the presentation of the complex in said reaction microactivity in said two or more microchannel structures; and (iv) characterizing said one or more reaction variables based on the values for presentation obtained in step (iii). | 2011-02-10 |
20110033954 | BIOFUNCTIONALIZED QUANTUM DOTS FOR BIOLOGICAL IMAGING - Novel biofunctionalized quantum dots include a mercaptoalkanoic acid linked to the surface of a nanocrystalline core and a biofunctional group linked to the surface. Biofunctionalized quantum dots are made by a novel synthesis method. Biofunctionalized quantum dots can be used in imaging or therapy applications. | 2011-02-10 |
20110033955 | NONVOLATILE FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench. | 2011-02-10 |
20110033956 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF CONFIRMING OPERATION OF LIQUID FLOWRATE CONTROL DEVICE - A substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of confirming an operation of a liquid flowrate control device are provided. The substrate processing apparatus comprises: a process chamber accommodating a substrate; a liquid source supply system supplying a liquid source into the process chamber; a solvent supply system supplying a solvent having a vapor pressure greater than that of the liquid source into the process chamber; a liquid flowrate control device controlling flowrates of the liquid source and the solvent; and a controller controlling the liquid source supply system, the solvent supply system, and the liquid flowrate control device so that the solvent is supplied into the liquid flowrate control device than the solvent supply system to confirm an operation of the liquid flowrate control device before the liquid source supply system supplies the liquid source into the process chamber. | 2011-02-10 |
20110033957 | INTEGRATED THIN FILM METROLOGY SYSTEM USED IN A SOLAR CELL PRODUCTION LINE - Embodiments of the present invention generally relate to systems, apparatuses, and methods used to form solar cell devices using processing modules adapted to perform one or more processes in the formation of the solar cell devices. In one embodiment, the system provides an inline inspection system of solar cell devices within a solar cell production line while collecting and using metrology data to diagnose, tune, or improve production line processes during manufacture of solar cell devices. In one embodiment, the inspection system provides an on-the-fly characterization module positioned downstream from one or more processing tools wherein the characterization module is configured to measure on-the-fly one or more properties of one or more photovoltaic layers formed on a substrate surface and a system controller in communication with the characterization module and the one or more processing tools, where the system controller is configured to analyze information received from the characterization module. | 2011-02-10 |
20110033958 | METHOD FOR FORMING OXIDE FILM ON SILICON WAFER - The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed. | 2011-02-10 |
20110033959 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A liquid crystal display (LCD) device having an array substrate with a top gate type TFT includes a first transparent metal layer deposited to enhance the adhesion between a data metal layer and an insulating substrate before a data metal deposition, and a second transparent metal layer deposited to enhance the adhesion between a gate metal layer and an insulating substrate before a gate metal deposition. The LCD device having the array substrate with a top gate type TFT can be fabricated with a reduced number of masking or sputtering processes, thereby reducing the fabrication time of the LCD device and increasing the yield of the LCD device. | 2011-02-10 |
20110033960 | ORGANIC LIGHT EMITTING DIODE DEVICE - An organic light emitting diode (OLED) device according to the present invention includes a first substrate; a first electrode on the first substrate in the pixel region, the first electrode formed of a metal; an organic light-emitting layer on the first electrode; a second electrode on the organic light-emitting layer, the second electrode formed of a transparent conductive material; and a transparent layer on the second electrode, the transparent layer including an inorganic material or a semiconductor material. | 2011-02-10 |
20110033961 | FLEXIBLE DISPLAY AND MANUFACTURING METHOD OF THE SAME - A flexible display of the present invention is an active matrix flexible display in which a TFT is provided for each pixel. In the flexible display, an adhesive layer, a protective layer, a gate electrode for the TFT, which is buried in the protective layer, a gate insulating layer for the TFT, source and drain electrodes for the TFT, a pixel electrode electrically connected to the drain electrode, an organic active layer for the TFT, an organic EL layer including a red (R) emitting layer, a green (G) emitting layer and a blue (B) emitting layer, which are formed on a plurality of the pixel electrodes, a metal electrode, and a sealing layer are formed on a plastic film. | 2011-02-10 |
20110033962 | HIGH EFFICIENCY LED WITH MULTI-LAYER REFLECTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - Provided are a high efficiency light emitting diode and a method for fabricating the same, in which a multi-layer reflector is laminated to a surface emission type light emitting diode to improve the efficiency of a light emitting diode. A high efficiency reflector is integrated on the light emitting diode using a dry etching process and a wet etching process. Although light produced from an active layer when applying a current thereto is emitted in several directions, the reflectors formed both sides of the active layer reflect the emitted light toward a surface of a semiconductor substrate, thus improving the light efficiency. Compared with the existing light emitting diode, the structure of the proposed light emitting diode is more efficient and therefore it can be used as a light source having low power consumption and high brightness. Also, the light emitting diode can be fabricated using the existing semiconductor process, thus reducing the complexity of the fabricating process. | 2011-02-10 |
20110033963 | FLEXIBLE DISPLAY AND MANUFACTURING METHOD OF THE SAME - A flexible display of the present invention is an active matrix flexible display in which a TFT is provided for each pixel. In the flexible display, an adhesive layer, a protective layer, a gate electrode for the TFT, which is buried in the protective layer, a gate insulating layer for the TFT, source and drain electrodes for the TFT, a pixel electrode electrically connected to the drain electrode, an organic active layer for the TFT, an organic EL layer including a red (R) emitting layer, a green (G) emitting layer and a blue (B) emitting layer, which are formed on a plurality of the pixel electrodes, a metal electrode, and a sealing layer are formed on a plastic film. | 2011-02-10 |
20110033964 | THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - A thin film deposition apparatus and a method of manufacturing an organic light-emitting display device using the thin film deposition apparatus. The thin film deposition apparatus includes a plurality of thin film deposition assemblies, each of which includes: a deposition source that discharges a deposition material; a deposition source nozzle unit that is disposed at a side of the deposition source and includes a plurality of deposition source nozzles; a patterning slit sheet that is disposed opposite to the deposition source nozzle unit and includes a plurality of patterning slits arranged in a first direction; and a barrier plate assembly that is disposed between the deposition source nozzle unit and the patterning slit sheet, in the first direction. The barrier plate assembly includes a plurality of barrier plates that partition a space between the deposition source nozzle unit and the patterning slit sheet into a plurality of sub-deposition spaces. | 2011-02-10 |
20110033965 | VERTICAL NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat. | 2011-02-10 |
20110033966 | GROWTH OF N-FACE LED WITH INTEGRATED PROCESSING SYSTEM - Embodiments described herein generally relate to apparatus and methods for forming Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and hydride vapor phase epitaxial (HVPE) processes. In one embodiment, a method for fabricating a nitrogen-face (N-face) polarity compound nitride semiconductor device is provided. The method comprises depositing a nitrogen containing buffer layer having N-face polarity over one or more substrates using a metal organic chemical vapor deposition (MOCVD) process to form one or more substrates having N-face polarity and depositing a gallium nitride (GaN) layer over the nitrogen containing buffer layer using a hydride vapor phase epitaxial (HVPE) deposition process, wherein the nitrogen containing buffer layer and the GaN layer are formed without breaking vacuum and exposing the one or more substrates to atmosphere. | 2011-02-10 |
20110033967 | Methods for trapping charge in a microelectromechanical system and microelectromechanical system employing same - Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive. | 2011-02-10 |
20110033968 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR PRODUCING THE SAME - A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region. | 2011-02-10 |
20110033969 | METHODS OF GROWING HETEROEPITAXIAL SINGLE CRYSTAL OR LARGE GRAINED SEMICONDUCTOR FILMS AND DEVICES THEREON - A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies. | 2011-02-10 |
20110033970 | METHODS AND RELATED SYSTEMS FOR THIN FILM LASER SCRIBING DEVICES - Methods and related systems for fabricating a solar-cell assembly are provided. An example method comprises forming a series of layers and scribing a series of aligned interconnect lines in the layers prior to forming any isolation line related features. The example method provides for the use of contiguously-scribed interconnect lines as compared to an existing method where at least one interconnect line is segmented to avoid scribing through a previously-formed isolation line related feature located where an isolation line is to be scribed. The ability to use contiguously-scribed interconnect lines may improve the throughput of the fabrication process. | 2011-02-10 |
20110033971 | ORGANIC INVERTER INCLUDING SURFACE-TREATED LAYER AND METHOD OF MANUFACTURING THE SAME - An organic inverter and a method of manufacturing the same are provided, which regulates threshold voltages depending on positions when an inverter circuit is manufactured on a substrate using an organic semiconductor. To form a depletion load transistor and an enhancement driver transistor at adjacent positions of the same substrate, the surface of the substrate is selectively treated by positions or selectively applied by self-assembly monolayer treatment. Thus, a D-inverter having a combination of a depletion mode and an enhancement mode is more easily realized than a conventional method using a transistor size effect. Also, the D-inverter can be realized even with the same W/L ratio, thereby increasing integration density. That is, the W/L ratio does not need to be increased to manufacture a depletion load transistor, thereby improving integration density. | 2011-02-10 |
20110033972 | PROGRAMMABLE POLYELECTROLYTE ELECTRICAL SWITCHES - An apparatus includes a first solid electrode on a substrate, a polyelectrolyte layer over a part of the first solid electrode, a second solid electrode on a portion of the polyelectrolyte layer, and an anchoring layer on the part of the first solid electrode. The polyelectrolyte layer is either chemically bonded to the anchoring layer or has a thickness of less than about 20 nanometers. | 2011-02-10 |
20110033973 | DEPOSITION APPARATUS FOR TEMPERATURE SENSITIVE MATERIALS - A system for the deposition of vaporized materials on a substrate is described, comprising at least first and second orientation-independent apparatuses for directing vaporized organic materials onto a substrate surface to form first and second films, each of the first and second orientation-independent apparatuses being arranged in a different relative orientation and comprising: a chamber containing a quantity of material; a permeable member at one end of the chamber with a heating element for vaporizing the material; and means for continuously feeding the material toward the permeable member as it is vaporized, whereby organic material vaporizes at a desired rate-dependent vaporization temperature at the one end of the chamber. A plurality of thin films may be deposited on a substrate using deposition apparatus in a variety of orientations. Such a design provides reduced costs and improved deposition rate control. | 2011-02-10 |
20110033974 | METHOD FOR FABRICATING HOLLOW NANOTUBE STRUCTURE - A method for fabricating a hollow nanotube structure is disclosed. The method includes the steps of providing a substrate, developing a plurality of nanowires on the substrate with a predetermined size on the seed layer at relatively low temperature by a hydro-thermal growth method, forming an outer covering layer on the surfaces of the nanowires, selectively etching an upper end of the outer coating layer to expose an upper end of the nanowires and removing the nanowires to remain the hollow outer coating layer to form a plurality of hollow nanotubes. The method can simplify the nanotube manufacturing process, increase the dimension precision of the nanotubes and enhance the photoelectric properties of micro-electro-mechanical elements. | 2011-02-10 |
20110033975 | Semiconductor device and method for manufacturing the same - A semiconductor device includes: a semiconductor element having first and second surfaces, wherein the semiconductor element includes at least one electrode, which is disposed on one of the first and second surfaces; and first and second metallic layers, wherein the first metallic layer is disposed on the first surface of the semiconductor element, and wherein the second metallic layer is disposed on the second surface of the semiconductor element. The one electrode is electrically coupled with one of the first and second metallic layers, which is disposed on the one of the first and second surfaces. The one electrode is coupled with an external circuit through the one of the first and second metallic layers. | 2011-02-10 |
20110033976 | SELF-ASSEMBLY OF CHIPS ON A SUBSTRATE - A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced. | 2011-02-10 |
20110033977 | METHOD OF FORMING SOLDERABLE SIDE-SURFACE TERMINALS OF QUAD NO-LEAD FRAME (QFN) INTEGRATED CIRCUIT PACKAGES - A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods. | 2011-02-10 |
20110033978 | STACKED SEMICONDUCTOR PACKAGE ELECTRICALLY CONNECTING SEMICONDUCTOR CHIPS USING OUTER SURFACES THEREOF AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same. The stacked semiconductor package includes a semiconductor chip module having two or more semiconductor chips which are stacked in the shape of steps. Each of the semiconductor chips includes pads located on an upper surface thereof and an inclined side surface connected with the upper surface. Connection patterns are formed in the shape of lines on the inclined side surfaces and the upper surfaces of the semiconductor chips to electrically connect pads of the semiconductor chips. | 2011-02-10 |
20110033979 | EDGE CONNECT WAFER LEVEL STACKING - A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package. | 2011-02-10 |
20110033980 | STACK PACKAGE THAT PREVENTS WARPING AND CRACKING OF A WAFER AND SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME - A stack package and a method for manufacturing the same. The stack package includes first and second semiconductor chips placed such that surfaces thereof, on which bonding pads are formed, face each other; a plurality of through-silicon vias formed in the first and second semiconductor chips; and a plurality of redistribution layers formed on the surfaces of the first and second semiconductor chips to connect the through-silicon vias to the corresponding bonding pad, wherein the redistribution layers of the first and second semiconductor chips contact each other. By forming the stack package in this manner, it is possible to prevent pick-up error and cracks from forming during the manufacturing process, and therefore the stack package can be reliable formed. | 2011-02-10 |
20110033981 | MODULAR DIE AND MASK FOR SEMICONDUCTOR PROCESSING - Modular dies and modular masks that can be used during the manufacture of semiconductor devices are described. The modular mask can be used repeatedly to make multiple, substantially-similar modular dies. The modular die contains a substrate with an integrated circuit as well as a conductive layer containing a source metal and a gate metal connected respectively to the source and gate of the integrated circuit. The gate metal of the conductive layer is located only in an outer portion of the modular die. The modular die can be made by providing the integrated circuit in a first and second portion of the substrate, providing the conductive layer on both the first and second portions, making a first modular die by patterning the conductive layer on the first portion using the modular mask; moving the modular mask to the second portion and using it to make a second modular die by patterning the conductive layer on the second portion. Thus, fewer mask sets need to be made, improving efficiency and reducing costs. Other embodiments are described. | 2011-02-10 |
20110033982 | Lead-forming die and method of manufacturing semiconductor device utilizing lead-forming die - Provided is that a lead-forming die includes an upper die and a lower die disposed so as to oppose the upper die; a supporting unit for semiconductor package, provided on an upper face of the lower die; a moving unit provided on a lower face of the upper die and movable in a direction that the upper die and the lower die oppose each other; a plurality of shafts supported by the moving unit so as to axially move with respect thereto; a presser provided above the supporting unit for semiconductor package, and at a lower end portion of the shaft; and a locking device that stops a movement of the shaft, provided between the upper die and the moving unit. | 2011-02-10 |
20110033983 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. | 2011-02-10 |
20110033984 | MOLD CLEANING SHEET AND METHOD OF PRODUCING SEMICONDUCTOR DEVICES USING THE SAME - A cleaning sheet ( | 2011-02-10 |
20110033985 | Manufacturing Method for Integrating a Shunt Resistor into a Semiconductor Package - An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads. | 2011-02-10 |
20110033986 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP AND RESIN SEALING PORTION - A method of manufacturing a semiconductor device includes preparing a semiconductor chip having a main surface, forming a conductive portion made from a material having conductivity and malleability on the main surface, arranging the semiconductor chip within a die after the step of forming the conductive portion, the die having an inner surface facing the main surface with a spacing therebetween, and a protruding portion protruding from the inner surface to press the conductive portion, and forming a sealing resin portion having a surface and an opening by filling the die with a resin and then removing the die, the surface facing the main surface, the opening passing through between the conductive portion and the surface. | 2011-02-10 |
20110033987 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate. | 2011-02-10 |
20110033988 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film. | 2011-02-10 |
20110033989 | SEMICONDUCTOR DEVICE HAVING MULTI-GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and includes the slabs, each slab having a first surface, a second surface facing a direction opposite to the first side, and a top surface. The first active region and the second active region are composed of identical or different materials. The second active region contacts at least one end of each of the slabs on the substrate to connect the slabs to one another The method includes forming a first active region in a line-and-space pattern on the substrate and forming the second active region. | 2011-02-10 |
20110033990 | TRANSISTOR, AND DISPLAY DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE USING THE SAME - It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected to the semiconductor film through a contact hole formed at least in the insulating film are included; the semiconductor film has a first range of a concentration of the impurity element (1×10 | 2011-02-10 |
20110033991 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole. | 2011-02-10 |
20110033992 | Thin Film Transistor, Method of Fabricating the Same, and Organic Light Emitting Display Device Including the Same - A thin film transistor (TFT) having improved characteristics, a method for fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT is constructed with a substrate, a semiconductor layer disposed on the substrate and including a channel region, source and drain regions, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer and corresponding to the channel region, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer. The channel region is made from polycrystalline silicon (poly-Si), and the source and drain regions are made from amorphous silicon (a-Si). The polycrystalline silicon of the channel region is formed by crystallizing amorphous silicon using Joule's heat generated by the gate electrode. | 2011-02-10 |
20110033993 | METHOD OF FABRICATING CMOS TRANSISTOR - The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required. | 2011-02-10 |
20110033994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar. | 2011-02-10 |
20110033995 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below. | 2011-02-10 |
20110033996 | METHOD FOR PRODUCING A CONDUCTIVE NANOPARTICLE MEMORY DEVICE - A method for producing a memory device with nanoparticles, comprising the steps of:
| 2011-02-10 |
20110033997 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions. | 2011-02-10 |
20110033998 | OPTIMIZED HALO OR POCKET COLD IMPLANTS - An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus. | 2011-02-10 |
20110033999 | DOPING METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A doping method includes: a first step of depositing a material solution containing an antimony compound containing elements selected from the group consisting essentially of hydrogen, nitrogen, oxygen, and carbon together with antimony to a surface of a substrate; a second step of drying the material solution to form an antimony compound layer on the substrate; and a third step of performing heat treatment so that antimony in the antimony compound layer is diffused into the substrate. | 2011-02-10 |
20110034000 | SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 2011-02-10 |
20110034001 | METHOD OF MAKING BIPOLAR TRANSISTOR - A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region ( | 2011-02-10 |
20110034002 | SYSTEMS AND METHODS TO LAMINATE PASSIVES ONTO SUBSTRATE - A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer. | 2011-02-10 |
20110034003 | Vacuum Cell Thermal Isolation for a Phase Change Memory Device - A memory device with improved thermal isolation. The memory cell includes a first electrode element, having an upper surface; an insulator stack formed on the first electrode element, including first, second and third insulating members, all generally planar in form and having a central cavity formed therein and extending therethrough, wherein the second insulator member is recessed from the cavity; a phase change element, generally T-shaped in form, having a base portion extending into the cavity to make contact with the first electrode element and making contact with the first and third insulating members, and a crossbar portion extending over and in contact with the third insulating member, wherein the base portion of the phase change element, the recessed portions of the second insulating member and the surfaces of the first and third insulating members define a thermal isolation void; and a second electrode formed in contact with the phase change member. | 2011-02-10 |
20110034004 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming a buffer oxide layer in a first region and a second region of a semiconductor substrate; forming a plurality of first preliminary mask patterns on the buffer oxide layer in the first region; forming a plurality of second preliminary mask patterns between every two adjacent first preliminary mask patterns from among the plurality of first preliminary mask patterns, respectively; forming a plurality of first mask patterns and a plurality of second mask patterns by trimming the plurality of first preliminary mask patterns and the plurality of second preliminary mask patterns; forming a plurality of first active region mask patterns for exposing the semiconductor substrate; defining a plurality of active regions in the semiconductor substrate by forming a trench including a plurality of first trench spaces having same width as the first space and a plurality of second trench spaces under the second space in the first region; and forming a first liner layer on the semiconductor substrate having the trench therein such that the plurality of first trench spaces are completely filled with the first liner layer. | 2011-02-10 |
20110034005 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film ( | 2011-02-10 |
20110034006 | METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE - A method for fabricating a semiconductor on insulator substrate by providing a first semiconductor substrate with a first impurity density of a first impurity type, subjecting the first semiconductor substrate to a first thermal treatment to thereby reduce the first impurity density in a modified layer adjacent a surface of the first semiconductor substrate being treated, transferring at least partially the modified layer with the reduced first impurity density onto a second substrate, to thereby obtain a modified second substrate, and providing a further layer on a transferred layer of the modified second substrate with the further layer having a second impurity density of a second impurity type that is different than the first impurity type of the transferred modified layer. By doing so, a contamination by dopants of the second impurity type of a fabrication line using semiconductor material with dopants of the first impurity type, can be prevented. | 2011-02-10 |
20110034007 | DIVIDING METHOD FOR PLATELIKE WORKPIECE - A dividing method for a platelike workpiece having a two-layer structure such that a solder layer (metal layer) is formed on the back side of a wafer (substrate). First, a modified layer is formed in the wafer along each division line formed on the front side of the wafer. Thereafter, the workpiece is bent along each division line to thereby divide the wafer along each division line from the corresponding modified layer as a starting point and simultaneously form a weak portion in the solder layer along each division line. Thereafter, an expandion tape attached to the solder layer is expanded to apply an external force to the solder layer, thereby dividing the solder layer along each division line from the corresponding weak portion as a starting point. Thus, the workpiece is completely divided. | 2011-02-10 |
20110034008 | METHOD FOR FORMING A TEXTURED SURFACE ON A SEMICONDUCTOR SUBSTRATE USING A NANOFABRIC LAYER - A method of forming a textured surface on a substrate or material layer within a semiconductor fabrication process. In one aspect of the disclosure, a sacrificial nanofabric layer is deposited over a material layer and an etch process is used to transfer the surface texture of the nanofabric layer downward to the material layer. In another aspect of the disclosure, a thin material layer is deposited over a nanofabric layer such that the surface texture of the nanofabric layer is transferred upward to the material layer. Within both aspects, varying the porosity of nanofabric layer provides a measure of control over the degree of texturization of the material layer. | 2011-02-10 |
20110034009 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - To provide a thin film transistor having a high field effect mobility and a small variation in characteristics thereof, a second amorphous semiconductor layer patterned in a predetermined shape is formed on a first crystalline semiconductor layer | 2011-02-10 |
20110034010 | PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions. | 2011-02-10 |
20110034011 | FORMATION OF GRAPHENE WAFERS ON SILICON SUBSTRATES - Processes for forming full graphene wafers on silicon or silicon-on-insulator substrates. The processes comprise formation of a metal carbide layer on the substrate and annealing of the metal carbide layer under high vacuum. For volatile metals, this annealing step results in volatilization of the metal species of the metal carbide layer and reformation of the carbon atoms into the desired graphene wafer. Alternatively, for non-volatile metals, the annealing step results in migration of the metal in the metal carbide layer to the top surface of the layer, thereby forming a metal rich top layer. The desired graphene layer is formed by the carbon atoms left at the interface with the metal rich top layer. The thickness of the graphene layer is controlled by the thickness of the metal carbide layer and by solid phase reactions. | 2011-02-10 |
20110034012 | PATTERNING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a patterning method is disclosed. The method includes applying an uncured imprint material containing a first curing agent and a second curing agent onto a substrate. The method includes pressing a template against the imprint material. The method includes reacting the first curing agent with the template pressed against the imprint material. The method includes stripping the template from the imprint material. In addition, the method includes reacting the second curing agent. | 2011-02-10 |
20110034013 | Low Temperature Ion Implantation - A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs. | 2011-02-10 |
20110034014 | COLD IMPLANT FOR OPTIMIZED SILICIDE FORMATION - A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained. | 2011-02-10 |
20110034015 | HEAT TREATMENT APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a heat treatment apparatus includes a light emitting unit to emit light to irradiate a wafer, a processing unit with a stage section and a control unit. The control unit implements a first irradiation to irradiate the light onto the wafer. After the first irradiation, the control unit changes at least one selected from a disposition of the wafer, a distribution of an intensity of the light on a major surface of the stage section along a circumferential edge direction of the wafer, and a distribution of a temperature of the wafer in a supplemental heating by the stage section along a circumferential edge direction of the wafer. After the changing, the control unit implements a second irradiation to irradiate the light onto the wafer. Durations of the first irradiation and the second irradiation are shorter than a time necessary for the changing. | 2011-02-10 |
20110034016 | METHOD OF MANUFACTURING A CMOS DEVICE WITH ZERO SOFT ERROR RATE - A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device. | 2011-02-10 |
20110034017 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs. | 2011-02-10 |
20110034018 | DIODE ASSEMBLY - A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode. | 2011-02-10 |
20110034019 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 2011-02-10 |
20110034020 | METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS - Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure. | 2011-02-10 |