06th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090032865 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A second electrode is electrically connected to a second zone of the semiconductor body. Furthermore, the semiconductor body has a drift path region, which is arranged in the semiconductor body between the first electrode and the second electrode. A cell region of the semiconductor component is subdivided into a main cell region and an auxiliary cell region, wherein the breakdown voltage of the auxiliary cells is greater than the breakdown voltage of the main cells. | 2009-02-05 |
20090032866 | METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FIN STRUCTURES - Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 2009-02-05 |
20090032867 | DMOS TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A DMOS type semiconductor device and a method for manufacturing the same are provided. An isolation oxide layer with an ion implantation opening is formed on a semiconductor. A gate oxide film is formed on the semiconductor within the ion implantation opening. A gate is formed on the isolation oxide layer and the gate oxide film. A body layer diffusively formed in the semiconductor by implanting ions of an impurity element having a first conduction type from the ion implantation opening. A regulation layer which is shallower than the body layer is diffusively formed in the body layer by implanting ions of an impurity element having a second conduction type opposite to the first conduction type from the ion implantation opening. A source layer is diffusively formed in the regulation layer by implanting ions of an impurity element having the second conduction type from the ion implantation opening. The regulation layer is formed so as to horizontally extend beyond a region in which a gate bird's beak occurs from an end of the gate toward underlying layers of the gate. | 2009-02-05 |
20090032868 | HIGH PERFORMANCE POWER MOS STRUCTURE - A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer. | 2009-02-05 |
20090032869 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator. | 2009-02-05 |
20090032870 | Semiconductor device and method for manufacturing same - A semiconductor device comprising a field effect transistor having higher breakdown voltage by reducing electric field concentration between the drain region and a gate electrode is provided. A semiconductor device includes, on a silicon substrate, an n-well source region and an n-well drain region, which are formed over a surface layer thereof to be spaced apart from each other; and a gate electrode provided via a gate insulating film, said gate insulating film being formed to extend over said source region and said drain region. Further, LOCOS oxide film | 2009-02-05 |
20090032871 | INTEGRATED CIRCUIT WITH INTERCONNECTED FRONTSIDE CONTACT AND BACKSIDE CONTACT - An integrated circuit includes a substrate including an active area, a first metal contact contacting a frontside of the active area, a second metal contact contacting a backside of the active area, and a wafer-level deposited metal structure positioned adjacent to an edge of the active area and interconnecting the first and second contacts. | 2009-02-05 |
20090032872 | MULTIPLE OXIDE THICKNESS FOR A SEMICONDUCTOR DEVICE - Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin. | 2009-02-05 |
20090032873 | Ultra thin single crystalline semiconductor TFT and process for making same - Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor single crystal semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing a cleaved surface of the exfoliation layer; subjecting the cleaved surface of the exfoliation layer to a dry etching process to produce a single crystal semiconductor layer of about 5-20 nm thickness; and forming a thin film transistor in the thin semiconductor layer. | 2009-02-05 |
20090032874 | METHOD FOR INTEGRATING SILICON-ON-NOTHING DEVICES WITH STANDARD CMOS DEVICES - A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit. | 2009-02-05 |
20090032875 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode. | 2009-02-05 |
20090032876 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 2009-02-05 |
20090032877 | METHOD OF ENHANCING DRIVE CURRENT IN A TRANSISTOR - A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing. | 2009-02-05 |
20090032878 | Semiconductor device and fabrication method thereof - A semiconductor device comprises a first gate electrode formed on a first region of a semiconductor substrate, a first impurity layer formed at least below both ends of the first gate electrode in the first region, a first side wall formed on both side surfaces of the first gate electrode, and a second impurity layer formed on both sides of the first side wall as viewed from the first gate electrode in the first region. The first impurity layer includes a first-conductivity type first impurity and a first-conductivity type second impurity having a larger mass number than that of the first impurity. | 2009-02-05 |
20090032879 | NITRIDE-BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped Al | 2009-02-05 |
20090032880 | METHOD AND APPARATUS FOR TUNABLE ISOTROPIC RECESS ETCHING OF SILICON MATERIALS - Methods and apparatuses to etch recesses in a silicon substrate having an isotropic character to undercut a transistor in preparation for a source/drain regrowth. In one embodiment, a cap layer of a first thickness is deposited over a transistor gate stack and spacer structure. The cap layer is then selectively etched in a first region of the substrate, such as a p-MOS region, using a first isotropic plasma etch process and a second anisotropic plasma etch process. In another embodiment, an at least partially isotropic plasma recess etch is performed to provide a recess adjacent to the channel region of the transistor. In a particular embodiment, the plasma etch process provides a recess sidewall that is neither positively sloped nor more than 10 nm re-entrant. | 2009-02-05 |
20090032881 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME IN WHICH A MOBILITY CHANGE OF THE MAJOR CARRIER IS INDUCED THROUGH STRESS APPLIED TO THE CHANNEL - A semiconductor device includes a semiconductor substrate, a gate structure formed on the semiconductor substrate, wherein the gate structure includes a gate electrode formed on the semiconductor substrate and spacers formed on sidewalls of the gate electrode, source/drain regions formed in the semiconductor substrate on both sides of the gate structure, and an etch stop layer, which is formed on the gate structure, and includes a first region formed on the spacers and a second region formed on the gate electrode, wherein the thickness of the first region is about 85% that of the thickness of the second region or less. | 2009-02-05 |
20090032882 | SEMICONDUCTOR DEVICE HAVING INSULATED GATE FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURING THE SAME - N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers. | 2009-02-05 |
20090032883 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which comprises one or more metal-insulator-semiconductor field effect transistors (MISFETs), each including: a gate insulating film composed of a silicon oxide film, a first hafnium-containing nitrided silicate film, and a second hafnium-containing nitrided silicate film which are sequentially deposited on a substrate; and a gate structure having an electrode consisting of a metal silicide deposited on the gate insulating film. The first hafnium-containing nitrided silicate film has a hafnium concentration in a range from 5 to 10% and has a nitrogen concentration in a range from 5 to 10%. The second hafnium-containing nitrided silicate film has a hafnium concentration in a range from 50 to 60% and has a nitrogen concentration in a range from 20 to 45%. The gate insulating film has a thickness in a range from 1.8 to 3.0 nm. | 2009-02-05 |
20090032884 | Semiconductor device, and method for manufacturing the same - According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi | 2009-02-05 |
20090032885 | Buried Isolation Layer - The present disclosed integrated circuit includes a substrate having a top surface, a buried N type layer in the substrate, N type contact region extending from the surface to the buried N type region, a buried P type region abutting and above the buried N type region in the substrate, a P type contact region extending from the surface to the buried P type region, and an N type device region in the surface and above the buried P type region. The P type impurity of the buried P type region including an impurity of a lower coefficient of diffusion than the coefficient of diffusion of the impurities of the P type contact region. | 2009-02-05 |
20090032886 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 2009-02-05 |
20090032887 | TRANSISTOR HAVING GATE ELECTRODE WITH CONTROLLED WORK FUNCTION AND MEMORY DEVICE HAVING THE SAME - A transistor includes a gate insulation layer over a substrate, a gate line comprising electrodes each having a different work function on the gate insulation layer, and a source junction and a drain junction formed inside portions of the substrate on first and second sides of the gate line. | 2009-02-05 |
20090032888 | SEMICONDUCTOR DEVICE - A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process. | 2009-02-05 |
20090032889 | FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE - The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge. | 2009-02-05 |
20090032890 | MULTILAYER DIELECTRIC - An apparatus and method relating to a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer and having a second lesser concentration of defects are disclosed. | 2009-02-05 |
20090032891 | STRUCTURE OF MAGNETIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A structure of magnetic random access memory includes a magnetic memory cell formed on a substrate. An insulating layer covers over the substrate and the magnetic memory cell. A write current line is in the insulating layer and above the magnetic memory cell. A magnetic cladding layer surrounds the periphery of the write current line. The magnetic cladding layer includes a first region surrounding the top of the write current line, and a second region surrounding the side edge of the write current line, and extending towards the magnetic memory cell and exceed by a distance. | 2009-02-05 |
20090032892 | Image TFT array of a direct X-ray image sensor and method of fabricating the same - A method of fabricating an image TFT array of a direct X-ray image sensor includes forming a first transparent conductive layer on a substrate; forming a gate line including a gate electrode, a common line, and a common electrode jutting out from the common line; forming an insulation layer; forming a semiconducting island on the insulation layer in the transistor region; forming a first via hole for the common electrode; forming a data line and a source electrode and a drain electrode; forming a passivation layer and a second via hole penetrating the passivation layer for the source electrode; forming a second transparent conductive layer as a top electrode. The insulation layer is formed on the first transparent conductive layer to serve as a dielectric layer of a capacitor before the TFT structure formed and can be formed at a relatively high temperature. | 2009-02-05 |
20090032893 | Image sensor package and fabrication method thereof - An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via hole therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to the first substrate, so that the driving circuit, formed on the first substrate, can electrically connect to and further control the photosensitive device, formed on the second substrate. A solder ball is formed on a backside of the first substrate and electrically connects to the via hole for transmitting a signal from the driving circuit. Because the photosensitive device and the driving circuit are fabricated individually on the different substrates, fabrication and design thereof is more flexible. Moreover, the image sensor package is relatively less thick, thus, the dimensions thereof are reduced. | 2009-02-05 |
20090032894 | Flip-Chip Photodiode - A photodiode is provided according to various embodiments. In some embodiments, the photodiode includes a substrate and an active region. The active region is configured to receive light through the substrate. In such a configuration, the substrate not only participates in the photodiode operation acts as a light filter depending on the substrate material. In some embodiments, the active region may include solder balls that may be used to couple the photodiode to a printed circuit board. In some embodiments, the active region is coupled face-to-face with the printed circuit board. | 2009-02-05 |
20090032895 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. The image sensor comprises at least one unit pixel, an interlayer dielectric, a color filter, a planarization layer, and a microlens. The microlens has a smooth surface after performing a plasma treatment process. | 2009-02-05 |
20090032896 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed on the base layer. A thickness of the emitter layer is equal to or less than an absorption length of the incident light in the semiconductor substrate. | 2009-02-05 |
20090032897 | Semiconductor Device and Method for Its Manufacture - In semiconductor devices and methods for their manufacture, the semiconductor devices are arranged as a trench-Schottky-barrier-Schottky diode having a pn diode as a clamping element (TSBS-pn), and having additional properties compared to usual TSBS elements which make possible adaptation of the electrical properties. The TSBS-pn diodes are produced using special manufacturing methods, are arranged in their physical properties such that they are suitable for use in a rectifier for a motor vehicle generator, and are also able to be operated as Z diodes. | 2009-02-05 |
20090032898 | Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same - A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo. | 2009-02-05 |
20090032899 | Integrated circuit design based on scan design technology - An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal. | 2009-02-05 |
20090032900 | METHOD OF PROTECTING SHALLOW TRENCH ISOLATION STRUCTURE AND COMPOSITE STRUCTURE RESULTING FROM THE SAME - A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and a second process after the first process. The method includes forming a silicon nitride layer in the recess along the profile of the same during the second process. | 2009-02-05 |
20090032901 | Method of curing hydrogen silsesquioxane and densification in nano-scale trenches - Trenches in a semiconductor substrate are filled by (i) dispensing a film forming material on the semiconductor substrate and into the trenches; (ii) curing the dispensed film forming material in the presence of an oxidant at a first low temperature for a first predetermined period of time; (iii) curing the dispensed film forming material in the presence of an oxidant at a second low temperature for a second predetermined period of time; (iv) curing the dispensed film forming material in the presence of an oxidant at a third high temperature for a third predetermined period of time; and (v) forming filled oxide trenches in the semiconductor substrate. The film forming material is hydrogen silsesquioxane. | 2009-02-05 |
20090032902 | Semiconductor Devices and Methods for Manufacturing the Same - Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat into a furnace and thermally treating the boat under an oxygen atmosphere. | 2009-02-05 |
20090032903 | MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR - An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (V | 2009-02-05 |
20090032904 | ORIENTATION-INDEPENDENT MULTI-LAYER BEOL CAPACITOR - A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal. | 2009-02-05 |
20090032905 | Electronic Devices Including Electrode Walls with Insulating Layers Thereon - An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer. | 2009-02-05 |
20090032906 | ELECTRO STATIC DISCHARGE DEVICE AND METHOD FOR MANUFACTURING AN ELECTRO STATIC DISCHARGE DEVICE - An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type. The third semiconductor region is isolated from the first semiconductor region by the second semiconductor region. A resistor structure is arranged in the semiconductor body and comprises at least one trench structure. The resistor structure is arranged at least in the second semiconductor region and provides a high-resistance electrical connection between a first portion and a second portion of the second semiconductor region. | 2009-02-05 |
20090032907 | Method for Producing GaxIn1-xN(0<x>) Crystal Gaxin1-xn(0<x<1) Crystalline Substrate, Method for Producing GaN Crystal, GaN Crystalline Substrate, and Product - It seems that a conventional method for producing a GaN crystal by using HVPE has a possibility that the crystallinity of a GaN crystal can be improved by producing a GaN crystal at a temperature higher than 1100° C. However, such a conventional method has a problem in that a quartz reaction tube ( | 2009-02-05 |
20090032908 | Semiconductor device and method of manufacturing it - A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value. | 2009-02-05 |
20090032909 | SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS - Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. | 2009-02-05 |
20090032910 | DIELECTRIC STACK CONTAINING LANTHANUM AND HAFNIUM - Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. | 2009-02-05 |
20090032911 | PATTERNED THIN SOI - A process for treating a structure to prepare it for electronics or optoelectronics applications. The structure includes a bulk substrate, an oxide layer, and a semiconductor layer, and the process includes providing a masking to define on the semiconductor layer a desired pattern, and applying a thermal treatment for removing a controlled thickness of oxide in the regions of the oxide layer corresponding to the desired pattern to assist in preparing the structure. | 2009-02-05 |
20090032912 | Semiconductor component with buffer layer - A semiconductor component having at least one pn junction and an associated production method. The semiconductor component has a layer sequence of a first zone having a first dopant. The first zone faces a first main area. Adjacent to the first zone are a second zone having a low concentration of a second dopant, a subsequent buffer layer, the third zone, also having the second dopant and a subsequent fourth zone having a high concentration of the second dopant. The fourth zone faces a second main area. In this case, the concentration of the second doping of the buffer layer is higher at the first interface of the barrier layer with the second zone than at the second interface with the fourth zone. According to the invention, the buffer layer is produced by ion implantation. | 2009-02-05 |
20090032913 | Component and assemblies with ends offset downwardly - A stackable microelectronic component includes a dielectric layer having an attachment portion. The dielectric layer has a first side, a second side, and outer ends lying outwardly of the attachment portion. The outer ends are offset from the attachment portion. A semiconductor chip is assembled to the second side of the dielectric layer at the attachment portion. First terminal structures are carried by the outer ends of the dielectric layer for connecting the semiconductor chip with external circuitry located above the first side of the dielectric layer. Second terminal structures are carried by the outer ends of the dielectric layer for connecting the semiconductor chip with external circuitry located below the second side of the dielectric layer. | 2009-02-05 |
20090032914 | THREE-DIMENSIONAL PACKAGE MODULE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING PASSIVE DEVICE APPLIED TO THE THREE-DIMENSIONAL PACKAGE MODULE - Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer. | 2009-02-05 |
20090032915 | TFCC (TM) & SWCC (TM) thermal flex contact carriers - Two groups of interconnection devices and methods are described. Both provide columns between electronic packages and boards or between chips and substrates or the like. In the first group, called Thermal Flex Contact Carrier (TFCC), the column elements are carved out of a flat laminated structure and then formed to suit. In the second group, the carrier, which carries the connecting elements, is made out of a soluble or removable material, which acts at the same time, as a solder mask, to prevent the solder from wicking along the stem of the elements. | 2009-02-05 |
20090032916 | SEMICONDUCTOR PACKAGE APPARATUS - A semiconductor package apparatus and a method of fabricating the semiconductor package apparatus. The semiconductor package apparatus includes: semiconductor chips comprising active and inactive surfaces and protected by a packing portion; a substrate on which the semiconductor chips are installed; leads comprising front portions electrically coupled to the active surfaces of the semiconductor chips and rear portions extending substantially to the substrate; and bonding materials bonded between ends of the rear portions of the leads and the substrate to electrically couple the leads to the substrate. Ends of the rear portions of the leads may stand on the substrate. Thus, solder joint reliability can be improved, and a wetting characteristic of solder can be improved during surface installation. Also, semiconductor package apparatuses having similar attributes can easily be multilayered. In addition, a foot print of the semiconductor package apparatus can be reduced to enable high-density installation. Moreover, shapes of the bonding materials (solder) can be controlled to optimize bonding strength of the leads, quantity of the bonding materials, or the like. | 2009-02-05 |
20090032917 | Lead frame package apparatus and method - The present disclosure relates to a lead frame package comprising a die attach pad and two or more electrical interconnections, wherein at least one of the two or more interconnections is affixed to the die attach pad for electrically grounding the lead frame package. The present disclosure further relates to a method for providing a lead frame package. The lead frame package comprises two or more electrical interconnections and a die attach pad. At least one electrical interconnection is affixed to the die attach pad to ground the lead frame package and at least one of the electrical interconnections is an RF signal interconnection. At least one of the die attach pad and the at least one grounding electrical interconnection is connected to a grounding contact of a circuit-board. The at least one RF signal electrical interconnection is connected to an RF signal contact on the circuit-board, thereby forming a mounted semi-conductor circuit. | 2009-02-05 |
20090032918 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICES - An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle. | 2009-02-05 |
20090032919 | Semiconductor device and lead frame - A semiconductor device which can surely prevent a wire bonded to an island from breaking due to, for instance, thermal shock and temperature cycle upon mounting. The semiconductor device includes a semiconductor chip; an island die bonded with the semiconductor chip on the surface; and a wire for electrically connecting the electrode formed on the surface of the semiconductor chip with the island. The semiconductor device is further characterized in that the island has a die bonding region where the semiconductor chip is die bonded, a wire bonding region where the wire is wire bonded, and a continuous groove reaching a circumference of the island are formed between the die bonding region and the wire bonding region of the island. | 2009-02-05 |
20090032920 | LASER RELEASE PROCESS FOR VERY THIN SI-CARRIER BUILD - A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided. | 2009-02-05 |
20090032921 | PRINTED WIRING BOARD STRUCTURE AND ELECTRONIC APPARATUS - According to one embodiment, a printed wiring board structure includes first and second semiconductor packages each including a substrate, and a printed wiring board including first and second component mounting surfaces having a relationship given as front and back surfaces and an inter-chip connection part provided at one portion thereof, the inter-chip connection part being provided with a plurality of arrayed through conductors penetrating through the first and second component mounting surfaces, wherein the substrates of the first and second semiconductor packages are arranged on the printed wiring board in a positional relationship such that the substrates mounted on the component mounting surfaces are partially overlapped via the printed wiring board, the external connection electrodes provided on the substrates are arrayed on the overlapped portion and are conductively connected to the through conductors arrayed in the inter-chip connection part. | 2009-02-05 |
20090032922 | Semiconductor Package, Printed Wiring Board Structure and Electronic Apparatus - According to one embodiment, a semiconductor package comprises a substrate having one surface mounted with a semiconductor chip, and the other surface mounted with a plurality of arrayed external connection electrodes, a differential line pair provided on the surface of the substrate mounted with the semiconductor chip, and making a connection between the semiconductor chip and a predetermined pair of electrodes included in the external connection electrodes, and a coupling capacitor pair inserted between the differential lines. | 2009-02-05 |
20090032923 | METHOD AND APPARATUS FOR STACKING ELECTRICAL COMPONENTS USING VIA TO PROVIDE INTERCONNECTION - An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces. | 2009-02-05 |
20090032924 | HERMETICALLY SEALED PACKAGE WITH WINDOW - A method for manufacturing a cover assembly including a transparent window portion and a frame of gas-impervious material that can be hermetically attached to a micro-device package base to form a hermetically sealed micro-device package. First a frame of gas-impervious material is provided the frame having a continuous sidewall defining a frame aperture there through. The sidewall includes a frame seal-ring area circumscribing the frame aperture. A sheet of a transparent material is also provided, the sheet having a window portion defined thereupon. The window portion has finished top and bottom surfaces. A sheet seal-ring area is prepared on the sheet, the sheet seal-ring area circumscribing the window portion. The frame is positioned against the sheet such that at least a portion of the frame seal-ring area and at least a portion of the sheet seal-ring area contact one another along a continuous junction region that circumscribes the window portion. The frame is pressed against the sheet with sufficient force to produce a predetermined contact pressure between the frame seal-ring area and the sheet seal-ring area along the junction region. The junction region is heated to produce a predetermined temperature along the junction region. The predetermined contact pressure and the predetermined temperature are maintained until a diffusion bond is formed between the frame and sheet all along the junction region. | 2009-02-05 |
20090032925 | PACKAGING WITH A CONNECTION STRUCTURE - In a package including an image sensor die with an interconnect extending therethrough, a cover allowing light to pass is coupled to the die using at least one solder ball and a corresponding number of pads on each of the cover and die. Such pads are added to the cover despite the die's interconnect allowing contact with external devices at a location distal from the cover. The solder balls help govern the parallel orientation (or an alternate orientation) between the die and the cover. In addition, connectors other than solder balls may be used; multi-layered covers with connectors between the layers may be used; and packages other than imagers may be assembled. | 2009-02-05 |
20090032926 | Integrated Support Structure for Stacked Semiconductors With Overhang - The present disclosure relates to an integrated circuit packaging, a strip having a plurality of integrated circuit packages, and method of manufacture thereof, and more particularly, to a substrate having an integrated overhang support structure to support a ledge created by stacking a large circuit die on a small circuit die. In one embodiment, the upper substrate surface comprises a protrusion as an integrated support structure. The structure may include passages to direct the flow of underfill into the limited support area to create an open area for vacuum or for placement of passive or active components. | 2009-02-05 |
20090032927 | SEMICONDUCTOR SUBSTRATES CONNECTED WITH A BALL GRID ARRAY - A stacked module has an upper semiconductor package that includes a substrate having opposed first and second surfaces. A cavity defined in the second surface receives at least a portion of a semiconductor mounted on the substrate of a lower semiconductor package. A plurality of solder bumps disposed between the first and second packages connect the two substrates. | 2009-02-05 |
20090032928 | Multi-chip stack structure having through silicon via and method for fabrication the same - The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier. | 2009-02-05 |
20090032929 | SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP - Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate. | 2009-02-05 |
20090032930 | PACKAGING SUBSTRATE HAVING CHIP EMBEDDED THEREIN AND MANUFACTURING METHOD THEREOF - A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed. | 2009-02-05 |
20090032931 | Power semiconductor module with connecting devices - A power semiconductor module having a housing with first connecting devices for arrangement on an external cooling component, at least one substrate carrier with power-electronics circuit arrangements constructed thereon and electrical terminal elements extending therefrom to second connecting devices for connection to external power lines, wherein the first and/or the second connecting devices are constructed as essentially hollow cylindrical metallic molded die-cast parts which are connected to the housing by injection molding. | 2009-02-05 |
20090032932 | INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES - An integrated circuit packaging system comprising: forming a substrate including; patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof. | 2009-02-05 |
20090032933 | REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE - Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board. | 2009-02-05 |
20090032934 | POTENTIAL-FREE HOUSING LEADTHROUGH - The invention relates to a circuit arrangement with an electronic circuit on a printed circuit board and an electrically screening housing surrounding the circuit board, wherein there are on said circuit board a HF plug-and-socket connector connected to the electronic circuit with an outer conductor part and an inner conductor part, wherein the HF plug-and-socket connector penetrates through an opening in the housing. The outer conductor part of the HF plug-and-socket connector is electrically isolated from the housing, and wherein a tunnel-like screening sleeve surrounds the outer conductor part both axially and circumferentially at least partially, the sleeve being connected electrically to the housing and capacitively to the outer conductor part of the HF plug-and-socket connector. | 2009-02-05 |
20090032935 | Semiconductor device - Embodiments of a semiconductor device are disclosed. | 2009-02-05 |
20090032936 | SEMICONDUCTOR DEVICE, METHOD FOR THE SAME, AND HEAT RADIATOR - A semiconductor device includes a semiconductor chip, and a multicomponent alloy layer formed on a face of the semiconductor chip, the multicomponent alloy layer being in a solid-liquid coexisting state in a specific temperature range, and including a surface having concavity and convexity caused by solidification segregation. | 2009-02-05 |
20090032937 | COOLING SYSTEMS FOR POWER SEMICONDUCTOR DEVICES - A cooling device is provided for liquid cooling a power semiconductor device. The device includes a coolant diverter for guiding liquid coolant to the power semiconductor device. The coolant diverter has a first plate for dividing the coolant diverter into a first cavity and a second cavity. The second cavity positioned adjacent the power semiconductor device. The first plate further includes an opening to fluidly couple the first cavity with the second cavity such that the liquid coolant flows into the first cavity, through the opening in the first plate, and into the second cavity to cool the power semiconductor device. The first cavity has a cross-sectional area that generally decreases in a downstream direction, and the second cavity has a cross-sectional area that generally increases in the downstream direction. | 2009-02-05 |
20090032938 | Electronic Package With Direct Cooling Of Active Electronic Components - A cooling assembly includes a package with one or more dies cooled by direct cooling. The cooled package includes one or more dies with active electronic components. A coolant port allows a coolant to enter the package and directly cool the active electronic components of the dies. | 2009-02-05 |
20090032939 | METHOD OF FORMING A STUD BUMP OVER PASSIVATION, AND RELATED DEVICE - A method of forming a stud bump over passivation, and related device. At least some of the illustrative embodiments are methods comprising depositing a first passivation layer over a semiconductor die, depositing a capping metal layer over the first passivation layer (the capping metal layer comprises a capping metal pad), and depositing a stud bump onto the capping metal pad. | 2009-02-05 |
20090032940 | Conductor Bump Method and Apparatus - Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer. | 2009-02-05 |
20090032941 | Under Bump Routing Layer Method and Apparatus - Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second site electrically connected to a second redistribution layer structure. A solder structure is formed on the conductor structure. | 2009-02-05 |
20090032942 | SEMICONDUCTOR CHIP WITH SOLDER BUMP AND METHOD OF FABRICATING THE SAME - A semiconductor chip having a solder bump and a method of fabricating the same are provided. The semiconductor chip includes at least one under bump metal (UBM) layer formed on an electrode pad of the semiconductor chip, an adhesion enhance layer (AEL) formed on the UBM layer and having at least one concavo-convex portion on a top surface thereof, and the solder bump formed on the AEL. Thereby, adhesive solder bump is increased, and thereby the reliability of the semiconductor chip can be improved. Further, it is possible to prevent tin (Sn) in the solder bump from being diffused due to the AEL. | 2009-02-05 |
20090032943 | SUBSTRATE, SUBSTRATE FABRICATION, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE FABRICATION - A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface. | 2009-02-05 |
20090032944 | ELECTRONIC DEVICE, METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE - A semiconductor device includes n | 2009-02-05 |
20090032945 | SOLDER BUMP ON A SEMICONDUCTOR SUBSTRATE - A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer. | 2009-02-05 |
20090032946 | INTEGRATED CIRCUIT - Integrated circuits and methods for making integrated circuits having a base layer, a side substrate, a circuit substrate and a connection. A bottom face of the base layer is disposed on the side substrate. The side substrate includes a first contact field, at least a second contact field, and a signal line. The first contact field is arranged on the bottom face in an area of an opening of the base layer, the second contact field is arranged on another face of the side substrate, and the signal line connects the first contact field to the second contact field. The circuit substrate is disposed on the base layer and alongside the side substrate. The connection connects the circuit substrate to the second contact field of the side substrate. | 2009-02-05 |
20090032947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device has a semiconductor die having at least one bond pad formed on a first surface thereof. A substrate has at least one bond finger formed on a first surface thereof. A second surface of the semiconductor die is attached to the first surface of the substrate. A conductive wire connects the bond pad of the semiconductor die and the bond finger of the substrate wherein at least one end of the conductive wire has a stack bump. An encapsulant is provided to encapsulate the semiconductor die and the conductive wire. | 2009-02-05 |
20090032948 | SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR DESIGNING THE SAME - A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array. | 2009-02-05 |
20090032949 | Method of depositing Tungsten using plasma-treated tungsten nitride - Devices structures utilizing, and methods of forming, tungsten interconnects in semiconductor fabrication are disclosed. Tungsten deposition is accomplished by a three-step process that does not require a resistive nucleation material to be deposited prior to bulk tungsten deposition. By treating a tungsten nitride material with a hydrogen plasma, thereby reducing the tungsten nitride to tungsten, the necessity of a resistive nucleation layer is eliminated. Other embodiments describe methods of tungsten deposition requiring a thinner resistive nucleation material (<10 angstroms) than currently known. | 2009-02-05 |
20090032950 | FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, PROGRAM AND RECORDING MEDIUM - An adhesion between a Cu diffusion barrier film and a Cu wiring in a semiconductor device is improved and reliability of the semiconductor device is improved. A film forming method for forming a Cu film on a substrate to be processed is provided with a first process of forming an adhesion film on the Cu diffusion barrier film formed on the substrate to be processed, and a second process of forming a Cu film on the adhesion film. The adhesion film includes Pd. | 2009-02-05 |
20090032951 | Small Area, Robust Silicon Via Structure and Process - A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via. | 2009-02-05 |
20090032952 | TANTALUM AMIDO-COMPLEXES WITH CHELATE LIGANDS USEFUL FOR CVD AND ALD OF TaN AND Ta205 THIN FILMS - Tantalum compounds of Formula I hereof are disclosed, having utility as precursors for forming tantalum-containing films such as barrier layers. The tantalum compounds of Formula I may be deposited by CVD or ALD for forming semiconductor device structures including a dielectric layer, a barrier layer on the dielectric layer, and a copper metallization on the barrier layer, wherein the barrier layer includes a Ta-containing layer and sufficient carbon so that the Ta-containing layer is amorphous. According to one embodiment, the semiconductor device structure is fabricated by depositing the Ta-containing barrier layer, via CVD or ALD, from a precursor including the tantalum compound of Formula I hereof at a temperature below about 400° C. in a reducing or inert atmosphere, e.g., a gas or plasma optionally containing a reducing agent. | 2009-02-05 |
20090032953 | Semiconductor device and method of manufacturing the same - A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of the lower electrode, and an upper electrode opposed to the lower electrode with the capacitor film sandwiched therebetween. | 2009-02-05 |
20090032954 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first insulation film having a plurality of openings which exposes predetermined regions of a semiconductor substrate, a plurality of first conductive patterns partially filling the openings and a plurality of second conductive patterns disposed on the first conductive patterns within the openings and separated from inner walls of the openings. | 2009-02-05 |
20090032955 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD AND DISPLAY APPARATUS - A semiconductor device including n, where notation n denotes a positive integer at least equal to three, conductive layers created as stacked layers on a substrate and connected to each other through a contact pattern, a manufacturing method thereof and a display apparatus thereof are provided. | 2009-02-05 |
20090032956 | DUMMY METAL FILL SHAPES FOR IMPROVED RELIABILITY OF HYBRID OXIDE/LOW-K DIELECTRICS - A semiconductor structure including a first rigid dielectric layer and a second rigid dielectric layer. A first non-rigid low-k dielectric layer is formed between the first and second rigid dielectric layer. A plurality of dummy fill shapes is formed in the first non-rigid layer which replace portions of the first non-rigid low-k dielectric layer with lower coefficient of thermal expansion (CTE) metal such that an overall CTE of the first non-rigid low-k dielectric layer and the plurality of dummy fill shapes matches a CTE of the first and second rigid dielectric layers more closely than that of the first non-rigid low-k dielectric layer alone. | 2009-02-05 |
20090032957 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a lower structure, an insulation layer, metal contacts, a bridge and a metal pad. The lower structure has a metal wiring. An insulation layer is formed on the lower structure. The metal contacts penetrate the insulation layer to be connected to the metal wiring. The bridge is provided in the insulation layer, the bridge connecting the metal contacts to one another. The metal pad is provided on the insulation layer, the metal pad making contact with the metal contacts. | 2009-02-05 |
20090032958 | Intermetallic conductors - Intermetallic conductive materials are used to form interconnects in an integrated circuit. In some cases, the intermetallic conductive material may be an intermetallic alloy of aluminum. | 2009-02-05 |
20090032959 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 2009-02-05 |
20090032960 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed. | 2009-02-05 |
20090032961 | SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE - By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment, an electroless deposition process may provide the alloy-forming species on the exposed metal region on the basis of an electroless plating process. | 2009-02-05 |
20090032962 | CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION - The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component. | 2009-02-05 |
20090032963 | SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS AND METHODS TO FORM SAME - Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines. | 2009-02-05 |
20090032964 | System and method for providing semiconductor device features using a protective layer - Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises disposing a protective layer over the first side of the substrate, removing a portion of the protective layer over at least a portion of the opening to provide access to the hole, and filling at least a portion of the hole with a fill material. | 2009-02-05 |