05th week of 2011 patent applcation highlights part 13 |
Patent application number | Title | Published |
20110024811 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a pad insulating layer on a semiconductor substrate, forming a recess by etching the pad insulating layer and the semiconductor substrate, forming a buried gate buried in the recess, forming an insulating layer for defining a bit line contact hole over the buried gate and the pad insulating layer, forming a bit line over a bit line contact for filling the bit line contact hole, and forming a storage electrode contact hole by etching the insulating layer and the pad insulating layer to expose the semiconductor substrate. As a result, the method increases the size of an overlap area between a storage electrode contact and an active region without an additional mask process, resulting in a reduction in cell resistance. | 2011-02-03 |
20110024812 | RESONANT BODY TRANSISTOR AND OSCILLATOR - A resonator body has an inversion gate, an accumulation gate, and a center region. The resonator body also has a source contact coupled to the center region and a drain contact coupled to the center region. The resonator body further has a first dielectric layer coupled between the inversion gate and the center region. The resonator body also has a second dielectric layer coupled between the accumulation gate and the center region. A resonant body transistor is also disclosed. The resonant body transistor has an inversion gate electrode, an accumulation gate electrode, a source electrode, a drain electrode, and a plurality of anchor beams. The resonant body transistor also has a resonator body coupled-to and suspended-from the inversion gate electrode, the accumulation gate electrode, the source electrode, and the drain electrode by the plurality of anchor beams. A resonant body oscillator is also disclosed. | 2011-02-03 |
20110024813 | MOS CAPACITOR STRUCTURES - Methods and apparatus are described for MOS capacitors (MOS CAPs). The apparatus comprises a substrate having Ohmically coupled N and P semiconductor regions covered by a dielectric. A conductive electrode overlies the dielectric above these N and P regions. Use of the Ohmically coupled N and P regions substantially reduces the variation of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions have unequal doping, the capacitance variation may still be substantially compensated by adjusting the properties of the dielectric above the N and P regions and/or relative areas of the N and P regions or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP. | 2011-02-03 |
20110024814 | Semiconductor Device - The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged. | 2011-02-03 |
20110024815 | SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor apparatus including a buried gate removes factors deteriorating the operational reliability of the semiconductor device such as the electrical connection between a contact and a word line, and increases a processing margin when forming the contact disposed on a source/drain region. The method includes forming a recess in a semiconductor substrate, forming a gate in a lower portion of the recess, forming a first insulation layer over the gate, growing silicon over the first insulation layer in the recess, and depositing a second insulation layer over the semiconductor substrate and in the remaining portion of the recess. | 2011-02-03 |
20110024816 | FLASH MEMORY DEVICE HAVING VERTICLE CHANNEL STRUCTURE - A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region. | 2011-02-03 |
20110024817 | FLASH MEMORY DEVICE AND MASK FOR FABRICATING THE SAME - A flash memory device includes an active region, drain contacts, a source contact line, and source contacts. The active regions are formed on a substrate extend at least from a source region to a drain region of the substrate. The drain contacts are formed over the active regions in the drain region. The source contact line is formed in the source region of the semiconductor substrate. The source contact line intersects the active regions and is continuously line-shaped. The source contact line includes source contacts formed at locations where the source contact line and the active regions intersect. The source contacts are zigzag-shaped and are separated from corresponding drain contacts by a given distance. | 2011-02-03 |
20110024818 | VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench. | 2011-02-03 |
20110024819 | HIGH QUALITY GATE DIELECTRIC FOR SEMICONDUCTOR DEVICES AND METHOD OF FORMATION THEREOF - Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown Q | 2011-02-03 |
20110024820 | METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film. | 2011-02-03 |
20110024821 | PUSH-PULL FPGA CELL - A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate. | 2011-02-03 |
20110024822 | ISOLATION REGIONS - A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is removed substantially concurrently from the first and second trenches to expose substantially all of the dielectric liner within the second trench and to form a plug of the material in the one or more first trenches. A second layer of dielectric material is formed substantially concurrently on the plug in the first trench and on the exposed portion of the dielectric liner in the second trench. The second layer of dielectric material substantially fills a portion of the first trench above the plug and the second trench. | 2011-02-03 |
20110024823 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween. | 2011-02-03 |
20110024824 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion; | 2011-02-03 |
20110024825 | SEMICONDUCTOR MEMORY - A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction. | 2011-02-03 |
20110024826 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other. | 2011-02-03 |
20110024827 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer. | 2011-02-03 |
20110024828 | SEMICONDUCTOR STORAGE DEVICE - An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other. | 2011-02-03 |
20110024829 | SEMICONDUCTOR DEVICE HAVING VOIDS ALONG BURIED GATES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having voids along buried gates and a method of manufacturing the same is presented. The semiconductor device includes recesses, a first gate electrode, a second gate electrode, and a gate protection layer. The first gate electrode fills in a lower portion of the recess. The second gate electrode is formed on the first gate electrode and partially fills in the upper portion of the recess such that the second gate electrode has a downwardly tapered width. The gate protection layer fills in the remaining portion of the recess while leaving voids next to the second gate electrode. Accordingly, it is thought that the voids reduce gate resistance and improve the gate-induced drain leakage (GIDL) characteristics of the resultant device. | 2011-02-03 |
20110024830 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate. | 2011-02-03 |
20110024831 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (A | 2011-02-03 |
20110024832 | Semiconductor apparatus and manufacturing method thereof - A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions. | 2011-02-03 |
20110024833 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region. | 2011-02-03 |
20110024834 | Semiconductor Devices Including Electrodes with Integrated Resistances and Related Methods - A semiconductor device may include an insulating layer and a semiconductor electrode on the insulating layer. An area of increased electrical resistance may separate a contact area of the semiconductor electrode from an active area of the semiconductor electrode. In addition, a metal contact may be provided on the contact area of the semiconductor electrode opposite the insulating layer. | 2011-02-03 |
20110024835 | HIGH FREQUENCY FIELD-EFFECT TRANSISTOR - The invention relates to a field-effect transistor having a higher efficiency than the known field-effect transistors, in particular at higher operating frequencies. This is achieved by electrically connecting sources of a plurality of main current paths by means of a strap line (SL) being inductively coupled to a gate line (Gtl) and/or a drain line (Drnl) for forming an additional RF-return current path parallel to the RF-return current path in a semiconductor body (SB). The invention further relates to a field-effect transistor package, a power amplifier, a multi-stage power amplifier and a base station comprising such a field-effect transistor. | 2011-02-03 |
20110024836 | Field Effect Transistor With Trench-Isolated Drain - A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a heavily doped source contact diffusion region formed in the source region, a lightly doped drain region of the second conductivity type formed in the body region where the lightly doped drain region is a drift region of the MOS transistor, a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region; and an insulating trench formed in the lightly doped drain region adjacent the drain contact diffusion region. The insulating trench blocks a surface current path in the drift region thereby forming vertical current paths in the drift region around the bottom surface of the trench. | 2011-02-03 |
20110024837 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate formed over a substrate, a junction region formed in the substrate at both sides of the gate, and a depletion region expansion prevention layer surrounding sidewalls of the junction region in the substrate. | 2011-02-03 |
20110024838 | SEMICONDUCTOR DEVICE - There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer. | 2011-02-03 |
20110024839 | Lateral DMOS Field Effect Transistor with Reduced Threshold Voltage and Self-Aligned Drift Region - A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor. | 2011-02-03 |
20110024840 | SOI TRANSISTORS HAVING AN EMBEDDED EXTENSION REGION TO IMPROVE EXTENSION RESISTANCE AND CHANNEL STRAIN CHARACTERISTICS - A silicon-on-insulator (SOI) transistor device includes a buried insulator layer formed over a bulk substrate; an SOI layer formed on the buried insulator layer; and a pair of silicon containing epitaxial regions disposed adjacent opposing sides of a gate conductor, the epitaxial regions corresponding to source and drain regions of the transistor device; wherein portions of the epitaxial regions are embedded in the buried insulator and are in contact with both vertical and bottom surfaces of the SOI layer corresponding to source and drain extension regions at opposing ends of a channel region of the transistor device. | 2011-02-03 |
20110024841 | MOSFET WITH ASYMMETRICAL EXTENSION IMPLANT - A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure. | 2011-02-03 |
20110024842 | PROCEDURE FOR THE USE OF NATURAL CELLULOSIC MATERIAL, SYNTHETIC MATERIAL OR MIXED NATURAL AND SYNTHETIC MATERIAL, SIMULTANEOUSLY AS PHYSICAL AND DIELECTRIC SUPPORT IN SELF-SUSTAINABLE FIELD EFFECT ELECTRONIC AND OPTOELECTRONIC DEVICES - The present invention refers to the use and creation of natural cellulosic material, synthetic or mixed material and corresponding production process to be used simultaneously as physical and dielectric support in the creation of new field-effect electronic or optoelectronic devices, designated C-MOS structured electronic devices, designated interstrate, wherein its functionality depends on the capacity per unit area of the paper depending on how the fibers thereof are distributed, the fibers being coated by an active ionic or covalent semiconductor and allowing the production of flexible self-sustainable devices, disposable devices, based on the new integrated interstrate concept, of monolithic or hybrid types. | 2011-02-03 |
20110024843 | Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device includes a latch circuit which includes a first node for keeping a first potential corresponding to a data, and a second node for keeping a second potential corresponding to the same data, a diffusion layer continuously formed between the first node and the second node, and a transistor provided on the diffusion layer to isolate the first node from the second node. | 2011-02-03 |
20110024844 | SRAM CELL AND SRAM DEVICE - An SRAM cell comprising a first to fourth semiconductor thin plates standing on a single substrate and sequentially arranged parallel to each other, on the first semiconductor thin plate a first four-terminal double gate FET with a first conduction type and a second four-terminal double gate FET with a second conduction type being formed and connected in series to each other, on the second semiconductor thin plate a third four-terminal double gate FET with the second conduction type being formed, on the third semiconductor thin plate a fourth four-terminal double gate FET with the second conduction type is formed, on the fourth semiconductor thin plate a fifth four-terminal double gate FET with the first conduction type and a sixth four-terminal double gate FET with the second conduction type being formed and connected in series to each other. The second and sixth four-terminal double gate FETs constitute select transistors with logic signal input gates thereof being connected to a word line. The first and third four-terminal double gate FETs and the fourth and the fifth four-terminal double gate FETs respectively constitute cross-coupled complementary inverters to realize a flip-flop. The SRAM cell is characterized in that the first four-terminal double gate FET and the third four-terminal double gate FET are neighboring with each other and logic signal input gates thereof are formed on the side surfaces facing to each other of the respective semiconductor thin plates; the fourth four-terminal double gate FET and the fifth four-terminal double gate FET are neighboring with each other and logic input gates thereof are formed on the side surfaces facing to each other of the respective semiconductor thin plates; the third four-terminal double gate FET and the fourth four-terminal double gate FET are neighboring with each other and a threshold voltage control gates thereof are formed on the side surfaces facing to each other of the respective semiconductor thin plates; the second four-terminal double gate FET and the sixth four-terminal double gate FET are neighboring with each other sandwiching the second and third semiconductor thin plates and threshold voltage control gates thereof being formed on side surfaces facing to each other of the respective semiconductor thin plate; the threshold voltage control gates of the second, third, fourth, and sixth four-terminal double gate FETs are connected in common to a first bias wiring; threshold voltage control gates of the first and fifth four-terminal double gate FETs are connected in common to a second bias wiring; and the word line and the first and second bias wirings are arranged in a direction perpendicular to the alignment direction of the first to the fourth semiconductor thin plates. | 2011-02-03 |
20110024845 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first-conductivity-type-channel MOSFET formed on a semiconductor substrate, wherein the first-conductivity-type-channel MOSFET is typically a P-channel MOSFET, and is composed of a gate insulating film and a gate electrode provided over the semiconductor substrate, the gate electrode contains a metal gate electrode provided over the gate insulating film, a metal oxide film provided over the metal gate electrode, and another metal gate electrode provided over metal oxide film. | 2011-02-03 |
20110024846 | LEAKAGE CONTROL IN FIELD EFFECT TRANSISTORS BASED ON AN IMPLANTATION SPECIES INTRODUCED LOCALLY AT THE STI EDGE - In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region. | 2011-02-03 |
20110024847 | SEMICONDUCTOR DEVICE - There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. | 2011-02-03 |
20110024848 | METHODS AND DEVICES FOR SHIELDING A SIGNAL LINE OVER AN ACTIVE REGION - A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line. | 2011-02-03 |
20110024849 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate; an element isolation insulating film embedded in the vicinity of a front surface of the semiconductor substrate; a through plug penetrating the semiconductor substrate from a back surface to the front surface so as to penetrate through the element isolation insulating film, and having a multi-stage structure comprising an upper stage portion and a lower stage portion, the upper stage portion having a region surrounded by the element isolation insulating film in the semiconductor substrate, the lower stage portion having a diameter larger than that of the upper stage portion; and a contact plug connected to an end portion of the through plug on the frond surface side of the semiconductor substrate for connecting a conductive member formed above the front surface side of the semiconductor substrate to the through plug. | 2011-02-03 |
20110024850 | MICRO ELECTRONIC DEVICE AND METHOD FOR FABRICATING MICRO ELECTROMECHANICAL SYSTEM RESONATOR THEREOF - A method for fabricating a MEMS resonator is provided. A stacked main body including a silicon substrate, a plurality of metallic layers and an isolation layer is formed and has a first etching channel extending from the metallic layers into the silicon substrate. The isolation layer is filled in the first etching channel. The stacked main body also has a predetermined suspended portion. Subsequently, a portion of the isolation layer is removed so that a second etching channel is formed and the remained portion of the isolation layer covers an inner sidewall of the first etching channel. Afterwards, employing the isolation layer that covers the inner sidewall of the first etching channel as a mask, an isotropic etching process through the second etching channel is applied to the silicon substrate, thereby forming the MEMS resonator suspending above the silicon substrate. The method for fabricating MEMS resonator can be integrated with the process of fabricating the CMOS circuit, thereby the process of fabricating a microelectronic device can be simplified and the cost of fabricating a micro electronic device can be reduced. A micro electronic device is also provided in the present invention. | 2011-02-03 |
20110024851 | MICRO-ELECTROMECHANICAL SYSTEM MICROPHONE STRUCTURE - A method of fabricating a micro-electromechanical system microphone structure is disclosed. First, a substrate defining a MEMS region and a logic region is provided, and a surface of the substrate has a dielectric layer thereon. Next, at least one metal interconnect layer is formed on the dielectric layer in the logic region, and at least one micro-machined metal mesh is simultaneously formed in the dielectric layer of the MEMS region. Therefore, the thickness of the MEMS microphone structure can be effectively reduced. | 2011-02-03 |
20110024852 | MEMS DEVICE AND MEMS SPRING ELEMENT - A micro electromechanical system (MEMS) spring element is disposed on a substrate, and includes a fixing portion and a moveable portion. The fixing portion is fixed on the substrate, and includes an insulating layer, a plurality of metal-fixing layers and a plurality of supporting-fixing layers. The insulating layer is disposed on the substrate. The metal-fixing layers are disposed above the insulating layer. The supporting-fixing layers are connected between the metal-fixing layers. The moveable portion has a first end and a second end. The first end is connected with the fixing portion, and the second end is suspended above the substrate. The moveable portion includes a plurality of metal layers and at least a supporting layer. The supporting layer is connected between the adjacent metal layers, and a hollow region is formed between the supporting layer and the adjacent metal layers. The deformation of the MEMS spring element generated because of the different thermal expansion may be avoided and the working performance of the MEMS spring element can be improved. | 2011-02-03 |
20110024853 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together. | 2011-02-03 |
20110024854 | SOLID-STATE IMAGE SENSING DEVICE CONTAINING ELECTRON MULTIPLICATION FUNCTION - A solid state imaging device includes a P-type semiconductor substrate | 2011-02-03 |
20110024855 | PHOTODETECTOR - An infrared detector ( | 2011-02-03 |
20110024856 | COLUMNATED BACKSIDE ILLUMINATION METHOD AND STRUCTURE - Imager devices, systems including the imager devices and methods of forming the imager devices are provided. The imager device has a substrate with first and second opposing sides. The imager also includes an array of imager pixels at the first side of the substrate, each including a photoconversion device. An antireflective material is on the second side of the substrate and a dielectric material is over the antireflective material. A light guide material is disposed within a plurality of openings in the dielectric material and optically aligned with a respective photoconversion device. | 2011-02-03 |
20110024857 | SOLID-STATE IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS USING THE SAME - Disclosed herein is a solid-state image pickup element, including: a semiconductor substrate; a pixel portion which is formed on the semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion portion are arranged; an insulating layer formed on the semiconductor substrate so as to cover the photoelectric conversion portion; a hole portion formed in the insulating layer and above the photoelectric conversion portion; a silicon nitride layer formed so as to cover a bottom surface and a side surface of the hole portion; and a buried layer formed on the silicon nitride layer, wherein the silicon nitride layer is formed so as to contain a silicon nitride formed by utilizing an atomic layer deposition method. | 2011-02-03 |
20110024858 | SOLID-STATE IMAGING DEVICE AND METHOD FOR PRODUCING THE SAME - A solid-state imaging device includes a first substrate including a light-sensing portion configured to perform photoelectric conversion of incident light and a wiring portion provided on a light-incident side; an optically transparent second substrate provided on a wiring portion side of the first substrate at a certain distance; a through-hole provided in the first substrate; a through-via provided in the through-hole; a front-surface-side electrode connected to the through-via and provided on a front surface of the first substrate; a back-surface-side electrode connected to the through-via and provided on a back surface of the first substrate; and a stopper electrode provided on the front-surface-side electrode and filling a space between the front-surface-side electrode and the second substrate. | 2011-02-03 |
20110024859 | PHOTOELECTRIC CONVERSION DEVICE, FABRICATION METHOD FOR THE SAME, AND SOLID STATE IMAGING DEVICE - A photoelectric conversion device has a high S/N ratio and can increase the detection efficiency even under a low luminance. The photoelectric conversion device generates an increased electric charge by impact ionization in a photoelectric conversion unit formed from a chalcopyrite type semiconductor, so as to improve dark current characteristic. The photoelectric conversion device includes: a lower electrode layer; a compound semiconductor thin film of chalcopyrite structure disposed on the lower electrode layer and having a high resistivity layer on a surface; and a transparent electrode layer disposed on the compound semiconductor thin film, wherein the lower electrode layer, the compound semiconductor thin film, and the transparent electrode layer are laminated one after another, and a reverse bias voltage is applied between the transparent electrode layer and the lower electrode layer, and the multiplication by the impact ionization of the electric charge generated by photoelectric conversion is generated within the compound semiconductor thin film. It is also possible to provide a fabrication method for such photoelectric conversion device, and a solid state imaging device using the photoelectric conversion device. | 2011-02-03 |
20110024860 | Device For The Detection Of Electromagnetic Waves And Method For Producing Such A Device - Device for the detection of electromagnetic waves with
| 2011-02-03 |
20110024861 | MANUFACTURING METHOD FOR MOLDING IMAGE SENSOR PACKAGE STRUCTURE AND IMAGE SENSOR PACKAGE STRUCTURE THEREOF - A manufacturing method for molding an image sensor package structure and the image sensor package structure thereof are disclosed. The manufacturing method includes following steps of providing a half-finished image sensor for packaging, arranging a dam on the peripheral of a transparent lid of the half-finished image sensor, positioning the half-finished image sensor within a mold, and injecting a mold compound into the mold cavity of the mold. The dam is arranged on the top surface of the transparent lid and the inner surface of the mold can exactly contact with the top surface of dam so that the mold compound injected into the mold cavity is prevented from overflowing to the transparent lid by the dam. Furthermore, the arrangement of the dam and the mold compound can increase packaged areas and extend blockage to invasive moisture so as to enhance the reliability of the image sensor package structure. | 2011-02-03 |
20110024862 | IMAGE SENSOR PACKAGE STRUCTURE WITH LARGE AIR CAVITY - The present invention discloses an image sensor package structure with a large air cavity. The image sensor package structure includes a substrate, a chip, a cover and a package material. The chip is combined with the substrate. A plastic sheet of the cover is adhered to the chip and a transparent lid of the cover is combined with the plastic sheet to provide a covering over a sensitization area of the chip so as to form an air cavity. The package material is arranged on the substrate and encapsulated around the chip and the cover. The plastic sheet having a predetermined thickness can increase the distance between the transparent lid and the chip to enlarge the air cavity. Thus, the image-sensing effect of the image sensor package structure can be improved and the ghost image problem resulting from multi-refraction and multi-reflection of light can be minimized. | 2011-02-03 |
20110024863 | Mesa photodiode and method for manufacturing the same - A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D | 2011-02-03 |
20110024864 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a through electrode penetrating a semiconductor substrate, a conductor pad formed on the through electrode and made of a conductor electrically connected to the through electrode, and an interconnection layer formed on a surface of the semiconductor substrate and electrically connected to the conductor pad. | 2011-02-03 |
20110024865 | SEMICONDUCTOR LIGHT RECEIVING DEVICE - According to an exemplary aspect of the present invention, at least a semiconductor mesa and a semiconductor layer covering at least the side wall of the mesa and a semiconductor mesa are formed on an n-type semiconductor substrate. The semiconductor mesa includes at least a light absorption layer and a p-type contact layer. The principal surface of the semiconductor substrate tilts at an angle θ to the (100) plane. The angle θ is 0.1 degree≦|θ|≦10 degrees. | 2011-02-03 |
20110024866 | CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AICu PROCESS - An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension. | 2011-02-03 |
20110024867 | CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AlCu PROCESS - An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension. | 2011-02-03 |
20110024868 | METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications. | 2011-02-03 |
20110024869 | DESIGN METHOD, DESIGN PROGRAM AND DESIGN SUPPORT DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A design method for a semiconductor integrated circuit, includes : a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area. | 2011-02-03 |
20110024870 | LAYOUT FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - The invention relates to a semiconductor device and its layout, which allows a larger number of capacitors within the same area to increase the cell density, which enables to get a larger number of semiconductor chips out of one wafer, and which retains a sufficient gap between bit lines to prevent SAC failure of the storage node, and to a method of fabricating the semiconductor device. In a layout for a semiconductor device including active regions, device isolation films for defining the active regions, bit lines and word lines, and a method of fabricating the semiconductor device of the invention, each active region comprises a first active region, a right active region located on the right side of the first active region, a left active region located on the left side of the first active region, an upper active region located on the upper side of the first active region and a lower active region located on the lower side of the first active region, wherein the first active region, the right active region, the left active region, the upper active region and the lower active region respectively include an inclined portion having a bit-line contact region; and first and second portions having a storage node contact region, the first end and the second end being respectively formed on the left and right ends of the inclined portion at a predetermined tilt angle with respect to the inclined portion, the active region having two word lines and one bit line intersecting one another. | 2011-02-03 |
20110024871 | SEMICONDUCTOR STRUCTURE - A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well as a first undercut and a second undercut on opposite sides of the shallow trench isolation. Later, the first deep trench and the second deep trench are partially filled with Si. Afterwards, the first deep trench and the second deep trench are filled with an isolation material to form the isolation structure. | 2011-02-03 |
20110024872 | FUSE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A fuse of a semiconductor device includes first fuse metals formed over an underlying structure and a second fuse metal formed between the first fuse metals. Accordingly, upon blowing, the fuse metals are not migrated under conditions, such as specific temperature and specific humidity. Thus, reliability of a semiconductor device can be improved. | 2011-02-03 |
20110024873 | SEMICONDUCTOR DEVICE HAVING A FUSE REGION AND METHOD FOR FORMING THE SAME - A semiconductor device having a fuse region, the fuse region includes a conductive pattern and a fuse box formed to partially expose the conductive pattern which have an inclined edge on a bottom surface. | 2011-02-03 |
20110024874 | SEMICONDUCTOR DEVICE HAVING A 3D CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a three-dimensional capacitor and a method for manufacturing the same is presented. The semiconductor device may have lower electrodes, a buffer layer, a dielectric layer, and an upper electrode. The lower electrodes are formed over a semiconductor substrate. The buffer layer is formed on sidewalls of the lower electrodes. The dielectric layer and an upper electrode are formed over semiconductor substrate including over the lower electrodes and the buffer layer. Accordingly, sufficient space between the lower electrodes can be secured. Furthermore, the lower electrodes can be each formed of a ruthenium layer and a titanium nitride layer and configured to have a pillar form. The dielectric layer may be composed of titanium dioxide. | 2011-02-03 |
20110024875 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND SUBSTRATE PROCESSING APPARATUS - A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming an amorphous first insulating film comprising a first element on a substrate; adding a second element different from the first element to the first insulating film so as to form an amorphous second insulating film on the substrate; and annealing the second insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second insulating film. The concentration of the second element added to the first insulating film is controlled according to the annealing temperature. | 2011-02-03 |
20110024876 | CREATION OF THIN GROUP II-VI MONOCRYSTALLINE LAYERS BY ION CUTTING TECHNIQUES - Expungement ions, preferably including hydrogen ions, are implanted into a face of a first, preferably silicon, substrate such that there will be a maximum concentration of the expungement ions at a predetermined depth from the face. Subsequently a monocrystalline Group II-VI semiconductor layer, or two or more such layers, is/are grown on the face, as by means of molecular beam epitaxy. After this a second, preselected substrate is attached to an upper face of the Group II-VI layer(s). Next, the implanted expungement ions are used to expunge most of the first substrate from a remnant thereof, from the grown II-VI layer, and from the second substrate. In another embodiment, a group II-VI layer is grown on a first substrate silicon and an ionic implantation is conducted such that a maximum concentration of expungement ions occurs either in the silicon substrate at a predetermined depth from its interface with the II-VI layer or in the first Group II-VI semiconductor layer at a predetermined depth from the top face of the Group II-VI semiconductor layer. Thereafter all of the first substrate is expunged from the rest of the workpiece. Thin monocrystalline Group II-VI semiconductor structures may thus be mounted to substrates of the fabricator's choice; these substrates may be semiconductors, integrated circuits, MEMS structures, polymeric, metal or glass, may be flexible and may be curved. | 2011-02-03 |
20110024877 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A structure including a substrate, an intermediate layer provided and formed directly onto the substrate, a transition region, and a group II-VI bulk crystal material provided and formed as an extension of the transition region. The transition region acts to change the structure from the underlying substrate to that of the bulk crystal. In a method of manufacture, a similar technique can be used for growing the transition region and the bulk crystal layer. | 2011-02-03 |
20110024878 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor substrate and a method for manufacturing the same. The semiconductor substrate includes a substrate, a discontinuously formed hemispheric metal layer on the substrate, and a semiconductor layer on the hemispheric metal layer. A plurality of voids on the interface of the substrate and discontinuous hemisphere are formed to absorb or relax the stain of interface. Accordingly, even if a subsequent layer is relatively thickly formed on the substrate, substrate bow or warpage can be minimized. | 2011-02-03 |
20110024879 | METHOD TO REDUCE PRE-ALIGNMENT ERROR USING MULTI-NOTCH PATTERN OR IN COMBINATION WITH FLAT SIDE - A semiconductor wafer has a pre-alignment pattern including two or more notches on the wafer edge and the notches are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches are different. In another embodiment, distances along the wafer edge between any adjacent notches are each different. In another aspect, the pre-alignment pattern includes one or more notches on the wafer edge and one flat side on the wafer edge, wherein the notches and the flat side are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches or between the flat side and an adjacent notch are different. In another embodiment, distances along the wafer edge between any adjacent notches and between the flat side and an adjacent notch are each different. | 2011-02-03 |
20110024880 | NANO-PATTERNED SUBSTRATE AND EPITAXIAL STRUCTURE - A nano-patterned substrate includes a plurality of nano-particles or nanopillars on an upper surface thereof. A ratio of height to diameter of each of the nano-particles or each of the nanopillars is either greater than or equal to 1. Particularly, a ratio of height to diameter of the nanopillars is greater than or equal to 5. Each of the nano-particles or each of the nanopillars has an arc-shaped top surface. When an epitaxial growth process is applied onto the nano-patterned substrate to form an epitaxial layer, the epitaxial layer has very low defect density. Thus, a production yield of fabricating the subsequent device can be improved. | 2011-02-03 |
20110024881 | SEMICONDUCTOR DEVICE HAVING UNDER-FILLED DIE IN A DIE STACK - A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N. | 2011-02-03 |
20110024882 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region. | 2011-02-03 |
20110024883 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME - To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part. | 2011-02-03 |
20110024884 | Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors - A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level. | 2011-02-03 |
20110024885 | METHOD FOR MAKING SEMICONDUCTOR CHIPS HAVING COATED PORTIONS - A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads. | 2011-02-03 |
20110024886 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 2011-02-03 |
20110024887 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA BASE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base having a through-conductor spanning the height of the base, and having an insulator protecting the base and the through-conductor; mounting a chip over the base and connected to the base with a first interconnect; forming a second interconnect above the base and horizontally beside the chip; and encapsulating the chip, the first interconnect, and the second interconnect with an encapsulation. | 2011-02-03 |
20110024888 | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP - A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die. | 2011-02-03 |
20110024889 | PACKAGE ARCHITECTURE - A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit. | 2011-02-03 |
20110024890 | Stackable Package By Using Internal Stacking Modules - A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate. | 2011-02-03 |
20110024891 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY EDGE COATING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package. | 2011-02-03 |
20110024892 | THERMALLY ENHANCED HEAT SPREADER FOR FLIP CHIP PACKAGING - A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber. | 2011-02-03 |
20110024893 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a stacked semiconductor package and a method for manufacturing the same. The method for manufacturing a stacked semiconductor package includes preparing a substrate formed with a seed metal layer; laminating semiconductor chips having via holes aligned with one another on the seed metal layer to form a semiconductor chip module; and growing a conductive layer inside of the via holes using the seed metal layer to form a conductive growth layer inside of the via holes. | 2011-02-03 |
20110024894 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip. | 2011-02-03 |
20110024895 | Semiconductor Package Thermal Performance Enhancement and Method - A semiconductor device package and related method are disclosed for providing a semiconductor device encapsulated in a protective package body. The device has an exposed surface to which a thermal compound is applied for improving a thermal path for the egress of heat from the device. Preferred embodiments are disclosed in which a removable cover is attached to the thermal compound for further improved protection during handling. | 2011-02-03 |
20110024896 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device that can reduce the mounting area thereof will be provided. A first metal plate is connected to a first power terminal of a power chip. A second metal plate facing the first metal plate is connected to a second power terminal of the power chip. An insulating cover coats the power chip from outside of the first and second metal plates. An exterior signal terminal connected to the signal terminal of the power chip is derived from an upper surface of the insulating cover. The first and second metal plate respectively includes first and second exterior electric power terminals derived from a lower surface of the insulating cover. The first and second exterior electric power terminals are bent to opposite directions. In a bending direction of the first exterior electric power terminal or the second exterior electric power terminal, the second exterior electric power terminal is not present on opposite side of the first exterior electric power terminal across the insulating cover, and the first exterior electric power terminal is not present on opposite side of the second exterior electric power terminal across the insulating cover. | 2011-02-03 |
20110024897 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS - Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package. | 2011-02-03 |
20110024898 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 2011-02-03 |
20110024899 | SUBSTRATE STRUCTURE FOR CAVITY PACKAGE - Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure. | 2011-02-03 |
20110024900 | SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM - A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region. | 2011-02-03 |
20110024901 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed. | 2011-02-03 |
20110024902 | STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP - A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required. | 2011-02-03 |
20110024903 | Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring - A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive through hole vias (THV) are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV. | 2011-02-03 |
20110024904 | SEMICONDUCTOR PACKAGE, PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a wiring board; a first electrode for external connection; a ball pad; a semiconductor chip; a mold resin; an electrode unit connected with the ball pad and penetrating the mold resin; and a second electrode for external connection connected with a portion of the electrode unit on a side of an outer surface of the mold resin. The electrode unit includes a first ball disposed on the ball pad; a second ball disposed between the first ball and the second electrode; and a solder material connecting between the ball pad and the first ball, between the first ball and the second ball, and between the second ball and the second electrode for external connection; each of the first ball and the second ball including a core part having a glass transition temperature which is higher than a melting point of the solder material. | 2011-02-03 |
20110024905 | STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP - A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required. | 2011-02-03 |
20110024906 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element. | 2011-02-03 |
20110024907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique capable of improving the reliability on electric properties of a semiconductor device by devising the shape of the upper surface of a plug. A plug of the present invention has an upwardly convex dome-like shape in which the upper surface thereof projects from the surface (upper surface) of a contact interlayer insulating film. That is, the plug has the upper surface of an upwardly convex dome-like shape, wherein the height of the top edge portion of a barrier conductive film is larger than that of the upper surface of the contact interlayer insulating film, and the height of the top edge portion of a tungsten film is larger than that of the top edge portion of the barrier conductive film. | 2011-02-03 |
20110024908 | LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE - The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer. | 2011-02-03 |
20110024909 | BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures. | 2011-02-03 |
20110024910 | METALLURGY FOR COPPER PLATED WAFERS - Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer. An electrically insulating protective layer overlies the first aluminum metallization layer and the top wafer fabrication passivation layer. The protective layer is preferably formed from an organic material and includes a plurality of contact openings. Underbump metallization stacks are formed in the contact openings. Each underbump metallization stack is electrically connected to the first aluminum metallization layer through its associated contact opening in the protective layer. Solder bumps are preferably then adhered to the underbump metallization stacks. | 2011-02-03 |