05th week of 2012 patent applcation highlights part 17 |
Patent application number | Title | Published |
20120025236 | LIGHT EMITTING DIODE SUBSTRATE, METHOD OF MAKING SAME AND LIGHT EMPLOYING SAME - An LED light source ( | 2012-02-02 |
20120025237 | LIGHT EMITTING DIODE STRUTURE - A light emitting diode structure includes an electrically conductive substrate, a first lighting structure having a first n-type semiconductor layer, a first active layer and a first p-type semiconductor layer and a second lighting structure having a second n-type semiconductor layer, a second active layer and a second p-type semiconductor layer. The first n-type semiconductor layer is electrically connected with the second p-type semiconductor layer and the first p-type semiconductor layer is electrically connected with the second n-type semiconductor layer. A first transparent, conductive layer is formed on the first lighting structure and a second transparent, conductive layer is formed on the second lighting structure. The first transparent, conductive layer and the second transparent, conductive layer are connected together to combine the first lighting structure with the second lighting structure. | 2012-02-02 |
20120025238 | LED PACKAGE - An LED package comprises a substrate, an LED die, and an encapsulating layer. The substrate has circuit formed thereon. The LED die is arranged on the substrate and electrically connected to the circuit of the substrate. The encapsulating layer covers the LED die and at least a part of the substrate. The encapsulating layer and the substrate are made of cycloaliphatic epoxide. | 2012-02-02 |
20120025239 | NANOCOMPOSITES AND LIGHT EMITTING DEVICE PACKAGE INCLUDING THE SAME - Provided are nanocomposites and a light emitting device package including the same. The nanocomposites include nanoparticles, and silicon compounds bonded to surfaces of the nanoparticles and expressed by a specific chemical formula. The nanocomposites can be dispersed evenly in various matrices without the nanoparticles being agglutinated. | 2012-02-02 |
20120025240 | PACKAGE OF LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a package of light emitting device includes the following steps: providing a light emitting element and positioning the light emitting element at a bottom of a reflecting cup; providing phosphors and a compound of epoxy resin and silicone, and mixing the phosphors and the compound of epoxy resin and silicone to obtain a mixture by a process of kneading; and encapsulating the light emitting element with the mixture to form an encapsulant received in the reflecting cup. | 2012-02-02 |
20120025241 | SURFACE MOUNTED LED PACKAGING STRUCTURE AND METHOD BASED ON A SILICON SUBSTRATE - A surface mounted LED packaging structure based on a silicon substrate includes the silicon substrate, an LED chip, an annular convex wall and a lens. The silicon substrate has an upper surface of planar structure and without grooves. An oxide layer covers the upper surface of the silicon substrate. Metal electrode layers are arranged in the upper surface of the oxide layer, and the upper surfaces of the metal electrode layers are arranged with metal bumps. Vias through the silicon substrate are provided under the metal electrode layers. An insulating layer covers the inner wall of the vias and a part of the lower surface of the silicon substrate. A metal connection layer covers the insulating layer surface within the vias. Two conductive metal pads are respectively arranged under the lower surface of the silicon substrate and insulated from the silicon substrate. A heat conduction metal pad is arranged on the lower surface of the silicon substrate. The LED chip is flip-chip mounted on the silicon substrate. The annular convex wall and the lens cause the LED chip and the metal electrode layers therein to be isolated from environment. The structure of the present invention has its advantages of good heat dissipation effect and small volume, while packaging without gold wires makes the structure highly reliable and achieves large-scale production of wafer level, resulting in the reduction of the packaging cost. | 2012-02-02 |
20120025242 | SURFACE MOUNTED LED STRUCTURE AND PACKAGING METHOD OF INTEGRATING FUNCTIONAL CIRCUITS ON A SILICON - The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip. Peripheral functional circuits required by LED are integrated on the upper surface of said silicon substrate. The structure of the present invention has advantages of good heat dissipation effect and small volume, and direct integration of functional circuits such as protection and drive circuits etc. in the silicon substrate achieves large-scale production package of wafer level, reducing the cost of packaging and lighting fixture. | 2012-02-02 |
20120025243 | LED PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An LED package includes a substrate, an LED chip, a bounding dam, and a first encapsulation. The substrate includes a first surface and a second surface opposite to the first surface. The LED chip is mounted on the first surface of the substrate. The bounding dam is formed on the first surface of the substrate and surrounds the LED chip. The bounding dam and the substrate cooperatively define a receiving space. The bounding dam is made of thermoset resin. The first encapsulation is formed in the receiving space and encloses the LED chip. | 2012-02-02 |
20120025244 | LIGHT EMITTING DIODE HAVING DISTRIBUTED BRAGG REFLECTOR - Exemplary embodiments of the present invention provide light-emitting diodes having a distributed Bragg reflector. A light-emitting diode (LED) according to an exemplary embodiment includes a light-emitting structure arranged on a first surface of a substrate, the light-emitting structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. A first distributed Bragg reflector is arranged on a second surface of the substrate opposite to the first surface, the first distributed Bragg reflector to reflect light emitted from the light-emitting structure. The first distributed Bragg reflector has a reflectivity of at least 90% with respect to light of a first wavelength in a blue wavelength range, light of a second wavelength in a green wavelength range, and light of a third wavelength in a red wavelength range. The first distributed Bragg reflector has a laminate structure having an alternately stacked SiO | 2012-02-02 |
20120025245 | Substrate for electronic device and electronic device using same - Provided is an electronic device having a long life and a large effective area. Furthermore, provided is an optical device capable of controlling specular visibility. And provided is a substrate for the optical device, which includes a scattering layer having excellent scattering properties and having a desired refractive index while retaining surface smoothness. Further, there is provided a substrate for the electronic device, which includes a substrate having first and second main surfaces facing each other and an electrode pattern formed on the first main surface of the substrate, in which the first main surface of the first and second main surfaces is a surface which forms waviness made up of curved faces, the waviness of the surface has a wavelength Rλa of greater than 50 μm and a ratio Ra/Rλa of waviness roughness Ra of the surface which forms waviness to the wavelength Rλa of the waviness is from 1.0×10 | 2012-02-02 |
20120025246 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor light emitting device and a method of manufacturing the same. The method includes providing a substrate having first and second main surfaces opposing each other and forming a first uneven structure in the first main surface, forming a sacrificial layer on the first main surface of the substrate, forming a mask having open regions on the sacrificial layer so as to expose a portion of an upper surface of the sacrificial layer, forming a second uneven structure in the substrate by etching the sacrificial layer and the substrate through the open regions, removing the sacrificial layer and the mask from the substrate, and forming a light emitting stack on the first and second uneven structures of the substrate. | 2012-02-02 |
20120025247 | COMPONENT FOR LIGHT-EMITTING DEVICE, LIGHT-EMITTING DEVICE AND PRODUCING METHOD THEREOF - A component for a light-emitting device includes a sealing resin layer that is capable of sealing in a light emitting diode, a fluorescent layer that is formed on one face of the sealing resin layer and is capable of emitting fluorescent light, and a reflection layer that is provided on the other face of the sealing resin layer so as to avoid a region where the sealing resin layer seals in the light emitting diode and is capable of reflecting the light. | 2012-02-02 |
20120025248 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a semiconductor light emitting device. The semiconductor light emitting device includes a conductive substrate, a p-type electrode disposed on the conductive substrate, a transparent electrode layer disposed on the p-type electrode, a light emitting structure comprising a p-type semiconductor layer, an active layer, and an n-type semiconductor layer, which are sequentially stacked on the transparent electrode layer, and an n-type electrode disposed on the n-type semiconductor layer. The light emitting structure is disposed on a top middle of the transparent electrode layer to allow a side of the light emitting structure to be spaced from an edge of the transparent electrode layer. The transparent electrode layer has an uneven surface at an outer portion of the light emitting structure. | 2012-02-02 |
20120025249 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device and a light emitting device package. According to the light emitting device, a light emitting part and an electro-static discharge (ESD) protection part are disposed on a conductive support member. A connection layer electrically connects a first conducitve type semiconductor layer of the light emitting part to a second conductive type semiconductor layer of the ESD protection part. A ptrtection member is disposed on the connection layer and the ESD protection layer. | 2012-02-02 |
20120025250 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF - This application provides a semiconductor light-emitting device and the manufacturing method thereof. The semiconductor light-emitting device comprises a semiconductor light-emitting structure and a thinned substrate. The semiconductor light-emitting structure comprises a plurality of semiconductor layers and a plurality of first channels, wherein a plurality of first channels has a predetermined depth that penetrating at least two layers of the plurality of semiconductor layers. | 2012-02-02 |
20120025251 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a reflective electrode on a support; a first cladding layer; a light-emitting layer; a second cladding layer having a terrace structure formed of recesses and protrusions, a light-extracting structure having projections and depressions being formed on top surfaces of the protrusions and bottom surfaces of the recesses; and surface electrodes on the top surfaces of the protrusions. The second cladding layer has a stacked structure, which includes a first current-spreading layer, a first light-extracting layer on the first current-spreading layer and having the light-extracting structure on the bottom surfaces of the recesses, a second current-spreading layer on the first light-extracting layer, and a second light-extracting layer on the second current-spreading layer and having the light-extracting structure on the top surfaces of the protrusions, and the first and second light-extracting layer have lower light absorptance and higher resistance than the first and second current-spreading layer. | 2012-02-02 |
20120025252 | COMPOSITE SUBSTRATE FOR FORMATION OF LIGHT-EMITTING DEVICE, LIGHT-EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A composite substrate for the formation of a light-emitting device, ensuring that a high-quality nitride-based light-emitting diode can be easily formed on its top surface and the obtained substrate-attached light-emitting diode functions as a light-emitting device capable of emitting light for an arbitrary color such as white, is provided. A composite substrate for the formation of a light-emitting device, comprising a light-converting material substrate for radiating at least a part of incident light as light different in the wavelength through the surface opposite the incident surface, and at least two or more Al-containing nitride layers formed on the light-converting material substrate, wherein the light-converting material substrate has a texture comprising two or more oxide phases continuously and three-dimensionally entangled with each other, including an Al | 2012-02-02 |
20120025253 | ORGANIC LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE WITH THE ORGANIC LIGHT-EMITTING ELEMENT - The present invention provides a white organic light-emitting element high in the emission efficiency. In particular, the invention provides a white organic light-emitting element that has an emission spectrum having peaks in the respective wavelength regions of red color, green color and blue color and is high in the emission efficiency. | 2012-02-02 |
20120025254 | SEMICONDUCTOR LIGHT EMITTING DEVICE SUBSTRATE STRIPS AND PACKAGED SEMICONDUCTOR LIGHT EMITTING DEVICES - Semiconductor light emitting device packaging methods include fabricating a substrate configured to mount a semiconductor light emitting device thereon. The substrate may include a cavity configured to mount the semiconductor light emitting device therein. The semiconductor light emitting device is mounted on the substrate and electrically connected to a contact portion of the substrate. The substrate is liquid injection molded to form an optical element bonded to the substrate over the semiconductor light emitting device. Liquid injection molding may be preceded by applying a soft resin on the electrically connected semiconductor light emitting device in the cavity. Semiconductor light emitting device substrate strips are also provided. | 2012-02-02 |
20120025255 | PACKAGE FOR LIGHT EMITTING ELEMENT ACCOMMODATION CONTAINING ALUMINA AND BARIUM - [PROBLEMS] To provide a package for light emitting element accommodation that realizes enhanced reflectance without application of a metal plating onto a ceramic. [MEANS FOR SOLVING PROBLEMS] There is provided a package for light emitting element accommodation comprising ceramic substrate ( | 2012-02-02 |
20120025256 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND LIGHT-EMITTING APPARATUS INCLUDING THE SAME - A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency. | 2012-02-02 |
20120025257 | LED ASSEMBLY AND MANUFACTURING METHOD THEREOF - An LED assembly including a heat sink, a surface treatment dielectric layer, an electrically conductive layer, a thermally conductive layer and an LED chip. The surface treatment dielectric layer is disposed on an upper surface of the heat sink and defines at least one first through hole to expose a portion of the upper surface. The electrically conductive layer is formed on the surface treatment dielectric layer, includes a plurality of electrical traces and defines at least one second through hole corresponding to the first through hole. The thermally conductive layer is formed in the first and the second through holes and directly contacted with a portion of the upper surface exposed from the overlapped region of the first through hole and the second through hole. The LED chip includes a plurality of electrodes electrically connected to the electrical traces and is directly contacted with the thermally conductive layer. | 2012-02-02 |
20120025258 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE - An exemplary LED module includes a board and an LED package mounted on the plate. The LED package includes a base, an LED chip mounted on a top surface of the base, two electrodes formed on the base and electrically connected to the LED chip and the board, and an encapsulant encapsulating the LED chip. A plurality of grooves are defined in the bottom surface of the base. When the LED package is secured on the plate via solder paste, the grooves function as a container for receiving excessive solder paste, thereby preventing the solder paste from spilling and floating or inclination of the LED package. | 2012-02-02 |
20120025259 | ELECTRO-OPTIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electro-optic device ( | 2012-02-02 |
20120025260 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame, a first semiconductor element mounted on the lead frame, a frame-like member formed on the lead frame, surrounding the first semiconductor element, and a protective resin filling a space surrounded by the frame-like member. The lead frame has an external terminal protruding outside the frame-like member. The external terminal has a barrier portion which is located at an end portion thereof protruding from the frame-like member and rises from a top surface of the external terminal. | 2012-02-02 |
20120025261 | Method of minimizing field stop insulated gate bipolar transistor (IGBT) buffer and emitter charge variation - This invention discloses an insulated gate bipolar transistor (IGBT) formed in a semiconductor substrate. The IGBT comprises a buffer layer of a first conductivity type formed below an epitaxial layer of the first conductivity having body and source regions therein. The IGBT further includes a lowly doped substrate layer below the buffer layer and a dopant layer of a second conductivity type disposed below the lowly doped substrate layer and above a drain electrode of said IGBT attached to a bottom surface of said semiconductor substrate wherein the dopant layer of the second conductivity type has a higher dopant concentration than the lowly doped substrate layer. | 2012-02-02 |
20120025262 | MOS Type Semiconductor Device and Method of Manufacturing Same - An object of the present invention is to provide a MOS type semiconductor device allowing production at a low cost without lowering a breakdown voltage and avoiding increase of an ON resistance. A MOS type semiconductor device of the invention comprises: a p base region having a bottom part in a configuration with a finite radius of curvature and selectively disposed on a front surface region of a n | 2012-02-02 |
20120025263 | POWER SEMICONDUCTOR DEVICE - A plurality of cell structures of a vertical power device are formed at a semiconductor substrate. One cell structure included in the plurality of cell structures and located in a central portion CR of the main surface has a lower current carrying ability than the other cell structure included in the plurality of cell structures and located in an outer peripheral portion PR of the main surface. This provides a power semiconductor device having a long power cycle life. | 2012-02-02 |
20120025264 | SEMICONDUCTOR DEVICE HAVING DIODE-BUILT-IN IGBT AND SEMICONDUCTOR DEVICE HAVING DIODE-BUILT-IN DMOS - A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode. | 2012-02-02 |
20120025265 | PHOTODETECTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a photodetector structure is provided. The method includes forming a structural layer by making a trench in a bulk silicon substrate and filling the trench with a cladding material, forming a single-crystallized silicon layer on the structural layer, and forming a germanium layer on the single-crystallized silicon layer. | 2012-02-02 |
20120025266 | Transistors Comprising High-K Metal Gate Electrode Structures and Embedded Strain-Inducing Semiconductor Alloys Formed in a Late Stage - In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration. | 2012-02-02 |
20120025267 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 2012-02-02 |
20120025268 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor. | 2012-02-02 |
20120025269 | SEMICONDUCTOR STRUCTURE COMPRISING PILLAR - A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar. | 2012-02-02 |
20120025270 | ENHANCEMENT-MODE HIGH-ELECTRON-MOBILITY TRANSISTOR AND THE MANUFACTURING METHOD THEREOF - This invention discloses an enhancement-mode high-electron-mobility transistor and the manufacturing method thereof. The transistor comprises an epitaxial buffer layer on a substrate, a source and drain formed in the buffer layer, a PN-junction stack formed on the buffer layer and located between the source and drain, and a gate formed on the PN-junction stack, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor. | 2012-02-02 |
20120025271 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, METHOD OF JUDGING QUALITY OF SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor. | 2012-02-02 |
20120025272 | SEMICONDUCTOR INTEGRATED CIRCUIT CHIP AND LAYOUT METHOD FOR THE SAME - A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows×n columns from a corner of the chip above the corner portion. | 2012-02-02 |
20120025273 | ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE - A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells. | 2012-02-02 |
20120025274 | SOI SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side. | 2012-02-02 |
20120025275 | CCD SENSORS WITH MULTIPLE CONTACT PATTERNS - A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations. | 2012-02-02 |
20120025276 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING A PN JUNCTION BASED ON SILICON/GERMANIUM MATERIALS - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption. | 2012-02-02 |
20120025277 | MEASURING ELEMENT - A measuring element for recording a deflection includes a region which is situated on a semi-conductor substrate and an electrode for influencing a conductivity of the region, the electrode being mounted deflectably in relation to the region, in such a way that an overlap region is formed between the electrode and the region, the overlap region having a dimension that is variable with a deflection of the electrode. A change in the output signal of the measuring element is a function of the conductivity of the region and is controllable by a change in the dimension of the overlap region, the change in the dimension of the overlap region having a non-linear relationship with the deflection of the electrode so that a change in the output signal of the measuring element has a non-linear relationship with the deflection of the electrode. | 2012-02-02 |
20120025278 | SCHOTTKY DIODE - A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced. | 2012-02-02 |
20120025279 | LOW SCHOTTKY BARRIER SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A low Schottky barrier semiconductor structure is provided, comprising: a substrate; a SiGe layer with low Ge content formed on the substrate; a channel layer with high Ge content formed on the SiGe layer; a gate stack formed on the substrate and a side wall of one or more layers formed on both sides of the gate stack; a metal source and a metal drain formed in the channel layer and on the both sides of the gate stack respectively; and an insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively. | 2012-02-02 |
20120025280 | SOLID-STATE IMAGE SENSING DEVICE - A solid-state imaging device comprises a plurality of pixels that includes a photoelectric conversion portion, a charge-voltage converter that receives the charge and converts the charge to a voltage, an amplifier that outputs a signal corresponding to a potential of the charge-voltage converter, a transfer portion that transfers a charge from the photoelectric conversion portion to the charge-voltage converter, and a reset transistor that resets a potential of the charge-voltage converter; a connection transistor that connects or disconnects the charge-voltage converter of at least one of the pixels and the charge-voltage converter of at least one of the other pixels. A threshold voltage of the connection transistor is higher than a threshold voltage of the reset transistor. | 2012-02-02 |
20120025281 | SOLID-STATE IMAGING DEVICE - A pixel includes at least first to fourth semiconductor tiers. The first semiconductor tier includes a first semiconductor region that is electrically connected to a first external circuit, a second semiconductor region, and a third semiconductor region that is isolated from the first semiconductor region by the second semiconductor region and that is electrically connected to a second external circuit. The second semiconductor tier includes a MOS transistor that has insulating films and gate conductive electrodes that are electrically connected to a third external circuit. The third semiconductor tier includes a photodiode formed of the second and fourth semiconductor regions. A junction transistor is formed in which the fourth semiconductor region serves as a gate and in which one of the first and fifth semiconductor regions serves as a drain and the other serves as a source. | 2012-02-02 |
20120025282 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 2012-02-02 |
20120025283 | MEMORY DEVICE - In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced. | 2012-02-02 |
20120025284 | Semiconductor Device - A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j−1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced. | 2012-02-02 |
20120025285 | SYSTEM WITH LOGIC AND EMBEDDED MIM CAPACITOR - An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the logic region than in the memory region | 2012-02-02 |
20120025286 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming silicon pillar | 2012-02-02 |
20120025287 | Memory Cell, An Array, And A Method for Manufacturing A Memory Cell - A memory cell ( | 2012-02-02 |
20120025288 | SOI Trench DRAM Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, where at least a first portion of the backside strap underlies the doped portion of the top silicon layer, where the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, where the second epitaxially-deposited material further at least partially overlies the first portion of the backside strap. | 2012-02-02 |
20120025289 | METAL CONTROL GATE FORMATION IN NON-VOLATILE STORAGE - Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates. | 2012-02-02 |
20120025290 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole. | 2012-02-02 |
20120025291 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line. | 2012-02-02 |
20120025292 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the Si substrate side, a floating gate surrounding the outer periphery of the channel region with a tunnel insulating film interposed therebetween, a control gate surrounding the outer periphery of the floating gate with an inter-polysilicon insulating film interposed therebetween, and a control gate line connected to the control gate and extending in a predetermined direction. The floating gate extends to regions below and above the control gate and to a region below the control gate line. The inter-polysilicon insulating film is interposed between the floating gate and the upper surface, lower surface, and inner side surface of the control gate and between the control gate line and a portion of the floating gate that extends to the region below the control gate line. | 2012-02-02 |
20120025293 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING GATE AND A CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device having a memory cells and word lines is provided. The memory cells are formed in a semiconductor layer and arranged in matrix. Each of the memory cells has a floating gate and a control gate. Each plurality of the memory cells is connected in series in a row direction. Each of the word lines is connected to each plurality of the control gates in a column direction. First and second intervals are provided for the memory cells alternately in the column direction. The second interval is larger than the first interval. | 2012-02-02 |
20120025294 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO | 2012-02-02 |
20120025295 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer. | 2012-02-02 |
20120025296 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device comprises: forming a plurality of first pillar patterns each of which includes a sidewall contact by selectively etching a semiconductor substrate; forming a buried bit line at a lower portion of a region between two neighboring first pillar patterns; forming a plurality of second pillar patterns by selectively etching upper portions of the first pillar patterns; and forming a gate coupling second pillar patterns arranged in a direction crossing the bit line, the gate enclosing the second pillar patterns. | 2012-02-02 |
20120025297 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film. | 2012-02-02 |
20120025298 | WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads. | 2012-02-02 |
20120025299 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes forming an insulation layer, hydroxylating a surface of the insulation layer by performing a pre-treatment, forming an adhesive layer over the insulation layer, performing a post-treatment, and forming a conductive layer over the adhesive layer. | 2012-02-02 |
20120025300 | Semiconductor Devices Including Vertical Channel Transistors And Methods Of Manufacturing The Same - A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches. | 2012-02-02 |
20120025301 | Inverted-trench grounded-source FET structure with trenched source body short electrode - This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance. | 2012-02-02 |
20120025302 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode embedded in the trench via the gate insulating film and made of a polysilicon doped with an impurity; and an oxidation-resistant metal film disposed on a top surface of the gate electrode and covering the top surface. | 2012-02-02 |
20120025303 | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material. | 2012-02-02 |
20120025304 | Trench Semiconductor Device and Method of Manufacturing - A semiconductor device includes a semiconductor body including a trench with first and second opposing sidewalls. A first electrode is arranged in a lower portion of the trench and a second electrode in an upper portion of the trench. A dielectric structure is arranged in the trench, including a first portion between the electrodes. The first portion includes, in sequence along a lateral direction from the first sidewall to the second sidewall, a first part including a first dielectric material, a second part including a second dielectric material selectively etchable to the first dielectric material, a third part including the first dielectric material, the first dielectric material of the third part being continuously arranged along a vertical direction from a top side of the first electrode to a bottom side of the second electrode, a fourth part including the second dielectric material and a fifth part including the first dielectric material. | 2012-02-02 |
20120025305 | BIDIRECTIONAL SWITCH - An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer. A portion of the N type well layer interposed between a sidewall on an opposite side of the body layer of the trench in which the first gate electrode is formed and a sidewall on an opposite side of the body layer of the trench in which the second gate electrode is formed makes an N type drain layer serving as an electric field relaxation layer. A cross-sectional area of the N type drain layer makes a path of the ON current. | 2012-02-02 |
20120025306 | SEMICONDUCTOR DEVICE - In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings. | 2012-02-02 |
20120025307 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film. | 2012-02-02 |
20120025308 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING BIPOLAR-CMOS-DMOS - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions. | 2012-02-02 |
20120025309 | OFFSET GATE SEMICONDUCTOR DEVICE - An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench. | 2012-02-02 |
20120025310 | SEMICONDUCTOR DEVICE OF WHICH BREAKDOWN VOLTAGE IS IMPROVED - A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; a source diffusion layer and a drain diffusion layer formed on both sides of the gate electrode, respectively, in the semiconductor substrate; and a field drain section formed below the gate electrode in the semiconductor substrate so as to be positioned between the gate electrode and the drain diffusion region and include an insulator. The field drain section includes: a first insulating film configured to be contact with the semiconductor substrate, and a second insulating film configured to be formed on the first insulating film and has a dielectric constant higher than a dielectric constant of the first insulating film. | 2012-02-02 |
20120025311 | RADIATION-HARDENED SEMICONDUCTOR STRUCTURE, A SEMICONDUCTOR DEVICE INCLUDING THE RADIATION-HARDENED SEMICODUCTOR STRUCTURE, AND METHODS OF FORMING THE RADIATION-HARDENED SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE - A radiation-hardened semiconductor structure including an insulator material doped with at least one of a transition metal, a lanthanide, and an actinide, and a semiconductor material located over the insulator material. A semiconductor device including the radiation-hardened semiconductor structure is also disclosed as are method of forming the radiation-hardened semiconductor structure and the semiconductor device. | 2012-02-02 |
20120025312 | Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material - In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors. | 2012-02-02 |
20120025313 | Germanium FinFETs Having Dielectric Punch-Through Stoppers - A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin. | 2012-02-02 |
20120025314 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics. | 2012-02-02 |
20120025315 | Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region - The uniformity of transistor characteristics may be enhanced for transistors having incorporated therein a strain-inducing semiconductor material by using appropriately positioned dummy gate electrode structures. To this end, the dummy gate electrode structures may be positioned such that these structures may connect to or may overlap with the edge of the active region, thereby preserving a portion of the initial semiconductor material of the active region at the edge thereof upon forming the corresponding cavities. | 2012-02-02 |
20120025316 | Process for Forming FINS for a FinFET Device - An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices. | 2012-02-02 |
20120025317 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits. | 2012-02-02 |
20120025318 | Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric - Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled. | 2012-02-02 |
20120025319 | STRUCTURE AND METHOD FOR MAKING METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) WITH ISOLATION LAST PROCESS - In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material. | 2012-02-02 |
20120025320 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF - A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain. | 2012-02-02 |
20120025321 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode. | 2012-02-02 |
20120025322 | REDUCED-STEP CMOS PROCESSES FOR LOW COST RADIO FREQUENCY IDENTIFICATION DEVICES - Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices. | 2012-02-02 |
20120025323 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. | 2012-02-02 |
20120025324 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME AS WELL AS DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low voltage transistor. Each of the unit transistors may include a vertically extending portion of semiconductor providing a channel region and having a uniform height, a gate insulating film extending along a side surface of the vertically extending portion of semiconductor, a gate electrode separated by the gate insulating film from the vertically extending portion of semiconductor, and upper and lower diffusion regions being respectively disposed near the top and bottom of the vertically extending portion of semiconductor. The greater number of the unit transistors are connected in series to each other and have gate electrodes eclectically connected to each other. | 2012-02-02 |
20120025325 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 2012-02-02 |
20120025326 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An interface oxide layer, a gate insulating film, and a gate electrode are sequentially provided on the upper surface of a semiconductor substrate. The gate insulating film has a first high-k film and a second high-k film. The first high-k film is provided on the interface oxide layer, and contains nitrogen. The second high-k film is provided on the first high-k film, and contains nitrogen. The first high-k film has a lower nitrogen concentration than the second high-k film. | 2012-02-02 |
20120025327 | SEMICONDUCTOR DEVICE WITH METAL GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode. | 2012-02-02 |
20120025328 | MOSFET STRUCTURE AND METHOD FOR FABRICATING THE SAME - There are provided a MOSFET structure and a method for fabricating the same. The MOSFET structure comprises: a semiconductor substrate; a gate stack formed on the semiconductor substrate, including a high-k gate dielectric layer and a gate conductor layer formed sequentially on the semiconductor substrate; a first spacer which surrounds at least the high-k gate dielectric layer and comprises a La containing oxide; and a second spacer which surrounds the gate stack and the first spacer and is higher than the first spacer. Embodiments of the present invention are applicable to the fabrication of integrated circuits. | 2012-02-02 |
20120025329 | Spacer Shape Engineering for Void-Free Gap-Filling Process - A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer. | 2012-02-02 |
20120025330 | FABRICATION METHOD OF CARBON NANOTUBE FILM AND SENSOR BASED ON CARBON NANOTUBE FILM - A method for fabricating a carbon nanotube film floating on a bottom is provided. The fabrication method of a carbon nanotube film comprises: forming electrodes on a substrate; arranging a suspension comprising a plurality of carbon nanotubes on the electrodes; and arranging the carbon nanotubes on the electrodes by applying a voltage to the electrodes. | 2012-02-02 |
20120025331 | HORIZONTAL COPLANAR SWITCHES AND METHODS OF MANUFACTURE - A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity. | 2012-02-02 |
20120025332 | SYSTEMS AND METHODS FOR MOUNTING INERTIAL SENSORS - Systems and methods for mounting inertial sensors on a board. On a wafer containing one or more sensor packages having a substrate layer, a sensor layer and an insulator layer located between the sensor layer and the substrate layer, a V-groove is anisotropically etched into one of the substrate layer. The substrate layer is in the 100 crystal plane orientation. The sensor package is then separated from the wafer. Then, a surface of the substrate layer formed by the etching is attached to a board. In one example, three sensor packages are mounted to the board so that their sense axis are perpendicular to each other. | 2012-02-02 |
20120025333 | MEMS ELEMENT AND METHOD FOR MANUFACTURING SAME - An acceleration sensor is formed using an etched layer sandwiched between first and second substrates. In this case, a structure including a movable portion which is displaceable in the thickness direction of the substrates, and a support frame are formed in the etched layer. In addition, first and second fixed electrodes are formed on the first and second substrates, respectively, at a position facing the movable portion. Further, a remaining sacrificial layer is provided on the substrate by leaving a portion of a second sacrificial layer when a first sacrificial layer is entirely etched away. Therefore, when the first sacrificial layer is etched away, corrosion of the structure and the support beams is prevented because the second sacrificial layer is preferentially corroded as compared to the structure. | 2012-02-02 |
20120025334 | MEMS CAPACITIVE MICROPHONE - The present invention discloses an MEMS capacitive microphone including a rigid diaphragm arranged on an elastic element. When a sound wave acts on the rigid diaphragm, the rigid diaphragm is moved parallel to a normal of a back plate by elasticity of the elastic element. Thereby the variation of the capacitance is obtained between the rigid diaphragm and the back plate. | 2012-02-02 |
20120025335 | MICROELECTROMECHANICAL SYSTEMS (MEMS) PACKAGE - A micro-electromechanical systems (MEMS) transducer device comprises: a package substrate having a first coefficient of thermal expansion (CTE); and a transducer substrate comprising a transducer. The transducer substrate is disposed over the package substrate. The transducer substrate has a second CTE that substantially matches the first CTE. | 2012-02-02 |