05th week of 2014 patent applcation highlights part 66 |
Patent application number | Title | Published |
20140032791 | System and Method for Dynamically Detecting Storage Drive Type - An information handling system includes a cable, a backplane, and a processor. The cable is connected to a storage controller of the information handling system. The backplane is configured to connect a drive to the information handling system. The processor is in communication with the cable and with the backplane. The processor is configured to detect a presence of the drive, to output a pulse in response to the detection of the presence of the drive, to determine a first storage technology of the drive in response to the output pulse, to determine a second storage technology of the storage controller, to determine whether there is a misconfiguration between the first storage technology and the second storage technology, and to generate a notification when the misconfiguration is determined. | 2014-01-30 |
20140032792 | LOW PIN COUNT CONTROLLER - Described herein is a system having a multi-host low pin count (LPC) controller ( | 2014-01-30 |
20140032793 | DATA SNOOPING DIRECT MEMORY ACCESS FOR PATTERN DETECTION - A direct memory access controller for efficiently detecting a character string within memory, the direct memory access controller generating signatures of character strings stored within the memory and comparing the generated signatures with the signature of the character string for which detection is desired. | 2014-01-30 |
20140032794 | USB VIRTUALIZATION - Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request. | 2014-01-30 |
20140032795 | INPUT/OUTPUT PROCESSING - The present disclosure provides an electronic device that includes a lower device configured to process local input/output communications between the electronic device and a host, wherein the lower device is stateless. The electronic device also includes a memory comprising a data flow identifier used to associate a data flow resource of the host with a data flow resource corresponding to the lower device. A data packet sent from the lower device to the host includes the data flow identifier. | 2014-01-30 |
20140032796 | INPUT/OUTPUT PROCESSING - The present disclosure provides a system for processing local input/output. The system includes a processor coupled to a host memory through a memory controller. The system also includes an upper device communicatively coupled to the memory controller. The upper device includes one or more transmit/receive work queues. The system also includes a lower device communicatively coupled to the upper device, wherein the lower device is stateless. Data packets passed between the upper device and the lower include a data flow identifier used to identify data flow resources of the upper device and the lower device corresponding to the data packet. | 2014-01-30 |
20140032797 | METHOD FOR REPLACING A SIGNAL BOX, CONNECTED TO AN ELECTRONIC SIGNAL BOX, HAVING A RELAY INTERFACE INPUT/OUTPUT, WITH A FURTHER ELECTRONIC SIGNAL BOX HAVING AT LEAST ONE DATABUS INPUT/OUTPUT, AND ELECTRONIC SIGNAL BOX - In order to be able to replace a first signal box, connected to an electronic second signal box, in relay engineering with a further electronic third signal box in a time- saving fashion, the electronic second signal box used is an electronic second signal box having such generic functionality for its inputs/outputs that setting up a databus connection between the databus input/output of the further electronic third signal box and a databus input/output of the electronic second signal box involves a databus input/output of the electronic second signal box being activated and the relay interface input/output thereof being deactivated. An interruption of the databus connection involves the databus input/output of the electronic second signal box being deactivated and the relay interface input/output thereof being activated. | 2014-01-30 |
20140032798 | WIRELESS STATION AND METHOD FOR SELECTING A-MPDU TRANSMISSION CHARACTERISTICS - A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU, The method thus distinguishes between A-MSDU outside of the block ACK. agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the IEEE 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations. | 2014-01-30 |
20140032799 | Efficient Calibration of a Low Power Parallel Data Communications Channel - A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed. | 2014-01-30 |
20140032800 | VEHICLE MESSAGE FILTER - A message filtering system for a communications system in a vehicle enabling communication between various systems and subsystems via a vehicle bus. Electronic devices may be coupled to the bus. Electronic control units (ECUs) may be located therebetween. The ECU may regulate or control the flow of messages between the bus and the electronic devices. Message filters may apply a filter policy to incoming and outgoing messages. In addition, the message filtering system may have an alert policy for violations of the filter policy. In one embodiment, the source identity of outgoing messages may be overwritten by a message filter dedicated to outgoing messages; this message filter may be an application specific integrated circuit. | 2014-01-30 |
20140032801 | METHOD AND APPARATUS FOR ON-CHIP DEBUGGING - The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values. | 2014-01-30 |
20140032802 | DATA ROUTING SYSTEM SUPPORTING DUAL MASTER APPARATUSES - A data routing system supporting dual master apparatuses is provided. The system includes a first master apparatus, a second master apparatus, at least one first-type interface apparatus, and at least one second-type interface apparatus, which are connected in a daisy chain manner. The first master apparatus provides data transmission of a first channel and a second channel. The second master apparatus transmits data with the first master apparatus through the first channel by using a peer-to-peer data transmission method and bypasses data of the second channel. The first-type interface apparatus transmits data with the first master apparatus through the second channel, and the second-type interface apparatus transmits data with the second master apparatus through the first channel. | 2014-01-30 |
20140032803 | PREDICTION OF ELECTRONIC COMPONENT BEHAVIOR IN BUS-BASED SYSTEMS - Systems and methods for predicting electronic component behavior in bus-based systems are described. In some embodiments, a method may include identifying a first bus access request pending in a request queue, the first bus access request associated with a first master component operably coupled to a bus. The method may also include calculating a first wait time corresponding to the first bus access request, the first wait time indicative of a length of time after which the first master component is expected to be granted access to the bus. The method may further include, in response to the first wait time meeting a threshold value, issuing a command to the first master component. In some embodiments, various techniques disclosed herein may be implemented, for example, in a computer system, an integrated circuit, or the like. | 2014-01-30 |
20140032804 | SCHEDULED PERIPHERAL COMPONENT INTERCONNECT ARBITER - Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device. | 2014-01-30 |
20140032805 | ELECTRONIC DEVICE WITH CARD INTERFACE - When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode. | 2014-01-30 |
20140032806 | DOCKING STATION FOR AN ELECTRONIC DEVICE - The present invention is directed to a housing unit, which allows an electronic device such as a portable digital audio player to be substantially hermetically sealed within an audio device. The electronic device is controllable by a user while housed with the housing unit. The audio device is able to be used in a vehicle such as a car, a camper, or a boat or in other common consumer products. | 2014-01-30 |
20140032807 | METHOD AND SYSTEM FOR MULTIPLE SERVERS TO SHARE A POSTAL SECURITY DEVICE - Systems and methods that allow a PSD to be physically shared by multiple servers such that if a server fails, another server can be utilized as a backup server for the PSD without any manual intervention or moving of the PSD and without risking loss of data from the PSD. A PSD is interfaced by an interface device to a system level bus that allows for multiple initiators. An initiator is any server that can access and issue commands over the system level bus to access the PSD. When one of the servers fails, the functionality of the server can be rolled to a backup server which will be able to access the PSD over the bus. | 2014-01-30 |
20140032808 | INTEGRATED CIRCUIT HAVING A BUS NETWORK, AND METHOD FOR THE INTEGRATED CIRCUIT - A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state. | 2014-01-30 |
20140032809 | COMPOSITE DATA TRANSMISSION INTERFACE AND A JUDGMENT METHOD THEREOF - The present invention relates to a composite data transmission interface and a judgment method thereof which is based on metal contacts shared by a smart card and a universal series bus and comprise steps as follows: link a composite pin to a socket; electrical conductivity is completed with a socket linking a composite pin; a controller connected to the composite pin is activated by electricity; a smart card's or a universal series bus's electrical conductivity mode is enabled by the controller by means of the smart card's or the universal series bus's electrical connection mode. | 2014-01-30 |
20140032810 | APPLICATION SHARING IN MULTI HOST COMPUTING SYSTEMS - The present subject matter discloses methods and systems of application sharing in multi-host computing system ( | 2014-01-30 |
20140032811 | MULTI-ROOT PERIPHERAL CONNECT INTERFACE MANAGER - Described herein is a detachable multi-host computing system ( | 2014-01-30 |
20140032812 | METHOD AND DESIGN FOR HIGH PERFORMANCE NON-VOLATILE MEMORY - A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved. | 2014-01-30 |
20140032813 | METHOD OF ACCESSING A NON-VOLATILE MEMORY - A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits. | 2014-01-30 |
20140032814 | HYBRID STORAGE DEVICE HAVING DISK CONTROLLER WITH HIGH-SPEED SERIAL PORT TO NON-VOLATILE MEMORY BRIDGE - A hybrid storage device comprises at least one storage disk, a disk controller configured to control writing of data to and reading of data from the storage disk, a non-volatile electronic memory, and a bridge device coupled between the disk controller and the non-volatile electronic memory. The disk controller comprises a plurality of high-speed serial interfaces. In one embodiment, the high-speed serial interfaces include a first high-speed serial interface configured to interface the disk controller to a host device, and a second high-speed serial interface configured to interface the disk controller to the non-volatile memory via the bridge device. The non-volatile memory may comprise a flash memory, and the bridge device may comprise a flash controller. The disk controller may be implemented in the form of an SOC integrated circuit that is operative in a plurality of modes including a hybrid mode of operation and an enterprise mode of operation. | 2014-01-30 |
20140032815 | METHODS AND APPARATUSES FOR CALIBRATING DATA SAMPLING POINTS - Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a calibration command and an attribute. The memory may include a first register that is configured to store a tuning data pattern and a second register that is configured to receive and store the tuning data pattern stored in the first register. The second register may be further configured to store the tuning data pattern responsive, at least in part, to the memory receiving the calibration command. The memory may be configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute. | 2014-01-30 |
20140032816 | SERIAL INTERFACE FLASH MEMORY APPARATUS AND WRITING METHOD FOR STATUS REGISTER THEREOF - A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed. | 2014-01-30 |
20140032817 | VALID PAGE THRESHOLD BASED GARBAGE COLLECTION FOR SOLID STATE DRIVE - A method for garbage collection in a solid state drive (SSD) includes determining whether the SSD is idle by a garbage collection module of the SSD; based on determining that the SSD is idle, determining a victim block from a plurality of memory blocks of the SSD; determining a number of valid pages in the victim block; comparing the determined number of valid pages in the victim block to a valid page threshold; and based on the number of valid pages in the victim block being less than the valid page threshold, issuing a garbage collection request for the victim block. | 2014-01-30 |
20140032818 | PROVIDING A HYBRID MEMORY - A hybrid memory has a volatile memory and a non-volatile memory. The volatile memory is dynamically configurable to have a first portion that is part of a memory partition, and a second portion that provides a cache for the non-volatile memory. | 2014-01-30 |
20140032819 | COLLECTING INSTALLATION AND FIELD PERFORMANCE DATA FOR MEMORY DEVICES - An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system. | 2014-01-30 |
20140032820 | DATA STORAGE APPARATUS, MEMORY CONTROL METHOD AND ELECTRONIC DEVICE WITH DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus comprises a first controller, a second controller, and a third controller. The first controller controls first write processing of writing data to a flash memory in accordance with a request from a host. The second controller controls second write processing of writing data to the flash memory, the second write processing is different from the first write processing. | 2014-01-30 |
20140032821 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided are a nonvolatile memory device and a method for operating the nonvolatile memory device. The method for operating the nonvolatile memory device includes generating a first program voltage, applying the generated first program voltage to a first word line to which a first memory cell is connected for performing a first program operation on the first memory cell, determining whether a number of pulses of a pumping clock signal for generating the first program voltage is greater than or equal to a predetermined critical value n (where n is a natural number), and stopping the performing of the first program operation on the first memory cell when the number of pulses of the pumping clock signal is determined to be greater than or equal to the predetermined critical value n. | 2014-01-30 |
20140032822 | WRITING DATA TO SOLID STATE DRIVES - Technologies and implementations for writing data to a solid state drive are generally disclosed. | 2014-01-30 |
20140032823 | MEMORY BLOCK IDENTIFIED BY GROUP OF LOGICAL BLOCK ADDRESSES, STORAGE DEVICE WITH MOVABLE SECTORS, AND METHODS - In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status. | 2014-01-30 |
20140032824 | Memory Controller, Memory System Including the Same, and Method for Operating the Same - A memory controller includes a first interface unit, a processor, a randomization unit, a state conversion unit, and a second interface unit. The first interface unit exchanges data with an external device, and the processor determines whether to randomize or state-convert the received data. The randomization unit randomizes data received through the first interface unit in response to the processor and generates randomization information in response to the randomization operation. The state conversion unit state-converts data received through the first interface unit in response to the processor and generates conversion information in response to the state conversion operation. The second interface unit receives the randomized data and the randomization information from the randomization unit, receives the state-converted data and the conversion information from the state conversion unit, and exchanges at least one of the randomized data, the randomization information, the state-converted data and the conversion information with a memory. | 2014-01-30 |
20140032825 | DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive. | 2014-01-30 |
20140032826 | METHOD OF TRAINING MEMORY CORE AND MEMORY SYSTEM - A method of training a memory device included in a memory system is provided. The method includes testing memory core parameters for a memory core of the memory device during a booting-up sequence of the memory system; determining trimmed memory core parameters based on the test results; storing the determined trimmed memory core parameters; and applying the trimmed memory core parameter to the memory device during a normal operation of the memory device. | 2014-01-30 |
20140032827 | DATA INVERSION BASED APPROACHES FOR REDUCING MEMORY POWER CONSUMPTION - Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache. | 2014-01-30 |
20140032828 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR COPYING DATA BETWEEN MEMORY LOCATIONS - A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction. | 2014-01-30 |
20140032829 | Energy Conservation in a Multicore Chip - Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip. More particularly, a directory entry may be accessed in the cache coherence directory stored in the DRAM. Some further examples may identify a cache coherence state of a block associated with the directory entry. In some examples, refresh of the directory entry stored in the DRAM may be selectively disabled based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved. | 2014-01-30 |
20140032830 | Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration - A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. | 2014-01-30 |
20140032831 | MULTI-UPDATABLE LEAST RECENTLY USED MECHANISM - A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register. | 2014-01-30 |
20140032832 | TCAM EXTENDED SEARCH FUNCTION - An apparatus includes a range determination module that determines a search range of TCAM content values and a search criteria module that creates a TCAM search value from a search range by combining common higher order bits with don't care lower order bits that change within the search range. A match module searches the TCAM using the search value to determine a match count. A division module creates upper and lower sub-ranges by creating upper and lower midpoint content values within the search range. The upper sub-range is between an upper content value and the upper midpoint content value and the lower sub-range is between the lower midpoint content value and a lower content value. The upper midpoint content value includes changing a most significant don't care bit to a 1 and remaining don't care bits to 0. The lower midpoint content value includes changing a most significant don't care bit to 0 and remaining don't care bits to 1. | 2014-01-30 |
20140032833 | Dynamic Disk Space Management In A File System - Dynamic disk space management in a file system, including: assigning, by a disk utilization manager upon creation of each file in the file system, a unique identifier to the file; tracking, by the disk utilization manager for each file in the file system, file characteristics in dependence upon the unique identifier of the file; prioritizing, by the disk utilization manager in dependence upon the tracked file characteristics and a predefined set of prioritization criteria, files in the file system; tracking, by the disk utilization manager, utilization of disk drive space; and, upon utilization of disk drive space exceeding a predetermined maximum threshold, reducing, by the disk utilization manager in dependence upon the priorities of files, disk drive space utilization to no greater than a predetermined capacity. | 2014-01-30 |
20140032834 | Managing A Solid State Drive ('SSD') In A Redundant Array Of Inexpensive Drives ('RAID') - Managing a solid state drive (‘SSD’) in a Redundant Array of Inexpensive Drives (‘RAID’), including: detecting, by a RAID engine, a number of cell failures of the SSD exceeding a predetermined threshold; responsive to detecting the number of cell failures of the SSD exceeding the predetermined threshold: redirecting, by the RAID engine, a write of data not originally stored in the RAID to a drive in the RAID other than the SSD; and redirecting, by the RAID engine, writes originally directed to data stored on the SSD to another drive in the RAID, including unmapping the data stored on the SSD. | 2014-01-30 |
20140032835 | MEMORY ARCHITECTURE - A write circuit in a memory array includes a global data line, a switching circuit, and a first local data line coupled with the switching circuit and with a first plurality of memory cells. The global data line is configured to receive data to be written to the memory cell from outside of the memory array. The switching circuit is configured to electrically couple the global data line with the first local data line to transfer the data to be written to a memory cell of the first plurality of memory cells to the first local data line. The memory cell of the first plurality of memory cells is configured to receive data on the first local data line. | 2014-01-30 |
20140032836 | BUFFER FOR RAID CONTROLLER WITH DISABLED POST WRITE CACHE - Enhancing management of controllers in a RAID system when a post-write-cache of a is disabled, by supplying a stripe buffer that stores sequential write requests—and before such requests are actually written in to the physical disc drives. The stripe buffer can temporarily store data, until the data level reaches the stripe buffer size. Thereafter, contents of the stripe buffer can be flushed onto disc. | 2014-01-30 |
20140032837 | STORAGE SYSTEM, STORAGE CONTROL METHOD AND STORAGE CONTROL PROGRAM - In tiered storage subsystems in which pages are automatically allocated to appropriate storage media based on the access frequency in page units, since the number of storage media is not simply proportional to the performance, it was difficult to design in advance a tier configuration satisfying the required performance. According to the present invention, a cumulative curve of I/O distribution is created based on a result of measurement of I/O accesses performed to the storage subsystem, and RAID groups (RG) are allocated sequentially in order from RGs belonging to tiers having higher performances to the cumulative curve of I/O distribution. When either a performance limitation value or a capacity of the RG exceeds the cumulative curve of I/O distribution, a subsequent RG is allocated, and the process is repeated so as to compute the optimum tier configuration. | 2014-01-30 |
20140032838 | COMPUTER SYSTEM, DATA MANAGEMENT APPARATUS, AND DATA MANAGEMENT METHOD - A data management apparatus of a computer system comprises, as a retention rule for volume data, change-time identification information for identifying a point-in-time for changing a logical unit, and migration-destination unit specification information for specifying a migration-destination logical unit. An edge storage apparatus stores first identification information, which enables the identification of volume data in a logical unit, and second identification information, which enables the identification of a logical unit in a storage system after associating the first identification information and the second identification information with each other. A data management apparatus (A1) transfers the volume data from a migration-source logical unit to the migration-destination logical unit conforming to the migration-destination unit specification information subsequent to a point-in-time identified in accordance with the change-time identification information. The edge storage apparatus (B1) associates the second identification information, which enables the identification of the migration-destination logical unit, with the first identification information, and stores the associated information in a storage device. | 2014-01-30 |
20140032839 | STORAGE SYSTEM AND METHOD FOR CONTROLLING STORAGE SYSTEM - According to an aspect of the present invention, provided is a storage system including a plurality of storage devices, a plurality of access control devices, a relay device, and a connection control device. The plurality of access control devices control access to each of the plurality of storage devices. The relay device connects each of the plurality of storage devices to one of the plurality of access control devices. The connection control device instructs, in response to load states of the plurality of access control devices, the relay device to switch an access control device connected to one of the plurality of storage devices so that deviation of loads among the plurality of access control devices is improved. | 2014-01-30 |
20140032840 | REQUESTING CLOUD DATA STORAGE - A method begins by a processing module determining that a data storage request is a cloud data storage request. The method continues with the processing module determining at least one of a cloud storage access reliability indication and a cloud storage data reliability indication for the data storage request. The method continues with the processing module sending the data storage request and the at least one of cloud storage access reliability indication and cloud storage data reliability indication to a cloud storage system. | 2014-01-30 |
20140032841 | SYSTEM AND METHOD FOR OBJECT DELETION IN PERSISTENT MEMORY USING BITMAP WINDOWS - A system and method for object deletion in persistent memory using bitmap windows representing memory chunks. In accordance with an embodiment, the system can generally be used with computing environments that use persistent memory, such as smart cards, Java Cards, and other resource-constrained environments. In accordance with an embodiment, the system comprises a processor or computational engine and a persistent memory for storage of software objects; and a data structure which can include one or more memory bitmap windows, each of which represents a chunk of addressable space in the persistent memory; wherein the system uses the one or more memory bitmap windows in deleting non-reachable objects from the persistent memory. | 2014-01-30 |
20140032842 | INVERTER DEVICE - An inverter device includes an inverter main circuit to which a load is connected, an input unit configured to receive an input operation by a user, a connector into which a hot-pluggable external storage device is insertable, and a control unit configured to control writing of a log to the external storage device inserted into the connector. When the external storage device is inserted in the connector, the control unit switches the external storage device to a connected state in which the log is allowed to be written to the external storage device. When the input unit receives the input operation during the connected state of the external storage device, the control unit stops writing of the log to the external storage device and switches the external storage device to a disconnected state in which the external storage connector is removable from the connector. | 2014-01-30 |
20140032843 | MANAGEMENT OF CHIP MULTIPROCESSOR COOPERATIVE CACHING BASED ON EVICTION RATE - Techniques described herein generally include methods and systems related to cooperatively caching data in a chip multiprocessor. Cooperatively caching of data in the chip multiprocessor is managed based on an eviction rate of data blocks from private caches associated with each individual processor core in the chip multiprocessor. The eviction rate of data blocks from each private cache in the cooperative caching system is monitored and used to determine an aggregate eviction rate for all private caches. When the aggregate eviction rate exceeds a predetermined value, for example the threshold beyond which network flooding can occur, the cooperative caching system for the chip multiprocessor is disabled, thereby avoiding network flooding of the chip multiprocessor. | 2014-01-30 |
20140032844 | SYSTEMS AND METHODS FOR FLUSHING A CACHE WITH MODIFIED DATA - Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache. | 2014-01-30 |
20140032845 | SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE - A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory. | 2014-01-30 |
20140032846 | SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD AND STORE ACCESSES OF A CACHE - Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data. | 2014-01-30 |
20140032847 | SEMICONDUCTOR DEVICE - A semiconductor device which can hold an instruction configuring a loop in a cache memory is provided. A main memory stores an instruction. A cache memory stores the instruction temporarily. A CPU reads an instruction from the main memory or the cache memory and executes the instruction. The cache control unit stops updating an instruction stored in the cache memory, when the same instruction as the instruction read in the past is again read within a prescribed number of read. | 2014-01-30 |
20140032848 | Sharing Pattern-Based Directory Coherence for Multicore Scalability ("SPACE") - A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry. | 2014-01-30 |
20140032849 | CACHE MANAGER FOR SEGMENTED MULTIMEDIA AND CORRESPONDING METHOD FOR CACHE MANAGEMENT - The invention concerns a cache manager ( | 2014-01-30 |
20140032850 | Transparent Virtualization of Cloud Storage - Embodiments present a virtual disk image to applications such as virtual machines (VMs) executing on a computing device. The virtual disk image corresponds to one or more subparts of binary large objects (blobs) of data stored by a cloud service, and is implemented in a log structured format. Grains of the virtual disk image are cached by the computing device. The computing device caches only a subset of the grains and performs write operations without blocking the applications to reduce storage latency perceived by the applications. Some embodiments enable the applications that lack enterprise class storage to benefit from enterprise class cloud storage services. | 2014-01-30 |
20140032851 | RANDOMIZED PAGE WEIGHTS FOR OPTIMIZING BUFFER POOL PAGE REUSE - In general, the disclosure is directed to techniques for choosing which pages to evict from the buffer pool to make room for caching additional pages in the context of a database table scan. A buffer pool is maintained in memory. A fraction of pages of a table to persist in the buffer pool are determined. A random number is generated as a decimal value of 0 to 1 for each page of the table cached in the buffer pool. If the random number generated for a page is less than the fraction, the page is persisted in the buffer pool. If the random number generated for a page is greater than the fraction, the page is included as a candidate for eviction from the buffer pool. | 2014-01-30 |
20140032852 | RANDOMIZED PAGE WEIGHTS FOR OPTIMIZING BUFFER POOL PAGE REUSE - In general, the disclosure is directed to techniques for choosing which pages to evict from the buffer pool to make room for caching additional pages in the context of a database table scan. A buffer pool is maintained in memory. A fraction of pages of a table to persist in the buffer pool are determined. A random number is generated as a decimal value of 0 to 1 for each page of the table cached in the buffer pool. If the random number generated for a page is less than the fraction, the page is persisted in the buffer pool. If the random number generated for a page is greater than the fraction, the page is included as a candidate for eviction from the buffer pool. | 2014-01-30 |
20140032853 | Method for Peer to Peer Cache Forwarding - A home node for selecting a source node using a cache coherency protocol, comprising a logic unit cluster coupled to a directory, wherein the logic unit cluster is configured to receive a request for data from a requesting cache node, determine a plurality of nodes that hold a copy of the requested data using the directory, select one of the nodes using one or more selection parameters as the source node, and transmit a message to the source node to determine whether the source node stores a copy of the requested data, wherein the source node forwards the requested data to the requesting cache node when the requested data is found within the source node, and wherein some of the nodes are marked as a Shared state corresponding to the cache coherency protocol. | 2014-01-30 |
20140032854 | Coherence Management Using a Coherent Domain Table - A computer program product comprising computer executable instructions stored on a non-transitory medium that when executed by a processor cause the processor to perform the following: assign a first, second, third, and fourth coherence domain address to a cache data, wherein the first and second address provides the boundary for a first coherence domain, and wherein the third and fourth address provides the boundary for a second coherence domain, inform a first resource about the first coherence domain prior to the first resource executing a first task, and inform a second resource about the second coherence domain prior to the second resource executing a second task. | 2014-01-30 |
20140032855 | INFORMATION PROCESSING APPARATUS AND METHOD - An information processing apparatus includes a processor, a memory, and a cache. Information read from the memory by the processor is stored in the cache. The processor writes the information stored in the memory in all of the regions of the cache at a predetermined timing. | 2014-01-30 |
20140032856 | SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE - A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache. | 2014-01-30 |
20140032857 | METHODS AND APPARATUS FOR MERGING SHARED CACHE LINE DATA IN A BUS CONTROLLER - Shared cache line data is merged in a bus controller by issuing a snoop request to a plurality of cache controllers with a cache line address for which a bus transaction is performed; collecting snoop responses from the plurality of cache controllers, wherein a snoop response from a given cache controller comprises a cache state of the cache line address in a given cache associated with the given cache controller, and an ownership control signal identifying which portions of the cache line are controlled by the given cache; collecting data responses from the cache controllers, wherein the data response from a given cache controller comprises a data value from the cache line address; merging the data values from the cache controllers based on the ownership control signals to obtain a merged data value; and broadcasting the merged data value to the cache controllers. | 2014-01-30 |
20140032858 | METHODS AND APPARATUS FOR CACHE LINE SHARING AMONG CACHE CONTROLLERS - Methods and apparatus are provided for cache line sharing among cache controllers. A cache comprises a plurality of cache lines; and a cache controller for sharing at least one of the cache lines with one or more additional caches, wherein a given cache line shared by a plurality of caches corresponds to a given set of physical addresses in a main memory. The cache controller optionally maintains an ownership control signal indicating which portions of the at least one cache line are controlled by the cache and a validity control signal indicating whether each portion of the at least one cache line is valid. Each cache line can be in one of a plurality of cache coherence states, including a modified partial state and a shared partial state. | 2014-01-30 |
20140032859 | MEMORY SYSTEM WITH MULTIPLE BLOCK WRITE CONTROL - An apparatus includes a memory module with a plurality of memory blocks and an address decoder module that decodes one or more address lines of the plurality of memory blocks. An address output of the address decoder module corresponds to each memory block. A BWE module includes a block write enable (“BWE”) signal corresponding to each memory block. Each BWE signal has a block write enable state and a block write disable state. In response to receiving a block write enable control (“BWEC”) signal in a normal use mode, a MUX module passes a corresponding address output of the address decoder module to a write enable input of each memory block. In response to receiving the BWEC signal in a state trace mode, the MUX module passes a corresponding BWE signal to the write enable input of each memory block. | 2014-01-30 |
20140032860 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR OPERATING SAME - First data to be written which is output from a function module ( | 2014-01-30 |
20140032861 | SYSTEMS AND METHODS FOR EFFICIENTLY STORING DATA - One method includes assigning a pointer from multiple logical blocks to the same original physical block if the multiple logical blocks include the same data. The method further includes receiving a command to write data to the first logical block and determining if the first logical block is a frequently accessed logical block. If the first logical block is a frequently accessed logical block, ownership of the original physical block is assigned to the first logical block. If ownership is established, the method includes copying any data stored in the original physical block to a new physical block, assigning a pointer from a second logical block to the new physical block, and performing the write command on the original physical block. A system includes a processor for performing the above method. One computer program product includes computer code for performing the method described above. | 2014-01-30 |
20140032862 | Backing Up An Image In A Computing System - Methods, apparatus, and products for backing up an image in a computing system that includes computer memory, including: receiving, by a backup image manager, an image for one or more computing devices within the computing system; identifying, by the backup image manager, available protected computer memory within the computing system, wherein the available protected computer memory within the computing system is restricted from alteration by a user of the computing system; slicing, by the backup image manager, the image into a plurality of image slices; and storing, by the backup image manger, one or more of the image slices in the available protected computer memory. | 2014-01-30 |
20140032863 | Electronic Device Mirroring Device Setting - An electronic device includes a target selection unit, a priority determination unit, and a mirroring execution unit. The target selection unit is configured to select, as a mirroring target, a setting value of each of items of the electronic device if the setting value is different from an initial value. The priority determination unit is configured to determine a priority of mirroring, designated for a setting value serving as the mirroring target. The mirroring execution unit is configured to perform the mirroring so as to cause a setting value, whose determined priority is relatively high, to remain on a priority basis. | 2014-01-30 |
20140032864 | SYSTEMS AND METHODS FOR RETAINING AND USING DATA BLOCK SIGNATURES IN DATA PROTECTION OPERATIONS - A system according to certain embodiments associates a signature value corresponding to a data block with one or more data blocks and a reference to the data block to form a signature/data word corresponding to the data block. The system further logically organizes the signature/data words into a plurality of files each comprising at least one signature/data word such that the signature values are embedded in the respective file. The system according to certain embodiments reads a previously stored signature value corresponding to a respective data block for sending from a backup storage system having at least one memory device to a secondary storage system. Based on an indication as to whether the data block is already stored on the secondary storage system, the system reads the data block from the at least one memory device for sending to the secondary storage system if the data block does not exist on the secondary storage system, wherein the signature value and not the data block is read from the at least one memory device if the data block exists on the secondary storage system. | 2014-01-30 |
20140032865 | STORAGE SYSTEM IN WHICH INFORMATION IS PREVENTED - According to one embodiment, a storage system includes a host device, a first storing medium, and a second storing medium. The first storing medium includes: a memory provided with a protected first storing region which stores first information sent from the host device, and a second storing region which stores encoded contents; and a controller which carries out authentication processing for accessing the first storing region. The host device and the storing medium produce a bus key which is shared only by the host device and the storing medium by authentication processing, and which is used for encoding processing when information of the first storing region is sent and received between the host device and the storing medium. The host device has the capability to request the storing medium to send a status. | 2014-01-30 |
20140032866 | STORAGE SYSTEM IN WHICH INFORMATION IS PREVENTED - According to one embodiment, a storage system includes a host device, | 2014-01-30 |
20140032867 | STORAGE SYSTEM IN WHICH INFORMATION IS PREVENTED - According to one embodiment, a storage system includes a host device, 2 storing medium. The secure storing medium includes: a memory provided with a protected first storing region which stores secret information sent from the host device, and a second storing region which stores encoded contents; and a controller which carries out authentication processing for accessing the first storing region. The host device and the secure storing medium produce a bus key which is shared only by the host device and the secure storing medium by authentication processing, and which is used for encoding processing when information of the first storing region is sent and received between the host device and the secure storing medium. The host device has the capability to request the secure storing medium to send a status. | 2014-01-30 |
20140032868 | STORAGE SYSTEM IN WHICH INFORMATION IS PREVENTED - According to one embodiment, a storage system includes a host device, 2 storing medium. The secure storing medium includes: a memory provided with a protected first storing region which stores secret information sent from the host device, and a second storing region which stores encoded contents; and a controller which carries out authentication processing for accessing the first storing region. The host device and the secure storing medium produce a bus key which is shared only by the host device and the secure storing medium by authentication processing, and which is used for encoding processing when information of the first storing region is sent and received between the host device and the secure storing medium. The host device has the capability to request the secure storing medium to send a status. | 2014-01-30 |
20140032869 | SYNCHRONOUS EXTENT MIGRATION PROTOCOL FOR PAIRED STORAGE - Exemplary method, system, and computer program embodiments for, in a data storage environment configured for synchronous replication between a primary and secondary pair of storage entities, each having tiered storage devices, extent migration are provided. In one embodiment, by way of example only, a migration instruction is sent, by the primary storage entity, to the secondary storage entity, the migration instruction including a relative priority based on a primary ordered heat map of the tiered storage devices of the primary storage entity. The relative priority is used against a secondary ordered heat map of the tiered storage devices of the secondary storage entity to perform the extent migration, regardless of whether the primary and secondary storage entities are identical. | 2014-01-30 |
20140032870 | SYSTEM LSI - The present invention provides a system LSI that integrates, on a single semiconductor, a logic circuit, a CPU, and a program memory storing a program of the CPU. The system LSI includes a program eraser erasing contents stored in the program memory, and at least two program erasing trigger terminals controlling execution of the program eraser. The program eraser erases a program stored in the program memory on the basis of potentials of the two program erasing trigger terminals. | 2014-01-30 |
20140032871 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell. | 2014-01-30 |
20140032872 | STORAGE RECOMMENDATIONS FOR DATACENTERS - Systems, computer readable media, and methods are provided. An example method can include classifying a plurality of storage mapping systems as a plurality of storage tiers in a datacenter, assigning a chargeback level to each of the plurality of storage tiers, analyzing a plurality of storage volumes of a plurality of servers in the datacenter to obtain characteristics of each of the plurality of storage volumes where the characteristics include one of the plurality of storage mapping systems, assigning the chargeback level to each of the plurality of storage volumes based on the storage mapping system for each of the plurality of storage volumes, and determining a storage recommendation for a number of configuration item (CIs) based on a criticality of the number of CIs where the criticality corresponds to at least one of the chargeback levels assigned to each of the plurality of storage tiers. | 2014-01-30 |
20140032873 | WORKLOAD ADAPTIVE ADDRESS MAPPING - Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions. | 2014-01-30 |
20140032874 | COMPUTING DEVICE AND VIRTUAL DEVICE CONTROL METHOD FOR CONTROLLING VIRTUAL DEVICE BY COMPUTING SYSTEM - A virtual device control method of a computing device which includes a nonvolatile memory is provided. The virtual device control method includes receiving a virtualization request; assigning a first part of the nonvolatile memory to a virtual memory; assigning a second part of the nonvolatile memory to a virtual storage; and generating a virtual device including the assigned virtual memory and virtual storage. | 2014-01-30 |
20140032875 | Physical Memory Forensics System and Method - The method of the present inventive concept is configured to utilize Operating System data structures related to memory-mapped binaries to reconstruct processes. These structures provide a system configured to facilitate the acquisition of data that traditional memory analysis tools fail to identify, including by providing a system configured to traverse a virtual address descriptor, determine a pointer to a control area, traverse a PPTE array, copy binary data identified in the PPTE array, generate markers to determine whether the binary data is compromised, and utilize the binary data to reconstruct a process. | 2014-01-30 |
20140032876 | SYSTEM & METHOD FOR STORING A SPARSE MATRIX - A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix. | 2014-01-30 |
20140032877 | APPARATUS AND METHOD FOR AN INSTRUCTION THAT DETERMINES WHETHER A VALUE IS WITHIN A RANGE - A method is described that includes performing the following with a single instruction: receiving a first input operand V; receiving a second input operand S; calculating V−S; determining if V−S is positive or negative; and, providing as a resultant: V if V−S is negative; V−S if V−S is positive. | 2014-01-30 |
20140032878 | SPLIT EMBEDDED DRAM PROCESSOR - A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor. | 2014-01-30 |
20140032879 | CIRCUIT AND METHOD FOR SEARCHING A DATA ARRAY AND SINGLE-INSTRUCTION, MULTIPLE-DATA PROCESSING UNIT INCORPORATING THE SAME - Search circuitry responsive to a single instruction for undertaking a step of a search of a data array for an extreme value therein, a method of searching a data array to identify an extreme value therein and a location thereof and a single-instruction, multiple-data (SIMD) processing unit incorporating the search circuitry or the method. In one embodiment, the search circuitry includes: a comparison element configured to compare two values in the data array, (2) multiplexers coupled to the comparison element and configured to select a more extreme value of the two values and a location in the data array of the more extreme value and (3) an incrementer configured to increment a counter associated with the search. | 2014-01-30 |
20140032880 | MOBILE TERMINAL AND CONTROL METHOD THEREOF - A mobile terminal and a method for controlling the mobile terminal are disclosed. A mobile terminal according to one embodiment of the present invention comprises at least one sensor; a first processor for controlling operation of the at least one sensor; a second processor for controlling an application; and a vibration unit detecting a force applied by the user, where the vibration unit is woken up when a force applied by the user exceeds a predetermined magnitude while the at least one sensor, the first processor, the second processor, and the vibration unit are all in a sleep state; and if the first processor is woken up by the vibration unit, the first processor wakes up the second processor based on sensing data collected by the at least one sensor. | 2014-01-30 |
20140032881 | INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION - Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands. | 2014-01-30 |
20140032882 | MODIFICATION OF FUNCTIONALITY IN EXECUTABLE CODE - In an example embodiment, an instruction set is accessed. An instruction modifier is associated with the instruction set. Thereafter, the instruction set is transformed into a modified instruction set based on the instruction modifier. After the transformation, the modified instruction set is executed. | 2014-01-30 |
20140032883 | Lock Free Streaming of Executable Code Data - A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page. | 2014-01-30 |
20140032884 | Out-of-Order Checkpoint Reclamation in a Checkpoint Processing and Recovery Core Microarchitecture - Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level. | 2014-01-30 |
20140032885 | METHODS AND APPARATUS TO MANAGE PARTIAL-COMMIT CHECKPOINTS WITH FIXUP SUPPORT - Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions. | 2014-01-30 |
20140032886 | MEMORY CONTROLLERS - Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one type in the instruction set, executing a context switch instruction, and executing an instruction of a second type in the instruction set. in one such controller, a single machine executes instructions in an instruction set with instructions having an operational code, and instructions that do not have an operational code. | 2014-01-30 |
20140032887 | HYBRID HARDWIRED/PROGRAMMABLE RESET SEQUENCE CONTROLLER - A processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller that may be configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. In addition, the processor may also include a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller may control each of the additional reset controllers dependent on the value stored within the master control register | 2014-01-30 |
20140032888 | Integrated Circuit Boot Code and Fuse Storage Implemented on Interposer-Mounted Non-Volatile Memory - A method and apparatus for replacing a boot ROM and programmable fuses using a non-volatile memory and an interposer is disclosed. In one embodiment, an apparatus includes an integrated circuit (IC) implementing one or more processor cores. The apparatus further includes a non-volatile memory configured to store configuration settings and boot code for the IC. The apparatus further includes an interposer. Both of the IC and the non-volatile memory are mounted on a substrate of the interposer. The IC and the non-volatile memory are electrically coupled to one another through the substrate. During a system boot, the IC may access boot code and configuration settings from the non-volatile memory via electrical connections in the substrate that are externally inaccessible. | 2014-01-30 |
20140032889 | NETWORK BOOTING A MACHINE COUPLED TO THE NETWORK BY A LINK AGGREGATION GROUP - A technique includes network booting a physical machine coupled to a network by a link aggregation group. The technique includes selectively disabling ports of the physical machine associated with the link aggregation group in connection with the network booting until a driver of an operating system to group the ports together is installed on the physical machine. | 2014-01-30 |
20140032890 | STORAGE DEVICE COMPRISING VARIABLE RESISTANCE MEMORY AND RELATED METHOD OF OPERATION - A storage device includes a nonvolatile memory device including a variable resistance memory, and a controller configured to control the nonvolatile memory device. At a booting operation, the controller stores booting information in the variable resistance memory of the nonvolatile memory device. At a rebooting operation, the controller selectively performs a warm boot operation using the booting information stored in the variable resistance memory, based on a comparison result between a booting setting condition associated with the booting operation and a rebooting condition associated with the rebooting operation. | 2014-01-30 |