04th week of 2009 patent applcation highlights part 12 |
Patent application number | Title | Published |
20090020712 | PLATING PROCESSING METHOD, LIGHT TRANSMITTING CONDUCTIVE FILM AND ELECTROMAGNETIC WAVE SHIELDING FILM - A plating processing method comprises performing a continuous electrolytic plating of the surface of a film having a surface resistivity in the range of 1 Ωf/Sq to 1000 Ω/Sq, wherein a distance between the lowest contacting part of a negative electrode with the film and a plating liquid is in the range of 0.5 cm to 15 cm. | 2009-01-22 |
20090020713 | RADIATION PROTECTION SHIELD - The present invention in one of its preferred structural embodiments comprises a plurality of generally rectangular radiation attenuating panels having rollers mounted on the bottom of each panel and rollable in a lower track mounted on a base such as the concrete floor of a building for movement of each panel along the lower track to a designated position to isolate workers in a particular area from a source of harmful radiation, wherein an upper track is mounted on a rigid structure adjacent upper portions of the panels for laterally engaging in a guiding manner upper guide elements on the upper portions wherein the upper track has substantially the same longitudinal configuration (tracking axis) as the lower track. | 2009-01-22 |
20090020714 | IMAGING SYSTEM - The present invention relates to an imaging system which employs the same principles as coded aperture imaging. High angular resolution coded aperture imagers require a small aperture size and relatively large spacing between the coded aperture array and the detector. At such high resolutions diffraction effects can start to dominate and can degrade image quality. The present invention provides a detector array which receives radiation from a scene via a coded diffractive mask. The coded diffractive mask is designed such that its diffraction pattern at the waveband of interest is a well conditioned coded intensity pattern having a strong autocorrelation function with low sidelobes. Thus radiation reaching the detector array is diffracted by the diffractive mask but in a defined way and it is the diffraction pattern of the mask which provides the coding. The scene image can then be reconstructed using the same techniques as for conventional coded aperture imaging but using the diffraction pattern of the mask as the aperture function. The coded diffractive mask may be a binary or greyscale mask, may operate in reflection or transmission and may be an amplitude or phase modulating mask. | 2009-01-22 |
20090020715 | System and method for controlling a solenoid valve, particularly for a system for variable actuation of the valves of an internal combustion engine according to a multi-lift mode - A solenoid valve, particularly of the type to be used for controlling a hydraulic system for variable actuation of the valves of an internal-combustion engine, has a valve element co-operating with a valve seat and a pusher element, separate from the valve element, which is pushed against the valve element by the movable core of the solenoid valve when the solenoid of the solenoid valve is energized in order to bring the valve element into contact with the valve seat. After de-energization of the solenoid, the time necessary for bringing back the pusher element into the resting condition in contact with the valve element is reduced thanks to the application of a braking current to the solenoid of the solenoid valve during the stage in which the movable core and the pusher element associated thereto displace in the direction opposite to the direction of the movement generated by the magnetic field of the solenoid, following upon de-energization of the solenoid valve. | 2009-01-22 |
20090020716 | MOTOR DRIVEN VALVE AND COOLING/HEATING SYSTEM - To provide a motor-driven valve without requirement that a check valve is separately connected through piping in parallel and without a built-in check valve. A motor-driven valve | 2009-01-22 |
20090020717 | WATER FLOW CONTROL VALVE - The present invention provides a water flow control valve, which has an improved structure, thus reducing manufacturing costs and increasing the reliability of products. To achieve the above-mentioned purpose, the water flow control valve includes synchronous motors ( | 2009-01-22 |
20090020718 | VALVE PART OF A HYDRAULIC CONTROL VALVE FOR CONTROLLING FLOWS OF PRESSURIZED MEDIUM - A valve part of a hydraulic control valve for controlling flows of pressurized medium is provided, wherein the valve part includes a cylindrical valve housing with a first cylinder casing section extending in the axial direction and a first cylinder base section extending perpendicular to the axial direction, with the sections defining a valve housing hollow space that is open on one side. The first cylinder casing section is provided with a first work connection, a second work connection, and a pressure connection, each of which open into the valve housing hollow space. A cylindrical control piston is held in the valve housing hollow space so that it can move in the axial direction, and has a second cylinder casing section extending in the axial direction and a second cylinder base section extending perpendicular to the axial direction, with these sections defining a control piston hollow space that is open on one side. The second cylinder casing section adjacent to the second cylinder base section is provided with a radial discharge connection opening into the control piston hollow space, and the control piston is constructed such that the work connections can be connected selectively in a fluid conducting manner to the pressure connection and to the discharge connection through axial displacement of the control piston. The valve part is distinguished in that the discharge connection of the control piston includes at least one inclined opening, having a wall direction that assumes an angle of less than 90° to the axial direction. | 2009-01-22 |
20090020719 | LINEAR MOTION-TYPE GATE VALVE - A gate valve includes a valve plate for opening and closing a gas passageway, and an air cylinder and a shaft for linearly moving the valve plate between a main housing portion and a storage housing portion of a housing, and the air cylinder is arranged on the first lateral surface side of the housing in parallel with a moving direction of the valve plate, and the shaft is arranged so as to overlap with the valve plate in parallel with the moving direction. A tip end of the shaft is coupled with the valve plate at a position situated near a front end portion in the moving direction thereof. | 2009-01-22 |
20090020720 | METHODS AND APPARATUS TO ALIGN A SEAT RING IN A VALVE - Methods and apparatus to align a seat ring in a valve are described. An example fluid valve includes a valve body having a curved internal surface to receive a seat ring and a seat ring having a sealing surface to receive a movable control member and a curved surface opposite the sealing surface to engage the curved internal surface of the valve body. | 2009-01-22 |
20090020721 | Valve for Vacuum Exhaustion System - The invention provides a valve and a method of operating the valve that makes it possible to reduce the diameter of the vacuum exhaustion pipings to make the facility for the vacuum exhaustion system small, which results in lower costs and shortens vacuum exhaustion time, and also which can prevent corrosion, cloggings, and seal leakages inside the piping system caused by the accumulation of substances produced by the decomposition of gas flowing through the pipings. In particular, in accordance with the present invention, an aluminum passivation is applied on the piping parts, i.e. the valve and others, that are used in the vacuum exhaustion system so as to inhibit gas decomposition caused by temperature rise at the time of baking so that components for reduction in the diameter size in the vacuum exhaustion system are provided. Thus, corrosion, cloggings and seat leakages caused by gas decomposition are prevented. | 2009-01-22 |
20090020722 | Fluid Control Valve - For providing a fluid control valve capable of preventing looseness of a screw part between a valve main body and a valve upper body, the fluid control valve comprises a resin valve main body wherein a valve seat comes into or out of contact with a diaphragm, and a resin valve upper body engaged with the valve main body. The fluid control valve comprises a holding member to keep the valve main body and the valve upper body threadedly screwed together. | 2009-01-22 |
20090020723 | Manual valve - A manual valve comprises a valve element, a rod connected to the valve element, and a knob for moving the rod by screw feeding in an opening/closing direction with respect to the valve element. The valve element is moved by rotation of the knob through the rod. The rod includes an external thread portion on an outer periphery thereof and is not connected to the knob and is held against rotation. Further, the manual valve includes a cylindrical sliding nut rotatably held by a body and formed with an internal thread portion to be engaged with the external thread portion of the rod on its inner periphery and a clip fixed to the knob to be elastically deformably engaged with the sliding nut but disengaged when a larger torque than the predetermined value is applied. | 2009-01-22 |
20090020724 | COMBINED CHECK AND CONTROL VALVE - To overcome problems concerning the sticking of the check plate in a combined check and control valve, a stop is provided on the valve rod or a guide element in the vicinity of the valve rod, whose distance to the limiting element is smaller than the maximum stroke and larger than the nominal stroke of the limiting element. | 2009-01-22 |
20090020725 | FLUSH VALVE APPARATUS AND METHOD FOR FORMING A FRAME AND HOUSING FOR A FLUSH VALVE - A method of manufacturing a flush valve device is provided, including forming a mold for a first half and a second half of the flush valve device, performing injection molding on the mold, upon cooling, removing the first half and the second half from the mold, and forming the flush valve device by joining the first half and the second half. | 2009-01-22 |
20090020726 | PIEZOELECTRIC CERAMIC COMPOSITION - Disclosed is a piezoelectric ceramic composition which is produced by adding two or more metal elements and has excellent piezoelectric properties. The piezoelectric composition comprises the main ingredient represented by the general formula: [Li | 2009-01-22 |
20090020727 | Magnetic receptive plasters and compounds - Magnetic receptive Paints and coatings have been developed to allow one to paint a wall with this coating and apply magnets to this surface. The further development of magnetic receptive compounds lends itself to creating a one step process where one applies a magnetic receptive plaster or compound to a wall with a viscosity sufficient to smooth with a trowel leaving a magnetic receptive surface. In other applications one could spray a compound on a given surface. | 2009-01-22 |
20090020728 | METHOD FOR CONTROLLING THE THICKENING OF AQUEOUS SYSTEMS - A method for controlling the thickening of aqueous systems comprising silicates, which comprises adding to the aqueous system at least one copolymer of a mean molecular weight Mw of greater than 60 000 g/mol and the copolymer being made up essentially randomly from monoethylenically unsaturated monocarboxylic acids, monoethylenically unsaturated dicarboxylic acids and optionally other ethylenically unsaturated comonomers, the quantitative figures being respectively based on the total amount of all monomers used. | 2009-01-22 |
20090020729 | Composition Intended to Be Applied in Steels for Corrosion Protection of Their Surfaces and Process for Preparing the Same - The invention is related to a composition destined to protect steels against corrosion by utilization of the own steel rust as passivating element, the rust being removed from the steel and/or being synthetically prepared and agglutinated with a resin, where the resin can have or can not have as a electric conductivity promoter material an intrinsically conductor polymer (ICP), in this case polyaniline, in its conducting form (emeraldine salt) or non conducting (emeraldine base), besides load(s) and a dispersant oil. | 2009-01-22 |
20090020730 | A DOPANT SOLUTION FOR AN ELECTROCONDUCTIVE POLYMER, AN OXIDANT AND DOPANT SOLUTION FOR AN ELECTROCONDUCTIVE POLYMER, AN ELECTROCONDUCTIVE COMPOSITION AND A SOLID ELECTROLYTIC CAPACITOR - The present invention provides: a dopant solution for an electroconductive polymer characterized in that it comprises at least one selected from the group consisting of alkylamine salts and imidazole salts of benzene skeleton sulfonic acids and naphthalene skeleton sulfonic acids, having at least one OH group and at least one sulfonate group, at a concentration of 40 mass % or more; an oxidant and dopant solution for an electroconductive polymer including a mixture of the organic salt of the dopant as mentioned above, and a persulfate organic salt as an oxidant; an electroconductive composition including an electroconductive polymer prepared by using the oxidant and dopant solution as mentioned above; and solid electrolytic capacitor using the electroconductive composition as a solid electrolyte. The electroconductive composition has an improved electric conductivity, and the solid electrolytic capacitor has an improved reliability for a long time. | 2009-01-22 |
20090020731 | EFFICIENT PROCESS OF VULCANIZATION OF NONCONJUGATED CONDUCTIVE POLYMERS INCLUDING RUBBERS - Nonconjugated conductive polymers, which are all polymers that have a ratio of double bonds to total bonds of less than ½ are doped with iodine to produce compositions with unexpected characteristics in this invention. The mechanical and elastomeric properties of a nonconjugated polymer can be enhanced by doping the polymer with an electron acceptor such as iodine, in order to cure the polymer. Among the nonconjugated polymers are the cis-1,4-polyisoprene, cis-1,4 polybutadiene, styrene-butadiene copolymers (SBR), ethylene-propylene-diene monomer and poly (β-pinene). A heated mixture of iodine and sulfur produces a faster rate of vulcanization of rubber than using sulfur alone. | 2009-01-22 |
20090020732 | METHOD OF SELECTIVELY SEPARATING CARBON NANOTUBES, ELECTRODE COMPRISING METALLIC CARBON NANOTUBES SEPARATED BY THE METHOD AND OLIGOMER DISPERSANT FOR SELECTIVELY SEPARATING CARBON NANOTUBES - Provided is method of selectively separating carbon nanotubes into metallic carbon nanotubes and semiconducting carbon nanotubes, the method including: preparing a mixture including a dispersant, carbon nanotubes, and a solvent; dispersing the carbon nanotubes in the mixture; and separating the semiconducting carbon nanotubes from the mixture in which the carbon nanotubes are dispersed, wherein the dispersant is an oligomer including about 2 to about 24 repeat units, each including a head moiety and a tail moiety, wherein the head moiety comprises 1 to about 5 aromatic hetero rings, and the tail moiety comprises a hydrocarbon chain or chains connected to the head moiety. | 2009-01-22 |
20090020733 | CONDUCTIVE PASTE - A conductive paste that includes a binder containing a thermosetting resin and conductive particles, in which the lowest exothermic peak temperature T | 2009-01-22 |
20090020734 | Method of producing conducting polymer-transition metal electro-catalyst composition and electrodes for fuel cells - A method of producing an electro-catalyst composition for use as an electrode, gas diffusion layer-supported electrode, catalyst-coated solid electrolyte layer, and membrane-electrode assembly in a proton exchange membrane (PEM) type fuel cell. The method comprises: (a) preparing a proton- and electron-conducting polymer having an electronic conductivity no less than 10 | 2009-01-22 |
20090020735 | FLAME RETARDANT COMPOSITION EMPLOYING OIL SAND TAILINGS - A flame retardant composition comprising at least one polymeric material and at least one inorganic filler, where at least a portion of the filler comprises particles derived from oil sand tailings. Such flame retardant composition can be employed in the manufacture and use of flame retardant plastics, fibers, and/or paints. | 2009-01-22 |
20090020736 | Parallelogram Lift for Motor Vehicles - Parallelogram lift for motor vehicles, comprising a pair of base longitudinal members ( | 2009-01-22 |
20090020737 | JOINT CONNECTION SYSTEM - Disclosed is a joining technique to make handrails with stanchions that are the vertical supports that attach to the platform and/or stair stringer at their bottom and attach to the top rail at their top. The stanchions are usually welded or bolted on both ends | 2009-01-22 |
20090020738 | INTEGRATED CIRCUIT INCLUDING FORCE-FILLED RESISTIVITY CHANGING MATERIAL - An integrated circuit includes a first electrode, a second electrode, and force-filled resistivity changing material electrically coupled to the first electrode and the second electrode. | 2009-01-22 |
20090020739 | Method for Delineation of Phase Change Memory Cell Via Film Resistivity Modification - A PCM cell structure comprises a lower electrode composed of a Phase Change Memory (PCM) layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition. | 2009-01-22 |
20090020740 | RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 2009-01-22 |
20090020741 | PHASE CHANGE MEMORY DEVICE WITH REINFORCED ADHESION FORCE - A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions. A bottom electrode is formed in each phase change cell region of the semiconductor substrate. An insulation layer is formed on the semiconductor substrate to cover the bottom electrode, and the insulation layer includes a contact hole exposing the bottom electrode. A contact plug is formed within the contact hole. A stacked pattern comprising a phase change layer and a top electrode is formed over the insulation layer. In the phase change memory device a buffer layer is interposed between the insulation layer and the phase change layer to reinforce the adhesion force between them. The buffer layer prevents the phase change material from peeling off due to an inconstant adhesion force between the phase change material and the insulation layer. | 2009-01-22 |
20090020742 | SOLID ELECTROLYTE SWITCHING ELEMENT, AND FABRICATION METHOD OF THE SOLID ELECTROLYTE ELEMENT, AND INTEGRATED CIRCUIT - The switching element of the present invention is of a configuration that includes: a first electrode ( | 2009-01-22 |
20090020743 | SEMICONDUCTOR STRUCTURE, IN PARTICULAR PHASE CHANGE MEMORY DEVICE HAVING A UNIFORM HEIGHT HEATER - A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer and a sacrificial layer. The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics. | 2009-01-22 |
20090020744 | STACKED MULTILAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film. | 2009-01-22 |
20090020745 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE - Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer. | 2009-01-22 |
20090020746 | SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY - A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material. | 2009-01-22 |
20090020747 | METHOD FOR REALIZING A HOSTING STRUCTURE OF NANOMETRIC ELEMENTS - A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats. | 2009-01-22 |
20090020748 | SI/SIGE INTERBAND TUNNELING DIODES WITH TENSILE STRAIN - Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. | 2009-01-22 |
20090020749 | SEMICONDUCTIVE CROSSLINKABLE POLYMER COMPOSITION - The present invention relates to a crosslinkable polymer composition which is useful for the preparation of semiconductive layers of electric cables, the polymer composition comprising (a) an unsaturated polyolefm having at least 0.15 vinyl groups/1000 carbon atoms and (b) carbon black. | 2009-01-22 |
20090020750 | ACTIVE SEMICONDUCTOR DEVICES - Apparatus including a support body; an organic semiconductor composition body on the support body, —and a first body including a hydrogenated vinylaromatic-diene block copolymer on the organic semiconductor composition body. Apparatus including a support body, —a first body including a hydrogenated vinylaromatic-diene block copolymer on the support body; and an organic semiconductor composition body on the first body. Techniques for making an apparatus. | 2009-01-22 |
20090020751 | Method of forming thin film patterning substrate including formation of banks - Display devices such as EL elements or LED elements, are formed from thin film elements having banks of prescribed height and a thin film layer formed by an ink jet method in areas to be coated that are partitioned by those banks. The banks may be formed of an organic material on a bank formation surface configured of an inorganic material, plasma treatment is performed under conditions that the induction gas is fluorine-based and that fluorine is present excessively, and the areas enclosed by the banks subjected to surface treatment are filled with the liquid thin film material to form the thin film layer or layers. | 2009-01-22 |
20090020752 | RESISTANCE-SWITCHING OXIDE THIN FILM DEVICES - Resistance-switching oxide films, and devices therewith, are disclosed. Resistance-switching oxide films, according to certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix and dopant are preferably in solid solution. The insulator oxide matrix may also preferably include about 6 to about 12 atomic percent of a conducting material dopant. According to certain aspects of the present invention, the insulator oxide matrix, the conducting material dopant, or both, may have a perovskite crystal structure. The insulator oxide matrix may preferably include at least one of LaAlO | 2009-01-22 |
20090020753 | Method of manufacturing semiconductor active layer, method of manufacturing thin film transistor using the same and thin film transistor having semiconductor active layer - A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %. | 2009-01-22 |
20090020754 | Test structure for determining gate-to-body tunneling current in a floating body FET - In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET. | 2009-01-22 |
20090020755 | TEST STRUCTURE OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A test structure includes a transistor, a dummy transistor and a pad unit. The transistor is formed on a first active region of a substrate. The dummy transistor is formed on a second active region of the substrate and electrically connected to the transistor. The pad unit is electrically connected to the transistor. Plasma damage to the transistor is reduced due to the presence of dummy transistor. | 2009-01-22 |
20090020756 | Test structures of a semiconductor device and methods of forming the same - A test structure including a transistor, a conductive pattern and a pad unit is provided. The transistor may be formed on a substrate having circuit patterns. The conductive pattern is electrically connected to the transistor. The conductive pattern may be used in aligning the circuit patterns and/or sensing plasma damage to the semiconductor device. The conductive pattern may be used in reducing etching damage to the circuit patterns and sensing plasma damage to the semiconductor device. The pad unit is electrically connected to the transistor, and provides electrical signals to the transistor. The conductive pattern may serve as an antenna pattern and/or an align/overlay pattern or a dummy pattern. | 2009-01-22 |
20090020757 | Flash Anneal for a PAI, NiSi Process - A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate. | 2009-01-22 |
20090020758 | Display substrate and method of manufacturing the same - A display substrate includes a base substrate, a first metal pattern, a second metal pattern, a first transparent conductive layer and a second transparent conductive layer. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode connected to the gate line. The second metal pattern includes a data line crossing the gate line, a source electrode connected to the data line and a drain electrode being spaced apart from the source electrode. The first transparent conductive layer includes a capping layer capping the second metal pattern and a common electrode formed in a pixel area. The second transparent conductive layer includes a pixel electrode having a plurality of openings, contacting the capping layer capping the drain electrode, and facing the common electrode. | 2009-01-22 |
20090020759 | Light-emitting device - It is an object to provide a light-emitting device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the light-emitting device with high productivity. As for a light-emitting device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, a channel protective layer which is provided over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film, a source region and a drain region over the channel protective layer and the buffer layer, and a source electrode and a drain electrode over the source region and the drain region. | 2009-01-22 |
20090020760 | Methods for forming materials using micro-heaters and electronic devices including such materials - Nano-sized materials and/or polysilicon are formed using heat generated from a micro-heater, the micro-heater may include a substrate, a heating element unit formed on the substrate, and a support structure formed between the substrate and the heating element unit. Two or more of the heating element units may be connected in series. | 2009-01-22 |
20090020761 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A separation layer is formed over a substrate, an insulating film | 2009-01-22 |
20090020762 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer. | 2009-01-22 |
20090020763 | POLY SILICON LAYER AND STRUCTURE FOR FORMING THE SAME - A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. A polysilicon layer formed according to the above-mentioned fabrication method is also provided. The grains of the poly silicon layer are spherical in shape. | 2009-01-22 |
20090020764 | GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region. | 2009-01-22 |
20090020765 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween. | 2009-01-22 |
20090020766 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer. | 2009-01-22 |
20090020767 | Active Matrix Substrate - An active matrix substrate is provided. Within the field of the probe contact area of the pad portion, a buffer layer is arranged on a pad in order to increase the thickness of the pad portion; or, to hollow out the pad and form an opening within the probe contract area. Thus, the probe will not touch the pad directly even if the probe is pressed inadequately to pierce the conductive layer. As a result, the substrate structure can prevent the metallic pad from chemically reacting with the mist or the air, and further to avoid an electrical erosion state. Therefore the signal of the probe can still be transmitted through the conductive layer. | 2009-01-22 |
20090020768 | BURIED CONTACT DEVICES FOR NITRIDE-BASED FILMS AND MANUFACTURE THEREOF - A semiconductor device comprising: a substrate; a first contact; a first layer of doped semiconductor material deposited on the substrate; a semiconductor junction region deposited on the first layer; a second layer of doped semiconductor material deposited on the junction region, the second layer having opposite semiconductor doping polarity to that of the first layer; and a second contact; wherein the second contact is in electrical communication with the second layer and the first contact is embedded within the semiconductor device between the substrate and the junction region and is in electrical communication with the first layer; and processes for manufacture of an embedded contact semiconductor device. | 2009-01-22 |
20090020769 | Semiconductor light emitting element - A semiconductor light emitting element having a rectangular shape in plan view comprising at least a first side and a second side adjacent to the first side, the semiconductor light emitting element including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, a plurality of first electrodes having a long shape along the first side and being arranged on the first conductivity-type semiconductor layer in a lattice form of x columns (x≧2) along the first side and y rows (y>x) along the second side, and a second electrode arranged on the second conductivity-type semiconductor layer. The first electrode and the second electrode are arranged on the same surface side. The first electrode is surrounded by the first conductivity-type semiconductor layer, the second conductivity-type semiconductor layer, and the second electrode is provided. | 2009-01-22 |
20090020770 | LED CHIP PACKAGE STRUCTURE WITH HIGH-EFFICIENCY LIGHT-EMITTING EFFECT AND METHOD OF PACKAGING THE SAME - An LED chip package structure with high-efficiency light-emitting effect includes a substrate unit, a light-emitting unit, and a package colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace respectively formed on the substrate body. The light-emitting unit has a plurality of LED chips arranged on the substrate body, and each LED chip has a positive electrode side and a negative electrode side respectively and electrically connected with the positive electrode trace and the negative electrode trace of the substrate unit. The package colloid unit has a plurality of package colloids respectively covered on the LED chips. | 2009-01-22 |
20090020771 | III-Nitride Semiconductor Light Emitting Device And Method For Manufacturing The Same - The present disclosure relates to an III-nitride compound semiconductor light emitting device and a method of manufacturing the same. The III-nitride compound semiconductor light emitting device includes a substrate with a groove formed therein, a plurality of nitride compound semiconductor layers being grown on the substrate, and including an active layer for generating light by recombination of electron and hole, and an opening formed on the groove along the plurality of nitride compound semiconductor layers. | 2009-01-22 |
20090020772 | LIGHT-EMITTING DEVICE AND METHOD FOR MAKING THE SAME - A light-emitting device is capable of emitting a light having a wavelength ranging from 300 to 550 nm, and includes: a substrate; a p-type semiconductor layer disposed on the substrate; an active layer disposed on the p-type semiconductor layer; a n-type semiconductor layer disposed on the active layer and having a waveguide-disposing surface; and a waveguide structure formed on the waveguide-disposing surface of the n-type semiconductor layer and having a plurality of spaced apart nanorods extending from the waveguide-disposing surface. | 2009-01-22 |
20090020773 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor light emitting device. The method includes: mounting a semiconductor light emitting element on a flat substrate; covering the semiconductor light emitting element on the flat substrate by a cover layer in a domed shape to form a light emitting device, the cover layer including at least a phosphor layer and a coating resin layer that are laminated in order, so as to fill around the semiconductor light emitting element; measuring an emission condition of the light emitting device; and forming a convex lens unit on the outermost of the coating resin layer using a liquid droplet discharging apparatus to adjust an emission distribution of the light emitting device based on the measured emission condition. | 2009-01-22 |
20090020774 | PACKAGE OF LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - Provided is a package of a light emitting diode. The package includes a metal plate, a light-emitting diode chip, an insulating layer, a lead frame, a reflective coating layer, and a molding material. The light-emitting diode chip is surface-mounted on the metal plate, and the insulating layer is formed on the metal plate and is separated from the light-emitting diode chip. The lead frame is provided on the insulating layer, the reflective coating layer is formed on the lead frame, and the molding material molds the light-emitting diode chip in a predetermined shape. | 2009-01-22 |
20090020775 | RED LINE EMITTING COMPLEX FLUORIDE PHOSPHORS ACTIVATED WITH Mn4+ - New phosphor materials including a complex fluoride phosphor activated with Mn | 2009-01-22 |
20090020776 | Light-emitting device - A light-emitting device comprises a channel structure in the semiconductor layer for connecting an electrode and an ohmic contact layer by means of a substrate transfer process including a wafer-bonding process and a substrate-lifting-off process. The channel structure is formed in the semiconductor stack for electrically connecting the ohmic contact layer and the electrode and driving the current into the light-emitting device. Thereby, a horizontal type or a vertical type of light-emitting device has a good ohmic contact and high light efficiency. | 2009-01-22 |
20090020777 | VERTICAL RESONATOR TYPE LIGHT EMITTING DIODE - A novel vertical resonator type light emitting diode of which has a simplified structure of the reflector layer of its light emitting side an which is resistant to declination of its emission output power towards a high temperature range, has an active layer | 2009-01-22 |
20090020778 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The light emitting device | 2009-01-22 |
20090020779 | Method of preparing a sealed light-emitting diode chip - A method for producing a light emitting diode chip encapsulation product, the method comprising covering a light emitting diode chip connected onto a substrate with a thermosetting film, and thermally curing the thermosetting film. | 2009-01-22 |
20090020780 | LIGHT EMITTING DIODE WITH IMPROVED STRUCTURE - Disclosed is a light emitting diode (LED) with an improved structure. The LED comprises an N-type semiconductor layer, a P-type semiconductor layer and an active layer interposed between the N-type and P-type semiconductor layers. The P-type compound semiconductor layer has a laminated structure comprising a P-type clad layer positioned on the active layer, a hole injection layer positioned on the P-type clad layer, and a P-type contact layer positioned on the hole injection layer. Accordingly, holes are more smoothly injected into the active layer from the P-type semiconductor layer, thereby improving the recombination rate of electrons and holes. | 2009-01-22 |
20090020781 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING SAME - An exemplary nitride-based semiconductor light emitting device includes a substrate, a nitride-based multi-layered structure epitaxially formed on the substrate, a first-type electrode and a second-type electrode. The multi-layered structure includes a first-type layer, an active layer, and a second-type layer. The multi-layered structure has a developed mesa structure which at least includes the second-type layer and the active layer and whereby the first-type layer is partially exposed to form an exposed portion. The mesa structure has a roughened top surface and a plurality of roughened side surfaces adjoining the top surface. A crystal growth orientation of the multi-layered structure intersects with <0001 > crystal orientation thereof. The first-type electrode and the second-type electrode respectively come into ohmic contact with the first-type layer and the second-type layer. | 2009-01-22 |
20090020782 | Avalanche Photodiode With Edge Breakdown Suppression - The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source. The result is that both the dopant concentration and the diffusion depth decrease gradually from the center to the edge of the device. This tailored diffusion profile enables control of the electric field distribution such that edge breakdown is suppressed. | 2009-01-22 |
20090020783 | TRANSISTOR WITH DIFFERENTLY DOPED STRAINED CURRENT ELECTRODE REGION - A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively. | 2009-01-22 |
20090020784 | METHOD FOR DESIGNING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS. | 2009-01-22 |
20090020785 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s). | 2009-01-22 |
20090020786 | SEMICONDUCTOR DEVICE - A method for forming a semiconductor device on a substrate having a first major surface lying in a plane and the semiconductor device are disclosed. In one aspect, the method comprises, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to a major surface of the substrate, forming locally modified regions at locations in the substrate not covered by the structure, thus locally increasing etching resistance of these regions. Forming locally modified regions may prevent under-etching of the structure during further process steps in the formation of the semiconductor device. | 2009-01-22 |
20090020787 | SEMICONDUCTOR DEVICE USING SEMICONDUCTOR NANOWIRE AND DISPLAY APPARATUS AND IMAGE PICK-UP APPARATUS USING THE SAME - A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at least a part of the second region via an insulating layer. The semiconductor nanowire has a P-type semiconductor portion and an N-type semiconductor portion, and one of the P-type semiconductor portion and the N-type semiconductor portion is a common structural element of both the first and second regions. | 2009-01-22 |
20090020788 | METHOD OF IMPROVING SOLID-STATE IMAGE SENSOR SENSITIVITY - An imaging apparatus includes (a) a full-frame, charge-coupled device having (i) a conductive layer of a first dopant type; (ii) a plurality of pixels arranged as a charge-coupled device in the conductive layer that collects charge in response to incident light and transfers the collected charge; (iii) an overflow drain of a dopant type opposite the first type disposed in the conductive layer and laterally adjacent to each pixel; and the apparatus having (b) a voltage supply connected to the lateral overflow drain that is at a first voltage during readout and at a second voltage that is lower than the first voltage during integration. | 2009-01-22 |
20090020789 | CHARGE TRANSFER DEVICE AND IMAGING APPARATUS - An HCCD includes a channel | 2009-01-22 |
20090020790 | METHOD FOR FABRICATING POLYSILICON FILM, A GAS PHASE DEPOSITION APPARATUS AND AN ELECTRONIC DEVICE FORMED THEREBY - A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage. | 2009-01-22 |
20090020791 | PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT ETCH-STOP LINER LAYERS - Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion. | 2009-01-22 |
20090020792 | ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE - A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours. | 2009-01-22 |
20090020793 | FIELD EFFECT TRANSISTOR - A transistor comprising
| 2009-01-22 |
20090020794 | Image Sensor and Method of Manufacturing the Same - Provided are an image sensor and a method of manufacturing the same. The image sensor can be vertically arranged image sensor where the photodiode is provided above the circuitry on the substrate. The photodiode can be formed on a lower electrode provided electrically connected to a CMOS circuit on a substrate. The photodiode can have a PIN or PI photodiode structure including an intrinsic layer on the lower electrode and a conductive type layer on the intrinsic layer. A salicide layer can be disposed on the intrinsic layer, and the conductive type conduction layer can be disposed on the salicide layer. The intrinsic layer can be formed to create a light condensing portion, providing a convex-shaped upper surface. | 2009-01-22 |
20090020795 | SOLID-STATE IMAGING ELEMENT AND METHOD FOR FABRICATING THE SAME - A solid-state imaging element includes a photodiode formed in an upper portion of a semiconductor substrate to perform a photoelectric conversion, a silicon dioxide film formed on the substrate to cover the photodiode, and a silicon nitride film formed on the silicon dioxide film. The silicon nitride film has a thinner portion smaller in thickness than at least an end portion of the silicon nitride film entirely or partly over the photodiode. | 2009-01-22 |
20090020796 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGING SYSTEM USING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device includes photoelectric conversion elements and element isolation regions, both of which are arranged on a semiconductor substrate. The photoelectric conversion device further includes a plurality of interlayer insulation layers including a first interlayer insulation layer arranged nearest to the semiconductor substrate, and a second interlayer insulation layer arranged to cover the first interlayer insulation layer. Gaps extending from at least the second interlayer insulation layer to the first interlayer insulation layer are arranged in first and second interlayer insulation layer regions corresponding to the element isolation regions. | 2009-01-22 |
20090020797 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer ( | 2009-01-22 |
20090020798 | TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region. | 2009-01-22 |
20090020799 | Semiconductor device and method of manufacturing the same - One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films. | 2009-01-22 |
20090020800 | Semiconductor Device and Method of Making Same - A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly. | 2009-01-22 |
20090020801 | TWO-BIT FLASH MEMORY CELL STRUCTURE AND METHOD OF MAKING THE SAME - A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P | 2009-01-22 |
20090020802 | INTEGRATED SCHEME FOR FORMING INTER-POLY DIELECTRICS FOR NON-VOLATILE MEMORY DEVICES - Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride. | 2009-01-22 |
20090020803 | AGING DEVICE - An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate. | 2009-01-22 |
20090020804 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same. The semiconductor device includes a gate pattern formed on a semiconductor substrate, a first impurity-doped region formed in the substrate on one side of the gate pattern and a second impurity-doped region formed in the substrate on the other side of the gate pattern, a salicide shielding film pattern partially covering either the first impurity-doped region or the second impurity-doped region, an insulating film formed on the semiconductor substrate, the insulating film including a first hole which exposes the salicide shielding film pattern, and a second hole which partially exposes the first impurity-doped region or the second impurity-doped region that is not covered by the salicide shielding film pattern, and a first line coming in contact with the salicide shielding film pattern through the first hole. | 2009-01-22 |
20090020805 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced. | 2009-01-22 |
20090020806 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 2009-01-22 |
20090020807 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a semiconductor device and a method for fabrication of the same. The fabrication method may include selectively forming an oxide layer pattern on a semiconductor substrate, forming an insulation layer pattern on the same substrate to cover edge portions of the oxide layer pattern, etching the oxide layer pattern and the substrate to form a recess as well as first and second oxide layer patterns corresponding to the edge portions of the oxide layer pattern, forming a third oxide layer pattern on the substrate in the recess to produce a gate insulation layer comprising the first, second, and third oxide layer patterns, and forming a gate pattern in the recess. The fabricated semiconductor device minimizes occurrence of current leakage such as gate induction drain leakage, among other things, thereby improving transistor performance. | 2009-01-22 |
20090020808 | Semiconductor integrated circuit devices and fabrication methods thereof - A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material. | 2009-01-22 |
20090020809 | Semiconductor device including trench gate transistor and method of forming the same - A semiconductor device includes an active region having a groove, a gate insulating film, and a gate electrode. The gate electrode may include first and second layers. The first layer extends along the gate insulating film. The first layer is electrically conductive. The second layer extends along the first layer. The second layer is separate from the gate insulating film by the first layer. | 2009-01-22 |
20090020810 | Method of Forming Power Device Utilizing Chemical Mechanical Planarization - A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench. | 2009-01-22 |
20090020811 | GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION - A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions. | 2009-01-22 |