| 03rd week of 2010 patent applcation highlights part 62 |
| Patent application number | Title | Published |
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| 20100017596 | System and method for managing authentication cookie encryption keys - There is provided a system and method for managing authentication cookie encryption keys. The system comprises a computing device including a memory with authentication data having a key identifier and encrypted data with a session identifier. The key identifier references a key having a validity period, the key capable of decrypting the authentication data. A processor of the computing device can respond to user requests for information by retrieving the authentication data and transmitting it to a server. The server can then authenticate the user by verifying the encrypted session identifier using the referenced key. There is also provided a method by which a key server can manage encryption keys. The key server receives an encryption key having a validity period, receives a validity request, confirms or rejects the validity of the encryption key, and automatically invalidates the encryption key upon expiration of the validity period. | 2010-01-21 |
| 20100017597 | SECURE NETWORK ADDRESS PROVISIONING - A network in which a client receives a network credential, such as a valid network address, following an exchange of messages with a credential server that includes security information. The security information may validate the credential, avoiding rogue devices inadvertently or maliciously distributing credential information that can interfere with clients attempting to connect to the network or with the network itself. If obtaining a network credential requires an exchange of information about the configuration of the client that could reveal security vulnerabilities, the security information may be used to ensure the confidentiality of that configuration information. The security information may be incorporated into messages according to a known protocol, such as by incorporating it into options fields of DHCP messages. | 2010-01-21 |
| 20100017598 | Secure E-Mail Messaging System - According to one embodiment, a secure e-mail messaging system includes an e-mail relay server coupled to a secure client configured on a secure domain and an external client configured on an external domain. The e-mail relay server has a memory for storage of an actual address of the secure client, a first certificate associated with the actual address, an alias address associated with the actual address, and a second certificate associated with the alias address. The e-mail relay server receives an e-mail message that includes the alias address from the external client and decrypts the e-mail message according to the second certificate. The e-mail messaging server then replaces the alias address with the actual address to form a modified e-mail message, encrypts the modified e-mail message according to the first certificate, and transmits the modified e-mail message to the secure client. | 2010-01-21 |
| 20100017599 | SECURE DIGITAL CONTENT MANAGEMENT USING MUTATING IDENTIFIERS - Methods and system for managing manipulation of digital content stored in a content server. One method includes receiving a first mutating identifier at a content manipulation device. The first mutating identifier includes a first secret key. The method also includes generating a content request for digital content stored in the content server at the content manipulation device, the content request encrypted with the first secret key and including an identifier of the digital content; transmitting the content request to an authenticator over at least one communication link; transmitting access rights from the authenticator to the content manipulation device over at least one communication link; transmitting the digital content from the content server to the content manipulation device; manipulating the digital content at the content manipulation device based on the access rights; and marking the first mutating identifier as used at the authenticator. | 2010-01-21 |
| 20100017600 | SECURE NEIGHBOR CACHE PRELOAD - The present invention relates to methods, apparatus, and systems for implementing a secure neighbor cache preload. The method includes initiating a data transfer request. The data transfer request is associated with a sequence of bytes. Further, receiving bytes associated with the data transfer request. Further, the method includes storing the bytes in the client system's personal cache, and processing the data transfer request through a filtering system. The filtering system is configured to determine whether the sequence of bytes is to be relayed to the plurality of clients. Then, based on the data transfer request passing through the filtering system, echoing the sequence of bytes to the plurality of client systems within the LAN using an Internet protocol (IP) broadcast operation, and storing within each of the plurality of client systems' public caches at least a portion of the relayed sequence of bytes associated with the data transfer request. | 2010-01-21 |
| 20100017601 | Method and Server for Providing a Mobility Key - A method and authentication server provide a mobile key. According to the method, upon receipt of an authentication message (access authentication) that is transmitted when a subscriber logs on to the network, the authentication server extracts a subscriber identification contained in said message and generates a corresponding mobile key, which is stored together with the respective extracted subscriber identification. Upon subsequent receipt of a key request message (key request) that is transmitted when a subscriber registers, the authentication server extracts a mobile identification of the subscriber contained in said message and searches for an identical mobile identification, which can be derived in accordance with a configurable derivation function from a subscriber identification that is stored in the authentication server. Once a derived mobile identification that is identical or can be uniquely assigned to the extracted mobile identification has been found, the authentication server provides the stored corresponding mobile key that has been generated, to cryptographically protect the mobile signaling messages of the registered subscriber. | 2010-01-21 |
| 20100017602 | Ad-Hoc Trust Establishment Using Visual Verification - Methods for ad-hoc trust establishment using visual verification are described. In a first embodiment, a visual representation of a shared data is generated on two or more devices and the visual representations generated can be visually compared by a user. This method can be used to verify that the correct devices are involved in a negotiation, when pre-existing trust relationships do not exist between the devices. The visual representation may, for example, comprise a picture with a number of different elements, each representing a part of the shared data. In another embodiment, a method of secure key exchange is described in which, before sharing the keys, the parties exchange information which encapsulates the key. This information can be used subsequently to check that a party has not changed the key that they are using and prevents a man in the middle attack. | 2010-01-21 |
| 20100017603 | Extensible Authentication Protocol Authentication and Key Agreement (EAP-AKA) Optimization - Systems and methods are described for improved authentication of subscribers wishing to connect to a wireless network using the EAP-AKA protocol. Embodiments exploit the requirement that the client store and transmit the Pseudonym and Fast Re-authentication Identities upon request. By using the Fast Re-authentication Identity to store session state key information, the need for the AAA server to store and replicate the EAP-AKA key information for every session is eliminated. | 2010-01-21 |
| 20100017604 | METHOD, SYSTEM AND DEVICE FOR SYNCHRONIZING BETWEEN SERVER AND MOBILE DEVICE - An arrangement and corresponding method for authentication synchronizing cryptographic key information between a server and a client device, via data signals, where the client device at least comprises one client. The server is at least configured to generate and send to the client device a current encryption key and a next encryption key. The client device is at least configured to encrypt information on the client device using the next encryption key and the client device is at least configured to return a correct One Time Password using the current encryption key. As a consequence of the received correct One Time Password the server then knows that the client has received the current encryption key, used it and stored the information with the next encryption key. | 2010-01-21 |
| 20100017605 | METHOD OF DETECTING AN ABNORMAL USE OF A SECURITY PROCESSOR - The invention relates to a method of detecting an abnormal use of a security processor invoked by at least one receiving terminal in order to control access to a scrambled digital content supplied by at least one operator to said receiving terminal. | 2010-01-21 |
| 20100017606 | Interoperable systems and methods for peer-to-peer service orchestration - Systems and methods are described for performing policy-managed, peer-to-peer service orchestration in a manner that supports the formation of self-organizing service networks that enable rich media experiences. In one embodiment, services are distributed across peer-to-peer communicating nodes, and each node provides message routing and orchestration using a message pump and workflow collator. Distributed policy management of service interfaces helps to provide trust and security, supporting commercial exchange of value. Peer-to-peer messaging and workflow collation allow services to be dynamically created from a heterogeneous set of primitive services. The shared resources are services of many different types, using different service interface bindings beyond those typically supported in a web service deployments built on UDDI, SOAP, and WSDL. In a preferred embodiment, a media services framework is provided that enables nodes to find one another, interact, exchange value, and cooperate across tiers of networks from WANs to PAs. | 2010-01-21 |
| 20100017607 | METHODS AND SYSTEMS TO RESOLVE MESSAGE GROUP - A method and system for resolving addresses of a message including looking up, from a source directory, a group name associated with a message address of the message, looking up through a cache of user names mapped to user addresses, a user address for each of the looked up user names and returning an associated user address, and addressing the message to each looked up user addresses. Expanding group address by looking up user name in for group from source directory, looking up user address for each user name from user cache, addressing message to looked up user, address, and transmitting message to looked up user address. | 2010-01-21 |
| 20100017608 | Distributed Network Management Hierarchy in a Multi-Station Communication Network - The invention relates to a network and to a method of operating a network. The network comprises a plurality of stations each able to transmit and receive data so that the network can transmit data between stations via at least one selected intermediate station. The network further comprises a plurality of levels of stations including a first level comprising user and/or seed stations, a second level comprising auxiliary stations providing access to auxiliary networks, a third level comprising at least one location management station, and a fourth level comprising at least one authentication station. The method comprises transmitting, from or on behalf of a station on the first level requiring authentication, to an authentication station via one or more stations, an authentication request message. In response, the authentication station transmits authentication data via one or more stations to the station on the first level to authenticate the station on the first level. The authentication station maintains a record of each authenticated station on the first level. A location management station monitors the location of each authenticated station on the first level with respect to its connectivity, whether directly or indirectly, with one or more stations on the second level. Where a station on the first level attempts to communicate with another station on any level and is assisted by a station on another level, the assisting station transmits connectivity data directly, or indirectly via other stations, to the station on the first level and/or to an intermediate station. | 2010-01-21 |
| 20100017609 | METHOD AND DEVICE FOR CONTROLLING AND MANAGING COMPRESSED AND FREELY DOWNLOADED MULTIMEDIA FILES - The present invention relates to a method for controlling the distribution and use of digital multimedia files composed of binary data blocks according to an original format, and separated into at least two parts, characterised in that it includes a step of transmission, from a server of utilisation conditions, of the preferred parameters for the reconstruction of the whole or a part of said original file on a terminal. | 2010-01-21 |
| 20100017610 | Authentication system - An authentication system determines if a counterfeit ineligible unit is installed in a main device. When connected with a battery pack, a notebook PC generates and combines a random number and a function determination signal using a signal combining unit and transmits same to the battery pack. A first function calculation unit calculates the function of the random number. The battery pack has a signal separation unit to separate the combined signal into the random number and function determination signal, and a second function calculation unit to calculate the function of the random number for transmitting back to the notebook PC. A comparison unit compares the calculation results by the first and second function calculation units to determine whether the connected battery pack is an authorized one and denies connection if the pack is an unauthorized one. | 2010-01-21 |
| 20100017611 | Authentication system - An authentication system determines if a counterfeit ineligible unit is installed in a main device. When connected with a battery pack, a notebook PC generates and combines a random number and a function determination signal using a signal combining unit and transmits same to the battery pack. A first function calculation unit calculates the function of the random number. The battery pack has a signal separation unit to separate the combined signal into the random number and function determination signal, and a second function calculation unit to calculate the function of the random number for transmitting back to the notebook PC. A comparison unit compares the calculation results by the first and second function calculation units to determine whether the connected battery pack is an authorized one and denies connection if the pack is an unauthorized one. | 2010-01-21 |
| 20100017612 | Electronic Apparatus and Communication System - According to one embodiment, an electronic apparatus includes a display process unit and a data transmission process unit. The display process unit is configured to display connection confirmation information, which is known to a user and is transmitted from a device via a network during a connection establishing process for establishing connection between the device and an electronic apparatus, on a display screen of the electronic apparatus. The data transmission process unit is configured to start a process of transmitting the data that is to be kept secret to the device via the network in response to a predetermined user operation which indicates that the user has confirmed that the connection confirmation information displayed on the display screen is correct. | 2010-01-21 |
| 20100017613 | DUAL USAGE SMART CARD OF CPU AND LOGICAL ENCRYPTION AND ITS DATA SYNCHRONIZATION METHOD - A dual usage smart card of CPU and logical encryption and its data synchronization method. Said method comprises that a CPU command processing module controls an accessing control module for the logical encryption storage region to read the data in the logical encryption storage region to a data format conversion module; said data format conversion module transmits the data to the CPU control storage region; the CPU command processing module controls the CPU control storage region again to transmit the data of CPU card to the accessing control module for the logical encryption storage region through the data format conversion module; and said accessing control module for the logical encryption storage region writes the data of CPU card into the logical encryption storage region. | 2010-01-21 |
| 20100017614 | ENCODING AND DETECTING APPARATUS - An encoding data processing apparatus generates a video material item marked copy by embedding a payload data word into the video material item. The video material item includes plural video frames. A code word generator generates a water mark code word from the payload data word and reads data representing the water mark code word into a shuffle data store. A shuffle processor generates pseudo randomly at least one address within an address space of the shuffle data store for each video frame and reads data representing part or parts of the water mark code word out from the data store at locations identified by the pseudo randomly generated address. A data embedding processor receives the video material item and embeds the data representing the part or parts of the water mark code word read out from the shuffle data store for each frame into a corresponding frame of the video material item. | 2010-01-21 |
| 20100017615 | DIGITAL DATA AUTHENTICATION - A method for protecting a digital document and user data typed into a digital document is presented. The method comprises computation of an authentication tag when the document is sent from a server. A similar authentication tag is computed when the document is shown on a client. When another document referenced in the document is requested by the client from the server, the authentication tag computed by the client is attached to the request for that other document. The server receiving the request compares the authentication tag it computed with the one it received to verify if the request came from an authentic copy of the document. The method is suitable for protection of online banking, online investment, online shopping, and other electronic applications. | 2010-01-21 |
| 20100017616 | WEB BASED SYSTEM THAT ALLOWS USERS TO LOG INTO WEBSITES WITHOUT ENTERING USERNAME AND PASSWORD INFORMATION - Systems and methods for securely managing Internet user passwords are presented herein. A formation component can enable a user to create a master account on a web server, the master account comprising a master username and password. An access component can enable the user to access a plurality of password protected websites from a web browser or non-browser software application resident on the user's computing device when the user logs into the master account by entering the valid master username and password. A selection component can log the user into a website of the plurality of password protected websites when the user selects a hyperlink associated with the website, selects a linked image associated with the website, or selects the website from a pulldown list contained in a toolbar of a web browser. A display component can open a web browser or tab associated with the website. | 2010-01-21 |
| 20100017617 | RADIO FREQUENCY IDENTIFICATION (RFID) SECURITY APPARATUS HAVING SECURITY FUNCTION AND METHOD THEREOF - Disclosed are a radio frequency identification (RFID) security apparatus and a method thereof. According to the RFID security method, a secure tag reader performs determining an AES key using security information received from a secure tag and generating an output key using the determined AES key, decrypting AES data received from the secure tag using the output key, and encrypting data to be transmitted to the secure tag using the output key and transmitting the data, and a secure tag performs generating an output key using an AES key and security information, and transmitting the security information to a secure tag reader, encrypting data to be transmitted to the secure tag reader using the output key, and transmitting the encrypted data to the secure tag reader, and decrypting data received from the secure tag reader using the output key. | 2010-01-21 |
| 20100017618 | METHOD AND SYSTEM FOR BIOMETRIC AUTHENTICATION AND ENCRYPTION - A biometric user authentication method, includes enrolling a user based on user's biometric samples to generate user's reference data; and authenticating the user based on a user's live biometric sample and the user's reference data; wherein enrolling a user includes acquiring the user's biometric samples; extracting an enrollment feature vector from each user's biometric sample; computing a biometric reference template vector as a mean vector based on the enrollment feature vectors; computing a variation vector based on the enrollment feature vectors and the mean vector; randomly generating an enrollment secret vector; computing an enrollment code vector based on the enrollment secret vector and the variation vector; computing a difference vector as a wrap-around difference between the enrollment code vector and the mean vector; computing an error correction vector based on the enrollment secret vector to enable error correction during the user authentication phase according to a given error tolerance level, wherein the error correction vector is not computed if the error tolerance level is equal to zero; and storing the variation vector, the difference vector, and the error correction vector as a part of the user's reference data to be used during the user authentication phase. | 2010-01-21 |
| 20100017619 | SYSTEMS AND METHODS FOR SECURE AND AUTHENTIC ELECTRONIC COLLABORATION - The present disclosure relates to systems and methods for secure and authentic electronic collaboration between a plurality of users using a combination of biometric security, a separate and secure network infrastructure, management processes, encrypted electronic storage, and collaborative templates. In an exemplary embodiment, an online collaboration system includes a server including a network interface connected to the Internet, a data store including electronic data storage, and a processor, wherein each of the network interface, the data store and the processor are communicatively coupled, and wherein the network interface, the data store and the processor are collectively configured to: biometrically authenticate a plurality of users; and enable online collaboration between the plurality of users. | 2010-01-21 |
| 20100017620 | SOFTWARE SELF-CHECKING SYSTEMS AND METHODS - Software self-checking mechanisms are described for improving software tamper resistance and/or reliability. Redundant tests are performed to detect modifications to a program while it is running. Modifications are recorded or reported. Embodiments of the software self-checking mechanisms can be implemented such that they are relatively stealthy and robust, and so that it they are compatible with copy-specific static watermarking and other tamper-resistance techniques. | 2010-01-21 |
| 20100017621 | RADIO TRANSCEIVER OR OTHER ENCRYPTION DEVICE HAVING SECURE TAMPER-DETECTION MODULE - An encryption device includes a system processor having a first key for encrypting information. The system processor periodically generates random data strings that are also encrypted using the first key. The encryption device also includes a first output for communicating the encrypted information to an external location and a tamper detection module for receiving on a periodic basis the random data strings generated by the system processor. The tamper detection module includes a second key that is the same as the first key, an encryption engine for encrypting the random data strings using the second key, and a second output for communicating the encrypted data strings to the system processor. The tamper detection module is configured to alter the second key upon detection of a tampering event so that the second key is different from the first key. | 2010-01-21 |
| 20100017622 | High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks - The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device. | 2010-01-21 |
| 20100017623 | Executable software security system - A computer system which is configured to load executable programs. This configuration first accepts an operator defined key; withdraws an encrypted executable program from memory; and, using the operator defined key, decrypts the encrypted executable program into a functional executable program. It is this functional executable program which is used by the processing unit. During shutdown, each executable program is checked to see if it was derived from an encrypted executable program; those that aren't, are verified as being legitimate by the operator prior to their storage into the memory. | 2010-01-21 |
| 20100017624 | From polymorphic executable to polymorphic operating system - A method, capable of being implemented in executable instructions or programmes in device(s), including computer system(s) or computer-controlled device(s) or operating-system-controlled device(s) or system(s) that is/are capable of running executable code, providing for the creation in Device(s) of executable code, such as boot code, programmes, applications, device drivers, or a collection of such executables constituting an operating system, in the form of executable code embedded or stored into hardware, such as embedded or stored in all types of storage medium, including read-only or rewriteable or volatile or non-volatile storage medium, such as in the form of virtual disk in physical memory or internal Dynamic Random Access Memory or hard disk or solid state flash disk or Read Only Memory, or read only or rewriteable CD/DVD/HD-DVD/Blu-Ray DVD or hardware chip or chipset etc.; the executable code being in the form of Polymorphic Executable (PE) or Executable with Unexecutable Code (EUC) or Polymorphic Executable with Unexecutable Code (PEUC) or Polymorphic Operating System (POS) containing PE, EUC and PEUC runnable in an authenticated or authorized state for the protection of intellectual property. | 2010-01-21 |
| 20100017625 | ARCHITECURE, SYSTEM, AND METHOD FOR OPERATING ON ENCRYPTED AND/OR HIDDEN INFORMATION - An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to keep such code inaccessible to users and user-controlled software programs. A memory architecture includes first and second protected memory spaces, respectively storing operating system instructions and a decrypted version of the encrypted information. The first protected memory space may further store a table linking the locations of the encrypted and/or hidden, decrypted information with a decryption and/or authorization key. The system includes the memory architecture and a processor for executing instructions, and the method loads, stores and operates on the encrypted and/or hidden information according to the memory architecture functionality and/or constraints. | 2010-01-21 |
| 20100017626 | INFORMATION PROCESSING APPARATUS, AUTHENTICATION METHOD, AND STORAGE MEDIUM - According to one embodiment, a storage medium comprises an encrypted content, key management information which is updated whenever necessary and includes a media key block including encrypted media keys obtained by encrypting a media key which is a base of an authentication key used for mutual authentication with another apparatus by using different device keys, and first and second application keys which encrypt the title keys for each application of the content and are alternately updated and encrypted when the key management information is updated. | 2010-01-21 |
| 20100017627 | ENSURING AUTHENTICITY IN A CLOSED CONTENT DISTRIBUTION SYSTEM - A technique for maintaining encrypted content received over a network in a secure processor without exposing a key used to decrypt the content in the clear is disclosed. | 2010-01-21 |
| 20100017628 | Systems for Using Different Power Supply Configurations with a Common Motherboard - In some embodiments, an information handling system may include a motherboard including a processor and memory coupled to the processor; one or more power supply units configured to provide power to the motherboard; and a connection system configured to deliver voltage from the one or more power supply units to the motherboard in both: (a) a first configuration including a single power supply unit providing power to the motherboard; and (b) a second configuration including multiple power supply units providing power to the motherboard. | 2010-01-21 |
| 20100017629 | FILE SHARING APPARATUS AND FILE SHARING SYSTEM - There is provided a file sharing system which allows accessing a memory that stores failure information and using the failure information even in a case where a CPU is shut down. When a failure occurs on a substrate, a control circuit on the substrate detects the failure and stores the information on the failure to an NVRAM. In a normal case, an OS loads the failure information and transmits it to a PC for maintenance. Upon shut down of the OS, a BMC loads the failure information from the NVRAM according to an instruction from the PC for maintenance. If an operator operates a manual switch upon power shut down, the BMC operates with the power supply from a battery, and the failure information is obtained from the NVRAM. | 2010-01-21 |
| 20100017630 | POWER CONTROL SYSTEM OF A HIGH DENSITY SERVER AND METHOD THEREOF - A power control system of a server system is described. The power control system includes a plurality of server motherboards, a power supply and a micro controller. Each server motherboard comprises a BIOS, a power switch and a baseboard management controller (BMC), wherein each power switch is operable to selectively switch on or switch off a power supplying of each corresponding server motherboard, and each BMC is operable to output a status order in response to a control information of each corresponding BIOS. The power supply is electrically connected to all the power switches of all the server motherboards and operable to supply power to all the server motherboards. The micro controller is electrically connected to all the BMCs and operable to order the power switches to selectively switch on or switch off a power supplying of each corresponding server motherboard in response to the status order. | 2010-01-21 |
| 20100017631 | Detection Algorithm for Delivering Inline Power Down Four Pairs of an Ethernet Cable to a Single Powered Device - Methods and apparatus for determining that all conductors of an Ethernet connection are connected to the same powered device (PD). In one disclosed embodiment, it is first determined that a signal conductor pair of the Ethernet connection is coupled to a valid PD according to a discovery process, and the unused conductor pair of the Ethernet connection is also coupled to a valid PD. However, it is not yet determined whether they are both coupled to the same PD. This disclosure provides for injecting a polluting signal into one of the conductor pairs, and performing the discovery process on the other conductor pair. If the discovery process fails on the other conductor pair as a result of the polluting signal, then it is determined that both of the conductor pairs are indeed coupled to same PD. | 2010-01-21 |
| 20100017632 | Managing Power-Consumption - Managing power-consumption, for use in a storage system comprising first data stored on one or more storage devices is provided. A receiver receives a policy comprising a power-management parameter, a first parameter and a rule associated with the policy. An analyser, responsive to receipt of a policy, analyzes second data associated with the rule. A determiner, responsive to the analysis, determines third data in accordance with the second data. The third data is associated with migration of the first data. | 2010-01-21 |
| 20100017633 | MEMORY DEVICE, CONTROL DEVICE FOR MEMORY DEVICE, AND CONTROL METHOD FOR MEMORY DEVICE - According to one embodiment, a control device includes: a calculation module acquiring at least one of speed information, and calculating a process time taken to write data group when the acquired speed information is used, each of the speed information corresponding to different swing speed; a selection module selecting one of the speed information based on the acquired speed information and the process time thereof; and a control module controlling a memory medium driving module, controlling the writing module to write the data group when the memory medium driving module is in operation, storing the data group in the memory module when the memory medium driving module is not in operation, controlling the swing module on the basis of the selected speed information, and controlling the writing module to write the data group stored in the memory module. | 2010-01-21 |
| 20100017634 | DUAL-MODE COMMUNICATION APPARATUS AND POWER MANAGEMENT METHOD THEREOF - A dual-mode communication apparatus and a method thereof are provided. The dual-mode communication apparatus comprises a microprocessor, a first tick generator, a second tick generator, and an operation system tick module that comprises a tick converter and an OS tick generator. The microprocessor receives an OS clock tick to execute a real-time program task. The first tick generator receives a first predetermined number of first clocks to generate a first clock tick when the first clock is active. The second tick generator receives a second predetermined number of second clocks to generate a second clock tick when the second clock is active. The tick converter, coupled to the first and second tick generators, converts the second clock tick such that the converted second clock tick has a converted clock tick rate substantially identical to the clock tick rate of the first clock tick. The OS tick generator, coupled to the tick converter, receives the first clock tick and the converted second clock tick to generate the OS clock tick for use in the microprocessor. | 2010-01-21 |
| 20100017635 | ZERO INDICATION FORWARDING FOR FLOATING POINT UNIT POWER REDUCTION - A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations. | 2010-01-21 |
| 20100017636 | POWER SUPPLY SYSTEM - In a power supply system having: a processor | 2010-01-21 |
| 20100017637 | PORTABLE ELECTRONIC TERMINAL AND METHOD THEREFOR - A portable electronic terminal capable of changing to an idle or sleep mode during which selective powering of portions of the electronics of the terminal takes place to save energy, the terminal comprising:—at least one memory storing, when in the idle or sleep mode, a program code of a background task and data necessary for the execution of the background task,—a calculator ( | 2010-01-21 |
| 20100017638 | System and Method for Reducing Power Requirements of Microprocessors Through Dynamic Allocation of Datapath Resources - There is provided a system and methods for segmenting datapath resources such as reorder buffers, physical registers, instruction queues and load-store queues, etc. in a microprocessor so that their size may be dynamically expanded and contracted. This is accomplished by allocating and deallocating individual resource units to each resource based on sampled estimates of the instantaneous resource needs of the program running on the microprocessor. By keeping unused datapath resources to a minimum, power and energy savings are achieved by shutting off resource units that are not needed for sustaining the performance requirements of the running program. Leakage energy and switching energy and power are reduced using the described methods. | 2010-01-21 |
| 20100017639 | POWER MANAGEMENT APPARATUS AND METHODS - A power management apparatus including power supply circuit and control unit is disclosed. The power supply circuit receives input voltage having voltage value, and converts voltage value into a first converted signal having a first voltage value and a second converted signal having a second voltage value through first and second converters, respectively. The first and second converters are reset according to first and second reset signals, respectively. The control unit receives the first and second converted signals, and compares the first and second voltage values with first and second reference ranges, respectively. The control unit further issues first reset signal when first voltage value is not within first reference range and second voltage value is within second reference range, and issues second reset signal when first voltage value is within first reference range and second voltage value is not within second reference range. | 2010-01-21 |
| 20100017640 | EFFICIENT TIME-BASED MEMORY COUNTERS - Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate the set of arrays with a set of predefined time intervals. Furthermore, a set of pointers may be used to reference the set of arrays of counters. An index is maintained to provide time-based management of the arrays of counters. The index includes a timestamp and the set of pointers. Each pointer logically points to a distinct one of the set of arrays. | 2010-01-21 |
| 20100017641 | Communication system communication device and method for determining duty ratio of PWM control - A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication. | 2010-01-21 |
| 20100017642 | Distributed Transaction Processing System Having Resource Managers That Collaborate To Decide Whether To Commit Or Abort A Transaction In Response To Failure Of A Transaction Manager - A distributed transaction processing system includes a plurality of resources, resource managers to manage corresponding ones of the resources, and a transaction manager to coordinate performance of a transaction with the resource managers. In response to failure of the transaction manager, the resource managers are configured to collaborate to decide whether to commit or abort the transaction. | 2010-01-21 |
| 20100017643 | Cluster system and failover method for cluster system - Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program ( | 2010-01-21 |
| 20100017644 | BYZANTINE FAULT TOLERANT DYNAMIC QUORUM USING A TRUSTED PLATFORM MODULE - A method implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable medium. The computer executable code is operable to dynamically adjust quorum requirements for a voting set V of a server cluster, including a plurality of servers, to ensure that a response of the server cluster to a client request remains Byzantine fault tolerant when at least one of: a failed server of the server cluster is replaced with at least one new server, such that a total set S of servers that have ever been members of the server cluster is increased, and an existing server is removed from the voting set V. | 2010-01-21 |
| 20100017645 | COMMUNICATION APPARATUS AND CONTROL METHOD - A communication apparatus includes: a transmitting unit, a receiving unit and a control unit. The transmitting unit transmits video data to an external apparatus via a first transmission line. The receiving unit receives a command from the external apparatus via a second transmission line. The control unit that resets the transmitting unit without resetting the receiving unit if a communication error relating to the first transmission line is detected, and resets the receiving unit without resetting the transmitting unit if a communication error relating to the second transmission line is detected. | 2010-01-21 |
| 20100017646 | CLUSTER SYSTEM AND NODE SWITCHING METHOD - When a first server node fails in a cluster system, a client node device transmits failure detection information to a second server node device. Upon receipt of the failure detection information, the second server node device transmits a survival confirmation request to the first server node device. When receiving no survival confirmation response from the first server node device, the second server node device determines that the first server node device has failed and starts the switching control of a server node device which performs a service process. Upon receipt of failure detection information, the second server node device starts switching control when further receiving failure detection information from another client node device. | 2010-01-21 |
| 20100017647 | MATCH SERVER FOR A FINANCIAL EXCHANGE HAVING FAULT TOLERANT OPERATION - Fault tolerant operation is disclosed for a primary match server of a financial exchange using an active copy-cat instance, a.k.a. backup match server, that mirrors operations in the primary match server, but only after those operations have successfully completed in the primary match server. Fault tolerant logic monitors inputs and outputs of the primary match server and gates those inputs to the backup match server once a given input has been processed. The outputs of the backup match server are then compared with the outputs of the primary match server to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup match server to take over for the primary match server in a fault situation wherein the primary and backup match servers are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment. As such, the primary match server need not be specifically designed or programmed to interact with the fault tolerant mechanisms. Instead, the primary match server need only be designed to adhere to specific basic operating guidelines and shut itself down when it cannot do so. By externally controlling the ability of the primary match server to successfully adhere to its operating guidelines, the fault tolerant mechanisms of the disclosed embodiments can recognize error conditions and easily failover from the primary match server to the backup match server. | 2010-01-21 |
| 20100017648 | COMPLETE DUAL SYSTEM AND SYSTEM CONTROL METHOD - A DB server included in an old operation node corrects a recovery log stored in a recovery log storage unit by using a difference log stored in a difference log storage unit. A duplication control device and a DBMS compare a difference log file stored in the difference log storage unit and a recovery log file stored in the recovery log storage unit, and correct the content of the recovery log file accordingly. | 2010-01-21 |
| 20100017649 | Data storage system with wear-leveling algorithm - The present invention discloses a data storage system employing a plurality of electrical memory devices, preferably non-volatile memory cards or sub-modules, whereby user data or application software codes or OS software codes are protected by RAID (redundant array of inexpensive disks) architecture, and wear-leveling algorithms are uniquely arranged to extend the life cycles of such data storage system. | 2010-01-21 |
| 20100017650 | NON-VOLATILE MEMORY DATA STORAGE SYSTEM WITH RELIABILITY MANAGEMENT - A non-volatile memory data storage system, comprising: a host interface for communicating with an external host; a main storage including a first plurality of flash memory devices, wherein each memory device includes a second plurality of memory blocks, and a third plurality of first stage controllers coupled to the first plurality of flash memory devices; and a second stage controller coupled to the host interface and the third plurality of first stage controller through an internal interface, the second stage controller being configured to perform RAID operation for data recovery according to at least one parity. | 2010-01-21 |
| 20100017651 | SYSTEM AND METHOD FOR EFFICIENT DETECTION AND RESTORATION OF DATA STORAGE ARRAY DEFECTS - The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array. | 2010-01-21 |
| 20100017652 | APPARATUS WITH REDUNDANT CIRCUITRY AND METHOD THEREFOR - An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry. | 2010-01-21 |
| 20100017653 | REFERENCE STATE INFORMATION GENERATION - A method for generating reference state information, the method includes: comparing between at least one sequence of block identifiers that are accessed during a test period and at least one corresponding reference sequence of block identifiers to provide a comparison result; determining whether to generate reference state information in response to the comparison result; and generating reference state information if determining to generate the reference state information. | 2010-01-21 |
| 20100017654 | Device-to-Device Communication Bus for Distributed Power Management - A Device-to-Device Communication Bus protocol may facilitate transmission of a two to four byte packet by any device sharing the bus. All devices on the bus may monitor the bus, receiving all packets transmitted by other devices and recognizing when they may initiate transmission. The first byte of the packet may be an Address byte uniquely identifying the sender and allowing hardware arbitration to uniquely select one of any number of senders who may wish to transmit and begin transmission simultaneously. Arbitration may take place during transmission of the Address byte, with the transmitting device monitoring a bus bit value as it is transmitting the Address byte. If the data value observed by the transmitting device doesn't match the transmitting device's desired transmit value, the transmitting device may recognize loss of arbitration and suspend transmission to retry once the packet is complete. The receive function in every device may accept the packet as a normal received packet. The arbitration scheme may also include a fairness mechanism to insure one or several devices cannot monopolize the bus. | 2010-01-21 |
| 20100017655 | Error Recovery During Execution Of An Application On A Parallel Computer - Methods, apparatus, and products are disclosed for error recovery during execution of an application on a parallel computer that includes a plurality of compute nodes. Such error recovery includes: storing, by the application during execution on the nodes, application restore data in a restore buffer at predetermined points during execution of the application, the restore data specifying an execution state of the application at one or more points during application execution; encountering, by at least one of the nodes executing the application, a recoverable error during application execution; determining, by the application, the nodes affected by the recoverable error; restarting, by each of the affected nodes, execution of the application; retrieving, by the restarted application executing on each of the affected nodes, the restore data from the restore buffer; and continuing, by each affected node, execution of the application with the execution state specified by the retrieved restore data. | 2010-01-21 |
| 20100017656 | System on chip (SOC) device verification system using memory interface - A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model. | 2010-01-21 |
| 20100017657 | System and Method for Performance Test in Outside Channel Combination Environment - Provided are a system and method for a performance test in an outside channel combination environment. In an outside channel combination environment including first and second outside-affairs servers in an active-active form, first and second outside channel combination servers, and first and second network devices, a system for a performance test includes: a plurality of test lines connected to one another so that a closed circuit is formed at outputs of the first and second network devices; and at least one load generator for generating loads corresponding to outbound messages to be sent to a plurality of outside authorities, and measuring system performance, wherein: the loads generated by the load generator are sent to the second outside channel combination server via the first outside-affairs server, the first outside channel combination server, the first network device, the test lines, and the second network device, and the second outside channel combination server generates a response message corresponding to the received load, and then sends the response message to the load generator via the second network device, the test lines, the first network device, the first outside channel combination server, and the first outside-affairs server, so that system performance is measured. Thus, a performance test for transmit/receive message can be effectively performed in advance in a newly built outside channel combination environment. | 2010-01-21 |
| 20100017658 | TEST SYSTEM AND METHOD WITH A SIMULATOR - A test system for testing various functions of electronic devices includes a master device and a simulation control device. The master device is connected to an input device and the electronic devices through the simulation control device. The master device records input signals of the input device and generate simulation signals according to the input signals. The simulation control device simulates the input signals of the input device according to the simulation signals to test the electronic devices. | 2010-01-21 |
| 20100017659 | Secure Boot Circuit and Method - A circuit includes a circuit identification storage module and a control module. The circuit identification storage module stores circuit identification information. The control module receives the circuit identification information and in response thereto selectively performs a secure boot procedure or a test boot procedure. The control circuit performs the secure boot procedure when the circuit identification information indicates that the circuit is a production circuit. The control circuit performs the test boot procedure when the circuit identification information indicates that the circuit is a test circuit. A related method is also disclosed. | 2010-01-21 |
| 20100017660 | System and method for protecting memory stacks using a debug unit - A method is disclosed for detecting a memory stack fault. The method may include reserving a memory stack for executing software instructions. The method may also include enabling a debug unit and as the software instructions are execute, utilizing the debug unit to monitor a memory space adjacent to the memory stack. The method may further include identifying a memory stack fault if a write operation to the memory space is attempted. | 2010-01-21 |
| 20100017661 | METHOD FOR DETECTING A FAULT ON A DATA LINE - Multiple embodiments relate to a method for detecting a fault on a data line in a bus system in a two-line data network having at least two control units. A data signal is emitted by a transmitter-receiver unit on the two data lines as a differential voltage signal that includes a defined quiescent current. The data lines are mutually connected through a resistance bridge for detecting the middle voltage. The middle voltage is detected directly by a microcontroller after a low-pass filter or as a digital value after an analog-to-digital conversion. The result is displayed and/or stored. A circuit arrangement for implementing the method is also provided. | 2010-01-21 |
| 20100017662 | METHOD AND APPARATUS FOR CALIBRATING AND/OR DESKEWING COMMUNICATIONS CHANNELS - A series of pulses may be driven down each drive channel, which creates a series of composite pulses at the output of the buffer. Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted until the individual pulses of the composite pulse align or closely align. Those timing offsets calibrate and/or deskew the drive channels, compensating for differences in the propagation delays through the drive channels. The composite pulse may be feed back to the tester through compare channels, and offsets associated with compare signals for each compare channel may be aligned to the composite pulse, which calibrates and/or deskews the compare channels. | 2010-01-21 |
| 20100017663 | DATA PROCESSING CIRCUIT AND METHOD - A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the target page data are saved as a first codeword and a second codeword. An errata locator polynomial is obtained according to the syndrome polynomials, and a first error count and a second error count are obtained according to the errata locator polynomial, the first codeword and the second codeword. A set of reference codes is obtained according to the errata locator polynomial. Read page data are outputted according to the addresses of the programmed-error bits, the first error count and the second error count. The read page data are corrected according to the set of reference codes to obtain corrected read page data. | 2010-01-21 |
| 20100017664 | EMBEDDED FLASH MEMORY TEST CIRCUIT - Provided is an embedded flash memory test circuit, including an embedded flash memory call array a read-only memory (ROM) built-in self test (BIST) unit, a ROM BIST control unit and a comparison unit. The embedded flash memory cell array includes multiple flash memory cells, and simultaneously outputs m pieces of read data, where m is a natural number. The ROM BIST unit generates first compressed data by compressing the m pieces of read data. The ROM BIST controller controls the ROM BIST unit. The comparison unit compares the first compressed data and expected data. | 2010-01-21 |
| 20100017665 | DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE - During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location. | 2010-01-21 |
| 20100017666 | FAULTY SITE IDENTIFICATION APPARATUS, FAULTY SITE IDENTIFICATION METHOD, AND INTEGRATED CIRCUIT - A faulty site identification apparatus for identifying a faulty site in an integrated circuit, the faulty site identification apparatus including a scan chain constituted by coupling a plurality of sequential circuit elements and adapted to output a scan data by shifting out setting data that is set to each of the plurality of sequential circuits, a setting section that sets the setting data to at least one sequential circuit element of the plurality of sequential circuit elements and an identification section that identifies a faulty site in the scan chain on the basis of the scan data from the scan chain to which the setting data is set to the at least one sequential circuit element by the setting section. | 2010-01-21 |
| 20100017667 | Method and Device to Detect Failure of Static Pervasive Control Signals - A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or more groups of the static pervasive signals and then monitoring the signal signature for any change of logic level. | 2010-01-21 |
| 20100017668 | SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING - Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided. | 2010-01-21 |
| 20100017669 | METHOD FOR CORRECTING HIGH-FREQUENCY CHARACTERISTIC ERROR OF ELECTRONIC COMPONENT - An electronic-component high-frequency characteristic error correcting method for allowing a calibration work to be performed on a two-terminal impedance component using the same correction-target measuring system as that used in actual measurement. At least three correction data acquisition samples having different high-frequency characteristics are measured by a reference measuring system and an actual measuring system. An equation for associating the value measured by the actual measuring system with the value measured by the reference measuring system using an error correction coefficient of a transmission line is determined. A given electronic component is measured by the actual measuring system. An estimated high-frequency characteristic value of the electronic component obtained when the electronic component is measured by the reference measuring system is calculated using the determined equation. | 2010-01-21 |
| 20100017670 | Automatic Data Recovery System - A method, programmed medium and system are provided for recovering media-stored program code and/or user data when data on the same media are lost or corrupted. The system includes retrieving user data and/or program code from an external source when the actual data/code is not readable. When initiating the load of local storage, an initial scan for damaged regions is performed. If the initial scan determines that there are damaged/bad regions, the media player will look for the necessary data and/or code to patch the digital media. In one embodiment, a hardware or software look-ahead reader function, for example, is enabled to retrieve the original undamaged data/code from the local storage when an attempt to read a region from an optical disk fails due to a bad region. If the region in question is not stored locally, then a request is automatically transmitted to the original data provider to re-send the original data/code, which may include original program code. The data provider will then respond by sending the missing data/code to the user system where it will, in turn, be stored within the local storage device for further access and use. | 2010-01-21 |
| 20100017671 | Hybrid Automatic Repeat Request Process Mapping Rule - A method is provided for associating initial transmissions and retransmissions. The method includes determining a HARQ process ID for the initial transmission based upon a system frame number, a subframe number, a period associated with the initial transmission and/or a number of reserved HARQ process IDs. The method further includes associating the initial transmission with a retransmission based upon the HARQ process ID. | 2010-01-21 |
| 20100017672 | Method Of Retransmission Control In Wireless Relay System, Wireless Relay Station, And Wireless Base Station - If a reception result from an MS for the previous transmission data is a reception failure, second allocation information for retransmitting the previous transmission data is generated by an RS based on allocation information on a wireless resource for transmission of new data. The second allocation information and the previous transmission data are transmitted to the MS, and the new data is buffered. | 2010-01-21 |
| 20100017673 | DATA TRANSMISSION SYSTEM AND DATA TRANSMISSION METHOD - A data transmission system includes a server, a network and a plurality of terminals. The server sends data to the terminals via the network and the network connects the server and the plurality of terminals, and the terminal includes a network interface unit that connects to the network and communicates with the other terminals or the server via the network, a storage unit that stores reception data and information on missing of data, a detection unit that detects that the reception data is missing or damaged, and a controller that controls the network interface unit to send a repair request message to the other terminals through multicast when the detection unit detects missing or damaged data of data received from the server, and that controls the network interface unit to send a repair request message to the server when there is not requested data in the other terminals. | 2010-01-21 |
| 20100017674 | RETRANSMISSION CONTROL TECHNIQUE - A retransmission control method, a transmitter and a receiver. The method comprises the steps of receiving, at a MIMO transmitter, a NACK signal indicating an unsuccessful decoding of a coded data packet at a MIMO receiver; receiving a reliability measure associated with one or more transmitted spatial data streams for the unsuccessfully decoded data packet; comparing the reliability measure with at least one predetermined threshold; and selecting a retransmission protocol based on the comparison of the reliability measure with the at least one predetermined threshold. | 2010-01-21 |
| 20100017675 | SUPPORTING HYBRID AUTOMATIC RETRANSMISSION REQUEST IN ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING ACCESS RADIO ACCESS SYSTEM - A method of supporting a hybrid automatic retransmission request (HARQ) in an orthogonal frequency division multiplexing access (OFDMA) radio access system is disclosed. Preferably, the method comprises receiving a downlink data frame comprising a data map information element and a data burst comprising a plurality of layers, wherein each layer is encoded with a corresponding channel encoder, and wherein the data map information element is configured to support multiple antennas to achieve space time transmit diversity by providing control information associated with each one of the plurality of layers, wherein the control information comprises allocation of acknowledgement status channels corresponding to the plurality of layers, and transmitting in an uplink data frame a plurality of acknowledgement status, each acknowledgement status being associated with whether a corresponding layer of the plurality of layers is properly decoded. | 2010-01-21 |
| 20100017676 | DECODING OF LINEAR CODES WITH PARITY CHECK MATRIX - A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code. Using the logic circuitry each probability message is passed through the factor graph by performing for each received symbol at the variable nodes the equality function, at the permutation nodes one of multiplication and division, and at the parity check nodes the parity check function, wherein each of the variable nodes provides an output symbol in dependence upon each received symbol. | 2010-01-21 |
| 20100017677 | DECODING DEVICE AND DECODING METHOD - To provide a decoder capable of efficiently dealing with various Z, even when in-block parallel degree is fixed in MP decoding of quasi-cyclic LDPC codes. A reception value aligning device keeps the first S or less reception value data from the block head. If block size Z is not a multiple of S, (S−(Z mod S)) data of the block head are added to the end of the reception value data of the block so that the block size Z is a multiple of S. The block size is written into reception value memory. A message aligning device performs cyclic permutation. If Z is not a multiple of S, the first (S−(Z mod S)) messages from the block output head are added to the end of the output message of the block so that the Z is a multiple of S and is outputted to the message memory. | 2010-01-21 |
| 20100017678 | Hierarchical Trellis Coded Modulation - A system and method for encoding information is disclosed. In one embodiment, information is encoded using a high protection code for the least significant bit and a low protection code for the next three most significant bits. The remaining bits are uncoded. The high protection code may be a turbo code and the low protection code may be a trellis coded modulation code. In this embodiment, the collection of bits is then mapped according to a diagonally shifted QAM constellation technique. | 2010-01-21 |
| 20100017679 | RECORDING AND REPRODUCING DATA TO/FROM A RECORDING MEDIUM HAVING A USER DATA AREA AND AN INFORMATION AREA FOR STORING INFORMATION ABOUT THE RECORDING MEDIUM - If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention. | 2010-01-21 |
| 20100017680 | TRANSMITTING/RECEIVING SYSTEM AND METHOD OF PROCESSING BROADCAST SIGNAL IN TRANSMITTING/RECEIVING SYSTEM - A receiving system and a method of processing data are disclosed herein. The receiving system includes a receiving unit, an equalizer, a block decoder, and an RS frame decoder. The receiving unit receives and demodulates a broadcast signal. Herein, the broadcast signal includes at least a mobile service data and a data group including a plurality of known data sequences. The equalizer channel-equalizes the data group included in the demodulated broadcast signal by using the plurality of the known data sequences. The block decoder performs turbo-decoding in block units on data of portion allocated to the channel equalized data group. And, the RS frame decoder configures an RS frame by gathering data of the turbo decoded M number of portions, wherein M is an integer greater than 1 (M>1). And, when a number of contiguous CRC errors is equal to (a maximum number of errors that can be corrected by RS erasure decoding)+1, wherein the number of contiguous CRC errors is determined by performing CRC decoding on each row of the RS frame, the RS frame decoder sets up erasure points in all data of the rows including the CRC errors, so as to perform RS erasure decoding on all columns of the RS frame in the column direction. | 2010-01-21 |
| 20100017681 | METHOD AND APPARATUS FOR ENHANCED HASHING - A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be a Cyclic Redundancy Code (CRC) type function and the second function can be an Error Checking and Correcting (ECC) type function. Further, an address of the table can include a concatenation of the results of the CRC and the ECC type functions. | 2010-01-21 |
| 20100017682 | Error correction code striping - A method is disclosed which decreases the amount of error correction code data required to detect and correct errors in digital data while still maintaining a specified ability to correct errors in large groups of contiguous data. The present invention accomplishes this by placing distance either in space or in time between bytes grouped mathematically for error correction code calculations. An error affecting contiguous bytes, like scratches or other defects in digital storage media, or certain types of interference in either wired or wireless digital communications, would affect many error correction code groups, but would only affect one byte from each group. The error can easily be corrected using only a one dimensional error correction code, removing the need for a two dimensional product error correction code and the additional data overhead that the column ECC data necessarily adds to the block. | 2010-01-21 |
| 20100017683 | DISK-DRIVE DEVICE AND METHOD FOR ERROR RECOVERY THEREOF - A method for an error recovery process in a disk-drive device. The method includes starting the error recovery process in response to an error which has occurred in a process corresponding to a command from a host to access a disk. The method also includes receiving a new read command from the host during the error recovery process. In addition, the method includes interrupting the error recovery process in accordance with preset conditions and reading out data from the disk at an address designated by the read command. Furthermore, the method includes transferring the read-out data to the host. | 2010-01-21 |
| 20100017684 | DATA RECOVERY IN SOLID STATE MEMORY DEVICES - Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed. | 2010-01-21 |
| 20100017685 | ADAPTIVE ERROR CORRECTION - A transmitter generates error correction data according to an error correction scheme that logically arranges the communication data in a number of rows and a number of columns. The transmitter transmits the communication data and the error correction data. A receiver receives the communication data and the error correction data. The receiver processes the error correction data to correct errors in the communication data. The receiver generates information regarding the errors in the communication data. The transmitter processes the information to alter at the number of rows and/or the number of columns. | 2010-01-21 |
| 20100017686 | FAST CHANNEL ZAPPING AND HIGH QUALITY STREAMING PROTECTION OVER A BROADCAST CHANNEL - Signaling the sending of source blocks within multiple physical layer blocks is done for both streaming and object delivery applications, using minimal additional overhead, and in some cases no overhead, to signal interleaved source blocks within a physical layer block, signaling how symbols are related to the source blocks from which they are generated, and signaled sending and indications of prioritized data for source blocks. Organizing and sending streams over one more channels can be done to improve the quality of delivered streams, while minimizing or improving the needed amount of channel resources and receiver power resources needed. | 2010-01-21 |
| 20100017687 | Method and Apparatus for N+1 Packet Level Mesh Protection - Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets. | 2010-01-21 |
| 20100017688 | Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously - Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach. | 2010-01-21 |
| 20100017689 | VSB TRANSMISSION SYSTEM - A vestigial sideband (VSB) modulation transmission system and a method for encoding an input signal in the system are disclosed. According to the present invention, the VSB transmission system includes a convolutional encoder for encoding an input signal, a trellis-coded modulation (TCM) encoder for encoding the convolutionally encoded signal, and a signal mapper mapping the trellis-coded signal to generate a corresponding output signal. Different types of the convolutional encoders are explored, and the experimental results showing the performances of the VSB systems incorporating each type of encoders reveals that a reliable data transmission can be achieved even at a lower input signal to noise ratio when a convolutional encoder is used as an error-correcting encoder in a VSB system. | 2010-01-21 |
| 20100017690 | METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM - A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO). | 2010-01-21 |
| 20100017691 | AUDIO CODEC AND BUILT-IN SELF TEST METHOD FOR THE SAME - An audio codec and a BIST method adapted for the audio codec are provided. The BIST method includes the following steps. A first channel digital-to-analog converter (DAC) of the audio codec converts a test signal into an analog signal. A first channel analog-to-digital converter (ADC) of the audio codec converts the analog signal into a digital signal. Use a second channel DAC of the audio codec and a second channel ADC of the audio codec to calculate the magnitudes of a plurality of spectral components of the DFT of the digital signal. Determine whether the audio codec passes the test according to the magnitudes of the spectral components. | 2010-01-21 |
| 20100017692 | METHOD AND APPARATUS FOR CYCLIC REDUNDANCY CHECK IN COMMUNICATION SYSTEM - A method for performing a Cyclic Redundancy Check (CRC) in a communication system is provided. An input message is divided into a predetermined number of segments. The CRC is performed on each segment to generate a CRC code of each segment. Polynomial addition is performed on CRC codes of respective segments to obtain a CRC code of the input message. | 2010-01-21 |
| 20100017693 | Visual Macro Showing How Some Icon or Object or Text was Constructed - A Visual Macro Program records and replays desired actions performed by a user in creating or editing a document. The recorded actions are appended to the document as an attachment that can be replayed by a user at a later time by enabling a tag associated with the recorded actions. | 2010-01-21 |
| 20100017694 | APPARATUS, AND ASSOCIATED METHOD, FOR CREATING AND ANNOTATING CONTENT - An apparatus, and an associated method, for facilitating creation and review of content. An accessor accesses content that is to be reviewed. If the review is to be made using media of a type different than the stored content, a converter converts the content into a desired media. And, reviewing of the content is carried out by way of a user interface. When a reviewer elects to add an annotation to the content, the annotation is made by way of the user interface. If the content is reviewed in textual form, the annotation is made by adding text to the reviewed content and, if the content is reviewed in audio form, the annotation is made as an audio annotation. Once annotation is made and review is completed, the content, together with the annotation made thereto, is stored, available for subsequent viewing or further review. | 2010-01-21 |
| 20100017695 | INTEGRATING AN APPLET INTO A MULTI-PAGE OR MULTI-TASKING WEB APPLICATION TO ENABLE APPLET STATE TO BE AUTOMATICALLY SAVED AND RESTORED - A Web page of a Web application can be identified. The identified Web page can include an applet. A navigation action from the identified Web page to another Web page of the multi-page Web application can be detected. A state of the applet can be automatically saved before the applet terminates and the next Web page is navigated to. A navigation action to return to the identified Web page can be detected. This navigation can cause the previously saved applet state to be automatically retrieved and applied to the identified Web page so that the Web page is presented in a state that it was in when last navigated away from. | 2010-01-21 |
