03rd week of 2012 patent applcation highlights part 26 |
Patent application number | Title | Published |
20120014132 | OPTICAL COMPONENT, BACKLIGHT MODULE AND DISPLAY APPARATUS USING SAME - An optical component adapted for using in a backlight module providing light sources to a display apparatus is provided in the present disclosure. The optical component includes a first optical layer comprising a plurality of first blind holes extending downward from an upper surface to a first predetermined depth of the optical component, and a second optical layer comprising a plurality of second blind holes extending upward from a lower surface to a second predetermined depth of the optical component. A backlight module and a display apparatus are also provided. | 2012-01-19 |
20120014133 | LIGHT SOURCE MODULE AND ELECTRONIC DEVICE INCLUDING THE SAME - According to a light source module of the present invention, a plurality of light guides ( | 2012-01-19 |
20120014134 | BACKLIGHT MODULE AND DISPLAY APPARATUS - The present invention provides a backlight module and a display apparatus. The display apparatus comprises the backlight module and a display panel. The backlight module comprises a light guide plate and a light source. The light guide plate has an out light surface. The light source is positioned at a side of the light guide plate, wherein the light source comprises a light source out light surface, and a predetermined angle exists between the light source out light surface and the out light surface of the light guide plate. The present invention is capable of promoting the light leakage issue. | 2012-01-19 |
20120014135 | EDGE TYPE BACKLIGHT UNIT AND METHOD FOR MANUFACTURING THE SAME - An edge type backlight unit and a method for manufacturing the same are disclosed. The edge type backlight unit includes light sources for providing light, a printed circuit board (PCB) on which the light sources are mounted, a metal bracket that contacts the printed circuit board and dissipates heat of the printed circuit board, and a thermal hardener formed between the printed circuit board and the metal bracket. The printed circuit board supplies an electrical signal for driving the light sources to the light sources. | 2012-01-19 |
20120014136 | LIGHT GUIDE PLATE AND BACKLIGHT UNIT INCLUDING THE SAME - A light guide plate having a pattern to minimize generation of a dark zone and a backlight unit including the same are disclosed. The light guide plate includes an intaglio pattern consisting of recesses formed in a surface opposite to a light emitting surface thereof to have a cross section having major-axis and minor-axis diameters and depth, the recesses being spaced apart from one another in first and second directions by first and second distances respectively. The density of the intaglio pattern is directly proportional to the major-axis and minor-axis diameters and depth, and is inversely proportional to the first and second distances. The intaglio pattern has the minimum density in a first region adjacent to a light source, and the maximum density in a second region that is the maximum distance from the light source. A density ratio of the maximum density to the minimum density is 900. | 2012-01-19 |
20120014137 | BACKLIGHT MODULE AND HOUSING UNIT STRUCTURE THEREOF - The present invention provides a backlight module and a housing unit structure thereof. The backlight module includes a back plate having a first edge, a second edge, a third edge and a fourth edge. The edges of the back plate are provided with a housing including two housing strips and housing unit structures. The housing strips are disposed on the first edge and the third edge. The length of the housing unit structure is shorter than that of the second or fourth edge of the back plate, so that the second or fourth edge can be mounted with a suitable number of the housing unit structures, while insufficient length portion is compensated by buffering strips. The backlight module uses an adjustable modular design to adjust the number of the housing unit structures and the buffering strips for being suitably applied to various backlight modules with different sizes. Except for reducing the use of material, the development cost and time of the backlight module can be saved. | 2012-01-19 |
20120014138 | PULSE WIDTH MODULATED RESONANT POWER CONVERSION - A power converter including a resonant circuit is controlled by pulse width modulation (PWM) of a switching circuit to control current in the resonant circuit near the frequency of the resonant circuit (a null-immittance criterion) in order to control current and voltage at the output of the resonant circuit. Further control of voltage can be performed by PWM of a switching circuit at the output of the resonant circuit such that centers of the duty cycles of respective switches for the output of the resonant circuit are substantially synchronized and substantially symmetrical about centers of said duty cycles of respective switches at the input of the resonant circuit. Thus, operation of the converter is substantially simplified by using only PWM, a wide range of input and output voltages can be achieved and the converter circuit can be configured for bi-directional power transfer. | 2012-01-19 |
20120014139 | POWER CONVERTING APPARATUS - In a power converting apparatus which converts AC power into DC power, an inverter circuit including at least one series-connected single-phase inverter is connected in a downstream of a stage in which an AC input is rectified in series therewith. In the downstream stage of the inverter circuit, there are provided a smoothing capacitor connected via a rectifier diode and a short-circuiting switch for bypassing the smoothing capacitor. The short-circuiting switch is set to an ON state only in each of short-circuiting phase ranges of which midpoint matches each of zero-crossing phases and an output of the inverter circuit is controlled by using a current command so that a DC voltage of the smoothing capacitor follows a target voltage and an input power factor is improved. | 2012-01-19 |
20120014140 | SYSTEMS AND METHODS FOR REDUCING TRANSIENT VOLTAGE SPIKES IN MATRIX CONVERTERS - Systems and methods are provided for delivering energy using an energy conversion module that includes one or more switching elements. An exemplary electrical system comprises a DC interface, an AC interface, an isolation module, a first conversion module between the DC interface and the isolation module, and a second conversion module between the AC interface and the isolation module. A control module is configured to operate the first conversion module to provide an injection current to the second conversion module to reduce a magnitude of a current through a switching element of the second conversion module before opening the switching element. | 2012-01-19 |
20120014141 | RESET VOLTAGE CIRCUIT FOR A FORWARD POWER CONVERTER - A reset voltage circuit for a forward power converter includes a reset capacitor and a memory capacitor. The reset capacitor is to be coupled to recycle energy from a primary winding of a transformer to an input bulk capacitor during a resetting of the transformer. The memory capacitor is to be coupled to store a first voltage equal to an input voltage of the power converter when the input voltage is at a steady-state value. The memory capacitor is further to set a voltage across the primary winding during the resetting of the transformer to a magnitude greater than or equal to the first voltage when the input voltage of the forward power converter drops below the steady-state value. | 2012-01-19 |
20120014142 | POWER CONVERSION APPARATUS FOR CORRECTING POWER FACTOR - A power conversion apparatus for correcting power factor, which converts an input voltage to an output voltage, comprises: an inductive component, a unidirectional conducting component, a switch, an energy storage component, a capacitive component, and an output circuit. The unidirectional conducting component connects to the inductive component and the switch in series. The energy storage component connects to the switch and the capacitive component in series. The capacitive component has a bias voltage. The output circuit couples to the energy storage component for outputting the output voltage. Wherein, the switch in a conduction state is capable of charging the inductive component by applying the input voltage and charging the energy storage component by applying the bias voltage, and the switch in a cutoff state is capable of discharging the capacitive component and the energy storage component to the output circuit and discharging the inductive component to the capacitive component. | 2012-01-19 |
20120014143 | INVERTER FILTER INCLUDING DIFFERENTIAL MODE AND COMMON MODE, AND SYSTEM INCLUDING THE SAME - An inverter filter is for a plurality of phases. The inverter filter includes a node; a differential mode filter including for each of the phases a first terminal, a second terminal, an inductor electrically connected between the first terminal and the second terminal, and first capacitor electrically connected between the inductor and the node. The inverter filter also includes a third terminal structured to be grounded, and a common mode filter. The common mode filter includes a resistor, and a second capacitor electrically connected in series with the resistor between the node and the third terminal. | 2012-01-19 |
20120014144 | POWER SUPPLYING APPARATUS - A power supplying apparatus includes a rectifier and a first electromagnetic interference (EMI) filter. The rectifier receives and rectifies an alternating current (AC) input power for generating a direct current (DC) power. The first EMI filter receives the DC power through a first power input terminal and a first reference input terminal thereof. The first EMI filter filters the DC power for generating a DC output power between a first power output terminal and a first reference output terminal thereof. The first EMI filter includes an inductor module, a first X capacitor, and a first Y capacitor. | 2012-01-19 |
20120014145 | STARTUP CIRCUIT - A startup circuit is installed in a switching power source apparatus. The startup circuit is configured to start up a controller with the use of a rectified voltage at startup of an AC power source and includes a detector (ZD | 2012-01-19 |
20120014146 | POWER-DEPENDANT MAINS UNDER-VOLTAGE PROTECTION - A method and controller for power dependant mains under-voltage (“brown-out”) protection is disclosed. Brown-out protection is meant for protection against overheating due to low mains voltage and associated high mains current. Usually this is coupled to the absolute value of the mains voltage, but for devices operating at low power this is not necessary, as overheating will not occur. The disclosed method and controller allow for lower mains voltages at low load by comparing the mains voltage with a signal indicating the actual power level of the power supply. | 2012-01-19 |
20120014147 | POWER LAYER GENERATION OF INVERTER GATE DRIVE SIGNALS - Solid state switches of inverters are controlled by timing signals computed in power layer interface circuitry for individual inverters. Multiple inverters may be placed in parallel with common three-phase output. Common control circuitry generates timing signals or data used to reconstruct the common signals and sends these signals to the power layer interface circuitry. A processor in a power layer interface circuitry used these signals to recomputed the timing signals. Excellent synchronicity may be provided between parallel inverters that each separately reconstruct the timing signals based upon the identical received data. | 2012-01-19 |
20120014148 | ADAPTIVE ON-TIME CONTROL FOR POWER FACTOR CORRECTION STAGE LIGHT LOAD EFFICIENCY - Light load efficiency of a power factor correction circuit is improved by adaptive on-time control and providing for selection between a continuous conduction mode and a discontinuous conduction mode wherein the discontinuous conduction mode increases time between switching pulses controlling connection of a cyclically varying voltage to a filter/inductor that delivers a desired DC voltage and thus can greatly reduce the switching frequency at light loads where switching frequency related losses dominate efficiency. The mode for controlling switching is preferably selected for each switching pulse within a half cycle of the cyclically varying input voltage. A multi-phase embodiment allows cancellation of EMI noise at harmonics of the switching frequency and adaptive change of phase angle allows for cancellation of dominant higher order harmonics as switching frequency is reduced. | 2012-01-19 |
20120014149 | POWER CONVERSION APPARATUS AND METHOD - According to one embodiment a power conversion apparatus includes a first switch, a second switch, and a pulse generator. The first switch is connected at both ends of an AC power supply through an inductor and capacitor connected in series. The second switch is connected at both ends of the first switch through a smoothing capacitor connected in series. The pulse generator generates a first pulse signal for driving the first switch at a frequency higher than a cycle of the AC voltage, and supplies it to the first switch, when the polarity of the voltage of the AC power supply is positive. The pulse generator generates a second pulse signal for driving the second switch at a frequency higher than a cycle of the AC voltage, and supplies it to the second switch, when the polarity of the voltage of the AC power supply is negative. | 2012-01-19 |
20120014150 | POWER FACTOR CORRECTION EFFICIENCY IMPROVEMENT CIRCUIT, A CONVERTER EMPLOYING THE CIRCUIT AND A METHOD OF MANUFACTURING A CONVERTER - The disclosure provides a power factor correcting (PFC) circuit, a power supply and a method of manufacturing a power converter. In one embodiment, the PFC circuit has a positive input terminal, an output terminal and a ground terminal and includes: (1) a power factor inductor coupled in series between the positive input terminal and the output terminal, (2) a main switch configured to periodically connect the power factor inductor to the ground terminal and (3) a clamping capacitor coupled to the power factor inductor and configured to provide zero turn-off loss for the main switch. | 2012-01-19 |
20120014151 | Power Conversion with Added Pseudo-Phase - Methods and systems for power conversion. An energy storage capacitor is contained within an H-bridge subcircuit which allows the capacitor to be connected to the link inductor of a Universal Power Converter with reversible polarity. This provides a “pseudo-phase” drive capability which expands the capabilities of the converter to compensate for zero-crossings in a single-phase power supply. | 2012-01-19 |
20120014152 | METHOD FOR CONTROLLING SWITCHING POWER UNIT - There is provided a method for controlling a switching power unit that converts AC input voltages of an AC source into a DC voltages while improving a power-factor of the AC input voltages, the switching power unit comprising an AC/DC converter circuit that is composed of a power-factor correction unit and a current resonance converter unit wherein at least a part of switching elements of the current resonance converter unit is shared with switching elements of the power-factor correction unit, wherein around timing that polarities of the AC source are switched between a positive half cycle and a negative half cycle, ON-and-OFF control of the switching elements are performed as that high frequency voltages that are applied to a primary winding of a high frequency transformer which is a part of the current resonance converter unit are to be symmetrical in a positive and negative relation. | 2012-01-19 |
20120014153 | SUPPLY CIRCUIT - The present invention relates to a supply circuit ( | 2012-01-19 |
20120014154 | MOTOR DRIVE COOLING DUCT SYSTEM AND METHOD - The present invention relates generally to tuning the flow of cooling air across converter and inverter heat sinks in a motor drive system. More specifically, present techniques relate to motor drive duct systems having parallel cooling air duct channels dedicated to providing cooling air for a converter heat sink and an inverter heat sink, respectively. In particular, a first duct channel through an inverter duct and a converter duct is dedicated to providing cooling air to the converter heat sink without cooling the inverter heat sink, whereas a second duct channel through the inverter duct and the converter duct is dedicated to providing cooling air to the inverter heat sink without cooling the converter heat sink. A guide vane adjacent to the inverter duct may control the flow of cooling air from a blower between the first and second duct channels. In addition, the inverter duct and the converter duct may both include baffled walls that direct cooling air into contact with the inverter heat sink and the converter heat sink, respectively, such that temperature gradients across the heat sinks are minimized. | 2012-01-19 |
20120014155 | SEMICONDUCTOR DEVICE AND POWER SUPPLY DEVICE USING THE SAME - A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced. | 2012-01-19 |
20120014156 | DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME - A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal. | 2012-01-19 |
20120014157 | SEMICONDUCTOR DEVICE - A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region. | 2012-01-19 |
20120014158 | MEMORY DEVICES - A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time. | 2012-01-19 |
20120014159 | MEMORY DEVICE - A memory device includes a memory unit including a plurality of first conductive lines and a plurality of second conductive lines that cross the first conductive lines, and a driving unit module coupled with the plurality of the first conductive lines through respective ones of a plurality of contacts and coupled with and the plurality of the second conductive lines through respective ones of the plurality of contacts, wherein as the first conductive lines become farther from the driving unit module along a direction that the second conductive lines extend, the respective contacts of the first conductive lines have lower resistance values. | 2012-01-19 |
20120014160 | Non-Volatile Re-Programmable Memory Device - A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr. | 2012-01-19 |
20120014161 | Memristive Negative Differential Resistance Device - A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material. | 2012-01-19 |
20120014162 | SEMICONDUCTOR MEMORY DEVICE FEATURING SELECTIVE DATA STORAGE IN A STACKED MEMORY CELL STRUCTURE - A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer. | 2012-01-19 |
20120014163 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line. | 2012-01-19 |
20120014164 | RESISTANCE-CHANGE MEMORY AND METHOD OF OPERATING THE SAME - According to one embodiment, a resistance-change memory includes a memory element in which its variable resistance state corresponds to data to be stored therein, a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude which changes the resistance state of the memory element from a high- to a low-resistance state, the third pulse having a third amplitude smaller than the first amplitude to read data in the memory element, the fourth pulse having a fourth amplitude between the first amplitude and the third amplitude, and a control circuit which controls the operations of the memory element and the pulse generation circuit. The control circuit supplies the fourth pulse to the memory element after supplying the first pulse to the memory element. | 2012-01-19 |
20120014165 | OPTIMIZED SOLID ELECTROLYTE FOR PROGRAMMABLE METALLIZATION CELL DEVICES AND STRUCTURES - A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 2012-01-19 |
20120014166 | RESISTIVE MEMORY - The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states. | 2012-01-19 |
20120014167 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring. | 2012-01-19 |
20120014168 | Dual Stage Sensing for Non-Volatile Memory - A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row. | 2012-01-19 |
20120014169 | NON-VOLATILE DATA-STORAGE LATCH - One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs. | 2012-01-19 |
20120014170 | Capacitive Crossbar Arrays - A capacitive crossbar array ( | 2012-01-19 |
20120014171 | SCHMITT TRIGGER-BASED FINFET SRAM CELL - The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage. | 2012-01-19 |
20120014172 | Static Random Access Memory Devices Having Read And Write Assist Circuits Therein That Improve Read And Write Reliability - Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The. write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell. | 2012-01-19 |
20120014173 | Disturb-Free Static Random Access Memory Cell - A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column. | 2012-01-19 |
20120014174 | Programmable Write Driver For STT-MRAM - A non-volatile memory structure comprises programmable write drivers for controlling drive strengths of write operations to storage elements. The memory structure comprises a storage element coupled to a bit line, a switching element coupled to the storage element, a source line and a word line, wherein the switching element is configured to change a logic state of the storage element. A first and a second write driver with programmable drive strengths are coupled to the bit line and source line respectively to enable control of drive strengths of write operations to the storage element. | 2012-01-19 |
20120014175 | Magnetic Tunnel Junction and Memristor Apparatus - A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current. | 2012-01-19 |
20120014176 | CREATING SPIN-TRANSFER TORQUE IN OSCILLATORS AND MEMORIES - A structure includes an electrically conductive material possessing spontaneous magnetization (“free magnet”) not in contact with an electrically resistive material possessing spontaneous magnetization (“pinned magnet”), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of magnetization of the free magnet is changed to a new direction of magnetization, by a spin current generated by transfer of heat between at least the spacer and the pinned magnet. Thereafter, the new direction of magnetization of the free magnet is sensed. Many such structures are fabricated to have an easy axis of magnetic anisotropy in the free magnet, to implement memories that write data by transferring heat. Several such structures are fabricated to have an easy plane of magnetic anisotropy in the free magnet, to implement oscillators that generate an oscillating signal, on transfer of heat. | 2012-01-19 |
20120014177 | SEMICONDUCTOR SWITCHING DEVICE - A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided that has a collector, a base and an emitter. The body region of the MOS transistor serves as the base of the bipolar transistor and the drain region of the MOS transistor serves as the collector of the bipolar transistor. Activation of the MOS transistor causes the bipolar transistor to turn on. The MOS transistor is activated to turn on the bipolar transistor and the bipolar transistor delivers current to the source region. | 2012-01-19 |
20120014178 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF REUSING SAME - A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder. | 2012-01-19 |
20120014179 | SOFT PROGRAM OF A NON-VOLATILE MEMORY BLOCK - A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition. | 2012-01-19 |
20120014180 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted. | 2012-01-19 |
20120014181 | Nonvolatile Semiconductor Memory - A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher. | 2012-01-19 |
20120014182 | APPARATUS FOR GENERATING A VOLTAGE AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME - An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal. | 2012-01-19 |
20120014183 | 3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB - A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node. | 2012-01-19 |
20120014184 | PROGRAMMING NON-VOLATILE MEMORY WITH BIT LINE VOLTAGE STEP UP - Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias. | 2012-01-19 |
20120014185 | CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY - An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations. | 2012-01-19 |
20120014186 | Fast Random Access To Non-Volatile Storage - Techniques are disclosed herein for efficiently operating memory arrays of non-volatile storage devices. In one embodiment, when reading data from an MLC block, reading is sped up by not discharging bit lines between successive sensing operations. For example, all even bit lines are charged up and odd bit lines are grounded to set up sensing of memory cells that are associated with a first word line and the even bit lines. Then, memory cells associated with the first word line and the even bit lines are read by, for example, sensing the even bit lines. Then, while the even bit lines are still charged, memory cells associated with another word line and the even bit lines are read. Because the even bit lines remain charged between the two sensing operations, time is saved in not having to re-charge the bit lines to an appropriate level for sensing. | 2012-01-19 |
20120014187 | Non-volatile memory device and method of operation therefor - In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well. | 2012-01-19 |
20120014188 | METHOD OF MAINTAINING THE STATE OF SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 2012-01-19 |
20120014189 | Semiconductor memory device and test method thereof - Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate. | 2012-01-19 |
20120014190 | Refresh Signal Generating Circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal. | 2012-01-19 |
20120014191 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of an embodiment includes memory cells | 2012-01-19 |
20120014192 | Two stage voltage level shifting - A voltage level shifter for shifting an output signal from a first voltage level to a second voltage level and then to a further boosted second voltage level is disclosed. The voltage level shifter comprises: an input for receiving an input signal; an output for outputting an output signal; a first power supply input for connecting to a first voltage source supplying said first voltage level; a second power supply input for connecting to a second voltage source supplying said second voltage level; and a third power supply input for connecting to a third voltage source supplying said boosted second voltage level; said voltage level shifter being responsive to a predetermined change in said input signal to isolate said first power supply input from said output and to connect said second power supply input to said output and being responsive to said output signal attaining a predetermined value to connect said third power supply input to said output and to isolate said second power supply input from said output. | 2012-01-19 |
20120014193 | CHARGE PUMP CIRCUIT, NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM - Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided. | 2012-01-19 |
20120014194 | Memory Cell with Equalization Write Assist in Solid-State Memory - A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors in series, or as a double-gate transistor. The equalization gate is controlled by a word line indicating selection of the row containing the cell in combination with a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to a selected cell, both gates are turned on, connecting the storage nodes of the cell to one another and assisting the write of the opposite date state from that previously stored. | 2012-01-19 |
20120014195 | SRAM with buffered-read bit cells and its testing - An SRAM with buffered-read bit cells is disclosed (FIGS. | 2012-01-19 |
20120014196 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate. | 2012-01-19 |
20120014197 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time. | 2012-01-19 |
20120014198 | SEMICONDUCTOR MEMORY DEVICE WITH TEMPERATURE SENSING DEVICE CAPABLE OF MINIMIZING POWER CONSUMPTION IN REFRESH - A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption. | 2012-01-19 |
20120014199 | Semiconductor device that performs refresh operation - To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2 | 2012-01-19 |
20120014200 | Multi-Time Programmable Memory - Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products. | 2012-01-19 |
20120014201 | DUAL RAIL MEMORY - A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column. | 2012-01-19 |
20120014202 | MEMORY DEVICE AND METHOD - A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period | 2012-01-19 |
20120014203 | SEMICONDUCTOR MEMORY APPARATUS - A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering to an external data in accordance with the second external reference voltage. | 2012-01-19 |
20120014204 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABLITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 2012-01-19 |
20120014205 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABILITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 2012-01-19 |
20120014206 | CLOSED KNEADING MACHINE AND KNEADING ROTOR - A kneading rotor, in which the length L | 2012-01-19 |
20120014207 | ELECTRIC APPLIANCE WITH DUAL SPEED OUTPUT - An electric appliance has first and second rotational output spindles located within a housing. The first and second spindles have respective first and second couplings for attachment of first and second work tools to the first and second spindles, respectively. The second rotational output spindle is concentric with the first rotational output spindle such that connection of one of the first and second work tools to the corresponding spindle excludes connection of the other of the first and second work tools to the corresponding spindle. The first rotational output spindle has a first rotational speed that is different from a second rotational speed of the second output spindle. | 2012-01-19 |
20120014208 | ENHANCED REEL FOR AGRICULTURAL MIXER - A mixing apparatus includes a hopper, a reel, and at least one auger. The hopper defines first and second chambers. The first chamber is disposed adjacent to the second chamber. The reel is disposed within the first chamber. The reel includes first and second hubs configured to rotate and at least one connecting member connecting the first hub to the second hub. The at least one auger is disposed in the second chamber. The first and second hubs rotate about a common axis of rotation. No connecting member connects a center of the first hub to a center of the second hub along the axis of rotation. An attachment point between each connecting member and the first hub is circumferentially offset with respect to an attachment point between the same connecting member and the second hub. | 2012-01-19 |
20120014209 | ENHANCED STATIC MIXING DEVICE - A high efficiency mixing device for mixing first and second fluids within a conduit. A biscuit element is positioned at the upstream end of the conduit having a longitudinal axis that coincides with the longitudinal axis of the conduit. The biscuit element is provided with a plurality of openings including a central opening positioned along the longitudinal axis and a plurality of additional openings spaced proximate to the central opening. The openings are provided with primary mixing elements which induce a rotational angular velocity to a first fluid passing therethrough of the same rotational sign. Second fluid feed ports are positioned within each of the openings for introducing a second fluid to the first fluid as the first fluid passes through the openings and into the conduit. Secondary and tertiary mixing elements are optionally located downstream of the biscuit element to enhance the mixing of the first and second fluids. | 2012-01-19 |
20120014210 | MULTIFUNCTIONAL MIXER - A multi-functional stirrer includes a frame, a container, a beater and a driving mechanism. A circular rail is installed at a lower portion of the frame; a bottom of the vertical cylindrical shaped container is a conical shaped barrel bottom which can be driven to lift up and down by a lifting mechanism automatically; the driving mechanism drives a container assembly to rotate on the circular rail of the frame in a direction opposite to a rotation direction of the beater at the same time of driving the beater to rotate; the beater is composed by fixing a plurality of stirring bars onto a horizontally arranged stirring bar frame; a rotation axis of the stirring bar frame is eccentrically disposed with respect to an axis of the vertical cylindrical shaped container. The present invention has different functions of mixing, peeling, cleaning, polishing and dampening, etc., when the stirring bars with different structures are used. | 2012-01-19 |
20120014211 | MONITORING OF OBJECTS IN CONJUNCTION WITH A SUBTERRANEAN WELL - Objects are monitored in a subterranean well. A well system can include at least one object having a transmitter, and at least one sensing device which monitors displacement of the object along a wellbore. A method of monitoring at least one object in a subterranean well can include positioning at least one sensing device in a wellbore of the well, and then displacing the object through the wellbore, the sensing device monitoring the object as it displaces through the wellbore. | 2012-01-19 |
20120014212 | CONTINUOUS COMPOSITE RELATIVELY ADJUSTED PULSE - The invention relates to continuously or near continuously acquiring seismic data where at least one pulse-type source is fired in a distinctive sequence to create a series of pulses and to create a continuous or near continuous rumble. In a preferred embodiment, a number of pulse-type seismic sources are arranged in an array and are fired in a distinctive loop of composite pulses where the returning wavefield is source separable based on the distinctive composite pulses. Firing the pulse-type sources creates an identifiable loop of identifiable composite pulses so that two or more marine seismic acquisition systems with pulse-type seismic sources can acquire seismic data concurrently, continuously or near continuously and the peak energy delivered into the water will be less, which will reduce the irritation of seismic data acquisition to marine life. | 2012-01-19 |
20120014213 | HIGH DENSITY SOURCE SPACING USING CONTINUOUS COMPOSITE RELATIVELY ADJUSTED PULSE - The invention relates to continuously or near continuously acquiring seismic data where at least one pulse-type source is fired in a distinctive sequence to create a series of pulses and to create a continuous or near continuous rumble. In a preferred embodiment, a number of pulse-type seismic sources are arranged in an array and are fired in a distinctive loop of composite pulses where the returning wavefield is source separable based on the distinctive composite pulses. Firing the pulse-type sources creates an identifiable loop of identifiable composite pulses so that two or more marine seismic acquisition systems with pulse-type seismic sources can acquire seismic data concurrently, continuously or near continuously and the peak energy delivered into the water will be less, which will reduce the irritation of seismic data acquisition to marine life. | 2012-01-19 |
20120014214 | TIME REVERSE IMAGING OPERATORS FOR SOURCE LOCATION WITH BOREHOLE DATA - A method and system for processing synchronous array seismic data includes acquiring synchronous passive seismic data from a plurality of sensors to obtain synchronized array measurements. A reverse-time data propagation process is applied to the synchronized array measurements to obtain a plurality of dynamic particle parameters associated with subsurface locations. Imaging conditions are applied to the dynamic particle parameters to obtain image values associated with subsurface energy source locations. | 2012-01-19 |
20120014215 | Time reverse reservoir localization with borehole data - A method and system for processing synchronous array seismic data includes acquiring synchronous passive seismic data from a plurality of sensors to obtain synchronized array measurements. A reverse-time data process is applied to the synchronized array measurements to obtain a plurality of dynamic particle parameters associated with subsurface locations. These dynamic particle parameters are stored in a form for display. Maximum values of the dynamic particle parameters may be interpreted as reservoir locations. The dynamic particle parameters may be particle displacement values, particle velocity values, particle acceleration values or particle pressure values. The sensors may be three-component sensors. Zero-phase frequency filtering of different ranges of interest may be applied. The data may be resampled to facilitate efficient data processing. | 2012-01-19 |
20120014216 | Time reverse reservoir localization - A method and system for processing synchronous array seismic data includes acquiring synchronous passive seismic data from a plurality of sensors to obtain synchronized array measurements. A reverse-time data process is applied to the synchronized array measurements to obtain a plurality of dynamic particle parameters associated with subsurface locations. These dynamic particle parameters are stored in a form for display. Maximum values of the dynamic particle parameters may be interpreted as reservoir locations. The dynamic particle parameters may be particle displacement values, particle velocity values, particle acceleration values or particle pressure values. The sensors may be three-component sensors. Zero-phase frequency filtering of different ranges of interest may be applied. The data may be resampled to facilitate efficient data processing. | 2012-01-19 |
20120014217 | System and method For Performing Time-Lapse Monitor Surverying Using Sparse Monitor Data - Techniques are disclosed for performing time-lapse monitor surveys with sparsely sampled monitor data sets. An accurate 3D representation (e.g., image) of a target area (e.g., a hydrocarbon bearing subsurface reservoir) is constructed ( | 2012-01-19 |
20120014218 | System and Method For Reconstruction of Time-Lapse Data - Techniques are disclosed for performing time-lapse monitor surveys with sparsely sampled monitor data sets ( | 2012-01-19 |
20120014219 | Wellbore Telemetry And Noise Cancellation Systems And Methods For The Same - A method of signal processing includes providing at least a first pressure sensor and a second pressure sensor spaced in a drilling system and using an algorithm to separate the downwardly propagating waves from the upwardly propagating waves. In one or more examples, an algorithm may include determining a velocity of pressure signals in a wellbore, time-shifting and stacking pressure signals from at least the first pressure sensor and the second pressure sensor to determine a downwardly propagating noise signal, and subtracting the downwardly propagating noise signal from at least the signal from the first pressure sensor. | 2012-01-19 |
20120014220 | SONAR NAVIGATION SYSTEM AND METHOD - A method for pre-determining an underwater objects GPS position using a forward scan sonar unit linked to a boat trolling motor, magnetic compass and GPS receiver. This system determines the underwater objects GPS position using the objects distance, compass heading and a GPS receiver/sonar on a boat. This system will provide real time longitude and latitude positions of underwater objects seen with sonar at a distance from a boat, and will allow for precise autopilot navigation or fixed position fishing. The system can also be used to correct for GPS errors when using previously stored waypoints positions of an object. The computer determines an objects underwater GPS position using a forward scan sonar transducer and compass mounted on a 360 degree movable mechanism such as a trolling motor unit, and formulates the objects position based on the distance and heading of the object in relation to the boats current GPS position. | 2012-01-19 |
20120014221 | MONOLITHIC FLEXURE PRE-STRESSED ULTRASONIC HORNS - A monolithic ultrasonic horn where the horn, backing, and pre-stress structures are combined in a single monolithic piece is disclosed. Pre-stress is applied by external flexure structures. The provision of the external flexures has numerous advantages including the elimination of the need for a pre-stress bolt. The removal of the pre-stress bolt eliminates potential internal electric discharge points in the actuator. In addition, it reduces the chances of mechanical failure in the actuator stacks that result from the free surface in the hole of conventional ring stacks. In addition, the removal of the stress bolt and the corresponding reduction in the overall number of parts reduces the overall complexity of the resulting ultrasonic horn actuator and simplifies the ease of the design, fabrication and integration of the actuator of the present invention into other structures. | 2012-01-19 |
20120014222 | ELECTROMAGNETIC ULTRASOUND TRANSDUCER - An electromagnetic ultrasound transducer is disclosed for receiving linearly polarized horizontal shear waves from an electrically conductive workpiece including a magnetizing unit, which provides a side facing the workpiece, along which a number n of permanent magnets are attached in at least two rows arranged next to one another in such a manner that the magnetic polarities of the magnetic poles which face the side alternate along a row periodically with a period length which corresponds to a trace wavelength λ | 2012-01-19 |
20120014223 | DEVICE INCORPORATING BOTH LIVE AND STATIC ADJUSTMENT FEATURES FOR DETERMINING FEEDING TIMES AND POSITION - A breastfeeding assist timepiece which includes a live time display combined with an iteratively resettable display, such further including a rotatable bezel feature which is repositionable between right and left sides of an associated crystal display and which, in combination with optional hour markings placed along the crystal display sides or upon the rotatable bezel, assists in establishing a dual-breast feeding cadence. | 2012-01-19 |
20120014224 | BACKLASH-COMPENSATING MECHANISM FOR A TIMEPIECE MOVEMENT - A backlash-compensating mechanism includes a cam, an actuating member bearing against the cam and a wheel coaxial to the cam and intended to be driven by a gear train of the movement. The cam and the wheel are connected to each other such that one revolution of the wheel includes a sequence of a first phase in which the wheel drives the cam whilst the co-operation between the cam and the actuating member cocks the latter, a second phase in which the actuating member uncocks and causes the cam to effect an instantaneous jump, and a third phase in which the cam is immobilized and the wheel continues to advance until it catches up with the cam to once again drive it during the first phase of the following revolution. This mechanism includes a resilient element acting between the cam and the wheel and applying a return torque to the wheel during the third phase to compensate the backlash in the gear train. | 2012-01-19 |
20120014225 | RADIO CONTROLLED TIMEPIECE - A radio controlled timepiece includes: a radio wave receiving section which outputs a time code signal; an indicator display section which performs a display regarding a reception condition; a level change detecting section which detects a change of a signal level of the time code signal in a predetermined detection interval in a period of 1 second; an indicator control section which controls a content of the display based on a number of times that the change of the detected signal level appears; and an interval setting section which specifies the detection interval as a whole interval of the period of 1 second during a detecting process of a synchronization point in the time code signal every 1 second, and narrows the detection interval to be a certain interval within the period of 1 second after a detection of the synchronization point every 1 second. | 2012-01-19 |
20120014226 | MARKER DETECTING APPARATUS AND RADIO-CONTROLLED TIMEPIECE - A marker detecting apparatus includes: a signal input section where a time code signal is inputted; a level detecting section detecting a signal level of a pulse signal of the time code signal at points in a marker characteristic interval to detect a match between the pulse signal and an ideal marker pulse signal in the signal level; a first calculating section calculating a number of the detected matches so as to obtain a value thereof, and correlating the obtained value with a pulse position of the pulse signal, the pulse position being a same in any of frames of the time code signal; a second calculating section adding up the obtained values correlated with the pulse position in the frames; and a marker determining section determining at which pulse position in the frames a marker pulse signal is disposed, based on the added-up value. | 2012-01-19 |
20120014227 | Stepping motor control circuit and analog electronic timepiece - A detection interval in which the rotation status of a stepping motor is divided into a first interval immediately after driving executed by a main driving pulse, a second interval later than the first interval, and a third interval later than the second interval. The driving is executed by a correction driving pulse and the main driving pulse is increased, when a control circuit drives the stepping motor in a driving way different from a driving way at the time of exceeding a predetermined voltage in a case where the voltage of a secondary battery is lowered to be equal to or less than the predetermined voltage and when a rotation detection circuit and a detection time comparison determination circuit detect an induced signal exceeding a first reference threshold voltage in the first interval and the second interval and do not detect the induced signal exceeding a second reference threshold voltage lower than the first reference threshold voltage in the third interval. | 2012-01-19 |
20120014228 | TIMEPIECE - This timepiece is furnished with a direct impulse escapement comprising a locking lever ( | 2012-01-19 |
20120014229 | BALANCE WITH INERTIA ADJUSTMENT WITH NO INSERTS - The invention concerns a timepiece balance ( | 2012-01-19 |
20120014230 | MAGNETIC RECORDING ELEMENT USED FOR THERMALLY-ASSISTED MAGNETIC RECORDING - A magnetic recording element that faces a recording medium and that executes a magnetic recording while the recording medium is heated, the element including a waveguide that is configured with a core and a cladding, the core, through which laser light propagates, including an enlarged part, which is enlarged at an air bearing surface facing the recording medium; and the cladding surrounding a periphery of the core. | 2012-01-19 |
20120014231 | WRITE-ONCE RECORDING MEDIUM, RECORDING METHOD, RECORDING APPARATUS, REPRODUCTION METHOD, AND REPRODUCTION APPARATUS - A write-once recording medium is provided, which comprises a management information area for recording management information for managing a recorded state, and a user data area for recording user data. The user data area is configured to contain at least one recording area. At least one session is configured to contain at least one of the at least one recording area. The management information contains range information indicating a recording range of the at least one recording area and identification information for identifying the recording area located at a boundary of the session. | 2012-01-19 |