03rd week of 2015 patent applcation highlights part 68 |
Patent application number | Title | Published |
20150019755 | DATA-CENTRIC COMMUNICATIONS SYSTEM, NODE, AND DATA FORWARDING METHOD - A node, when an object request message includes a location ID of a destination, sets the location ID of the destination as a search key to search the location-ID forwarding table thereof and forwards the object request message to a node that is a next hop obtained as the search result; and when the object request message does not include the location ID of the destination, sets the object ID included in the object request message as a search key to search the object-ID forwarding table thereof to forward the object request message to the node that is the next hop obtained as the search result. | 2015-01-15 |
20150019756 | COMPUTER SYSTEM AND VIRTUAL NETWORK VISUALIZATION METHOD - A computer system according to the present invention includes a managing unit which outputs a plurality of virtual networks managed by a plurality of controllers in a visually perceivable form with the plurality of virtual networks combined, on the basis of topology data of the virtual networks, the topology data being generated based on communication routes. This enables centralized management of the whole of a virtual network controlled by a plurality of controllers which use an OpenFlow technology. | 2015-01-15 |
20150019757 | GEOMETRIC DETERMINATION OF SHARED TRAVEL ROUTES - A method, computer program product, and computer system are provided for determining a convenient route. The method includes, for instance: obtaining, by a processor, a route that includes a starting point and an ending point; analyzing the route to determine whether at least one stored route is within a pre-defined acceptance zone of the route; and responsive to determining that at least one stored route is within a pre-defined acceptance zone, assigning a convenience factor of the at least one stored route relative to the route. | 2015-01-15 |
20150019758 | PROCESSING MULTIPLE NETWORK ADDRESS OBSERVATIONS - In one embodiment, a processing technique is provided that utilizes multiple network address observations. One or more records are obtained that maintain network address observations, each network address observation associating one or more attributes with a network address observed by one or more source devices. Multiple network addresses from the network address observations are clustered into one or more discrete groups of network addresses based on a clustering criteria. For a selected group of network addresses, an association is formed associating one or more refined attributes derived from the selected group with an individual network address that is a member of the selected group. | 2015-01-15 |
20150019759 | Method to Publish Remote Management Services Over Link Local Network for Zero-Touch Discovery, Provisioning, and Management - A system, method, and computer-readable medium are disclosed for using Zero Configuration Networking (ZeroConf) to automate the discovery of the Internet Protocol (IP) network address of a remote access controller (RAC). A RAC service associated with a networking device is registered programmatically or as a result of receiving user input to a command line interface. Available services that include the registered RAC service are browsed, followed by resolving the registered RAC service to an IP address, which is then discovered. The discovered IP address is then displayed within a user interface (UI) window. | 2015-01-15 |
20150019760 | STAGING ENGINE - Example methods and systems are directed to a staging engine. A system may comprise two computing devices. The first computing device may be accessible to a plurality of users. The second computing device may be inaccessible to the plurality of users, but accessible by the first computing device. The first computing device may cause a user interface (“UI”) to be presented to a user accessing the first computing device. The UI may include data retrieved from the second computing device and may be operable to store data. The data entered into the UI for storage may be incomplete relative to the data structures expected by the second computing device. The first computing device or the second computing device may stage the data until additional data that completes the expected data structures is received. After the expected data is complete, the data may be stored. | 2015-01-15 |
20150019761 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - According to one embodiment, a first controller is connected to one of a plurality of terminals. A detector is configured to detect a connection between each of the plurality of terminals and an MHL cable. A power supply module supplies electric power to a first connected apparatus connected via a first MHL cable in response to a first connection detection between a first terminal and the first MHL cable. A second controller is configured to connect the first terminal and the first controller, in response to the first connection detection, and to connect a second terminal and the first controller, when a signal is not received from the first connected apparatus via the first terminal at a timing of a second connection detection between the second terminal and a second MHL cable. | 2015-01-15 |
20150019762 | Analyzing Activity Data of an Information Management System - In an information management system, activity data is collected and analyzed for patterns. The information management system may be policy based. Activity data may be organized as entries including information on user, application, machine, action, object or document, time, and location. When checking for patterns in the activity or historical data, techniques may include inferencing, frequency checking, location and distance checking, and relationship checking, and any combination of these. Analyzing the activity data may include comparing like types or categories of information for two or more entries. | 2015-01-15 |
20150019763 | Multifunctional I/O Apparatus - Multifunctional I/O apparatus having one connection terminal with two connections and an electronic circuit, which with the assistance of a plurality of settable operating states detects an active input signal or passive input signal applied on the two connections of the connection terminal or controls/switches an externally driven load. | 2015-01-15 |
20150019764 | INFORMATION DISPLAYING METHOD, MOBILE TERMINAL DEVICE AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM - Examples of the present disclosure may provide an information displaying method, mobile terminal device and non-transitory computer readable storage medium. The method may include: monitoring an execution status of an application on a mobile terminal device, obtaining memory information of the mobile terminal device when a monitoring result shows that the application is executed and displaying the memory information of the mobile terminal device on the mobile terminal device. | 2015-01-15 |
20150019765 | VIRTUAL INTERRUPT FILTER - A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked. | 2015-01-15 |
20150019766 | BUFFER MEMORY RESERVATION TECHNIQUES FOR USE WITH A NAND FLASH MEMORY - This disclosure provides examples of circuits, devices, systems, and methods for managing a buffer memory. Regions of the buffer memory are dynamically reserved, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation. | 2015-01-15 |
20150019767 | SEMICONDUCTOR MEMORY DEVICE HAVING DATA COMPRESSION TEST CIRCUIT - A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal. | 2015-01-15 |
20150019768 | SOFTWARE INTERFACE FOR A SPECIALIZED HARDWARD DEVICE - Embodiments of the disclosure include methods, systems and computer program products for performing a data manipulation function. The method includes receiving, by a processor, a request from an application to perform the data manipulation function and based on determining that a specialized hardware device configured to perform the data manipulation function is available, the method includes determining if executing the request on the specialized hardware device is viable. Based on determining that the request is viable to execute on the specialized hardware device, the method includes executing the request on the specialized hardware device. | 2015-01-15 |
20150019769 | DATA EXCHANGE AND STORAGE DEVICE - The invention concerns a device ( | 2015-01-15 |
20150019770 | DYNAMICALLY CALIBRATING THE OFFSET OF A RECEIVER WITH A DECISION FEEDBACK EQUALIZER (DFE) WHILE PERFORMING DATA TRANSPORT OPERATIONS - Dynamically calibrating an offset of a receiver with a DFE while performing data transport operations, the DFE comprising a plurality of independent data transport banks, at least one data transport bank operating a data transport mode and at least one data transport bank operating in a calibration mode, including: iteratively, while carrying out data transport operations: utilizing the data transport bank operating in the data transport mode to perform data transport operations; calibrating the data transport bank operating in the calibration mode; and upon completing calibration of the data transport bank operating in the calibration mode, switching the mode of each data transport bank. | 2015-01-15 |
20150019771 | DAISY CHAIN COMMUNICATION BUS AND PROTOCOL - A battery pack has first and second battery terminals, plural battery cells each with a battery element, a cell supervisor electrically connected to the battery element, and a communication section to communicate with the cell supervisor. The battery elements are connected serially between the first and second battery terminals. Bus interfaces are arranged in alternating fashion with the battery cells to define a daisy chain bus, each such bus interface being configured for signal communication, the interfaces respectively connecting the communication sections of two adjacent battery cells. A battery manager communicates with the battery cells via the daisy chain bus. The battery manager sends a command message to the battery cells using a through mode protocol, and each battery cell sends at least one of a confirmation message and a service request to the battery manager using a shift mode protocol. | 2015-01-15 |
20150019772 | SIGNAL PROCESSING APPARATUS - A signal processing apparatus includes a switch, a signal conditioner, multiple storage units, and a controller. Each of the storage units stores a set of signal transmission parameters in compliance with a communication protocol. The controller sends one or more control signals to the switch. The switch selects one of the storage units according to the control signals and connects the signal conditioner to the selected storage unit. The signal conditioner retrieves a set of signal transmission parameters from the selected storage unit. The signal conditioner receives a data signal from a transmitter, conditions the data signal according to the retrieved set of signal transmission parameters, and transmits the conditioned data signal to a receiver. A signal processing method is also disclosed. | 2015-01-15 |
20150019773 | SIGNAL PROCESSING APPARATUS - A signal processing apparatus includes a switch, a signal conditioner, and multiple storage units. Each of the storage units stores a set of signal transmission parameters in compliance with a communication protocol. The switch selects one of the storage units and connects the signal conditioner to the selected storage unit. The signal conditioner retrieves a set of signal transmission parameters from the selected storage unit. The signal conditioner receives a data signal from a transmitter, conditions the data signal according to the retrieved set of signal transmission parameters, and transmits the conditioned data signal to a receiver. A signal processing method is also disclosed. | 2015-01-15 |
20150019774 | SIGNAL PROCESSING APPARATUS - A signal processing apparatus includes a storage unit, a signal conditioner, and a controller. The controller connected writes a set of signal transmission parameters in compliance with a communication protocol into the storage unit. The signal conditioner retrieves the set of signal transmission parameters from the storage unit. The signal conditioner receives a data signal from a transmitter, conditions the data signal according to the retrieved set of signal transmission parameters, and transmits the conditioned data signal to a receiver. A signal processing method is also disclosed. | 2015-01-15 |
20150019775 | Single Wire Programming and Debugging Interface - A microcontroller has a housing with external pins and an integrated debugging interface using only a single signal pin. In a method for operating a microcontroller as described above, the method includes the step of debugging or programming the microcontroller using only a single signal pin of the external pins. | 2015-01-15 |
20150019776 | SELECTIVE CHANGE OF PENDING TRANSACTION URGENCY - The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed. | 2015-01-15 |
20150019777 | CONFIGURATION VIA HIGH SPEED SERIAL LINK - Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided. | 2015-01-15 |
20150019778 | SWITCH FABRIC HAVING A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 2015-01-15 |
20150019779 | MICROCOMPUTER - To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality. | 2015-01-15 |
20150019780 | CONTROLLING OPERATIONS ACCORDING TO ANOTHER SYSTEM'S ARCHITECTURE - An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt. | 2015-01-15 |
20150019781 | MANAGING OVER-INITIATIVE THIN INTERRUPTS - A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt. | 2015-01-15 |
20150019782 | MESSAGE BROADCAST IN A 1-WIRE SYSTEM - A message is simultaneously broadcast to multiple systems on a 1-wire bus. A first addressed communication session is established between a microprocessor and a first 1-wire I/O expander via a 1-wire bus, where the first 1-wire I/O expander is electrically coupled to a first system. The first 1-wire I/O expander is placed into “fast access mode”, and then removed from the 1-wire bus by opening a switch to the 1-wire bus. A second addressed communication session is established between the microprocessor and a second 1-wire I/O expander before the switch recloses, where the second 1-wire I/O expander is electrically coupled to a second system. The second 1-wire I/O expander is then placed into “fast access mode”. In response to the timer expiring and the switch reclosing, an unaddressed message is broadcast from the microprocessor to the first and second systems via the first and second 1-wire I/O expanders. | 2015-01-15 |
20150019783 | SYSTEM AND METHOD FOR ACCESSING A USER INTERFACE VIA A SECONDARY DEVICE - An adapter provides a link between a digital media player having a memory on which is stored digital media files, a display device, and a remote control. The adapter receives from the digital media player data which is used to generate a representation of a user interface which is provided to the display device for display. The adapter also receives from the remote control data for use in generating commands for controlling operations of the digital media player whereby a change in state of the digital media player resulting from a performance of an operation caused by the remote control will be reflected in the user interface on the display device. | 2015-01-15 |
20150019784 | STORAGE DEVICE AND MOTHERBOARD ABLE TO SUPPORT THE STORAGE DEVICE - A motherboard assembly able to use a PCI slot either to expand system function or for the installation of additional memory includes a motherboard and a storage device. The motherboard includes a PCI expansion slot, a platform controller hub (PCH), and a power circuit. The PCI expansion slot includes a protrusion, four idle pins and first signal pins connected to the PCH, and first power pins connected to the power circuit. A control chip, a number of storage chips connected to the control chip, and a power unit are arranged on the storage device. A non-central notch is included in an edge connector arranged on a bottom edge of the storage device and the edge connector allows for power pins connected to the power unit and signal pins connected to the control chip. | 2015-01-15 |
20150019785 | INFORMATION PROCESSING APPARATUS AND METHOD FOR HOT PLUG - An information processing apparatus of the embodiment includes: a data storage unit to store a virtual address in association with first information that includes at least identification information of a slot; and circuitry. And the circuitry is configured to : detect an interrupt that notifies an operating system that a first PCI card was replaced and is output from a second PCI card by which the first PCI card was replaced on a certain slot; extract, from the data storage unit, a virtual address associated with first information that includes identification information of the certain slot, upon detecting the interrupt; and set the second PCI card so as to communicate using the extracted virtual address. | 2015-01-15 |
20150019786 | METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES - A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time. | 2015-01-15 |
20150019787 | DATA INTERLEAVING MODULE - The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register. | 2015-01-15 |
20150019788 | Providing A Sideband Message Interface For System On A Chip (SoC) - According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed. | 2015-01-15 |
20150019789 | METHOD AND APPARATUS FOR SECURING AND SEGREGATING HOST TO HOST MESSAGING ON PCIE FABRIC - A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols. | 2015-01-15 |
20150019790 | COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 2015-01-15 |
20150019791 | CONTROL CIRCUIT OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A control circuit includes a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the ROM address corresponding to said time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to said time point. | 2015-01-15 |
20150019792 | SYSTEM AND METHOD FOR IMPLEMENTING TRANSACTIONS USING STORAGE DEVICE SUPPORT FOR ATOMIC UPDATES AND FLEXIBLE INTERFACE FOR MANAGING DATA LOGGING - Systems and methods provide an efficient method for executing transactions on a storage device (e.g., a disk or solid-state disk) by using special support in the storage device for making a set of updates atomic and durable. The storage device guarantees that these updates complete as a single indivisible operation and that if they succeed, they will survive permanently despite power loss, system failure, etc. The storage device performs transaction (e.g., read/write) operations directly at storage device controllers. As a result, transactions execute with lower latency and consume less communication bandwidth between the host and the storage device. Additionally, a unique interface is provided which allows the application to manage the logs used by the hardware. | 2015-01-15 |
20150019793 | SELF-MEASURING NONVOLATILE MEMORY DEVICES WITH REMEDIATION CAPABILITIES AND ASSOCIATED SYSTEMS AND METHODS - Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU) and a nonvolatile memory device operably coupled to the CPU. The nonvolatile memory device can include a memory that stores pre-measurement instructions that are executable by the nonvolatile memory upon startup, but not executable by the CPU upon startup. In operation, the pre-measurement instructions direct the nonvolatile memory to take a measurement of at least a portion of its contents and to cryptographically sign the measurement to indicate that the measurement was taken by the nonvolatile memory device. In one embodiment, the CPU can use the measurement to determine whether the nonvolatile memory device is trustworthy. | 2015-01-15 |
20150019794 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device and a method of operating the same. The data storage device includes a nonvolatile memory device and a working memory device. The working memory device is configured to store an address mapping table to map a physical address associated with the nonvolatile memory device to a logical address associated with a host device. The data storage device further includes a controller configured to identify a hot address mapping table from a plurality of address mapping tables, based on an address mapping table classification, and store the hot address mapping table into the working memory device at an operation start time of the data storage device. | 2015-01-15 |
20150019795 | MEMORY SYSTEM FOR SHADOWING VOLATILE DATA - An apparatus configured to shadow volatile data while minimizing read latency is described. In an implementation, the apparatus includes a memory controller configured to operatively couple to a volatile memory device and a non-volatile memory device. The volatile memory device includes a volatile memory cell and the non-volatile memory device includes a corresponding non-volatile memory cell. The volatile memory device has a first transfer speed and the non-volatile memory device has a second transfer speed. The memory controller is configured to cause storage of data to the volatile memory cell and the non-volatile memory cell and to determine an occurrence of an unanticipated power outage. The memory controller is configured set a read speed to the second transfer speed and to cause replication of the data from the non-volatile memory cell to a corresponding volatile memory cell upon recovery from the unanticipated power outage. | 2015-01-15 |
20150019796 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a data storage device, which includes a first memory area and a second memory area, includes selecting a victim block for securing a free area from the first memory area, calculating a first cost required when a merge operation for the victim block is performed in the first memory area, calculating a second cost required when the merge operation for the victim block is performed in the second memory area, and performing the merge operation in the first memory area or the second memory area based on the first and second costs. | 2015-01-15 |
20150019797 | Method and Apparatus for Providing Improved Garbage Collection Process In Solid State Drive - An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection. | 2015-01-15 |
20150019798 | Method and Apparatus for Providing Dual Memory Access to Non-Volatile Memory - A method and system for providing a dual memory access to a non-volatile memory device using expended memory addresses are disclosed. The digital processing system such as a computer includes a non-volatile memory device, a peripheral bus, and a digital processing unit. The non-volatile memory device such as a solid state drive can store data persistently. The peripheral bus, which can be a peripheral component interconnect express (“PCIe”) bus, is used to support memory access to the non-volatile memory device. The digital processing unit such as a central processing unit (“CPU”) is capable of accessing storage space in the non-volatile memory device in accordance with an extended memory address and offset. | 2015-01-15 |
20150019799 | MULTI-LEVEL MEMORY, MULTI-LEVEL MEMORY WRITING METHOD, AND MULTI-LEVEL MEMORY READING METHOD - A memory comprising a memory array unit including a plurality of data units, and a controller. The controller is configured to receive data; convert the data into converted data using a conversion rule for converting a data piece into another data piece, wherein the conversion rule is selected based on the data received and independent of current data written in a data unit; and write the converted data and a conversion rule identifier corresponding to the conversion rule into the data unit. | 2015-01-15 |
20150019800 | Firmware Package to Modify Active Firmware - A computing device includes a non-volatile storage component with a first portion to include active firmware for components of the computing device and a second portion to include a firmware package to modify the active firmware. The computing device installs firmware from the firmware package and determines if the firmware is successfully installed before proceeding to install subsequent firmware from the firmware package. The computing device uninstalls the firmware package to restore the active firmware if a firmware from the firmware package fails to install. | 2015-01-15 |
20150019801 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device. | 2015-01-15 |
20150019802 | MONOLITHIC THREE DIMENSIONAL (3D) RANDOM ACCESS MEMORY (RAM) ARRAY ARCHITECTURE WITH BITCELL AND LOGIC PARTITIONING - A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device. | 2015-01-15 |
20150019803 | PARTITIONED MEMORY WITH SHARED MEMORY RESOURCES AND CONFIGURABLE FUNCTIONS - A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The memory device includes a memory block having a plurality of banks, wherein each of the banks has a plurality of memory cells, and wherein the memory block has multiple ports. An output interface provides data on a second plurality of serial links. A cache coupled to the IO interface and to the plurality of banks, stores write data designated for a given memory cell location when the given memory cell location is currently being accessed, thereby avoiding a collision. Memory device includes one or more memory access controllers (MACs) coupled to the memory block and one or more arithmetic logic units (ALUs) coupled to the MACs. The ALUs perform one or more operations on data prior to the data being transmitted out of the IC via the IO, such as read/modify/write or statistics or traffic management functions, thereby reducing congestion on the serial links and offloading appropriate operations from the host to the memory device. | 2015-01-15 |
20150019804 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 2015-01-15 |
20150019805 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR THE SAME, PROGRAM FOR THE SAME, AND STORAGE MEDIUM - An information processing apparatus according to an aspect of the present invention acquires temperature information for each of a plurality of memories in a wide IO memory device, and when execution of a job is instructed, decides on a memory having a lower temperature as the memory to be used by a functional module that corresponds to a function, based on the memory size to be used by the functional module that corresponds to the function, and on the acquired temperature information for the memories. | 2015-01-15 |
20150019806 | MEMORY DEVICE WITH PAGE EMULATION MODE - In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row. | 2015-01-15 |
20150019807 | LINEARIZED DYNAMIC STORAGE POOL - The present technology provides a two step process for providing a linearized dynamic storage pool. First, physical storage devices are abstracted. The physical storage devices used for the pool are divided into extents, grouped by storage class, and stripes are created from data chunks of similar classified devices. A virtual volume is then provisioned from and the virtual volume is divided into virtual stripes. A volume map is created to map the virtual stripes with data to the physical stripes, linearly mapping the virtual layout to the physical capacity to maintain optimal performance. | 2015-01-15 |
20150019808 | HYBRID STORAGE CONTROL SYSTEM AND METHOD - Disclosed are a hybrid storage control system and method. Hard disk arrays are divided into a solid-state hard disk array and a disk-type hard disk array according to a type, and the solid-state hard disk array is used as a default data read source, thereby improving a data read speed of the system without reducing security performance of the system. In addition, sequential write is adopted for a manner of writing data into a normal hard disk, so that disk head seeking is not required in a write operation, and the speed of writing the data into the normal hard disk matches the speed of writing the data in a solid-state hard disk, thereby further improving a data write speed. The present invention is applicable to various storage systems including both a solid-state hard disk and a disk-type hard disk. | 2015-01-15 |
20150019809 | PROVIDING REDUNDANCY IN A VIRTUALIZED STORAGE SYSTEM FOR A COMPUTER SYSTEM - A method for providing redundancy in a virtualized storage system for a computer system is provided. The method includes determining first set of first logical addresses to provide a virtual storage volume, A redundancy schema is then selected to provide redundancy data for primary data stored in the first set of first logical addresses. A second set of second logical addresses is determined to provide logical storage for the primary data and for the redundancy data. The first set of first logical addresses and the second set of second logical addresses are then mapped and a set of physical address es is selected from a set of physical storage elements. Mapping between the second set of second logical addresses and the set of physical addresses is then performed to provide physical storage for the primary data and the redundancy data stored in the virtual storage volume. | 2015-01-15 |
20150019810 | WRITING ADJACENT TRACKS TO A STRIDE, BASED ON A COMPARISON OF A DESTAGING OF TRACKS TO A DEFRAGMENTATION OF THE STRIDE - Compressed data is maintained in a plurality of strides of a redundant array of independent disks, wherein a stride is configurable to store a plurality of tracks. A request is received to write one or more tracks. The one or more tracks are written to a selected stride of the plurality of strides, based on comparing the number of operations required to destage selected tracks from the selected stride to the number of operations required to defragment the compressed data in the selected stride. | 2015-01-15 |
20150019811 | REMOVABLE STORAGE MEDIA CONTROL APPARATUS FOR PREVENTING DATA LEAKAGE AND METHOD THEREOF - A device and method for controlling a removable storage medium to prevent data leakage are provided. The device includes a storage medium determination unit, a storage medium policy acquisition unit, and a storage medium control unit. The storage medium determination unit determines whether a connected storage medium is a removable storage medium. If the storage medium is the removable storage medium, the storage medium policy acquisition unit acquires hierarchical storage medium policies having a hierarchical structure for the storage medium. The storage medium control unit controls the storage medium by switching between a storage medium connection state and a storage medium usage state using the acquired hierarchical storage medium policies. | 2015-01-15 |
20150019812 | REPLICATION BETWEEN SITES USING KEYS ASSOCIATED WITH MODIFIED DATA - Systems and methods are disclosed for replicating data stored in an in-memory data cache to a remote site. An example system includes an in-memory data cache and an in-memory keys cache. The system also includes a key insert module that detects a modification to the in-memory data cache, identifies one or more keys of the plurality of keys based on the modification, and inserts the identified one or more keys into the in-memory keys cache. The system further includes an update module that retrieves from the in-memory keys cache a set of keys, retrieves from the in-memory data cache modified data associated with the set of keys, and transmits to a remote site a modification list including the set of keys and the modified data associated with the set of keys. | 2015-01-15 |
20150019813 | MEMORY HIERARCHY USING ROW-BASED COMPRESSION - A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory. | 2015-01-15 |
20150019814 | Extract Target Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 2015-01-15 |
20150019815 | UTILIZING GLOBAL DIGESTS CACHING IN DATA DEDUPLICATION OF WORKLOADS - For utilizing a global digests cache in data deduplication of difficult workloads in a data deduplication system using a processor device in a computing environment, input data is partitioned into data chunks and digest values are calculated for each of the data chunks. A search for similar data in a repository of data is preformed. Input digests of the input data are matched with repository digests contained in the global digests cache for finding data matches, if the search for the similar repository data in the repository of data fails to find the similar repository data. | 2015-01-15 |
20150019816 | UTILIZING GLOBAL DIGESTS CACHING IN SIMILARITY BASED DATA DEDUPLICATION - Input data is partitioned into data chunks and digest values are calculated for each of the data chunks. The positions of similar repository data are found in a repository of data for each of the data chunks. The repository digests of the similar repository data are located and loaded into the global digests cache. The global digests cache contains digests previously loaded by other deduplication processes. The input digests of the input data are matched with the repository digests contained in the global digests cache for locating data matches. The processor prefers to match the input digests of the input data with the repository digests contained in the global digests cache which are of the similar repository data, rather than repository digests which are of other repository data that was not determined as similar to the input data chunks. | 2015-01-15 |
20150019817 | TUNING GLOBAL DIGESTS CACHING IN A DATA DEDUPLICATION SYSTEM - Input data is partitioned into data chunks and digest values are calculated for each of the data chunks. The positions of similar repository data are found in a repository of data for each of the data chunks. The repository digests of the similar repository data are located and loaded into the global digests cache. The global digests cache contains digests previously loaded by other deduplication processes. The input digests of the input data are matched with the repository digests contained in the global digests cache for locating data matches. A sample of the repository digests is loaded into a search mechanism within the global digests cache. | 2015-01-15 |
20150019818 | Maintaining Cache Size Proportional to Power Pack Charge - The present disclosure is directed to a method for managing a cache based on a charge of a power source. The method includes the step of determining a charge of the power source at a first time instance. The method also includes the step of designating for write back cache an amount of data in the cache which can be offloaded from the cache based on the charge of the power source at the first time instance. The method also includes the step of designating as write through cache an amount of data remaining in the cache which was not designated as write back cache. | 2015-01-15 |
20150019819 | PREFETCHING FOR MULTIPLE PARENT CORES IN A MULTI-CORE CHIP - Embodiments relate to a method and computer program product for prefetching data on a chip. The chip has at least one scout core, multiple parent cores that cooperate together to execute various tasks, and a shared cache that is common between the scout core and the multiple parent cores. An aspect of the embodiments includes monitoring the multiple parent cores by the at least one scout core through the shared cache for a shared cache access occurring in a base parent core. The method includes saving a fetch address by the at least one scout core based on the shared cache access occurring. The fetch address indicates a location of a specific line of cache requested by the base parent core. | 2015-01-15 |
20150019820 | PREFETCHING FOR A PARENT CORE IN A MULTI-CORE CHIP - Embodiments of the invention relate to prefetching data on a chip having at least one scout core, at least one parent core, and a shared cache that is common between the at least one scout core and the at least one parent core. A prefetch code is executed by the scout core for monitoring the parent core. The prefetch code executes independently from the parent core. The scout core determines that at least one specified data pattern has occurred in the parent core based on monitoring the parent core. A prefetch request is sent from the scout core to the shared cache. The prefetch request is sent based on the at least one specified pattern being detected by the scout core. A data set indicated by the prefetch request is sent to the parent core by the shared cache. | 2015-01-15 |
20150019821 | SPECIFIC PREFETCH ALGORITHM FOR A CHIP HAVING A PARENT CORE AND A SCOUT CORE - Embodiments relate to a method and computer program product for prefetching data on a chip having at least one scout core and a parent core. The method includes saving a prefetch code start address by the parent core. The prefetch code start address indicates where a prefetch code is stored. The prefetch code is specifically configured for monitoring the parent core based on a specific application being executed by the parent core. The method includes sending a broadcast interrupt signal by the parent core to the at least one scout core. The broadcast interrupt signal being sent based on the prefetch code start address being saved. The method includes monitoring the parent core by the prefetch code executed by at least one scout core. The scout core executes the prefetch code based on receiving the broadcast interrupt signal. | 2015-01-15 |
20150019822 | System for Maintaining Dirty Cache Coherency Across Reboot of a Node - Nodes in a data storage system having redundant write caches identify when one node fails. A remaining active node stops caching new write operations, and begins flushing cached dirty data. Metadata pertaining to each piece of data flushed from the cache is recorded. Metadata pertaining to new write operations are also recorded a corresponding data flushed immediately when the new write operation involves data in the dirty data cache. When the failed node is restored, the restored node removes all data identified by the metadata from a write cache. Removing such data synchronizes the write cache with all remaining nodes without costly copying operations. | 2015-01-15 |
20150019823 | METHOD AND APPARATUS RELATED TO CACHE MEMORY - A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line. | 2015-01-15 |
20150019824 | CACHE PRE-FETCH MERGE IN PENDING REQUEST BUFFER - An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured to receive a request for a first cache line from a pre-fetch engine, and store the received request in an entry of the pending request buffer. The control circuit may be further configured to receive a request for a second cache line from a processor, and store the request received from the processor in the entry of the pending request buffer in response to a determination that the second cache line is the same as the first cache line. | 2015-01-15 |
20150019825 | SHARING VIRTUAL MEMORY-BASED MULTI-VERSION DATA BETWEEN THE HETEROGENEOUS PROCESSORS OF A COMPUTER PLATFORM - A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data. | 2015-01-15 |
20150019826 | STORAGE CONTROLLING DEVICE AND CONTROLLING METHOD - A Controller Module (CM) includes a memory that temporarily stores therein data to be written into storage, a switch that connects to another CM and a DMA controller that transfers the data stored in the memory to the other CM via the switch. The DMA controller reads a transfer status of the transferred data from the switch and writes the read transfer status into the memory. | 2015-01-15 |
20150019827 | GENERATING AND USING CHECKPOINTS IN A VIRTUAL COMPUTER SYSTEM - To generate a checkpoint for a virtual machine (VM), first, while the VM is still running, a copy-on-write (COW) disk file is created pointing to a parent disk file that the VM is using. Next, the VM is stopped, the VM's memory is marked COW, the device state of the VM is saved to memory, the VM is switched to use the COW disk file, and the VM begins running again for substantially the remainder of the checkpoint generation. Next, the device state that was stored in memory and the unmodified VM memory pages are saved to a checkpoint file. Also, a copy may be made of the parent disk file for retention as part of the checkpoint, or the original parent disk file may be retained as part of the checkpoint. If a copy of the parent disk file was made, then the COW disk file may be committed to the original parent disk file. | 2015-01-15 |
20150019828 | SYSTEM AND METHOD FOR MIRRORING DATA - Disclosed is a data processing and/or storage system. The data processing and/or storage system includes at least two interfaces, wherein each of the at least two interfaces includes a non-dedicated communication port for communicating data to and form external data systems or clients based on a rule base. | 2015-01-15 |
20150019829 | DYNAMIC DATA SET REPLICA MANAGEMENT - Systems and methods dynamically manage replicas of data sets. A collection of data stores is used to redundantly store one or more replicas of one or more data sets. The replicas may be used to respond to read requests from multiple sources. Upon identification of a need to allocate storage space to a data object, space used by one or more of the replicas is allocated to the data object. Various parameters may be utilized in the selection of one or more replicas whose storage space can be allocated to the data object. The parameters may be based at least in part on characteristics of the one or more data sets relative to one another. | 2015-01-15 |
20150019830 | DYNAMIC ADDRESS MAPPING FOR FINISH IN THE FIELD - Implementations disclosed herein provide for dynamically mapping logical block addresses (LBA) of unfinished data blocks to unused data blocks during an in-the-field finishing process of a storage medium. Such dynamic mapping creates an impression that the storage medium operates at an advertised capacity before the effective capacity is equal to the advertised capacity. | 2015-01-15 |
20150019831 | DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM - A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous. | 2015-01-15 |
20150019832 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal. | 2015-01-15 |
20150019833 | HIERARCHICAL CONTENT DEFINED SEGMENTATION OF DATA - A method, system, and computer program product for segmenting data into variable size blocks based on content defined positions. Segmenting probabilities and associated segmenting conditions are defined. The segmenting conditions are ordered in accordance with the associated segmenting probabilities to form a hierarchy of the segmenting conditions. A segmenting condition associated with a highest segmenting probability is defined to be a lowest level segmenting condition in the hierarchy of the segmenting conditions. The segmenting condition associated with a lowest segmenting probability is defined to be a highest level segmenting condition in the hierarchy of the segmenting conditions. Hash values are calculated for each seed block in each consecutive byte position in the data. Each one of the hash values is evaluated using the segmenting conditions. A segmenting position is determined in the data for each hash value that satisfies one of the segmenting conditions. | 2015-01-15 |
20150019834 | MEMORY HIERARCHY USING PAGE-BASED COMPRESSION - A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory. | 2015-01-15 |
20150019835 | Predication Methods for Vector Processors - A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data. | 2015-01-15 |
20150019836 | REGISTER FILE STRUCTURES COMBINING VECTOR AND SCALAR DATA WITH GLOBAL AND LOCAL ACCESSES - The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit. | 2015-01-15 |
20150019837 | DATA PROCESSOR - A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers. | 2015-01-15 |
20150019838 | Vector Load and Duplicate Operations - A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern. | 2015-01-15 |
20150019839 | DETERMINING PROCESSOR OFFSETS TO SYNCHRONIZE PROCESSOR TIME VALUES - Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted. | 2015-01-15 |
20150019840 | Highly Integrated Scalable, Flexible DSP Megamodule Architecture - This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error. | 2015-01-15 |
20150019841 | ANTICIPATED PREFETCHING FOR A PARENT CORE IN A MULTI-CORE CHIP - Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. A method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch table address determined by the parent core to the scout core. The method includes accessing a fetch table that is indicated by the fetch table address by the scout core. The fetch table indicates how many of pieces of content are to be fetched by the scout core and a location of the pieces of content. The method includes based on the fetch table indicating, fetching the pieces of content by the scout core. The method includes returning the fetched pieces of content to the parent core. | 2015-01-15 |
20150019842 | Highly Efficient Different Precision Complex Multiply Accumulate to Enhance Chip Rate Functionality in DSSS Cellular Systems - This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product. | 2015-01-15 |
20150019843 | METHOD AND APPARATUS FOR SELECTIVE RENAMING IN A MICROPROCESSOR - A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register. | 2015-01-15 |
20150019844 | SYNTHETIC PROCESSING DIVERSITY WITHIN A HOMOGENEOUS PROCESSING ENVIRONMENT - A method of increasing processing diversity on a computer system includes: loading a plurality of instruction streams, each of the plurality of instruction streams being equivalent; executing, in a context, a first stream of the plurality of instruction streams; stopping execution of the first stream at a first location of the first stream; and executing, in the context, a second stream of the plurality of instruction streams at a second location of the second stream, the second location corresponding to the first location of the first stream. | 2015-01-15 |
20150019845 | Method to Extend the Number of Constant Bits Embedded in an Instruction Set - The invention allows a processor to maintain a fixed instruction width regardless of the width of the constants needed. The constant extension solves the problem of having variable length opcodes to accommodate longer constants. The invention allows the architecture to have a fixed width, regardless of the width of the constants specified, which simplify instruction decoding. Constant widths can be variable and extend beyond the fixed processor instruction width. | 2015-01-15 |
20150019846 | SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT - Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices. | 2015-01-15 |
20150019847 | Programmable CPU Register Hardware Context Swap Mechanism - A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context. | 2015-01-15 |
20150019848 | ASYNCHRONOUS LOOKAHEAD HIERARCHICAL BRANCH PREDICTION - Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a processing circuit, for an entry corresponding to the search request in a first-level branch target buffer. The method also includes, based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. The method additionally includes, based on locating the entries in the second-level branch target buffer, performing a bulk transfer of the entries from the second-level branch target buffer. | 2015-01-15 |
20150019849 | SEMI-EXCLUSIVE SECOND-LEVEL BRANCH TARGET BUFFER - Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB | 2015-01-15 |
20150019850 | Method and Apparatus for Firmware Based System Security, Integrity, and Restoration - Methods and systems for firmware based system security, integrity, and restoration are disclosed, including (a) determining in a pre-boot environment which mode a security and policy enforcement platform (“platform”) should be loaded into firmware of a computing system; (b) if the determination made in step (a) is that it is the first time for the platform to be loaded, then loading the platform into a setup mode; (c) if the determination made in step (a), above, is that a valid certificate from the platform is on a file system accessible in the firmware of the computing system, then loading the platform into a configuration mode; and (d) if the determination made in step (a), above, is that the platform is set to an active/active-test mode, then loading the platform into the active/active-test mode. Other embodiments are described and claimed. | 2015-01-15 |
20150019851 | STATE DEPENDENT OPTIMIZATION FOR SEQUENTIAL BOOTING OF HETEROGENEOUS SYSTEMS - A method and computer program product for implementing the method, where the method comprises obtaining boot dependencies among a plurality of systems, wherein a boot dependency identifies a dependent system, a service system that provides a service to the dependent system, a provide state of the service system, and a need state of the dependent system that requires the service system to have reached the provide state. The method further comprises obtaining historical measurements of the time periods between states for each of the systems. Then, during a process of booting the plurality of systems, the method initiates boot of each dependant system at a time that is determined, based on the historical measurements, to allow the dependent system to reach the need state no earlier than the time at which the service system is determined, based on the historical measurements, to reach the provide state. | 2015-01-15 |
20150019852 | VERIFICATION METHOD FOR SYSTEM EXECUTION ENVIRONMENT - The present invention provides a verification method for system execution environment. According to the present invention, at least an algorithm is used for operating a basic input/output system (BIOS) and loaded program check information, a first characteristic code and operation system check information, a second characteristic code and file system check information, a third characteristic system library check information, and a fourth characteristic code and application program check information for acquiring the first to fifth characteristic codes. After verifying the first to fourth characteristic codes, unlocking a storage, loading an operational system, loading a file system, and loading a system library are executed. After all characteristic codes have passed verification, the application program is executed. Thereby, whether the execution environment for the system or program is reliable can be confirmed. | 2015-01-15 |
20150019853 | BOOT-UP METHOD OF E-FUSE, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a power-up signal generation unit suitable for receiving a first power supply voltage and a second power supply voltage higher the first power supply voltage and generating a power-up signal when the first and second power supply voltage increase to reach target levels, respectively, a voltage level adjusting unit suitable for generating a third power supply voltage by adjusting a voltage level of the second power supply voltage, a boot-up signal generation unit suitable for generating a boot-up signal in response to the power-up signal, and a circuit operation unit suitable for performing a boot-up operation using the third power supply voltage in response to the boot-up signal. | 2015-01-15 |
20150019854 | Booting Display Control Method And Associated Apparatus - Booting display control method and associated apparatus are disclosed. The apparatus includes a processor chip, wherein the processor chip includes a processor and a display. After the processor chip is activated, the processor loads the leading program and displays control program; the processor detects whether a vehicle backing indicator indicates vehicle backing; when the vehicle backing indicator indicates vehicle backing, the processor controls the display controller to realize the vehicle backing video display function through the display control program; and when the vehicle backing indicator does not indicate vehicle backing, the processor loads the operating system program. Through the method, the present invention is capable of displaying vehicle backing video display when loading the operating system program. | 2015-01-15 |