02nd week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090008708 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal. | 2009-01-08 |
20090008709 | Power Semiconductor Devices with Trenched Shielded Split Gate Transistor and Methods of Manufacture - A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches. Electrical contact to the conductive shield electrode can be made inside the active area. The device can also include a perimeter trench extending at least partially around the active trenches such that at least some of the active trenches are perpendicular to the perimeter trench, gate fingers extending from a perimeter gate poly runner located in said perimeter trench, and shield poly fingers extending from a perimeter shield poly runner located in the perimeter trench. The gate fingers are staggered with respect to the shield poly fingers. | 2009-01-08 |
20090008710 | Robust ESD LDMOS Device - A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width. | 2009-01-08 |
20090008711 | Fully Isolated High-Voltage MOS Device - A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub. | 2009-01-08 |
20090008712 | CARBON NANO-TUBE (CNT) THIN FILM COMPRISING METALLIC NANO-PARTICLES, AND A MANUFACTURING METHOD THEREOF - Disclosed is a carbon nanotube (CNT) thin film having metallic nanoparticles. The CNT thin film includes a plastic transparent substrate and a CNT composition coated on the substrate. The CNT composition includes a CNT and metallic nanoparticles distributed on the CNT surface. The plastic transparent substrate is flexible. The metallic nanoparticles are formed by heating a metallic precursor adsorbed in the CNT surface. A method of manufacturing the CNT thin film having metallic nanoparticles is also disclosed. A CNT-dispersed solution is prepared by mixing a CNT with a dispersant or a dispersion solvent. The CNT-dispersed solution is used to form a CNT thin film. Metallic precursors are implanted in the CNT thin film. Then, a heat-treatment is applied to transform the metallic precursors into metallic particles including metallic nanoparticles. | 2009-01-08 |
20090008713 | DISPLAY DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A display device is provided which includes: pixel circuits for pixel electrode switching, arranged on a substrate; and an interlayer insulating film covering the pixel circuits. In this display device, the interlayer insulating film has connection holes which expose at bottom portions thereof connection portions of the pixel circuits, and connection portions of adjacent pixel circuits of the pixel circuits are exposed at the bottom portions of the connection holes. A method for manufacturing the above display device is also provided. | 2009-01-08 |
20090008714 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A semiconductor device includes a semiconductor layer disposed between a semiconductor substrate and a gate electrode, a back gate insulating layer pattern disposed between the semiconductor layer and the semiconductor substrate, and a gate insulating layer disposed between the semiconductor layer and the gate electrode. The semiconductor substrate extends from both sides of the back gate insulating layer pattern to the gate insulating layer and is directly in contact with a sidewall of the semiconductor layer. | 2009-01-08 |
20090008715 | Method for manufacturing semiconductor device, and semiconductor device and electronic device - It is an object of the present invention to manufacture a semiconductor device easily and to provide a semiconductor device whose cost is reduced. According to the present invention, a thin film integrated circuit provided over a base insulating layer can be prevented from scattering by providing a region where a substrate and the base insulating layer are attached firmly after removing a peeling layer. Therefore, a semiconductor device including a thin film integrated circuit can be manufactured easily. In addition, since a semiconductor device is manufactured by using a substrate except a silicon substrate according to the invention, a large number of semiconductor devices can be manufactured at a time and a semiconductor device whose cost is reduced can be provided. | 2009-01-08 |
20090008716 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and a second gate insulating film for generating no Fermi level pinning in the second gate electrode, or generating Fermi level pinning weaker than that generated in the first gate electrode in the second gate electrode. | 2009-01-08 |
20090008717 | Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same - Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided. | 2009-01-08 |
20090008718 | STRESS ENHANCED CMOS CIRCUITS - A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner. | 2009-01-08 |
20090008719 | METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS - A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric. | 2009-01-08 |
20090008720 | METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS - A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric. | 2009-01-08 |
20090008721 | Semiconductor device - The semiconductor device includes first and second common source semiconductor layers respectively extending in a first direction, first and second logic gate circuits respectively composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET. The sources of the three-dimensional P-type FETs in the first and second logic gate circuits are joined to the first common source semiconductor layer. The sources of the three-dimensional N-type FETs in the first and second logic gate circuits are joined to the second common source semiconductor layer. The semiconductor layers of the three-dimensional P-type and N-type FETs in the first logic gate circuit are joined in their drain side, and The semiconductor layers of the three-dimensional P-type and N-type FETs in the second logic gate circuit are joined in their drain side. The dissipation of the FinFET can be improved. | 2009-01-08 |
20090008722 | Three-Dimensional Memory Cells - The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. | 2009-01-08 |
20090008723 | SEMICONDUCTOR COMPONENT INCLUDING AN EDGE TERMINATION HAVING A TRENCH AND METHOD FOR PRODUCING - A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone. | 2009-01-08 |
20090008724 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device according to the present invention comprises a gate insulating film | 2009-01-08 |
20090008725 | METHOD FOR DEPOSITION OF AN ULTRA-THIN ELECTROPOSITIVE METAL-CONTAINING CAP LAYER - A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer. | 2009-01-08 |
20090008726 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer. | 2009-01-08 |
20090008727 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi | 2009-01-08 |
20090008728 | Semiconductor device and manufacturing method of the same - A semiconductor device includes: a sensor element having a plate shape with a surface and including a sensor structure disposed in a surface portion of the sensor element; and a plate-shaped cap element bonded to the surface of the sensor element. The cap element has a wiring pattern portion facing the sensor element. The wiring pattern portion connects an outer periphery of the surface of the sensor element and the sensor structure so that the sensor structure is electrically coupled with an external element via the outer periphery. The sensor element does not have a complicated multi-layered structure, so that the sensor element is simplified. Further, the dimensions of the device are reduced. | 2009-01-08 |
20090008729 | IMAGE SENSOR PACKAGE UTILIZING A REMOVABLE PROTECTION FILM AND METHOD OF MAKING THE SAME - The present invention discloses a structure of image sensor package utilizing a removable protection film. The structure comprises a substrate with a die receiving cavity and inter-connecting through holes. Terminal pads are formed under the inter-connecting through holes and metal pads are formed on an upper surface of the substrate. A die is disposed within the die receiving cavity by an adhesion material. Bonding pads are formed on the upper edge of the die. Bonding wires are coupled to the metal pads and the bonding pads. A protection layer is formed on the micro lens area to protect the micro lens from particle contamination. A removable protection film is formed over the protection layer to protect the micro lens from water, oil, dust or temporary impact during the packaging and assembling process. | 2009-01-08 |
20090008730 | Integrated optical filter - The disclosure relates to an integrated circuit comprising at least one photosensitive cell. The cell includes a photosensitive element, an input face associated with the said photosensitive element, an optical filter situated in at least one optical path leading to the photosensitive element and an interconnection part situated between the photosensitive element and the input face. The optical filter is disposed between the photosensitive element and the surface of the interconnection part closest to the input face. In particular, the optical filter can be disposed within the interconnection part. The disclosure also proposes that the filter be formed using a glass comprising cerium sulphide or at least one metal oxide. | 2009-01-08 |
20090008731 | Image Sensor and Method for Manufacturing the Same - An image sensor and method of manufacturing the same are provided. The image sensor can include a photodiode on a substrate, an interlayer insulation layer on the photodiode, and a color filter layer on the interlayer insulation layer. The color filter layer can include a nonsensitive color resin. | 2009-01-08 |
20090008732 | SEMICONDUCTOR PACKAGE - A chip-size semiconductor package can respond also to a semiconductor device in which an electrode pad pitch is narrow. A semiconductor package comprises a semiconductor substrate which has a first principal plane and a second principal plane, a circuit element formed on the first principal plane, two or more electrode pads connected to the circuit element provided on the first principal plane, two or more external connection terminals provided on the second principal plane, one or more through holes which reach at the second principal plane from the first principal plane, and two or more through wirings which connect the two or more electrode pads and the two or more external connection terminals through the one or more through holes respectively. | 2009-01-08 |
20090008733 | Electric field steering cap, steering electrode, and modular configurations for a radiation detector - A cap for a radiation detection device of the type that utilizes a semiconductor medium includes a bias connection pad, a steering electrode, and a shielding layer. The steering electrode may be a grid steering electrode positioned parallel to the bias connection pad opposite a medium, or may be an electrode disposed perpendicular to the bias connection pad along the edge of a medium. The bias connection pad may be electrically connected or equipotent to the steering electrode. The cap may be formed of flexible circuit board, which may also connect the semiconductor detector to bias, detection or processing circuitry. The bias connection pad and the shielding layer can be maintained with fixed spacing to prevent vibration. A mezzanine card may be used to connect multiple detectors in a modular fashion. | 2009-01-08 |
20090008734 | SEMICONDUCTOR LIGHT RECEIVING DEVICE AND PHOTOSEMICONDUCTOR MODULE - A semiconductor light receiving device includes: a light receiving section made of a semiconductor provided on a substrate; a mask layer provided above the light receiving section and having an opening configured to limit an irradiation area of the light receiving section; and a light scattering section provided in at least part of a light incident path in the opening and including a transparent material and light scattering particles dispersed in the transparent material. Light incident on the light receiving section passes through the light scattering section before being incident on the light receiving section. | 2009-01-08 |
20090008735 | PHOTO DETECTOR, IMAGE SENSOR, PHOTO-DETECTION METHOD, AND IMAGING METHOD - A photo detector includes a photoelectric conversion layer having a periodic structure made of a semiconductor material on a surface of the photoelectric conversion layer. In the photo detector, at least a part of a resonance region formed by the periodic structure is included in the photoelectric conversion layer of the photo detector. | 2009-01-08 |
20090008736 | METHOD FOR PHOTO-DETECTING AND APPARATUS FOR THE SAME - A method for photo-detecting and an apparatus for the same are provided. The apparatus for photo-detecting includes a first P-N diode and a second P-N diode. The first P-N diode, has a first P-N junction which has a first thickness, by which a first electrical signal is generated when irradiated by light, and the second P-N diode has a second P-N junction which has a second thickness, by which a second electrical signal is generated when irradiated by light. The second thickness is larger than the first thickness and an operation of the first electrical signal and the second electrical signal is proceeded for obtaining a third electrical signal. | 2009-01-08 |
20090008737 | Image Sensor Having Anti-Reflection Film and Method of Manufacturing the Same - Provided is an image sensor and a method of manufacturing the same. The image sensor includes anti-reflection films which are formed between a plurality of metal wire lines of the lowest metal wiring layer and a semiconductor substrate and between one of the metal wiring layers and another metal wiring layer. | 2009-01-08 |
20090008738 | AVALANCHE PHOTODIODE DETECTOR - An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region. | 2009-01-08 |
20090008739 | Photo Diodes Having a Conductive Plug Contact to a Buried Layer and Methods of Manufacturing the Same - Methods of manufacturing a photo diode include sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a substrate. The second and first epitaxial layers are etched to form a trench that exposes a portion of the buried layer. A conductive plug of the first conductivity type is formed in the trench. A first electrode is formed on an upper surface of the second epitaxial layer. A second electrode may be formed to contact an upper surface of the conductive plug. Photodiodes having a conductive plug contact to a buried layer are also provided. | 2009-01-08 |
20090008740 | Semiconductor Integrated Circuit Devices Having Conductive Patterns that are Electrically Connected to Junction Regions and Methods of Fabricating Such Devices - A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern. | 2009-01-08 |
20090008741 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT - A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion. | 2009-01-08 |
20090008742 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT - A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion. | 2009-01-08 |
20090008743 | CAPACITOR WITH PILLAR TYPE STORAGE NODE AND METHOD FOR FABRICATING THE SAME - A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer. | 2009-01-08 |
20090008744 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes: a first interlayer insulating film; a first conductive member provided lower than the first interlayer insulating film; a contact plug that penetrates through the first interlayer insulating film, and is electrically connected to the first conductive member, the contact plug including a small-diameter part, and a large-diameter part arranged on the small-diameter part, an outer diameter of the large-diameter part being larger than an outer diameter of the small-diameter part, and the outer diameter of the large-diameter part being larger than an outer diameter of a connection face between the second conductive member and the large-diameter part; and a second conductive member that is provided on the first interlayer insulating film, and is electrically connected to the contact plug. | 2009-01-08 |
20090008745 | Nitride Compound Semiconductor and Process for Producing the Same - A process for producing a nitride compound semiconductor represented by a general formula, In | 2009-01-08 |
20090008746 | METHOD OF FABRICATING SEMICONDUCTOR HIGH-VOLTAGE DEVICE - A semiconductor high-voltage device including a semiconductor substrate having a deep trench formed therein, a gate oxide film formed on sidewalls of the deep trench, a polysilicon layer formed in the deep trench and on the gate oxide film, and spacers formed on sidewalls of the trench at a portion of the deep trench above the gate oxide film. Loss of a gate oxide film can be prevented during processing, thereby also preventing a change of a current path, a phenomenon such as current leakage between a top surface of polysilicon and source/drain regions. | 2009-01-08 |
20090008747 | Semiconductor device and method for manufacturing thereof - A semiconductor device | 2009-01-08 |
20090008748 | ULTRA-THIN DIE AND METHOD OF FABRICATING SAME - In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die. | 2009-01-08 |
20090008749 | Device made of single-crystal silicon - A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a | 2009-01-08 |
20090008750 | SEAL RING FOR SEMICONDUCTOR DEVICE - A semiconductor device having a seal ring structure with high stress resistance is provided. The semiconductor device is provided with a semiconductor layer including a plurality of semiconductor elements, an insulating film formed on the semiconductor layer, and a body that passes through the insulating film and surrounds the semiconductor elements as a whole. The body includes a plurality of walls that are spaced apart from each other in a circumferential direction and are arranged in parallel with one another, and a plurality of bridges, each of which intersects at least one of the plurality of walls. | 2009-01-08 |
20090008751 | Method for Producing an Area having Reduced Electrical Conductivity Within a Semiconductor Layer and Optoelectronic Semiconductor Element - In a method for producing at least at least one area ( | 2009-01-08 |
20090008752 | Ceramic Thin Film On Various Substrates, and Process for Producing Same - The process of Polymer Assisted Chemical Vapor Deposition (PACVD) and the semiconductor, dielectric, passivating or protecting thin films produced by the process are described. A semiconductor thin film of amorphous silicon carbide is obtained through vapor deposition following desublimation of pyrolysis products of polymeric precursors in inert or active atmosphere. PA-CVD allows one or multi-layers compositions, microstructures and thicknesses to be deposited on a wide variety of substrates. The deposited thin film from desublimation is an n-type semiconductor with a low donor concentration in the range of 10 | 2009-01-08 |
20090008753 | INTEGRATED CIRCUIT WITH INTRA-CHIP AND EXTRA-CHIP RF COMMUNICATION - An integrated circuit includes a first integrated circuit die having a first circuit and a first intra-chip interface and a second integrated circuit die having a second circuit and a second intra-chip interface and a remote interface, wherein the first intra-chip interface and the second intra-chip interface electro-magnetically communicate first signals between the first circuit and the second circuit, and wherein the remote interface is coupled to engage in electromagnetic communications with a remote device. In an embodiment of the present invention, a shielding element shields the electromagnetic communications with the remote device from the electromagnetic communication of the first signals. In other embodiments, antenna beam patterns or differing polarizations are used to isolate the electromagnetic communications with the remote device from the electromagnetic communication of the first signals. | 2009-01-08 |
20090008754 | RESIN-SEALED SEMICONDUCTOR DEVICE, LEADFRAME WITH DIE PADS, AND MANUFACTURING METHOD FOR LEADFRAME WITH DIE PADS - A resin-sealed semiconductor device with built-in heat sink prevents internal bulging and cracking caused by exfoliation of a semiconductor element from the heat sink when the vapor pressure of moisture absorbed into a gap between the semiconductor element and the heat sink rises during mounting of the semiconductor device to a printed circuit board using lead-free solder. By providing a plurality of separated die pads ( | 2009-01-08 |
20090008755 | STRUCTURE AND METHOD FOR MANUFACTURING SMD DIODE FRAME - A structure of an SMD (surface mount device) diode frame is provided that comprises a plastic seat and a plurality of metal pins. One side of the plastic seat has a concave functional area and the other side of the plastic seat corresponding to the functional area has a plurality of concave reserved holes. The functional area and the reserved holes are respectively formed via a forming bolt and a positioning bolt in a mold. If the forming bolt and the positioning bolt abut against the metal pins respectively, the preciseness of the size of the functional area is increased and the overflow of the material of the plastic seat is decreased. Furthermore, the yield of the manufacturing processes is improved. | 2009-01-08 |
20090008756 | Multi-Chip Electronic Package with Reduced Stress - An electronic component includes lead fingers and a die paddle. A tape pad is mounted below the lead fingers and the die paddle. A first semiconductor chip is bonded onto the tape pad by a layer of first adhesive and a second semiconductor chip is bonded onto the die paddle by a layer of second adhesive. Electrical contacts are disposed between the contact areas of the semiconductors chips and the lead fingers. An encapsulating compound covers part of the lead fingers, the tape pad, the semiconductor chips and the electrical contacts. | 2009-01-08 |
20090008757 | METHOD OF FABRICATING SUBSTRATE FOR PACKAGE OF SEMICONDUCTOR LIGHT-EMITTING DEVICE - In the invention, a substrate and fabrication thereof for a package of at least one semiconductor device, such as semiconductor light-emitting devices, are disclosed. In particular, a base together with a frame supporting the base of the substrate according to the invention is formed of a thick-walled metal material, a special-shaped metal plate or a normal-shaped metal plate. The at least one semiconductor device is to mounted on a top surface of the base. Moreover, the base serves as a heat sink. | 2009-01-08 |
20090008758 | USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE - A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length. | 2009-01-08 |
20090008759 | Semiconductor device, lead frame, and manufacturing method for the lead frame - Provided is a semiconductor device having an element covered with a resin mold and a metal lead protruding from the resin mold in which a lead-tip portion thereof is entirely covered by solder plating and in which a lead-tip end surface, which is not covered by solder plating, has an area less than half of a cross-sectional area of the metal lead, whereby solder wettability of the metal lead is improved and a bonding strength to a circuit board is also improved. | 2009-01-08 |
20090008760 | SEMICONDUCTOR DEVICE HAS ENCAPSULANT WITH CHAMFER SUCH THAT PORTION OF SUBSTRATE AND CHAMFER ARE EXPOSED FROM ENCAPSULANT AND REMAINING PORTION OF SURFACE OF SUBSTRATE IS COVERED BY ENCAPSULANT - A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device. | 2009-01-08 |
20090008761 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEX BUMP - An integrated circuit package system includes: forming a flex bump over an integrated circuit device structure, the flex bump having both a base portion and an offset portion over the base portion; forming a first ball bond of a first internal interconnect over the offset portion; and encapsulating the integrated circuit device structure, the flex bump, and the first internal interconnect. | 2009-01-08 |
20090008762 | ULTRA SLIM SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic. Further, since the package thickness is very thin, the semiconductor package contributes to the slimming of diverse electronic products. | 2009-01-08 |
20090008763 | SEMICONDUCTOR PACKAGE - A semiconductor package, which may include a structure of a semiconductor package having a minimized mounting area and height. The semiconductor package may include a board, a first package comprising at least one first semiconductor chip, and disposed on the board so as to be supported, a second package comprising at least one second semiconductor chip, and disposed on the board so as be supported, and a third package that comprises at least one third semiconductor chip, the third package having a cross-sectional area greater than a cross-sectional area of the first package, the third package being disposed on the first package and the second package so as to be supported, wherein the cross-sectional areas of the third package and the first package are taken along a plane parallel to the board. | 2009-01-08 |
20090008764 | Ultra-Thin Wafer-Level Contact Grid Array - Wafer-level chip-scaled packaging (WLCSP) features are described in a semiconductor die having a plurality of lands providing electrical connection between a surface of the semiconductor die and an active layer of the semiconductor die. Each of the plurality of lands rises above the surface no more than 10 μm. The device also has a plurality of solder bars at corners of the semiconductor die, the plurality of solder bars also rising above the surface no more than 10 μm. The solder bars add overall contiguous surface area to the solder joints between the die package and its final attachment. | 2009-01-08 |
20090008765 | CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip. | 2009-01-08 |
20090008766 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes two semiconductor devices formed on the same surface, without stacking to each other. One of the semiconductor devices is directly installed on a fine line circuit layer, and the other semiconductor device is installed on the fine line circuit layer within a dielectric layer cavity. In the method of the present invention, electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 2009-01-08 |
20090008767 | INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED THERMAL PERFORMANCE - An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die. | 2009-01-08 |
20090008768 | SEMICONDUCTOR PACKAGE SYSTEM WITH PATTERNED MASK OVER THERMAL RELIEF - A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief. | 2009-01-08 |
20090008769 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first electrically conductive carrier composed of a first material, a second electrically conductive carrier composed of the first material, an electrically insulating element composed of a second material, which connects the first carrier and the second carrier to one another, a first semiconductor substrate applied to the first carrier, a second semiconductor substrate applied to the second carrier, and an electrically conductive layer applied above the first carrier, the second carrier and the insulating element. The electrically conductive layer electrically conductively connects the first semiconductor substrate to the second semiconductor substrate. | 2009-01-08 |
20090008770 | HEAT DISSIPATION PLATE AND SEMICONDUCTOR DEVICE - A heat dissipation plate having a lamination of a copper layer, a molybdenum layer and a graphite layer, and outer copper layers each provided on a surface of the lamination, is disclosed. And also a semiconductor device using the heat dissipation plate is disclosed. | 2009-01-08 |
20090008771 | SEMICONDUCTOR MODULE DEVICE, METHOD OF MANUFACTURING THE SAME, FLAT PANEL DISPLAY, AND PLASMA DISPLAY PANEL - Metal foil | 2009-01-08 |
20090008772 | Semiconductor Switching Module - A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer. | 2009-01-08 |
20090008773 | Mounted Semiconductor Device And A Method For Making The Same - A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses. | 2009-01-08 |
20090008774 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode terminals constitute a second transistor portion. The semiconductor device is quadrangular. | 2009-01-08 |
20090008775 | SEMICONDUCTOR DEVICE WITH WELDED LEADS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a manufacturing method for preventing mechanical and thermal damage to the semiconductor chip. A laser beam welds a first connection pad formed on a first external lead to a first electrode formed on the surface of the semiconductor chip. A first connection hole is formed in the first connection pad, and the first connection hole overlaps the first connection electrode. A laser beam irradiates an area including the first connection hole, and the first connection pad in a portion around the first connection hole is melted to form a melting section, that is welded to the first connection electrode to easily form a semiconductor device with more excellent electrical characteristics. | 2009-01-08 |
20090008776 | Electronic Component Mounted Body, Electronic Component with Solder Bump, Solder Resin Mixed Material, Electronic Component Mounting Method and Electronic Component Manufacturing Method - In an electronic component mounted body, an electrode of a first electronic component and an electrode of a second electronic component are electrically connected by a solder connecter, and the solder connecter contains solder and insulation filler. Alternatively, a solder bump is formed on the electrode of the electronic component, and the solder bump includes the insulation filler. | 2009-01-08 |
20090008777 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME - An interconnecting structure for a semiconductor die assembly, comprising: a substrate with pre-formed wiring circuit formed therein; a die having contact pads on an active surface; an adhesive material formed over the substrate to adhere the die over the substrate, wherein the substrate includes a via through the substrate and the adhesive material; and conductive material refilled into the via to couple the contact pads of the die to the wiring circuit of the substrate. | 2009-01-08 |
20090008778 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 2009-01-08 |
20090008779 | Composite Carbon Nanotube-Based Structures and Methods for Removing Heat from Solid-State Devices - One embodiment involves an article of manufacture that includes: a copper substrate plug with a front surface and a back surface; a catalyst on top of a single surface of the copper substrate plug; and a thermal interface material on top of the single surface of the copper substrate plug. The thermal interface material comprises: a layer of carbon nanotubes that contacts the catalyst, and a filler material located between the carbon nanotubes. The carbon nanotubes are oriented substantially perpendicular to the single surface of the copper substrate plug. The copper substrate plug is configured to be incorporated in a peripheral structure of a heat spreader or a heat sink. In another embodiment, the thermal interface material is on top of both the top and bottom surfaces of the copper substrate plug. | 2009-01-08 |
20090008780 | METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS - Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole. | 2009-01-08 |
20090008781 | SEMICONDUCTOR DEVICE - A semiconductor device structure includes a substrate, a first conductive layer over the substrate, a second conductive layer between the first conductive layer and the substrate and extending over the sidewalls of the first conductive layer, a dielectric layer between the second conductive layer and the substrate, a cap layer over the first conductive layer and the second conductive layer, and a liner layer on the sidewalls of the second conductive layer. | 2009-01-08 |
20090008782 | INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is disposed in the dielectric layer, having a recess portion. The low-k dielectric layer is disposed on the dielectric layer. The plug is disposed in the low-k dielectric layer and has a protruding bonding portion on the bottom of the plug. The bonding portion is extended into the dielectric layer and connected to the recess portion of the conductive structure. | 2009-01-08 |
20090008783 | SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY - A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film. | 2009-01-08 |
20090008784 | Power semiconductor substrates with metal contact layer and method of manufacture thereof - A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer. | 2009-01-08 |
20090008785 | ETCH PROCESS FOR IMPROVING YIELD OF DIELECTRIC CONTACTS ON NICKEL SILICIDES - The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device | 2009-01-08 |
20090008786 | Sputtering Target - The present invention provides a sputtering target comprising aluminum and one or more alloying elements including Ni, Co, Ti, V, Cr, Mn, Mo, Nb, Ta, W, and rare earth metals (REM). The addition of very small amounts of alloying element to pure aluminum and aluminum alloy target improves the uniformity of the deposited wiring films through affecting the target's recrystallization process. The range of alloying element content is 0.01 to 100 ppm and preferably in the range of 0.1 to 50 ppm and more preferably from 0.1 to 10 ppm weight which is sufficient to prevent dynamic recrystallization of pure aluminum and aluminum alloys, such as 30 ppm Si alloy. The addition of small amount of alloying elements increases the thermal stability and electromigration resistance of pure aluminum and aluminum alloys thin films while sustaining their low electrical resistivity and good etchability. This invention also provides a method of manufacturing microalloyed aluminum and aluminum alloy sputtering target. | 2009-01-08 |
20090008787 | HIGH EFFICIENCY SOLAR CELL FABRICATION - A method of forming a contact structure and a contact structure so formed is described. The structure contacts an underlying layer of a semiconductor junction, wherein the junction comprises the underlying layer of a semiconductor material and is separated from an overlying layer of semiconductor material by creating an undercut region to shade subsequent metal formation. Various steps are performed using inkjet printing techniques. | 2009-01-08 |
20090008788 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device. A first wiring level is formed on a top surface of a substrate. The first wiring level includes alternating layers of a first dielectric material and a second dielectric material. The layers of the first dielectric material includes at least two layers of the first dielectric material. The layers of the second dielectric material includes at least two layers of the second dielectric material. The first dielectric material includes an organic dielectric material. The second dielectric material includes an inorganic dielectric material. The substrate includes one or more dielectric materials. A first layer of the layers of the first dielectric material includes the organic dielectric material being in direct mechanical contact with the substrate. The layers of the first dielectric material and the layers of the second dielectric material are a same number of layers. | 2009-01-08 |
20090008789 | Method of manufacturing micro tunnel-junction circuit and micro tunnel-junction circuit - A method of manufacturing a micro tunnel-junction circuit capable of remarkably relieving the limitation of a circuit pattern to be manufactured and remarkably relieving the limitation of a metallic material to be used. In the method, a three-layer structure is formed by laminating a first metal, an insulator, and a second metal on a substrate in this order, a narrow wall part is formed by cutting the three-layer structure in the depth direction by using a converging ion beam, at least one laterally passed through-hole is formed in the wall part by using the converging ion beam, and at least one recessed portion positioned adjacent to the hole is formed by cutting the upper surface of the wall part in the depth direction. The hole is a through-hole starting at the position of the head of the second metal to the position of the head of the substrate and the recessed part is formed to be recessed from the upper surface of the wall part into the first metal. | 2009-01-08 |
20090008790 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole. | 2009-01-08 |
20090008791 | Circuit Structure with Low Dielectric Constant Regions - A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects. | 2009-01-08 |
20090008792 | Three-dimensional chip-stack package and active component on a substrate - The 3D chip-stack package comprises a component-embedded plate and a side IC. The PCB has a plurality of conductive contacts. The component-embedded plate comprises a dielectric layer; an active component embedded in the dielectric layer, one surface of each active component exposed outside the dielectric layer, the active components having a plurality of TSVs (Through Silicon Via), one ends of the TSVs exposed outside the exposed surface, the other ends of the TSVs corresponding to the conductive contacts of the PCB; and an electrical circuit on the dielectric layer and in electrical connection between the other ends of the TSVs of the active component and the corresponding conductive contacts of the PCB, respectively. The side IC has a plurality of pads. The pads are electrically connected with the exposed ends of the TSVs of the active component. | 2009-01-08 |
20090008793 | SEMICONDUCTOR DEVICE - A description is given of a device comprising a first semiconductor chip, a molding compound layer embedding the first semiconductor chip, a first electrically conductive layer applied to the molding compound layer, a through hole arranged in the molding compound layer, and a solder material filling the through hole. | 2009-01-08 |
20090008794 | Thickness Indicators for Wafer Thinning - A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set. | 2009-01-08 |
20090008795 | Stackable microelectronic device carriers, stacked device carriers and methods of making the same - A method of manufacturing a microelectronic package. The method includes the steps of attaching at least one microelectronic element to a tape having upper terminals projecting upwardly from an upper surface of a dielectric layer, so that top surfaces of the terminals are disposed coplanar with or above a top surface of the microelectronic element after the attaching step, electrically connecting the microelectronic element to at least some of the upper terminals; and further includes the step of applying an encapsulant to cover at least a portion of the upper surface of the dielectric layer, leaving the upper terminals surfaces of the terminals exposed. | 2009-01-08 |
20090008796 | COPPER ON ORGANIC SOLDERABILITY PRESERVATIVE (OSP) INTERCONNECT - Provided is a semiconductor package, and a method for constructing the same, including a first substrate, a first semiconductor chip attached to the first substrate, and a first copper wire. At least one of the first substrate and the first semiconductor chip has an Organic Solderability Preservative (OSP) material coated on at least a portion of one surface, and the first copper wire is wire bonded through the OSP material to the first substrate and the first semiconductor chip. | 2009-01-08 |
20090008797 | BOND PAD REROUTING ELEMENT, REROUTED SEMICONDUCTOR DEVICES INCLUDING THE REROUTING ELEMENT, AND ASSEMBLIES INCLUDING THE REROUTED SEMICONDUCTOR DEVICES - A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements. | 2009-01-08 |
20090008798 | SEMICONDUCTOR DEVICE SUITABLE FOR A STACKED STRUCTURE - A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate. | 2009-01-08 |
20090008799 | Dual mirror chips, wafer including the dual mirror chips, multi-chip packages, methods of fabricating the dual mirror chip, the wafer, and multichip packages, and a method for testing the dual mirror chips - Example embodiments provide a dual mirror chip, a wafer including the dual mirror chip, multi-chip packages and methods of fabricating the same. Example embodiments also provide a method of testing the dual mirror chip. According to example embodiments, a dual mirror chip may include a first type chip with a first output pad portion on a first side of the first type chip and a first input pad portion on a second side of the first type chip. The dual mirror chip may also include a second type chip to the side of the first type chip. The second type chip may include a second input pad portion on a first side of the second type chip and a second output pad portion on a second side of the second type chip. The dual mirror chip may also include at least one conductive line connecting the input pad portions. | 2009-01-08 |
20090008800 | FLIP CHIP MOUNTING BODY, FLIP CHIP MOUNTING METHOD AND FLIP CHIP MOUNTING APPARATUS - The flip chip mounted body of the present invention includes: a circuit board ( | 2009-01-08 |
20090008801 | Semiconductor device and method for fabricating the same - This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer. | 2009-01-08 |
20090008802 | FLEXIBLE CARRIER FOR HIGH VOLUME ELECTRONIC PACKAGE FABRICATION - An assembly for producing partially packaged semiconductor devices is provided. In one embodiment, the assembly includes a magnetic plate; a flexible substrate disposed adjacent the magnetic plate and having two surfaces; a nonstick coating disposed on one surface of the flexible substrate thereby exposing a nonstick surface; and a tape layer having two surfaces. The tape layer is adhesively attached to the nonstick surface to expose a surface of the tape layer. A frame is disposed on the exposed surface of the tape layer, and a plurality of integrated circuit (IC) die is positioned within the frame and supported by the tape layer. A panel is formed within the frame that at least partially surrounds the plurality of IC die and that contacts the tape layer. | 2009-01-08 |
20090008803 | LAYOUT OF DUMMY PATTERNS - A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads. | 2009-01-08 |
20090008804 | Power semiconductor package - A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode. | 2009-01-08 |
20090008805 | Air Disperser for a Spray Dryer and a Method for Designing an Air Disperser - The air disperser ( | 2009-01-08 |
20090008806 | REACTION VESSEL FOR AN OZONE CLEANING SYSTEM - A reaction vessel for entraining ozone gas in an aqueous ozone solution for an industrial cleaning system is described. The reaction vessel includes a conical-shaped surface having two or more edges. The conical-shaped surface defines a generally hollow interior, and the two or more edges are in contact with the generally hollow interior. An inlet port is in fluidic communication with a supply of an aqueous ozone solution to supply the aqueous ozone solution to the conical-shaped surface. Nozzles are in fluidic communication with a supply of water, and the nozzles direct the water under pressure at the conical-shaped surface, and the water mixes with the aqueous ozone solution from the inlet port. An outlet is in fluidic communication with the industrial cleaning system. The reaction vessel may receive the aqueous ozone solution from an injector. The reaction vessel reduces the bubbles of ozone gas in the aqueous ozone solution and entrains the bubbles of ozone gas in the aqueous ozone solution to increase the oxidation reduction potential of the aqueous ozone solution. | 2009-01-08 |
20090008807 | APPARATUS AND METHOD OF DISSOLVING A GAS INTO A LIQUID - The present invention relates to an apparatus and a process for dissolving gas in a liquid is provided. The process comprises: tangentially introducing a liquid into a cylindrical chamber having a cylindrical inner wall with sufficient volume and pressure to develop a vortex in the flowing liquid; introducing gas into the flowing liquid during at least a portion of its travel along vessel, the gas being introduced orthogonally to the stream through means located at the chamber inner wall for developing gas bubbles within the liquid. The apparatus comprises: a cylindrical chamber having a cylindrical inner wall, the chamber being oriented in any direction enclosed at both ends and with an entry port to introduce liquid to develop a spiral flow of liquid along the chamber inner wall toward the output end, a porous wall to permit the introduction of gas orthogonally into the stream to develop gas bubbles within the stream, and an exit port to discharge the mixture of gas bubbles and liquid. | 2009-01-08 |