01st week of 2016 patent applcation highlights part 55 |
Patent application number | Title | Published |
20160005411 | VERSATILE MUSIC DISTRIBUTION - Methods and devices are described whereby a representation of an original PCM signal may be reversibly degraded in a controlled manner and information losslessly embedded to produce a streamable PCM signal, which provides a controlled audio quality when played on standard players and conditional access to a lossless presentation of the original PCM signal. Using such techniques allows control over the level of degradation of the signal and also flexibility in the type information of information embedded. Some methods require a song key, which is employed in one or both of the degrading and embedding steps and for creating a token. These methods may further require a user key, which is used to encrypt the song key before creating the token. | 2016-01-07 |
20160005412 | GENERATION OF A SIGNATURE OF A MUSICAL AUDIO SIGNAL - The invention concerns a method for generating a signature of a musical audio signal of a given duration, the method comprising the following steps: —modelling ( | 2016-01-07 |
20160005413 | Audio Signal Enhancement Using Estimated Spatial Parameters - Received audio data may include a first set of frequency coefficients and a second set of frequency coefficients. Spatial parameters for at least part of the second set of frequency coefficients may be estimated, based at least in part on the first set of frequency coefficients. The estimated spatial parameters may be applied to the second set of frequency coefficients to generate a modified second set of frequency coefficients. The first set of frequency coefficients may correspond to a first frequency range (for example, an individual channel frequency range) and the second set of frequency coefficients may correspond to a second frequency range (for example, a coupled channel frequency range). Combined frequency coefficients of a composite coupling channel may be based on frequency coefficients of two or more channels. Cross-correlation coefficients, between frequency coefficients of a first channel and the combined frequency coefficients, may be computed. | 2016-01-07 |
20160005414 | SYSTEM AND METHOD FOR COMPRESSED DOMAIN ESTIMATION OF THE SIGNAL TO NOISE RATIO OF A CODED SPEECH SIGNAL - The present disclosure is directed towards a process for estimating the signal to noise ratio of a speech signal. The process may include receiving, at a computing device, a speech signal having a bitstream and a signal-to-noise ratio (“SNR”) associated therewith. The process may further include estimating the SNR directly from the bitstream or using a partial decoder that is configured to extract one or more parameters, the parameters including at least one of a fixed codebook gain, an adaptive codebook gain, a pitch lag, and a line spectral frequency (“LSF”) coefficient. | 2016-01-07 |
20160005415 | AUDIO SIGNAL PROCESSING APPARATUS AND AUDIO SIGNAL PROCESSING METHOD THEREOF - An audio signal processing apparatus and an audio signal processing method thereof are provided. The audio signal processing apparatus is configured to receive an audio signal and divide the audio signal into a plurality of frames. The audio signal processing apparatus is also configured to apply Fourier Transform on each of the frames to obtain a plurality of acoustic spectra. The audio signal processing apparatus is also configured to apply Fourier Transform again on each of component combinations corresponding to respective acoustic frequencies in these acoustic spectra to obtain a two-dimensional joint frequency spectrum. The two-dimensional joint frequency spectrum has an acoustic frequency dimension and a modulation frequency dimension. The audio signal processing apparatus is also configured to calculate at least one feature of the audio signal according to the two-dimensional joint frequency spectrum. | 2016-01-07 |
20160005416 | Continuous Pitch-Corrected Vocal Capture Device Cooperative with Content Server for Backing Track Mix - Techniques have been developed to facilitate (1) the capture and pitch correction of vocal performances on handheld or other portable computing devices and (2) the mixing of such pitch-corrected vocal performances with backing tracks for audible rendering on targets that include such portable computing devices and as well as desktops, workstations, gaming stations, even telephony targets. Implementations of the described techniques employ signal processing techniques and allocations of system functionality that are suitable given the generally limited capabilities of such handheld or portable computing devices and that facilitate efficient encoding and communication of the pitch-corrected vocal performances (or precursors or derivatives thereof) via wireless and/or wired bandwidth-limited networks for rendering on portable computing devices or other targets. | 2016-01-07 |
20160005417 | A NOISE REDUCTION METHOD AND SYSTEM - Noise reduction methods and systems for reducing unwanted sounds in signals received from an arrangement of microphones are disclosed, the method including the steps of: sensing sound sources distributed around a specified target direction by way of an arrangement of microphones to produce left and right microphone output signals; determining the magnitude or power of the left and right microphone signals; attenuating the signals based on the difference of the magnitudes or powers or values derived from the magnitudes or powers of the left and right microphone signals. | 2016-01-07 |
20160005418 | SIGNAL PROCESSOR AND METHOD THEREFOR - The signal processor suppresses noise components contained in input sound signals by iterative spectral subtraction. The processor derives coherence from first and second directional signals having directivity characteristics on the basis of a pair of input sound signals, and controls the times of iteration of spectral subtraction on the basis of the coherence, thereby suppressing the noise components contained in the input sound signals. | 2016-01-07 |
20160005419 | NONLINEAR ACOUSTIC ECHO SIGNAL SUPPRESSION SYSTEM AND METHOD USING VOLTERRA FILTER - A nonlinear acoustic echo signal suppression system and method using a Volterra filter is disclosed. The nonlinear acoustic echo signal suppression system includes an acoustic echo signal estimator configured to estimate a nonlinear acoustic echo signal by using a Volterra filter in a frequency filter, and a near-end talker speech signal generator configured to generate a near-end talker speech signal, in which the nonlinear acoustic echo signal is suppressed, by using a gain function based on a statistical model. | 2016-01-07 |
20160005420 | VOICE EMPHASIS DEVICE - An input signal analyzer determines a boundary frequency within the limit of a range which does not exceed a first frequency from the mode of an input signal. A spectrum compressor compresses a power spectrum of frequencies in a band higher than the first frequency in a frequency direction. A gain corrector performs a gain correction on the compressed power spectrum. A spectrum synthesizer reflects the power spectrum outputted from the gain corrector in a band determined by both the first frequency and the boundary frequency. A frequency-to-time converter converts both a synthesized power spectrum provided by the spectrum synthesizer and a phase spectrum of the input signal into ones in the time domain, and outputs these spectra. | 2016-01-07 |
20160005421 | LANGUAGE ANALYSIS BASED ON WORD-SELECTION, AND LANGUAGE ANALYSIS APPARATUS - The invention relates to a method for wording-based speech analysis. In order to provide a method that allows automated analysis of largely arbitrary features of a person from whom a voice file that needs to be analysed comes, the invention detaches itself from the known concept of evaluating static keyword lists for the personality type. The method according to the invention comprises the preparation of a computer system by formation of a reference sample that allows the comparison that is necessary for feature recognition with other persons. The preparation of the computer system involves the recording and storage of a further voice file in addition to the voice files of the reference sample, the analysis of the additionally recorded voice file and the output of the recognized features using at least one output unit connected to the computer system. Furthermore, the invention relates to a speech analysis device for carrying out the method. | 2016-01-07 |
20160005422 | USER ENVIRONMENT AWARE ACOUSTIC NOISE REDUCTION - Examples of the disclosure describe user environment aware single channel acoustic noise reduction. A noisy signal received by a computing device is transformed and feature vectors of the received noisy signal are determined. The computing device accesses classification data corresponding to a plurality of user environments. The classification data for each user environment has associated therewith a noise model. A comparison is performed between the determined feature vectors and the accessed classification data to identify a current user environment. A noise level, a speech level, and a speech presence probability from the transformed noisy signal are estimated and the noise signal is reduced based on the estimates. The resulting signal is outputted as an enhanced signal with a reduced or eliminated noise signal. | 2016-01-07 |
20160005423 | DATA MANAGEMENT FOR A DATA STORAGE DEVICE WITH ZONE RELOCATION - Managing data stored on media of a Data Storage Device (DSD) using zone relocation. At least a portion of the media is logically divided into a plurality of zones and zones are identified with access counts greater than or equal to a threshold. The access count for each of the identified zones indicates a number of times data in the zone has been read or written. Data is relocated from at least one zone of the identified zones to at least one destination zone on the media to reduce a data access time between the identified zones. | 2016-01-07 |
20160005424 | MULTI-STACK READER WITH SPLIT MIDDLE SHIELD - A reader includes top and bottom reader stacks disposed between a top and bottom shield. The top and bottom reader stacks are offset relative to each other in a downtrack direction. Top side shields surround the top reader stack in a crosstrack direction, and bottom side shields surround the bottom reader stack in the crosstrack direction. A split middle shield is between the top and bottom reader stacks and the top and bottom side shields. The split middle shield includes top and bottom portions separated by an isolation layer, the top and bottom portions respectively coupled to the top and bottom reader stacks. | 2016-01-07 |
20160005425 | LEADS COUPLED TO TOP AND BOTTOM READER STACKS OF A READER - A reader includes top and bottom reader stacks that are offset relative to each other in a downtrack direction and disposed between a top shield and a bottom shield. Top side shields surround the top reader stack in a crosstrack direction, and bottom side shields surround the bottom reader stack in the crosstrack direction. A middle shield is between the top and bottom reader stacks and the top and bottom side shields. The middle shield includes a common electrical conductive path coupled to the top and bottom reader stacks. A middle lead is coupled to an edge of the middle shield. | 2016-01-07 |
20160005426 | METHOD AND APPARATUS FOR CONTROLLING CAMBER ON AIR BEARING SURFACE OF A SLIDER - An apparatus and method of a parting a slider from a slider bar is disclosed. A slider bar comprising a plurality of sliders and having an air bearing surface (ABS) side and a back side opposite to the ABS side is received. At least one slider is parted from the slider bar with a cutter, wherein the cutter enters the slider bar at least in part on the backside and exits the slider bar at least in part on the ABS side. | 2016-01-07 |
20160005427 | MICROMETER SCALE COMPONENTS - Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile. | 2016-01-07 |
20160005428 | GRADED SIDE SHIELD GAP READER - Embodiments of the present invention generally include magnetoresistive heads, such as read heads, having a sensor structure and side shields disposed adjacent to the sensor structure. The distance between the side shields and the sensor structure increase in a direction from an ABS in the off-track direction. The magnetoresistive heads may include tapered surfaces on the side shields or sensor structure, or may include stepped surfaces on the side shields or sensor structure. | 2016-01-07 |
20160005429 | QUASI-STATICALLY ORIENTED, BI-DIRECTIONAL TAPE RECORDING HEAD - A computer program product for orienting a head, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith that are readable/executable by a controller to cause the controller to determine a desired pitch for transducers of a magnetic head for reading and/or writing to a magnetic tape, and are readable/executable by the controller to cause the controller to cause a mechanism to orient the magnetic head towards first and second positions to achieve the desired pitch when the tape travels in first and second directions, respectively. Outer data transducers of the third array are about aligned with outer data transducers of the second array when the magnetic head is positioned towards the first position, and the outer data transducers of the third array are about aligned with outer data transducers of the first array when the magnetic head is positioned towards the second position. | 2016-01-07 |
20160005430 | MAGNETIC RECORDING MEDIUM - The magnetic recording medium of the present invention comprises: a non-magnetic substrate; a non-magnetic layer formed on one of principal surfaces of the non-magnetic substrate; and a magnetic layer formed on a principal surface of the non-magnetic layer opposite to the non-magnetic substrate. Mr and t satisfy 0.0020 μT·m≦Mr·t≦0.0150 μT·m, where Mr is the residual magnetic flux density of the magnetic layer, and t is the average thickness of the magnetic layer, L1 satisfies 2 nm≦L1≦6 nm, where L1 is the average thickness of a first mixed layer that is formed on the surface of the magnetic layer opposite to the non-magnetic layer, and L2 satisfies 0.1≦L2/t≦0.45, where L2 is the average thickness of a second mixed layer that is formed on the surface of the magnetic layer facing the non-magnetic layer. | 2016-01-07 |
20160005431 | GLASS SUBSTRATE FOR MAGNETIC DISK AND MAGNETIC DISK - A magnetic-disk glass substrate has a circular center hole, a pair of main surfaces and an edge surface. The edge surface has a side wall surface and chamfered surfaces interposed between the side wall surface and the main surfaces, and a roundness of an edge surface on an outer circumferential side is 1.5 μm or less. Also, a midpoint A between centers of two least square circle respectively derived from outlines in a circumferential direction respectively obtained at two positions spaced apart by 200 μm in a substrate thickness direction on the side wall surface on the outer circumferential side, and centers B and C respectively derived from a respective one of two chamfered surfaces on the outer circumferential side in the substrate thickness direction, are located such that a sum of respective distances between A and B, and A and C, is 1 μm or less. | 2016-01-07 |
20160005432 | HIGH DENSITY HYBRID STORAGE SYSTEM - A computer-implemented method includes receiving a request for data; determining whether the data is stored in a linear storage media tier and/or in a second storage tier having higher performance than the linear storage media tier. The linear storage media tier includes: reels having linear media thereon, a rest area for storing the reels when not in use, linear media drive(s) configured for reading and/or writing the linear media, and mobile robot(s) for transporting the linear storage media between the rest area and the linear media drive(s). The method also includes instructing the mobile robot to transport one of the reels having the data thereon to one of the linear media drives in the linear storage media tier when the data is stored in the linear storage media tier; receiving the data from the one of the linear media drives; and sending the data. | 2016-01-07 |
20160005433 | APPLICATION FOR ENHANCING A MULTIMEDIA USAGE ON AN ELECTRONIC DEVICE - The present invention relates to implementing an application that enhances the multimedia usage by allowing the consumer to record a video seamlessly without interrupting the streaming of an audio file that is played either in the foreground or in the background on an electronic device. Further, the application allows the user to synchronize the recorded video file with an audio file and merge a plurality video files that are recorded. Furthermore, the application can be used to monitor the speed of the video file that is streamed on the electronic device. | 2016-01-07 |
20160005434 | WRITING DATA TO A TAPE - A method of writing data to a tape on which during a write operation successive data unit groups that comprise a plurality N of data units are written across the tape as N track portions to form N data tracks that extend in a lengthways direction of the tape. The method includes identifying data units written during the write operation that need to be rewritten and writing a rewrite data unit group that contains data units identified as needing to be rewritten. The rewrite data unit group has N track portions written across the tape to form a part of the data tracks. The N track portions contain N-n data units identified as needing to be rewritten and data unit identifier information comprising respective data unit identifiers for the N-n data units contained in at least one list of data unit identifiers. N and n are positive integers. | 2016-01-07 |
20160005435 | AUTOMATIC GENERATION OF VIDEO AND DIRECTIONAL AUDIO FROM SPHERICAL CONTENT - A spherical content capture system captures spherical video and audio content. In one embodiment, captured metadata or video/audio processing is used to identify content relevant to a particular user based on time and location information. The platform can then generate an output video from one or more shared spherical content files relevant to the user. The output video may include a non-spherical reduced field of view such as those commonly associated with conventional camera systems. Particularly, relevant sub-frames having a reduced field of view may be extracted from each frame of spherical video to generate an output video that tracks a particular individual or object of interest. For each sub-frame, a corresponding portion of an audio track is generated that includes a directional audio signal having a directionality based on the selected sub-frame. | 2016-01-07 |
20160005436 | AUTOMATIC GENERATION OF VIDEO FROM STRUCTURED CONTENT - Apparatus for generation of playable media from structured data, comprises a structured data reading unit for reading in of content of a first structure, a transformation unit for transforming said content into a second structure, said transformation comprising incorporating media play instructions, and a rendering unit for rendering content from the second structure using said media play instructions to generate playable media from the content. | 2016-01-07 |
20160005437 | METHOD AND SYSTEM FOR MATCHING AUDIO AND VIDEO - The present application relates to the field of media processing and more particularly to audio and video processing. The present application addresses the problem that videos collected by fans at concerts and other events generally have poor sound quality and provides a solution that matches a high quality sound to the video. | 2016-01-07 |
20160005438 | ASSOCIATING PLAYBACK DEVICES WITH PLAYBACK QUEUES - In an example implementation, a system groups a first playback device and a second playback device into first player group. The system associates the first player group with a first playback queue that includes items for playback by the first player group. The first and second playback devices are configured to play items from the first playback queue while in the first player group. The system associates a third playback device with a second playback queue that includes items for playback by the second playback device. Thereafter, the system groups the first, second and third playback devices to form a second player group such that each of the first, second, and third playback devices are configured to play items from the second playback queue. The system removes the first playback device from the second player group and automatically associates the first playback device with the first playback queue. | 2016-01-07 |
20160005439 | SYSTEMS AND METHODS FOR NETWORKED MEDIA SYNCHRONIZATION - This disclosure illustrates systems and methods for generating synchronized audio output signals. The synchronization may be performed based on an audio synchronization message received by an audio synchronization computing platform over a communication network. The audio synchronization computing platform may generate a synchronized audio output signal from an audio signal. The audio synchronization computing platform may provide the synchronized audio output signal to one or more audio playback devices over the same communication network. The communication network may be a single ethernet network. | 2016-01-07 |
20160005440 | PROVISION OF VIDEO DATA - Individual time stamp data inputs generated by different viewers of a broadcast or other video output are used to identify parts of the video data to be used to generate a sequence of video clips or “highlights”. The individual time stamps for each event are aggregated to generate a single marker flag ( | 2016-01-07 |
20160005441 | CHARGE PUMP SYSTEM AND ASSOCIATED CONTROL METHOD FOR MEMORY CELL ARRAY - A charge pump system includes a logic circuit, a signal processing circuit, a charge pump circuit, a switching circuit, a first controllable discharge path, and a second controllable discharge path. The logic circuit receives a program enabling signal and generates a first control signal. The signal processing circuit receives a pump enabling signal, and generates a second control signal and a third control signal. The charge pump circuit receives the third control signal and generates an output signal. The switching circuit has a control terminal receiving the third control signal, a first terminal connected with the output terminal of the charge pump circuit, and a second terminal connected with a reservoir capacitor. The first controllable discharge path receives the first control signal, and the second controllable discharge path receives the second control signal. | 2016-01-07 |
20160005442 | Memory Programming Methods and Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described. | 2016-01-07 |
20160005443 | MEMORY AND MEMORY SYSTEM - A memory may include first to N | 2016-01-07 |
20160005444 | DATA STORAGE DEVICE - A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation. | 2016-01-07 |
20160005445 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section. | 2016-01-07 |
20160005446 | MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS - An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal. | 2016-01-07 |
20160005447 | INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES - Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space. | 2016-01-07 |
20160005448 | Memory Circuitry Using Write Assist Voltage Boost - Within a memory | 2016-01-07 |
20160005449 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS WITH RARE EARTH-TRANSITION METAL LAYERS - A magnetic junction usable in magnetic devices is described. The magnetic junction includes a reference layer, a free layer, a nonmagnetic spacer layer between the reference and free layers, and a rare earth-transition metal (RE-TM) layer in the reference and/or free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. If the RE-TM layer is in the free layer then the RE-TM layer is between hard and soft magnetic layers in the free layer. In this aspect, the RE-TM layer has a standby magnetic moment greater than a write magnetic moment. If the RE-TM layer is in the reference layer, then the magnetic junction includes a second RE-TM layer. In this aspect, a first saturation magnetization quantity of the RE-TM layer matches a second saturation magnetization quantity of the second RE-TM layer over an operating temperature range. | 2016-01-07 |
20160005450 | DATA HOLDING CIRCUIT AND DATA RECOVERY METHOD - A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other. | 2016-01-07 |
20160005451 | FRAM CELL WITH CROSS POINT ACCESS - A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines. | 2016-01-07 |
20160005452 | SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING HAVING DIFFERENT REFRESH OPERATION PERIODS FOR DIFFERENT SETS OF MEMORY CELLS - Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle. | 2016-01-07 |
20160005453 | SEMICONDUCTOR DEVICE - A semiconductor device may include pad blocks configured for receiving and outputting data. The semiconductor device may also include input/output driving blocks configured to transfer data received from global input/output lines to the pad blocks in response to a read operation, and transfer data from the pad blocks to the global input/output lines in response to a write operation. The input/output driving blocks are disposed in a peripheral region and control a width of the data. | 2016-01-07 |
20160005454 | METHODS FOR MANUFACTURING AND OPERATING A MEMORY DEVICE AND A METHOD FOR OPERATING A SYSTEM HAVING THE SAME - A method for manufacturing a memory device includes detecting, with a tester, whether memory cells included in a memory device are defective, and programming, with the tester, start addresses of defect-free memory regions for addressing modes of the memory device based on a result of the detection. | 2016-01-07 |
20160005455 | MEMORY CONTROLLER AND MEMORY DEVICE COMMAND PROTOCOL - Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers. | 2016-01-07 |
20160005456 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled. | 2016-01-07 |
20160005457 | DIRECTED PER BANK REFRESH COMMAND - A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition. | 2016-01-07 |
20160005458 | Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features - A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. | 2016-01-07 |
20160005459 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation. | 2016-01-07 |
20160005460 | SOFT INFORMATION MODULE - A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value. | 2016-01-07 |
20160005461 | SENSING A NON-VOLATILE MEMORY DEVICE UTILIZING SELECTOR DEVICE HOLDING CHARACTERISTICS - Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory. | 2016-01-07 |
20160005462 | ELECTRONIC DEVICE - An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other. | 2016-01-07 |
20160005463 | RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY, AND OPERATING METHOD OF THE RESISTIVE MEMORY DEVICE - An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal. | 2016-01-07 |
20160005464 | COUNTER FOR WRITE OPERATIONS AT A DATA STORAGE DEVICE - A data storage device includes a resistive random access memory (ReRAM). A method includes storing data in the ReRAM by performing a first number of write operations to a storage region of the ReRAM. The storage region is tracked by a counter. The method further includes incrementing a value of the counter a second number of times responsive to storing the data in storage region. The second number is less than the first number. | 2016-01-07 |
20160005465 | CONTENT ADDRESSABLE MEMORY - The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers. | 2016-01-07 |
20160005466 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a semiconductor substrate and a plurality of first dummy memory cells connected between the first main memory cells and a common source line. The second memory string includes a plurality of second main memory cells formed on the pipe transistor and a plurality of second dummy memory cells connected between the second main memory cells and a bit line. The number of the second dummy memory cells is greater than the number of the first dummy memory cells. | 2016-01-07 |
20160005467 | COMMAND SIGNAL MANAGEMENT IN INTEGRATED CIRCUIT DEVICES - Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal. | 2016-01-07 |
20160005468 | Reduced Size Semiconductor Device And Method For Manufacture Thereof - A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided. | 2016-01-07 |
20160005469 | NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE - A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted. | 2016-01-07 |
20160005470 | SEMICONDUCTOR MEMORY DEVICE - A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks. | 2016-01-07 |
20160005471 | AUTOMATIC WORD LINE LEAKAGE MEASUREMENT CIRCUITRY - The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device. | 2016-01-07 |
20160005472 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory block including memory cells connected to a word line, and an operation circuit suitable for consecutively applying a main program pulse and a sub program pulse to the word line to perform a program operation of the memory cells, and suitable for performing a program verification operation of the memory cells, wherein the sub program pulse has a lower voltage level than the main program pulse. | 2016-01-07 |
20160005473 | PROGRAMMING OF MEMORY DEVICES - Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage. | 2016-01-07 |
20160005474 | MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF - An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line. | 2016-01-07 |
20160005475 | MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS - A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described. | 2016-01-07 |
20160005476 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional U-shaped structure. The peripheral circuit is configured to perform an erase operation on the pipe cell. A method of operating the semiconductor memory device includes selecting the memory string and performing the erase operation on the pipe cell. | 2016-01-07 |
20160005477 | SELECTING MEMORY CELLS - A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals. | 2016-01-07 |
20160005478 | MEMORY SYSTEM AND METHOD OF DRIVING MEMORY SYSTEM USING ZONE VOLTAGES - A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation. | 2016-01-07 |
20160005479 | READING METHOD FOR A CELL STRING - A reading method for a cell string includes a pre-charging step and a reading step to read a selected word line cell WL[k]. The pre-charging step comprises applying a positive pass voltage (V | 2016-01-07 |
20160005480 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level. | 2016-01-07 |
20160005481 | MEMORY PAGE BUFFER - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 2016-01-07 |
20160005482 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 2016-01-07 |
20160005483 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 2016-01-07 |
20160005484 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 2016-01-07 |
20160005485 | Semiconductor Device Having Features to Prevent Reverse Engineering - A ROM circuit includes a first N channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a P channel circuit is connected to the first N channel transistor; a pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn ON the pass transistor when the word line is asserted; and the P channel circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first N channel transistor when pass transistor is turned ON. | 2016-01-07 |
20160005486 | SENSE AMPLIFIER FOR A MEMORY CELL WITH A FAST SENSING SPEED - A sense amplifier comprises a cell current generator, a reference current generator, a first and a second charge/discharge elements, a first and a second voltage trigger circuits, and a data holder. The cell current generator is used to output a cell current of a memory cell. The reference current generator is used to output a duplicated reference current. The first and the second charge/discharge elements are used to convert the cell current and the duplicated reference current to voltage signals respectively. The first voltage trigger circuit is used to output a data signal according to a voltage signal outputted from the first charge/discharge element. The second voltage trigger circuit is used to output a hold control signal according to a voltage signal outputted from the second charge/discharge element. The data holder is used to hold a voltage level of the data signal according to the hold control signal. | 2016-01-07 |
20160005487 | VOLTAGE SWITCH CIRCUIT - A voltage switch circuit includes plural transistors, a first control circuit and a second control circuit. The first transistor has a source terminal connected to a first voltage source and a gate terminal connected to a node b | 2016-01-07 |
20160005488 | EXTERNAL STORAGE DEVICE AND METHOD OF SETTING REFERENCE FREQUENCY FOR THE SAME - An external storage device and method of setting a reference frequency for the same are provided. The external storage device includes: a device manager configured to set a reference frequency using information about the reference frequency for a high-speed mode received in a low-speed mode after the external storage device starts initialization, and control the external storage device to operate at the reference frequency in the high-speed mode, wherein the external storage device is a removable device which is attachable to and detachable from a host and is configured to operate according to a reference clock signal with the reference frequency in the high-speed mode. | 2016-01-07 |
20160005489 | Controlling a Flash Device Having Time-Multiplexed, On-Die-Terminated Signaling Interface - An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line. | 2016-01-07 |
20160005490 | NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME - A non-volatile memory device includes a memory cell array having a plurality of memory cells programmable into one of multiple logic states, the plurality of memory cells disposed at intersections of a plurality of wordlines and a plurality of bitlines, and a plurality of page buffers respectively connected to the plurality of bitlines and performing verifying read operations on the plurality of memory cells, The verifying read operations are performed on a first memory cell having a target state and a second memory cell having a lower state than the target state. | 2016-01-07 |
20160005491 | Look Ahead Read Method For Non-Volatile Memory - A read operation for selected memory cell on a selected word line compensates for program disturb which is a nonlinear function of the data state of an adjacent memory cell on an adjacent word line. When a command to perform a read operation for the selected memory cell is received, a read operation is first performed on the adjacent memory cell to determine its data state, or to classify the adjacent memory cell into a threshold voltage range which includes one or more data states, or a portion of a data state. The selected memory cell is then read using a baseline control gate voltage which does not provide compensation, and one or more elevated control gate voltages which provide compensation, to distinguish between two adjacent data states. An optimal sensing result is selected based on the data state or threshold voltage range of the adjacent memory cell. | 2016-01-07 |
20160005492 | OTP READ SENSOR ARCHITECTURE WITH IMPROVED RELIABILITY - Circuits and methods for reading an OTP memory cell with improved reliability. To read a first OTP memory cell, a first current amount generated by a second, programmed, OTP memory cell is received. A second current amount generated by a third, unprogrammed, OTP memory cell is received. Current generated by the first OTP memory cell is sunk. The amount of current sunk from the first OTP memory cell is equal to a sum of a third current amount that is proportional to the first current amount plus a fourth current amount that is proportional to the second current amount. While sinking said current from the first OTP memory cell a voltage at a current output of the first OTP memory cell is compared to a threshold voltage. | 2016-01-07 |
20160005493 | METHODS AND APPARATUS FOR TESTING AND REPAIRING DIGITAL MEMORY CIRCUITS - An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority. | 2016-01-07 |
20160005494 | E-FUSE TEST DEVICE AND SEMICONDUCTOR DEVICE INCLUDINGTHE SAME - An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two. | 2016-01-07 |
20160005495 | REDUCING DISTURBANCES IN MEMORY CELLS - Methods for reducing program disturb in non-volatile memories are described. In some embodiments, a non-volatile storage system may acquire a first set of intermediate data to be written to a plurality of memory cells, determine a current set of intermediate data written in the plurality of memory cells, determine whether to invert the first set of intermediate data based on the current set of intermediate data, invert the first set of intermediate data, and write the inverted first set of intermediate data to the plurality of memory cells. The memory cells that are already at the correct state may be skipped over and not programmed, thereby improving programming speed and reducing the cumulative voltage stress applied to unselected memory cells. | 2016-01-07 |
20160005496 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a memory cell array including a plurality of word lines; a repair fuse section programmed with one or more repair-target addresses and fuse enable information; an address generation section suitable for generating test addresses during a test operation, corresponding to the word lines based on the repair-target addresses and the fuse enable information; and a word line control section suitable for selectively activating the word lines based on the test addresses. | 2016-01-07 |
20160005497 | A PRACTICAL MOLTEN SALT FISSION REACTOR - A nuclear fission reactor comprising a core, a pool of coolant liquid, and a heat exchanger. The core comprises an array of hollow tubes which contain molten salts of fissile isotopes. The tube array is at least partly immersed in the pool of coolant liquid. The tube array comprises a critical region, where the density of the fissile isotopes during operation of the reactor is sufficient to cause a self-sustaining fission reaction. Heat transfer from the molten salts of fissile isotopes to the tubes is achieved by any one or more of natural convection of the molten salts, mechanical stirring of the molten salts, and oscillating fuel salt flow within the tubes. The molten salts of fissile isotopes are contained entirely within the tubes during operation of the reactor. | 2016-01-07 |
20160005498 | Electricity Generation Facility Comprising a Device for Producing Steam of Reduced Height, Application to PWR and BWR Reactors - The invention relates to an electrical energy generation facility comprising:—a steam generation device ( | 2016-01-07 |
20160005499 | METHODS OF COATING A NUCLEAR REACTOR COMPONENT WITH A COLLOIDAL SOLUTION - A method of coating a nuclear reactor component includes introducing the nuclear reactor component into a colloidal solution at a first rate to obtain an immersed component. The colloidal solution is a non-crosslinked mixture including a dispersed phase within a dispersion medium. The dispersed phase may include n-type metal oxide particles. The method additionally includes removing the immersed component from the colloidal solution at a second rate to obtain a wet component. The method also includes drying the wet component to obtain a dried component. The method further includes baking the dried component to obtain a coated component. Accordingly, the nuclear reactor component is provided with a protective layer that reduces or prevents the occurrence of corrosion. | 2016-01-07 |
20160005500 | Rack For Storage of Multiple Spent Fuel Assemblies - A skeleton rack for storing nuclear fuel rods, the rack having a rectangular array of vertically extending cells, the cells being formed by a plurality of elongated, relatively narrow rigid metal shafts, each disposed at a corner of a cell, rigid metal bridge members fixed to adjacent shafts proximal to upper ends of the shafts, apertured rigid metal end walls proximal to lower ends of the shafts and fixed to four shafts at corners of a respective cell. | 2016-01-07 |
20160005501 | VENTILATED TRANSFER CASK WITH LIFTING FEATURE - An apparatus for transferring spent nuclear fuel in the form of a cask having a cylindrical inner shell forming a cavity configured to receive a canister containing spent nuclear fuel, an intermediate shell disposed concentrically around and spaced apart from the inner shell and an outer shell disposed concentrically around and spaced apart from the intermediate shell. A bottom flange is affixed to bottoms of each of the shells, and a bottom lid is removably affixed to the bottom flange. A top flange is affixed to tops of each of the shells, and a top lid is seated on the top flange. An annulus for air flow may be formed between the inner shell and the canister; the bottom lid may include an impact zone including impact absorbing structure; and the top flange may have integrally formed trunnions. | 2016-01-07 |
20160005502 | DEVICE FOR PROTECTING AGAINST IONISING RADIATION AND CONTAINMENT ENCLOSURE PROVIDED WITH SUCH A DEVICE - A protection device for providing protection against ionizing radiation passing through an orifice defined by a wall bushing structure. The device includes a structure for attenuating ionizing radiation passing through the orifice, which structure can cover, or close off, the orifice, and includes a fastener configured to ensure that the structure for attenuating ionizing radiation can be fastened releasably to the wall bushing structure. The structure for attenuating ionizing radiation includes a sleeve that is open at both ends, that is deformable under its own weight, and that is configured to be fastened to the wall bushing structure by the fastener at a first open end of the sleeve. | 2016-01-07 |
20160005503 | PLASMONIC ASSISTED SYSTEMS AND METHODS FOR INTERIOR ENERGY-ACTIVATION FROM AN EXTERIOR SOURCE - A method and a system for producing a change in a medium disposed in an artificial container. The method places in a vicinity of the medium at least one of a plasmonics agent and an energy modulation agent. The method applies an initiation energy through the artificial container to the medium. The initiation energy interacts with the plasmonics agent or the energy modulation agent to directly or indirectly produce the change in the medium. The system includes an initiation energy source configured to apply an initiation energy to the medium to activate the plasmonics agent or the energy modulation agent. | 2016-01-07 |
20160005504 | ELECTROCONDUCTIVE MICROPARTICLES, ANISOTROPIC ELECTROCONDUCTIVE MATERIAL, AND ELECTROCONDUCTIVE CONNECTION STRUCTURE - The present invention aims to provide electroconductive microparticles which are less likely to cause disconnection due to breakage of connection interfaces between electrodes and the electroconductive microparticles even under application of an impact by dropping or the like and are less likely to be fatigued even after repetitive heating and cooling, and an anisotropic electroconductive material and an electroconductive connection structure each produced using the electroconductive microparticles. The present invention relates to electroconductive microparticles each including at least an electroconductive metal layer, a barrier layer, a copper layer, and a solder layer containing tin that are laminated in said order on a surface of a core particle made of a resin or metal, the copper layer and the solder layer being in contact with each other directly, the copper layer directly in contact with the solder layer containing copper at a ratio of 0.5 to 5% by weight relative to tin contained in the solder layer. | 2016-01-07 |
20160005505 | FLAME RETARDANT COMPOSITION COMPRISING A THERMOPLASTIC POLYETHERESTER ELASTOMER - A polymer composition comprising:—a thermoplastic copolyetherester elastomer comprising 40-65 wt. % of soft segments derived from poly(tetrahydrofuran)diol (pTHF), having a number average molecular weight (Mn) of between 1000 and 2500 kg/kmol.—at least 15 wt % of a metal hydrate,—at least 12.5 wt. % of an oligomeric phosphate ester. | 2016-01-07 |
20160005506 | COMPOSITION, AND METHOD FOR PRODUCING FOAM MOLDED MATERIAL AND ELECTRIC WIRE - The present invention aims to provide a composition which can provide molded foams and foamed electric wires having a small average cell size and a high expansion ratio. The composition of the present invention includes a fluororesin; and boron nitride having an average particle size of 10.5 μm or greater, or boron nitride having a particle size distribution represented by (D84−D16)/D50 of 1.2 or lower. | 2016-01-07 |
20160005507 | ELONGATED, DUCTILE, RIDGED, COIL-RETAINING MEMBER - An insulated cable that includes conductors has a first interface at one end that is configured to detachably attach to a first electronic device and a second interface at the other end that is configured to detachably attach to a second electronic device so that the first electronic device and the second electronic device are interconnected. An elongated, ductile, ridged, coil-retaining member is attached at the other end of the insulated cable, and it is configured to hold the electric signal cable in a wound state when the elongated, ductile, ridged, coil-retaining member is wrapped on itself such that ridges on a surface of the elongated, ductile, ridged, coil-retaining member are received by valleys on the surface of the elongated, ductile, ridged, coil-retaining member in order to limit a translatory motion of the elongated, ductile, ridged, coil-retaining member when it is subjected to a tensile stress. | 2016-01-07 |
20160005508 | CABLE FOR CONVEYING AN ELECTRICAL SUBMERSIBLE PUMP INTO AND OUT OF A WELL BORE - A cable for conveying an electrical submersible pump into and out of a well bore includes at least one strength member made of a composite material comprising a fiber reinforced plastic. A plurality of electrical conductors forming circumferential segments is disposed externally to the at least one strength member. A protective jacket encapsulates the at least one strength member and the plurality of electrical conductors. | 2016-01-07 |
20160005509 | MULTI-LAYERED STRUCTURE AND METHOD - One aspect relates to a method for producing a layered structure, including providing a substrate, forming a first layer onto at least part of the substrate, the first layer being a first polymer, and forming a second layer onto at least part of the first layer, the second layer being a second polymer. The substrate and the second layer are electrically conductive and the first layer is insulating or the substrate and the second layer are insulating and the first layer is electrically conductive. Forming each of the first and second layers includes forming such that each layer is no more than one tenth of the thickness of the substrate. | 2016-01-07 |
20160005510 | FLEXIBLE FLAT CABLE FOR LOW VOLTAGE DIFFERENTIAL SIGNALING - A flexible flat cable for low voltage differential signaling, includes upper and lower insulating films, and conductive lines interposed between the upper and lower insulating films and arranged at a predetermined pitch in parallel to each other. Each conductive line includes a central part having a circular sectional surface and a rolled part having flat upper and lower surfaces, which are formed by performing a rolling process with respect to an end portion of the central portion, and subject to a heat treatment process, end portions of rolled parts are arranged at a predetermined pitch and exposed to an outside to form a terminal part, a predetermined number of conductive lines interposed between the upper and lower insulating films are grouped in a strip, and a cutting line is formed while passing through the upper insulating film, a space between strips, and the lower insulating film. | 2016-01-07 |