| 01st week of 2011 patent applcation highlights part 48 |
| Patent application number | Title | Published |
|---|
| 20110004712 | STORAGE SYSTEM EFFECTIVELY USING FREE PORTS - A first free port present in a controller or a switch device is physically connected to a second free port present in a switch device (switch device in another storage device unit) other than the controller or switch device comprising the first free port. The possibility of logical connection via a physical path connecting the first free port and second free port is controlled. | 2011-01-06 |
| 20110004713 | INFORMATION TRANSMISSION SYSTEM, INFORMATION TRANSMISSION DEVICE, INFORMATION TRANSMISSION METHOD AND A COMPUTER READABLE MEDIUM STORING A PROGRAM FOR INFORMATION TRANSMISSION - The present invention provides an information transmission system including: a transmission path that transmits information in serial; a first information transmission device including, a transmitting section that transmits the information in the transmission path at a predetermined transmission speed, and a controller that controls the transmitting section to transmit predetermined first information in the transmission path when establishing communication, the first information including a same value in successive plurality of bits; and a second information transmission device including, a receiving section that receives the information transmitted via the transmission path, and a communication establishing section that establishes the communication based on the first information, when the receiving section receives the first information. | 2011-01-06 |
| 20110004714 | Method and Device for Priority Generation in Multiprocessor Apparatus - A device for generating a priority value of a processor in a multiprocessor apparatus, the device comprising a counter, an interface for receiving signals from an arbiter, wherein the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus. The counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The device is also adapted to send the modified value of the counter as a new priority value to the arbiter. | 2011-01-06 |
| 20110004715 | METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores. | 2011-01-06 |
| 20110004716 | DISCRETE LATERAL MOSFET POWER AMPLIFIER EXPANSION CARD - The teachings are directed to a power amplifier expansion card (“amplifier card”) for a computer. The amplifier card receives audio data through an input port and amplifies the audio data to high-level passive speaker power for transmissions through an output port. The amplifier card can comprise a circuit board having (i) at least two audio channels; (ii) an audio power amplification circuit for amplifying audio power to at least 20 W RMS per channel; and (iii) an onboard cooling system. The amplifier card can be used, for example, in a multimedia system having at least a studio controller operably connected to the amplifier card for receiving and processing input audio data. Examples of such multimedia systems include, but are not limited to, a television home entertainment system, an audio home entertainment system, a music production studio system, a gaming system, a personal computing system, or any combination thereof. | 2011-01-06 |
| 20110004717 | DOCKING SYSTEM - First and second portions of a docking system are releasably connected with one another using at least one latch mechanism that can be reusably released either from the first portion of the docking system or from the second portion of the docking system. | 2011-01-06 |
| 20110004718 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ORDERING A PLURALITY OF WRITE COMMANDS ASSOCIATED WITH A STORAGE DEVICE - A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order. | 2011-01-06 |
| 20110004719 | Memory Element - Disclosed is memory apparatus ( | 2011-01-06 |
| 20110004720 | METHOD AND APPARATUS FOR PERFORMING FULL RANGE RANDOM WRITING ON A NON-VOLATILE MEMORY - A method for performing random writing on a NV memory includes: writing page mapping information regarding a portion of a full range of addresses of the NV memory and providing at least one page mapping table corresponding to a predetermined size; and accessing the NV memory according to the page mapping information. An apparatus for performing full range random writing on an NV memory includes: a controller arranged to perform the full range random writing; and a program code, at least a portion of which is embedded within the controller or received from outside the controller. The controller executing the program code writes page mapping information regarding at least a portion of a full range of addresses of the NV memory and provides at least one page mapping table corresponding to a predetermined size. The controller executing the program code accesses the NV memory according to the page mapping information. | 2011-01-06 |
| 20110004721 | LOADING SECURE CODE INTO A MEMORY - A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory; if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed. | 2011-01-06 |
| 20110004722 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 2011-01-06 |
| 20110004723 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for a flash memory and a control circuit and a storage system using the same are provided. The data writing method includes determining whether the size of data to be stored by a host system is smaller than a predetermined value according to a write command received from the host system, when the size of the data is smaller than the predetermined value, the data is written into a corresponding buffer physical block or a corresponding spare buffer physical block. The data writing method further includes combining valid data belonging to the same logical block during the executions of several write commands. Accordingly, the response time during the execution of each write command is shortened, and the problem of timeout is avoided. | 2011-01-06 |
| 20110004724 | METHOD AND SYSTEM FOR MANIPULATING DATA - A method of manipulating data includes receiving a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The method further includes mapping the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. A system for manipulating data includes a host and a flash translation layer. The host transmits a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The flash translation layer maps the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. | 2011-01-06 |
| 20110004725 | DATA STORAGE DEVICE AND METHOD - According to one embodiment, a data storage device, includes: a recording medium, statuses of storage areas of the recording medium being managed by groups; a managing table storage module storing a managing table in which bit information pieces are associated to indexes representing the groups, the bit information pieces indicating the statuses of the storage areas initially set to an erased status; a transfer controller storing, upon receiving a write command, data in the storage areas; and a controller updates the bit information pieces of one of the groups to which the storage areas belongs to a stored status. Upon receiving an erase command, the transfer controller overwrites the storage areas by predetermined data. The main controller is configured to update the bit information pieces to the erased status. | 2011-01-06 |
| 20110004726 | PIECEWISE ERASURE OF FLASH MEMORY - Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device. | 2011-01-06 |
| 20110004727 | TAPE STORAGE EMULATION FOR OPEN SYSTEMS ENVIRONMENTS - A method according to one embodiment is performed in an environment wherein a plurality of backup hosts are connected to a plurality of virtual tape library servers (VTL servers) which in turn are connected to each of a plurality of disk library units (DLUs), each VTL server being adapted to receive tape storage commands, and in response to receiving a tape storage command, the respective VTL server accepts the tape storage command and responding as if the VTL server were the respective target tape storage device, and wherein data simultaneously streaming from the plurality of backup hosts is received by multiple of the VTL servers, where the multiple VTL servers receiving the simultaneously streamed data write to the same DLU. | 2011-01-06 |
| 20110004728 | ON-DEVICE DATA COMPRESSION FOR NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES - A non-volatile memory-based mass storage device that includes a host interface attached to a package, at least one non-volatile memory device within the package, a memory controller connected to the host interface and adapted to access the non-volatile memory device in a random access fashion through a parallel bus, a volatile memory cache within the package, and co-processor means within the package for performing hardware-based compression of cached data before writing the cached data to the non-volatile memory device in random access fashion and performing hardware-based decompression of data read from the non-volatile memory device in random access fashion. | 2011-01-06 |
| 20110004729 | Block Caching for Cache-Coherent Distributed Shared Memory - Methods, apparatuses, and systems directed to the caching of blocks of lines of memory in a cache-coherent, distributed shared memory system. Block caches used in conjunction with line caches can be used to store more data with less tag memory space compared to the use of line caches alone and can therefore reduce memory requirements. In one particular embodiment, the present invention manages this caching using a DSM-management chip, after the allocation of the blocks by software, such as a hypervisor. An example embodiment provides processing relating to block caches in cache-coherent distributed shared memory. | 2011-01-06 |
| 20110004730 | CACHE MEMORY DEVICE, PROCESSOR, AND CONTROL METHOD FOR CACHE MEMORY DEVICE - A cache memory device that connects an instruction controlling unit outputting a memory access request for requesting data and a storage device storing data, the cache memory device including: a data memory unit that holds data for each cache line, a tag memory unit that holds, for each cache line linked with a cache line of the data memory unit, tag addresses specifying storage positions of data covered by the memory access request at the storage device and status data indicating states of the data of the data memory unit corresponding to the tag addresses, a search unit that searches for a cache line of the tag memory unit corresponding to an index address included in the memory access request, a comparison unit that compares a tag address held in the found cache line of the tag memory unit and a tag address included in the memory access request and, when the two do not match, detects a “cache miss” and reads out the status information of the found cache line, and a controlling unit that, when the comparison unit detects a cache miss, requests data covered by the memory access request to the storage device and, when the cache line storing the data requested at the storage device is not present in the data memory unit, stops the supply of a clock to the data memory unit based on the status information of the cache line that the comparison unit read out. | 2011-01-06 |
| 20110004731 | CACHE MEMORY DEVICE, CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM - A cache memory device includes: a storage unit in which data and attribute information can be stored in association with each other; and a cache controller which (i) obtains, from CPU, a request signal requesting access to data and an indication signal indicating whether or not the requested data is a synchronization primitive, and when the indication signal indicates that the data requested by the request signal is the synchronization primitive, (ii) stores in association, into the storage unit, the requested data and synchronization primitive attribute information indicating that the requested data is a valid synchronization primitive. The cache controller prohibits purge of the data stored in the storage unit in association with the synchronization primitive attribute information. | 2011-01-06 |
| 20110004732 | DMA in Distributed Shared Memory System - An example embodiment of the present invention provides processes relating to direct memory access (DMA) for nodes in a distributed shared memory system with virtual storage. The processes in the embodiment relate to DMA read, write, and push operations. In the processes, an initiator node in the system sends a message to the home node where the data for the operation will reside or presently resides, so that the home node can directly receive data from or send data to the target server, which might be a virtual I/O server. The processes employ a distributed shared memory logic circuit that is a component of each node and a connection/communication protocol for sending and receiving packets over a scalable interconnect such as InfiniBand. In the example embodiment, the processes also employ a DMA control block which points to a scatter/gather list and which control block resides in shared memory. | 2011-01-06 |
| 20110004733 | Node Identification for Distributed Shared Memory System - An example embodiment of the present invention provides processes relating to a connection/communication protocol and a memory-addressing scheme for a distributed shared memory system. In the example embodiment, a logical node identifier comprises bits in the physical memory addresses used by the distributed shared memory system. Processes in the embodiment include logical node identifiers in packets which conform to the protocol and which are stored in a connection control block in local memory. By matching the logical node identifiers in a packet against the logical node identifiers in the connection control block, the processes ensure reliable delivery of packet data. Further, in the example embodiment, the. logical node identifiers are used to create a virtual server consisting of multiple nodes in. the distributed shared memory system. | 2011-01-06 |
| 20110004734 | SYSTEM AND METHOD FOR PROVIDING MORE LOGICAL MEMORY PORTS THAN PHYSICAL MEMORY PORTS - Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle. | 2011-01-06 |
| 20110004735 | METHOD AND APPARATUS FOR TWO-PHASE STORAGE-AWARE PLACEMENT OF VIRTUAL MACHINES - Techniques for placement of a virtual machine in a computing system. A first request is sent from a pool management subsystem to a placement subsystem. The first request includes specification of available storage capacities of storage systems in a computer network. The placement subsystem automatically determines a target storage system based, at least in part, on the available storage capacities. An identification of the target storage system is received at the pool management subsystem. At least one disk image of the virtual machine is written to the target storage system. Then, a second request is sent to the placement subsystem. The placement subsystem automatically determines a target computer. The latter determination is based, at least in part, on connectivity between the target computer and the target storage system. The virtual machine is installed at the target computer. The techniques facilitate live migration of virtual machines placed thereby. | 2011-01-06 |
| 20110004736 | COMPUTER SYSTEM AND CONTROL METHOD FOR THE COMPUTER SYSTEM - A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting. | 2011-01-06 |
| 20110004737 | METHOD AND APPARATUS FOR PROTECTED CONTENT DATA PROCESSING - Methods and an apparatuses that perform protected content data processing with limited access to system resources are described. One or more regions in a memory (including a source memory and a destination memory) can be allocated and unprocessed content data can be mapped to the source memory. A process can be initialized with the source and destination memories to process the content data. The process can be prevented from accessing resource other than the allocated regions in the memory. The processed content data can be stored in the destination memory. In one embodiment, the content data can include media content. A playing device can be instructed to play the media content based on the processed content data via the destination memory. | 2011-01-06 |
| 20110004738 | DATA STORAGE DEVICE AND DATA MANAGEMENT METHOD - A data storage device for storing and managing data includes a data memory, an input unit, a data writer, and a data deleter. The data memory stores data. The data memory includes a preferential deletion area for storing data which needs to be preferentially deleted. The input unit accepts input data. The data writer stores the input data in the data memory. The data deleter deletes data stored in the data memory. The data deleter starts to delete data stored in the preferential deletion area before starting to delete data stored in the data memory other than the preferential deletion area when a predefined condition is satisfied. | 2011-01-06 |
| 20110004739 | EXTENDED PAGE SIZE USING AGGREGATED SMALL PAGES - A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted. | 2011-01-06 |
| 20110004740 | DATA TRANSFER APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF SETTING DATA TRANSFER RATE - A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information. | 2011-01-06 |
| 20110004741 | Spilling Method in Register Files for Microprocessor - A spilling method in register files for a processor is proposed. The processor is of Parallel Architecture Core (PAC) structure, and accordingly includes a first cluster, a second cluster and a memory. Each of the first and second clusters includes a first function unit (e.g., M-Unit), a second function unit (e.g., I-Unit), a first local register file, a second local register file and a global register file. The first and second local register files are used by the first and second function units, respectively. For a specified live range, the method includes the steps of calculating communication costs of the first local register file, the second local register file and the global register file in each of the first and second clusters, and communication cost of the memory for storing the live range when spilling occurs; calculating use ratios of the first local register file, the second local register file and the global register file in each of the first and second clusters, and use ratio of the memory for the live range; and selecting one of the first local register file, the second local register file and the global register file in each of the first and second clusters and the memory for storing the live range based on the communication costs and the use ratios. | 2011-01-06 |
| 20110004742 | Variable-Cycle, Event-Driven Multi-Execution Flash Processor - A Multi-Execution Flash Processor core performs operations associated with accessing non-volatile semiconductor based memory units. Execution units included in the core can execute instructions requiring different numbers of clock cycles to complete by generating an event control signal in response to completing an instruction. The core can be used in a controller to access and control external memory units. Data memory access operations include using an instruction decoder to select one or more execution units to perform an operation associated with the instruction, and generating an event control signal upon completion of the operation. In some cases, executing the instruction includes selecting a second execution unit. | 2011-01-06 |
| 20110004743 | Pipe scheduling for pipelines based on destination register number - A data processing apparatus | 2011-01-06 |
| 20110004744 | DATA PROCESSING APPARATUS INCLUDING RECONFIGURABLE LOGIC CIRCUIT - There is provided a data processing apparatus ( | 2011-01-06 |
| 20110004745 | Method of Controlling a Measurement Instrument - A method of controlling a hibernation mode for a measurement instrument comprising a computer system and a computer system is provided. In a case that a power switch is turned off in a hibernation mode, contents of a memory of the computer system is transferred to a non-volatile storage device such as a hard disk drive unit under control of an operating system of the computer system and a power circuit of the measurement instrument is turned off. In a case that the power switch is turned on in the hibernation mode, the power circuit is turned on, the transferred contents stored in the non-volatile storage device is transferred to the memory under control of the operating system and the measurement device is initialized under control of application software and data stored in the memory. | 2011-01-06 |
| 20110004746 | UNIT USING OS AND IMAGE FORMING APPARATUS USING THE SAME - A chip mountable on a customer replaceable unit monitoring memory (CRUM) unit used in an image forming job includes a central processing unit (CPU) with its own operating system (OS), which operates separately from an OS of the image forming apparatus, to perform authentication communication with a main body of the image forming apparatus using the OS of the CPU. The security of a unit on which the chip is mounted can thereby be reinforced and random changes of data of the unit can be prevented. | 2011-01-06 |
| 20110004747 | Initializing Femtocells - A femtocell may be initialized on a network by automatically contacting a network service provider. The access point then automatically downloads an initial configuration from a bootstrap server belonging to the network service provider. In some cases, a femtocell access point may automatically determine, after boot up, whether it was pre-provisioned with credentials to authenticate itself with the network service provider. If so, it may use a domain name service to obtain an address of a bootstrap server. Otherwise, it may use dynamic host configuration protocol to discover the bootstrap server's Internet Protocol address. | 2011-01-06 |
| 20110004748 | ELECTRICAL CIRCUITRY FOR USE IN VOLTAGE CONTROLLERS - An integrated circuit resides on a circuit board. During operation, the digital controller integrated circuit produces control signals to control a power supply for delivery of power to a load. The integrated circuit can include multiple connectivity ports, on-board memory, and mode control logic. The multiple connectivity ports such as pins, pads, etc., of the integrated circuit can be configured to provide connections between internal circuitry residing in the integrated circuit and external circuitry residing on a circuit board to which the integrated circuit is attached. The mode control logic monitors a status of one or more connectivity ports of the integrated circuit to detect when a board handler places the digital controller in a power island mode in which the integrated circuit is powered so that the board handler can access (e.g., read/write) the memory in the digital controller integrated circuit while other portions of the board are unpowered. | 2011-01-06 |
| 20110004749 | Launching An Application From A Power Management State - A method for launching a selected application in a computer system that is either in a sleep state or a power-off state, the computer system includes an operating system (OS) installed therein to execute applications in a normal mode of the OS. The method includes, while the computer system is in one of the sleep state and the power-off state, receiving a command to launch the selected application in the computer system, loading the OS in a sandbox mode preconfigured for the selected application, and the OS in the sandbox mode launching the selected application to run in the computer system. | 2011-01-06 |
| 20110004750 | Hierarchical skipping method for optimizing data transfer through retrieval and identification of non-redundant components - A method for optimizing data transfer through retrieval and identification of non-redundant components. Efficiently packing each network transmission block using sequence search criteria. A hierarchical skipping method. Avoidance of sending undesired pieces. Segmentation of each file and object into a hierarchy of pieces in a plurality of types. | 2011-01-06 |
| 20110004751 | SYSTEMS AND METHODS FOR PROVIDING PRODUCT INFORMATION OVER A CARRIER WAVE - A customer relationship management (CRM) method using IBOC-radio signals is provided. A message in the radio signal is parsed to obtain a key. The key is compared to a plurality of stored keys. When the received key matches a stored key, a data structure associated with the message is outputted. A device comprising a lookup table with a plurality of stored keys, a tuner unit that receives a CRM in an IBOC signal, and a controller in electrical communication with the lookup table and tuner is provided. The controller comprises (i) instructions for comparing a key in the CRM to one or more stored keys in the plurality of stored keys and (ii) instructions for permitting the display of a display text associated with the received key when there is a match between the received key and a key in the plurality of stored keys. | 2011-01-06 |
| 20110004752 | PERFORMING SECURE AND NON-SECURE COMMUNICATION OVER THE SAME SOCKET - A packet processing type determiner includes a non-secure packet processing module configured to process packets received over a single socket using a non-secure protocol. The packet processing type determiner also includes a data indicator checking module configured to check the packets for a first indicator denoting a beginning of a secure data record. The packet processing type determiner further includes a secure packet processing module configured to use a secure protocol to process the packets when a packet with the first indicator is detected until a packet with a second indicator denoting an end of the secure data record is detected. | 2011-01-06 |
| 20110004753 | CERTIFICATE GENERATING/DISTRIBUTING SYSTEM,CERTIFICATE GENERATING/DISTRIBUTING METHOD AND CERTIFICATE GENERATING/DISTRIBUTING PROGRAM - In a certificate generating/distributing system, an authentication apparatus includes token transmitting means transmitting, to a service mediating apparatus, a certificate generation request token, which is information corresponding to a first certificate valid in the service mediating apparatus, together with the first certificate. The service mediating apparatus includes mediating apparatus token forwarding means forwarding the certificate generation request token to a service providing apparatus. The service providing apparatus includes certificate requesting means transmitting the certificate generation request token to the authentication apparatus when requesting a second certificate valid in the service providing apparatus. The authentication apparatus includes certificate transmitting means transmitting, to the service providing apparatus , the second certificate generated based on the first certificate in response to the request of the second certificate by the certificate requesting means. | 2011-01-06 |
| 20110004754 | Method And Apparatuses For Authentication And Reauthentication Of A User With First And Second Authentication Procedures - A method of authenticating a user to a network, the user being in possession of first and second authentication credentials associated respectively with first and second authentication procedures. The method comprises sending a challenge from the network to the user according to said second authentication procedure, receiving the challenge at the user and computing a response using said first credential or keying material obtained during an earlier running of said first authentication procedure, and said second credential, sending the response from the user to the network, and receiving the response within the network and using the response to authenticate the user according to said second authentication procedure. | 2011-01-06 |
| 20110004755 | User information providing system - In the system, when the service providing apparatus is used through the multi-functional peripheral, user authentication is performed and user information is provided to the service providing apparatus, and the authenticating apparatus holds authentication information and user information associating each information with identification information of a user, performs user authentication based on the input of the authentication information of the user for the multi-functional peripheral, transmits the identification information of the user to the multi-functional peripheral by authentication, and is allowed access to the service providing apparatus through the multi-functional peripheral by receiving the identification information, and the service providing apparatus, by receiving a service request from the multi-functional peripheral and the identification information, transmits the identification information to the authenticating apparatus, and thereby obtains user information transmitted from the authenticating apparatus. | 2011-01-06 |
| 20110004756 | GPS-BASED PROVISIONING FOR MOBILE TERMINALS - A computing device to enable a feature thereof according to a current location and a control method thereof, the computing device including: a location unit to determine the current location of the computing device; and a licensing unit to determine whether the current location corresponds to a predetermined authorized location, and to enable the feature if the current location corresponds to the authorized location. Accordingly, a permission to use a software feature or a hardware feature of the computing device can be controlled according to the current location of the computing device. | 2011-01-06 |
| 20110004757 | Apparatus, Method, System and Program for Secure Communication - Embodiments provide an apparatus, method, product and storage medium for secure communication, wherein a message is sent over a secure signalling path to a recipient, the message including a value indicating a key for encrypting or decrypting information for secure communication, or a key derivation value for deriving a key. The message further includes an indication indicating the type of usage of the value. The receiver of the message may return a message which also includes a key or key derivation value and an indication indicating the type of key or type of usage of the value. | 2011-01-06 |
| 20110004758 | Application Specific Master Key Selection in Evolved Networks - An authentication method comprises providing a set of N plural number of master keys both to a user terminal ( | 2011-01-06 |
| 20110004759 | MASS SUBSCRIBER MANAGEMENT - An authentication and mass subscriber management technique is provided by employing a key table derived as a subset of a larger key pool, a network edge device, and authentication tokens attached on both the network edge device and on a subscriber's computing device. The network edge device and subscriber's computing device are provided with secure, tamper-resistant network keys for encrypting all transactions across the wired/wireless segment between supplicant (subscriber) and authenticator (network edge device). In an embodiment of the invention, a secure, secret user key is shared between a number of subscribers based upon commonalities between serial numbers of those subscribers' tokens. In another embodiment of the invention, a unique session key is generated for each subscriber even though multiple subscribers connected to the same network connection point might have identical pre-stored secret keys. | 2011-01-06 |
| 20110004760 | METHOD AND APPARATUS OF DERIVING SECURITY KEY(S) - A method, apparatus and a wireless communication system to derive security key(s) over an air link in a secure manner by sending by a mobile station over the air a single direction permutation of a mobile station ID, establishing keys with the base station and sending the mobile station real ID in a secure manner. | 2011-01-06 |
| 20110004761 | VIRAL FILE TRANSFER - A method of distributing data between mobile devices while retaining control of that data. In particular, Digital Rights Management parameters are monitored and modified to control the distribution, and distribution is only permitted to devices which are approved or authorized. Mechanisms are provided for validating the identity of devices requesting transmission of the file. | 2011-01-06 |
| 20110004762 | SECURITY FOR A NON-3GPP ACCESS TO AN EVOLVED PACKET SYSTEM - A home subscriber server ( | 2011-01-06 |
| 20110004763 | CERTIFICATE VALIDATION METHOD AND CERTIFICATE VALIDATION SERVER AND STORAGE MEDIUM - A certificate validation method for causing a certificate validation server to receive a certificate validation request from a given terminal device, build a certification path of from a first certificate authority (CA) to a second CA, perform validation of the certification path, and send a validation result to the terminal which issued the certificate validation request is disclosed. The validation server detects either a key update of any given CA or a compromise of the given CA, acquires a certificate of relevant CA and first certificate status information and second certificate status information, stores the acquired information in a storage unit or, alternatively, updates the information stored in the storage based on the acquired information, and performs the building of a certification path and validation of the certification path by use of the information of the storage unit. | 2011-01-06 |
| 20110004764 | SECURE METER ACCESS FROM A MOBILE READER - Generally described, the disclosed subject matter is directed to improved processes for securely accessing a meter. In accordance with one embodiment, a method for providing a mobile meter reader with an authorization that may be used to establish a secure session with a meter is implemented. In particular, the method includes issuing a request for authorization to access the meter from the mobile meter reader. If the mobile meter reader maintains sufficient rights, an authorization having an encoded digital signature is generated at a host computer system and provided to the mobile meter reader. Then the method formulates and transmits an authorization command to the meter having the encoded digital signature that was generated by the host computing system. | 2011-01-06 |
| 20110004765 | LICENSE MANAGING METHOD AND DEVICE - A license managing device sets a security area for storing a license file, maintains the security area as an encoded file in an inactive state of the security area by encoding the security area, maintains the security area as a directory in an active state of the security area by decoding the security area, and encodes a license file by using a file encoding key according to the user's request and stores the same in a security area in an active state of the security area. | 2011-01-06 |
| 20110004766 | IP ADDRESS DELEGATION - A method of verifying a request made in respect of an IPv6 address comprising a network routing prefix and a cryptographically generated Interface Identifier. The request includes a delegation certificate containing a public key of the host, one or more further parameters or a formula or formulae for generating one or more further parameters, a specification of a range or set of IPv6 network routing prefixes, an identity of a delegated host, and a digital signature taken over at least the identity and the specification of a range or set of IPv6 network routing prefixes using a private key associated with the public key. The method verifies that the network routing prefix of said IPv6 address is contained within the specification, verifying that the public key and the further parameter(s) can be used to generate the cryptographically generated Interface Identifier, and verifying said signature using the public key. | 2011-01-06 |
| 20110004767 | BIDIRECTIONAL ENTITY AUTHENTICATION METHOD BASED ON THE CREDIBLE THIRD PARTY - A bidirectional entity authentication method based on the credible third party includes the steps that: entity A receives message | 2011-01-06 |
| 20110004768 | UNIT USING OS AND IMAGE FORMING APPARATUS USING THE SAME - A chip mountable on a replaceable unit used in an image forming job is disclosed. The chip includes a central processing unit (CPU) to perform at least one of authentication and cryptographic data communication with a main body of the image forming apparatus using an operating system (OS) of the CPU which operates separately from an OS of the image forming apparatus. With the use of such a configuration, security for a unit in which the chip is mounted can thereby be reinforced. | 2011-01-06 |
| 20110004769 | PASSWORD INPUT SYSTEM USING AN ALPHANUMERIC MATRIX AND PASSWORD INPUT METHOD USING THE SAME - The present invention relates to a password input algorithm, more particularly to a password input system and method using an alphanumeric matrix. An aspect of the invention can provide a password input system and method that can defend against keylogging attacks and shoulder surfing attacks, by having the final password inputted by way of certain alphanumeric matrix letters which are separated by a particular distance from the letters forming the password in the alphanumeric matrix. Also, an aspect of the invention can provide a password input system and method that can further increase the probability of defending against keylogging attacks and shoulder surfing attacks, by having the final password inputted by way of certain alphanumeric matrix letters which are separated by a particular distance from the letters forming the password in the alphanumeric matrix, but with the alphanumeric matrix rotated every time a letter is inputted. | 2011-01-06 |
| 20110004770 | ENCRYPTION SYSTEM THAT PREVENTS ACTIVATION OF COMPUTER VIRUSES - System for preventing activation of computer viruses operates in such a way that all executable files must be kept separated from other files and encrypted when written to Hard Disk Drive or Solid State Drive, with a key that is uniquely assigned to this hardware and entered by user. During the reading procedure all data is decrypted automatically by the hardware with the same key written in this hardware and used only for decryption. Since only regular programs can be installed and encrypted with the key known to the user, viruses and the other malicious software can be kept on Hard Disk Drive or Solid State Drive just in plaintext. This causes only regular programs can be sent into the main memory in plaintext, but viruses cannot, because they are destroyed in decryption procedure. | 2011-01-06 |
| 20110004771 | ELECTRONIC TERMINAL, CONTROL METHOD, COMPUTER PROGRAM AND INTEGRATED CIRCUIT - An electronic terminal performs early detection of unauthorized analysis thereon and prevents unauthorized acquisition and falsification of confidential information that is not to be released to a third party. The electronic terminal stores confidential information that is protected by consecutive application of a plurality of protection measures for defense against an attack from a third party. The electronic terminal monitors for attacks to the protection measures from an external source, and upon detecting an attack on one protection measure, updates a protection state of the confidential information to a new protection state in which either a new protection measure has been added to a protection path from the one attacked protection means to the confidential information, or the one protection measure on the path has been updated to a higher defense level. | 2011-01-06 |
| 20110004772 | PORTABLE ELECTRONIC DEVICE AND METHOD FOR USING THE SAME - A portable electronic device includes a main power supply, a power management unit (PMU) connected to the main power supply, and a receiver unit connected to the PMU. The main power supply supplies electric power to the portable electronic device through the PMU. The receiver unit includes a processor module connected to the PMU. The processor module stores a lock code, the processor module directs the PMU to prevent the main power supply from providing electric power to the portable electronic device when the receiver unit receives wireless signals corresponding to the lock code. | 2011-01-06 |
| 20110004773 | Powered device for power over ethernet system with increased cable length - Increased cable length Power over Ethernet (PoE) systems are provided. Embodiments can be designed for compliance with IEEE 802.3af, IEEE 802.3at, or legacy PoE standards. Embodiments include PSE and PD designs enabled for increased length PoE. Embodiments include example modifications of IEEE 802.3af PSE system rules, including example modifications of PSE port voltage ranges to support IEEE 802.3af compliant PDs across increased cable lengths. Embodiments include example modifications of IEEE 802.3af PD system rules, including example modifications of PD port voltage ranges to enable current IEEE compliant PSEs to support increased cable length PoE. Embodiments include PDs having increased voltage process and/or added voltage protection circuitry to support increased length PoE. Modifications of PSE system rules and PD system rules can be performed independently of each others, so that modified PSEs can be made to work with existing PDs, or vice versa. | 2011-01-06 |
| 20110004774 | Temperature Compensating Adaptive Voltage Scalers (AVSs), Systems, and Methods - Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions. | 2011-01-06 |
| 20110004775 | Methods and Systems for Use-Case Aware Voltage Selection - Systems and methods according to these exemplary embodiments provide for optimizing voltage use in digital circuits. This can be obtained by creating situations for digital circuits such that the effective critical path (ECP) can be used such as, for example, the case where a digital circuit includes a plurality of voltage domains powered by individual and possibly different voltage sources. This can then reduce voltage use in digital circuits. | 2011-01-06 |
| 20110004776 | ELECTRIC DEVICE, AND METHOD AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING POWER SUPPLY IN ELECTRIC DEVICE - An electric device includes at least one or more processing units that perform a predetermined process; a power-supply control unit that controls supply of electric power from a power source to the processing units and shutoff of the supply; a main control unit that performs a start-up process if the main control unit is supplied with power from the power source; and a sub control unit that controls the power-supply control unit so as not to supply the electric power to all or some of the processing units after the start-up process. | 2011-01-06 |
| 20110004777 | DISPLAY CONTROL CIRCUIT AND DISPLAY CONTROL METHOD - A display control circuit in accordance with an exemplary aspect of the present invention is including a display memory that stores display data to be displayed on a display device, the display memory being supplied with electric power through a power-supply terminal, a power-supply unit that connects the power-supply terminal to a power-supply or a ground according to a request, and a control unit that requests the power-supply unit to connect the power-supply terminal to a ground when the display memory enters a standby mode in which no displaying is performed on the display device, and requests the power-supply unit to connect the power-supply terminal to a power supply when a predetermined time has elapsed after the request even if the display memory is in the standby mode. | 2011-01-06 |
| 20110004778 | Method for Controlling Power on a Computer System Having a Network Device and a Wakeup Function - A method for controlling power in a computer system having a network device and a wakeup function is disclosed. A determination is made whether or not the network device is in an associated state at the time when the computer system moves into a power saving mode. In response to a determination that the network device is not in the associated state, power supply is turned off from a power source to the network device. In response to a determination that the network device is in the associated state, power supply is continually provided from the power source to the network device. | 2011-01-06 |
| 20110004779 | REDUNDANT POWER AND DATA IN A WIRED DATA TELECOMMUNICATIONS NETWORK - Redundancy of data and/or inline power in a wired data telecommunications network from a pair of network devices via a selection device is provided by communicating redundant signals with each of the pair of network devices and coupling ports of the first network device and corresponding ports of the second network device to paired inputs of the selection device. The selection device operates: 1) under the control of the pair of network devices, one acting as master and one as slave, the master selecting (for each port or for all ports) one of the two paired inputs and causing the selection device to communicate data and/or inline power via a third port of the selection device to a third network device receiving data connectivity and/or inline power from the selection device; or 2) to route two redundant signals to a third network device which then selects one for use. | 2011-01-06 |
| 20110004780 | SERVER SYSTEM AND CRASH DUMP COLLECTION METHOD - There is provided a server system that collects memory information at the time of occurrence of a failure if a failure occurs in the operating system so as to enable failure analysis. Stall monitoring of a firmware is performed by hardware and, if a stall is detected, a reset is performed. A memory has a memory area used by a boot loader of the firmware and a memory area used by another part of the firmware. It is determined based on a reset factor retained in a device whether the reset is a normal reset or a reset associated with the stall detection. In the case where the reset is a reset associated with the stall detection, information of the memory area of the memory used by the another part of the firmware at the time of occurrence of the stall is collected. | 2011-01-06 |
| 20110004781 | PROVISIONING AND REDUNDANCY FOR RFID MIDDLEWARE SERVERS - The present invention provides for the provisioning and redundancy of RFID middleware servers. Middleware servers can be automatically provisioned and RFID device/middleware server associations can be automatically updated. Some implementations of the invention provide for automatic detection of middleware server malfunctions. Some such implementations provide for automated provisioning and automated updating of RFID device/middleware server associations, whether a middleware server is automatically brought online or is manually replaced. Changes and reassignments of the RFID device populations may be accommodated. | 2011-01-06 |
| 20110004782 | FAULT-TOLERANT COMMUNICATIONS IN ROUTED NETWORKS - A method for providing fault-tolerant network communications between a plurality of nodes for an application, including providing a plurality of initial communications pathways over a plurality of networks coupled between the plurality of nodes, receiving a data packet on a sending node from the application, the sending node being one of the plurality of nodes, the data packet being addressed by the application to an address on one of the plurality of nodes, and selecting a first selected pathway for the data packet from among the plurality of initial communications pathways where the first selected pathway is a preferred pathway. | 2011-01-06 |
| 20110004783 | FAULT-TOLERANT COMMUNICATIONS IN ROUTED NETWORKS - A method for providing fault-tolerant network communications between a plurality of nodes for an application, including providing a plurality of initial communications pathways over a plurality of networks coupled between the plurality of nodes, receiving a data packet on a sending node from the application, the sending node being one of the plurality of nodes, the data packet being addressed by the application to an address on one of the plurality of nodes, and selecting a first selected pathway for the data packet from among the plurality of initial communications pathways where the first selected pathway is a preferred pathway. | 2011-01-06 |
| 20110004784 | DATA ACCESSING METHOD AND DATA ACCESSING SYSTEM UTILIZING THE METHOD - A data accessing method applied to a data accessing system, comprising: (a) performing a logic operation to a plurality of data units to generate at least one logic operation data unit; (b) performing an anti logic operation to the logic operation data unit and an other data unit to obtain a recovery data unit wherein the other data unit comprises the data units except a specific data unit in the data units; and (c) replacing the specific data unit with the recovery data unit, when the specific data unit is read and is found having an error. | 2011-01-06 |
| 20110004785 | STORAGE SYSTEM AND CONTROL METHOD OF STORAGE SYSTEM - A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting. | 2011-01-06 |
| 20110004786 | ANOMALY NOTIFICATION CONTROL IN DISK ARRAY - In a storage device incorporating a plurality of kinds of disk drives with different interfaces, the controller performs sparing on a disk drive, whose errors that occur during accesses exceed a predetermined number, by swapping it with a spare disk drive that is prepared beforehand. | 2011-01-06 |
| 20110004787 | SELF-REPAIRING ELECTRONIC DATA SYSTEM - An array of logic devices capable of self-determining the program, inputs and outputs from configuration information provided by its nearest neighbours. The rules used by each device to self-determine its behaviour are identical to those of every other device in the array. This facilitates the development of robust array configurations and robust behaviour of the device as a whole. This system's logic devices utilize three shift-registers, two are programmed before operation, the third is programmed on-the-fly by the other two. This facilitates a fast response to changes in the performance of the array in the event of partial dynamic or static failures of the array. An iterative design algorithm for the array ensures optimum use of the resources of the array. | 2011-01-06 |
| 20110004788 | HANDLING AND PROCESSING OF MASSIVE NUMBERS OF PROCESSING INSTRUCTIONS IN REAL TIME - A system is designed for processing instructions in real time during a session. This system comprises: a preloader for obtaining reference data relating to the instructions, the reference data indicating the current values of each specified resource account data file, and the preloader being arranged to read the reference data for a plurality of received instructions in parallel from a master database; an enriched instruction queue for queuing the instructions together with their respective preloaded reference data; an execution engine for determining sequentially whether each received instruction can be executed under the present values of the relevant resource account files and for each executable instruction to generate an updating command; and an updater, responsive to the updating command from the execution engine (for updating the master database with the results of each executable instruction, the operation of the plurality of updaters being decoupled from the operation of the execution engine. | 2011-01-06 |
| 20110004789 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING SYSTEM - An image processing apparatus includes an input portion for inputting image information, an information storage portion for storing the input image information, a transmission portion for transmitting the image information, and a control portion for processing input, storage and transmission of image information in parallel. The control portion, in the case where an input error occurs in the middle of performing input of image information, causes a transmission portion to transmit an instruction to delete information that has been transmitted to a transmission destination, and to start a retransmission after combining the image information before the input error occurs with the image information input after the input error occurred to form one file. | 2011-01-06 |
| 20110004790 | Asynchrony Debugging Using Web Services Interface - A system and method for debugging a running process of an application or component is disclosed. A debugging client has a user interface for receiving user commands to configure and control a debugging program. A debugging agent is resident in a local network area with the running process and has a direct connection with the running process. The debugging agent is configured to execute the debugging program to obtain debugging information on the running process, and to send the debugging information to the debugging client. A Web services communication link is established between the debugging client and the debugging agent for communicating signals to the debugging agent from the debugging client representing the user commands to configure and control the debugging program. | 2011-01-06 |
| 20110004791 | SERVER APPARATUS, FAULT DETECTION METHOD OF SERVER APPARATUS, AND FAULT DETECTION PROGRAM OF SERVER APPARATUS - It is an object to enable mapping of even a logical resource with a physical resource used by a respective host OS/guest OS. An agent execution unit | 2011-01-06 |
| 20110004792 | BIT ERROR RATE REDUCTION IN CHAOTIC COMMUNICATIONS - A system for chaotic sequence spread spectrum communications includes a transmitter ( | 2011-01-06 |
| 20110004793 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 2011-01-06 |
| 20110004794 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal. | 2011-01-06 |
| 20110004795 | METHOD FOR ENHANCING VERIFICATION EFFICIENCY REGARDING AN ERROR HANDLING MECHANISM OF A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate. | 2011-01-06 |
| 20110004796 | ACKNOWLEDGMENT CHANNEL DESIGN FOR WIRELESS ACCESS NETWORKS - Embodiments of the present invention provide an acknowledgment channel design in which an acknowledgment sequence is scrambled with a station-specific scrambling sequence. Other embodiments may be described and claimed. | 2011-01-06 |
| 20110004797 | METHODS AND ARRANGEMENTS IN A WIRELESS COMMUNICATIONS SYSTEM - The present invention relates to methods and arrangements that enable continuous adaptive control of the number of autonomous HARQ retransmissions. This is achieved by a solution, where the UE and the radio base station are using a number of autonomous HARQ retransmissions that can be adjusted based on observations in the UE and/or the radio base station. What is observed is the amount of HARQ retransmissions needed for the radio base station to correctly decode the latest received data packet(s). | 2011-01-06 |
| 20110004798 | Cooperation Communication Method and System Using Feedback Signal - Disclosed are a cooperation communication method and system using feedback signals. The cooperation communication method includes transmitting a packet to a base station by a terminal, determining, by the terminal, whether decoding of the transmitted packet is successfully performed using a feedback signal from the base station, and re-transmitting the packet to the base station by the terminal according to whether decoding of a packet of an adjacent terminal within a prescribed distance from the terminal is successfully performed. | 2011-01-06 |
| 20110004799 | MULTICARRIER MOBILE COMMUNICATION SYSTEM - A transmitting unit divides a transmit data into a plurality of code blocks, and encodes each of the plurality of code blocks to generate a transmission signal. The transmitting unit transmits the transmission signal, and a receiving unit receives the transmission signal as a reception signal. The receiving unit receives performs an iterative decoding to each of the plurality of code blocks of the reception signal. The iterative decoding is terminated to a first code block group in which an error has not been detected before a first setting iteration count. The receiving unit, when being an error in the reception signal, transmits a retransmission request feedback data which contains a NACK data and a data indicating the first code block group to the transmitting unit. First resources are assigned for each of the plurality of code blocks of the transmission signal. The transmitting unit assigns resources of the first code block group of the plurality of code blocks of the transmission signal to second resources which are fewer than the first resources, based on the retransmission request feedback data, and retransmits the transmission signal to the receiving unit. | 2011-01-06 |
| 20110004800 | Method and system for transmitting and receiving management message in communication network - A method for transmitting management message by a transmitting device in a communication network includes receiving a management message that is to be transmitted in the communication network. The transmitting device determines whether a feedback is required for the management message when the management message is transmitted in the communication network. The transmitting device also includes a feedback request information in a Medium Access Control (MAC) Protocol Data Unit (PDU) including a last fragment of the management message. The management message can be transmitted in one or more MAC PDUs and can be divided into one or more fragments. The transmitting device also transmits the MAC PDU indicating the feedback request information. | 2011-01-06 |
| 20110004801 | SYSTEM AND METHOD FOR SELECTING REPEATERS - A method is described for selecting repeaters comprising: transmitting a first signal from a first node to a second node; measuring signal strength of the first signal at the second node; transmitting a second signal from the second node to the first node; measuring signal strength of the second signal at the first node; and selecting the second node as a repeater based on the signal strength of the first signal and/or the signal strength of the second signal. | 2011-01-06 |
| 20110004802 | METHOD AND SYSTEM FOR CONTROL OF COMMUNICATION EQUIPMENT BASED ON A BIT ERROR RATE DERIVED FROM A FRAME ALIGNMENT SIGNAL - Consistent with the present disclosure, circuitry may be provided in an optical receiver that can determine a bit error rate (BER) associated with an incoming signal by dividing the number of errored bits in a frame alignment signals (FAS) by the number of bits in the FAS. Accordingly, although an optical signal may be severely degraded and forward error correction (FEC) cannot be performed, a BER may be obtained if the FAS can be identified. The BER can then be used in a feedback loop to control various optical or electrical components in the receiver to improve or reduce the BER to a level, for example, at which FEC can be performed. | 2011-01-06 |
| 20110004803 | EXECUTION DECISION APPARATUS, RECEIVING APPARATUS, RADIO COMMUNICATION SYSTEM, AND EXECUTION DECISION METHOD - An execution decision apparatus decides whether to execute a detection process for a turbo equalization apparatus which detects data before coding, by repeating processes performed on transmission data coded by error correction coding, by an equalization unit for compensating distortion by a propagation path and a decoding unit for performing an error correction process, and includes an equalization unit I/O characteristic acquisition unit which acquires an I/O characteristic of the equalization unit; a decoding unit I/O characteristic acquisition unit which acquires an I/O characteristic of the decoding unit; and a decision unit which decides whether to execute the detection process in the turbo equalization apparatus based on the I/O characteristic acquired for each of the equalization unit and the decoding unit. | 2011-01-06 |
| 20110004804 | Systems and methods for channel coding of wireless communication - Embodiments of an apparatus and method for coding of wireless transmissions channel are generally described herein. Other embodiments may be described and claimed. | 2011-01-06 |
| 20110004805 | Semiconductor Memory Device Capable of Reducing Current in PASR Mode - A semiconductor memory device capable of reducing current consumption in a partial-array self-refresh (PASR) mode includes a plurality of banks and at least one parity bank. A specific area to be self-refreshed is individually selected from each of some banks selected out of the plurality of banks to perform a self-refresh operation. Data of the specific area to be self-refreshed is verified using an error correction code (ECC) stored in the parity bank. | 2011-01-06 |
| 20110004806 | DATA RECEIVING CIRCUIT AND DATA PROCESSING METHOD - A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data. | 2011-01-06 |
| 20110004807 | LOADING SECURE CODE INTO A MEMORY - A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory. | 2011-01-06 |
| 20110004808 | SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR RATE AND/OR DIVERSITY ADAPTATION FOR PACKET COMMUNICATIONS - A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one integrated circuit assembly provides media over packet transmissions and holds bits defining reconstruction of a packet stream having a primary stage and a secondary stage. The secondary stage has one or more of linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains. The packet stream has an instance of single packet loss, and the reconstruction includes receiving a packet sequence represented by P(n)P(n−1)′, [Lost Packet], P(n+2)P(n+1)′, and P(n+3)P(n+2)′, obtaining as information from the secondary stage one or more of the linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains, and performing an excitation reconstruction utilizing said packet sequence thus received. | 2011-01-06 |
| 20110004809 | Method and Apparatus for Detecting Frame Delimiters in Ethernet Passive Optical Networks with Forward Error Correction - Embodiments of the present invention provide a system that identifies an even delimiter in a forward error correction (FEC)-coded Ethernet frame. The system receives an FEC-coded Ethernet frame that includes the even delimiter, which is a predetermined sequence that separates a conventional Ethernet frame and FEC parity bits in the FEC-coded Ethernet frame. Next, the system scans a bit stream of the FEC-coded Ethernet frame. Then, the system determines a first Hamming distance between a first consecutive set of frame bits in the bit stream and the even delimiter. The system also determines a second Hamming distance between a second consecutive set of frame bits in the bit stream and the even delimiter. Both the first and second Hamming distances are shorter than a predefined value. The system subsequently selects one of the first and second sets of frame bits having the shorter Hamming distance as the even delimiter. | 2011-01-06 |
| 20110004810 | Method and System of Receiving Data with Enhanced Error Correction - A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s). | 2011-01-06 |
| 20110004811 | Encoding/decoding apparatus and method - An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each variable node corresponding to a codeword symbol position. The protograph has a plurality of groups of nodes, each group of nodes comprising both variable nodes and check nodes. Each of the check nodes in a group is of degree 2 and has connections to two variable nodes in the same group. The protograph also has a plurality of check nodes of degree n, where n is the number of said plurality of groups, wherein each of the plurality of check nodes has a connection to a variable node in each group such that the symbol positions in a codeword are interleaved between the groups of nodes. | 2011-01-06 |
