Entries |
Document | Title | Date |
20110093830 | Integrated Circuit Optimization Modeling Technology - A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results. | 04-21-2011 |
20110126167 | Multi-Mode Redundancy Removal - A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output. | 05-26-2011 |
20110145777 | Intelligent memory system compiler - Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system. | 06-16-2011 |
20110191740 | ZONE-BASED OPTIMIZATION FRAMEWORK - Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation. | 08-04-2011 |
20110209112 | METHOD FOR CLOCK LOAD ALIGNMENT DURING STANDARD CELL OPTIMIZATION - A computing device may include a memory to store instructions and a processor. The processor may execute the instructions to conduct an initial cell optimization for an integrated circuit layout; designate clock loads associated with a first-level clock buffer; receive, after the initial standard-cell optimization, a set of initial placement locations; align the clock loads according to the set of placement locations; conduct, using the aligned clock loads, a re-optimization of the integrated circuit layout; and store, in the memory, a circuit layout based on the re-optimization. | 08-25-2011 |
20110219348 | AUTOMATIC DESIGN SUPPORT APPARATUS AND METHOD - Design variable value sets for predetermined design variables are generated, and for each of the predetermined design variables, parameter value sets for predetermined parameters are generated. For each combination of them, circuit simulation is carried out to obtain a performance item value set for predetermined performance items. Then, for each of the design variable value sets, and further for each of the parameter value sets generated for a corresponding design variable value set, combinations of the design variable value set and parameter value set are identified, for which performance item values for all of the predetermined performance items are not less than performance item values obtained for a combination of the corresponding design variable value set and a corresponding parameter value set, and a yield rate is calculated by dividing the number of identified combinations by the number of parameter value sets generated for the corresponding design variable value set. | 09-08-2011 |
20110231811 | MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION - An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V | 09-22-2011 |
20110283249 | METHOD AND SYSTEM TO PREDICT A NUMBER OF ELECTROMIGRATION CRITICAL ELEMENTS - A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors. | 11-17-2011 |
20110283250 | Method and apparatus for performing asynchronous and synchronous reset removal during synthesis - A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed. | 11-17-2011 |
20110289470 | Methods and Systems to Meet Technology Pattern Density Requirements of Semiconductor Fabrication Processes - Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die. | 11-24-2011 |
20110289471 | Simultaneous Multi-Layer Fill Generation - Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met. | 11-24-2011 |
20110296367 | Optimizing Cell Libraries for Integrated Circuit Design - A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library. | 12-01-2011 |
20110296368 | Optimizing Integrated Circuit Design Based on Cell Library - A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library. | 12-01-2011 |
20110302546 | METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION - Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be associated with a process corner, an operating condition, and/or an operating mode. During operation, the system can receive a set of scenarios over which the circuit design is to be optimized. Next, the system can compute values of constrained objects in the circuit design over the set of scenarios. The system can then determine a subset of scenarios based at least on the values of the constrained objects, so that if the circuit design meets design constraints in each scenario in the subset of scenarios, the circuit design is expected to meet the design constraints in each scenario in the set of scenarios. | 12-08-2011 |
20110302547 | METHOD AND APPARATUS FOR USING SCENARIO REDUCTION IN A CIRCUIT DESIGN FLOW - Some embodiments of the present invention provide techniques and systems for using scenario reduction in a design flow. The system can use scenario reduction to determine two subsets of scenarios that correspond to two sets of design constraints. Next, the system can optimize the circuit design using one of the sets of design constraints over the associated subset of scenarios. Next, the system can optimize the circuit design using both sets of design constraints over the union of the two subsets of scenarios. In some embodiments, the system can iteratively optimize a circuit design by: performing multiple optimization iterations on the circuit design over progressively larger subsets of scenarios which are determined by performing scenario reduction with relaxation; and performing at least one optimization iteration on the circuit design over a subset of scenarios which is determined by performing scenario reduction without relaxation. | 12-08-2011 |
20120011485 | MODELING THE SKIN EFFECT USING EFFICIENT CONDUCTION MODE TECHNIQUES - Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrands for calculating the matrix elements into simplified terms that are less computationally intensive than the integrands and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media). | 01-12-2012 |
20120011486 | Optimizing a Circuit Design Library - A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library. | 01-12-2012 |
20120030641 | PERFORMING SCENARIO REDUCTION USING A DOMINANCE RELATION ON A SET OF CORNERS - Some embodiments of the present invention provide techniques and systems for performing scenario reduction using a dominance relation on a set of corners. During operation, the system can receive a design library which specifies gate characteristics at each corner in a set of corners. Next, the system can use the design library to determine a dominance relation on the set of corners for each gate type. The dominance relations can be stored with the design library. The system can then receive a set of scenarios over which a circuit design is to be optimized. Next, the system can determine a subset of the set of scenarios using one or more dominance relations on the set of corners. The system can then optimize the circuit design over the subset of the set of scenarios. | 02-02-2012 |
20120110540 | METHOD OF OPTIMIZING PARAMETERS OF ELECTRONIC COMPONENTS ON PRINTED CIRCUIT BOARDS - In a method of optimizing parameters of electronic components on printed circuit boards (PCBs), a first experiment table for m variables of one type of parameter of P electronic components on a PCB is designed using n values of each variable and the RSM. P EHs of each first experiment are obtained by simulating, and P EH empirical formulas are computed according to the P EHs. A second experiment table for the m variables is designed using n′ values of each variable and the full factorial design, and P EHs of each second experiment are computed using the P EH empirical formulas. Experiments, all the P EHs of which are greater than 1, are filtered from the second experiment tables, and an average EH of each filtered experiment is computed to pick an experiment the average EH of which is the greatest. The values of the m variables in the picked experiment are considered as optimized. | 05-03-2012 |
20120144361 | PARAMETERIZED DUMMY CELL INSERTION FOR PROCESS ENHANCEMENT - The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value. | 06-07-2012 |
20120159418 | TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES - A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform. | 06-21-2012 |
20120167033 | Controlling Plating Stub Reflections In A Chip Package - Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width. | 06-28-2012 |
20120198409 | Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integrated Circuit Net Assignment - A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations. | 08-02-2012 |
20120210290 | Method and Device for Reconstructing Scan Chain Based on Bidirectional Preference Selection in Physical Design - Reconstruction methods and devices are disclosed for scan chains in physical design that is based on two-way priority selection. The structural reconstruction method in the scan chains, in the first place, establishes a first preference sequence for a certain number of scanning elements in each of these scan chains as well as a secondary preference sequence for these scan chains in each of these scanning elements respectively. Then, two-way selection is executed between the scan chains and scanning elements based on the corresponding first preference sequence and secondary preference sequence, so that these scanning elements can be redistributed to these scan chains. The structural reconstruction method and device in the invention conduct an integrated optimization for a global scan chain, where the global wiring length is shortened dramatically and the wiring efficiency is improved. | 08-16-2012 |
20120246608 | DEVICE FOR ELECTRO-OPTICAL MODULATION OF LIGHT INCIDENT UPON THE DEVICE - A method and apparatus for designing a device to operate in a coupling mode, a detection mode, or a reflection mode for incident light. The incident light has a wavelength λ and is incident upon a semiconductor structure of the device at an angle of incidence (θ | 09-27-2012 |
20120290998 | DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD - The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation. | 11-15-2012 |
20120304143 | Planar Lightwave Circuit, Design Method for Wave Propagation Circuit, and Computer Program - A planar lightwave circuit is provided which can be easily fabricated by an existing planar-lightwave-circuit fabrication process, which can lower the propagation loss of signal light and which can convert inputted signal light so as to derive desired signal light. A planar lightwave circuit having a core and a clad which are formed on a substrate, has input optical waveguide(s) ( | 11-29-2012 |
20120331436 | VARIABLE Z0 ANTENNA DEVICE DESIGN SYSTEM AND METHOD - A variable Z | 12-27-2012 |
20130014071 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 01-10-2013 |
20130014072 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 01-10-2013 |
20130014073 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 01-10-2013 |
20130019221 | Circuit Design Library Optimization - A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library. | 01-17-2013 |
20130024832 | DFM Improvement Utility with Unified Interface - A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern. | 01-24-2013 |
20130024833 | Reducing Metal Pits Through Optical Proximity Correction - A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit. | 01-24-2013 |
20130047132 | METHOD OF DESIGNING NONVOLATILE MEMORY DEVICE - In a computer-implemented method of designing a nonvolatile memory device, first parameters associated with external environmental conditions are set. Second parameters associated with structural characteristics and internal environmental conditions are set. A first initial operation condition associated with an erase operation is determined based on the first and second parameters. A second initial operation condition associated with a program operation is determined based on the first and second parameters and the first initial operation condition. A final operation condition associated with reliability is determined based on the first and second parameters, and the first and second initial operation condition. | 02-21-2013 |
20130061196 | TARGET-BASED DUMMY INSERTION FOR SEMICONDUCTOR DEVICES - The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout. | 03-07-2013 |
20130091482 | METHOD AND APPARATUS FOR DESIGN SPACE EXPLORATION ACCELERATION - A method for accelerating design space exploration of a target device when a behavioral description of the target device is given, includes: parsing the behavioral description to build a dependency parse tree; creating independent sets of clusters based on the dependency parse tree, each cluster being a set of a node or nodes of the dependency parse tree and independently explorable; exploring synthesizable operations of each cluster exhaustively in order to establish impact of each operation synthesized differently on a final circuit in designing of the target device; and combining attributes for the clusters to create designs with improved characteristics under constraints. | 04-11-2013 |
20130104096 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage. | 04-25-2013 |
20130125080 | CIRCUIT OPTIMIZATION METHOD AND APPARATUS FOR ANALOG CIRCUIT MIGRATION - A circuit optimization apparatus and a circuit optimization method used in analog circuit migration which migrates a source circuit to a target circuit are disclosed. The circuit optimization method comprises: dividing the source circuit into at least one direct current path; determining an adaptation sequence of the at least one direct current path; and optimizing the at least one direct current path in the target circuit one by one in the adaptation sequence. The circuit optimization apparatus and the circuit optimization method improve an optimization efficiency of the analog circuit migration. | 05-16-2013 |
20130132923 | Method for Constant Power Density Scaling - A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors. | 05-23-2013 |
20130132924 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 05-23-2013 |
20130185691 | TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS - A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful. | 07-18-2013 |
20130227512 | OPTIMIZATION FOR CIRCUIT DESIGN - Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics. | 08-29-2013 |
20130268909 | IMPEDANCE OPTIMIZED CHIP SYSTEM - A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips. | 10-10-2013 |
20140033159 | Method of Optimizing Design for Manufacturing (DFM) - The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters. | 01-30-2014 |
20140040849 | QUANTUM GATE OPTIMIZATIONS - Disclosed are systems and methods for improving quantum computation simulation execution time by “growing” sets of small quantum gates into larger ones. Two approaches are described. In the first approach, sub-strings may be replaced by a single representative that may be used multiple times throughout the quantum circuit. In the second approach, nearby gates may be coalesced in an iterative fashion, to thereby build larger and larger gates. Results may be cached for re-use. Both of these approaches have proven effective and have gained typical simulation speed-ups of 1-2 orders of magnitude. | 02-06-2014 |
20140040850 | Manufacturability - Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice. | 02-06-2014 |
20140137067 | FILTER DESIGN TOOL - A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately. | 05-15-2014 |
20140137068 | FILTER DESIGN TOOL - A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately. | 05-15-2014 |
20140137069 | FILTER DESIGN TOOL - A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately. | 05-15-2014 |
20140181778 | INTEGRATED CIRCUIT OPTIMIZATION - A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a channel implementation area, corresponding to the substrate, for each of a plurality of signal channels, based on the channel priority assigned to the signal channel and based on the block implementation areas. The device may generate an integrated circuit design comprising the channel implementation area allocated for each of the plurality of signal channels. | 06-26-2014 |
20140201697 | DETERMINING OVERALL OPTIMAL YIELD POINT FOR A SEMICONDUCTOR WAFER - A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where the weight factor represents an importance of a component to the semiconductor device. The computer then determines an overall optimal yield point based on the component yield point and weight factor determined for each component of the plurality of components, the overall optimal yield point representing the process parameter values where maximum yield is achieved for the semiconductor device. | 07-17-2014 |
20140245249 | SYSTEMS AND METHODS FOR SOLVING COMPUTATIONAL PROBLEMS - Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits. | 08-28-2014 |
20140250417 | EXPERT SYSTEM-BASED INTEGRATED INDUCTOR SYNTHESIS AND OPTIMIZATION - Apparatus and method for designing an electrical component including a processor and a user interface, enabling a user to input a desired characteristic of the electrical component, such as inductance or quality factor at an operating frequency for an integrated spiral inductor. The processor is configured to determine sufficiently optimal characteristics of the electrical component, combining the user desired characteristic with other preset characteristics of the electrical component, to define a first model of the electrical component, to simulate the model having the combined characteristics to determine performance, and to draw on a rule-set of expert knowledge relating to the general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion in order to enable modification of the model, thereby iteratively to determine a design solution for the electrical component through one or more simulations and modifications using the rule-set. | 09-04-2014 |
20140310672 | ANALYTICAL SYNTHESIS METHOD AND OTRA-BASED CIRCUIT STRUCTURE - An analytical synthesis method (ASM) for designing a higher-order voltage-mode operational trans-resistance amplifier and capacitor (OTRA-C) based filter is disclosed. A decomposition of a complicated nth-order transferring a function is converted into a set of equations corresponding to a set of sub-circuitries. Then, a circuit structure is constructed by combining said sub-circuitries. | 10-16-2014 |
20150113496 | THERMALLY AWARE PIN ASSIGNMENT AND DEVICE PLACEMENT - Embodiments of the disclosure relate to methods for facilitating the design of an integrated circuit (IC) using thermally aware pin assignment and device placement. The method includes creating a layout for the IC, the layout including a plurality of macros each having devices and pin assignments and revising the layout for the IC by repositioning a macro or a device to meet a timing requirement of the IC. The method also includes creating a thermal map of the IC based on the layout for the IC and a workload model for the IC and identifying at least one thermally critical pin assignment based on the thermal map of the IC. The method includes revising the layout by repositioning a thermally critical pin assignment and a device. | 04-23-2015 |
20150331984 | SWITCHED MODE POWER SUPPLY OUTPUT FILTER CONFIGURATION - Method determines a configuration of capacitors in an output filter of a switched mode power supply (SMPS). Candidate configurations are generated, each associated with a respective cost function value calculated based on number of capacitors of each kind in the candidate configuration and cost assigned to each kind of capacitor. The candidate configurations are ordered based on their cost function values. A binary search through the ordered candidate configurations determines a capacitor configuration associated with a lowest cost function value to allow a defined load transient response requirement of the SMPS. Whether a candidate configuration allows the defined load transient response requirement of the SMPS is determined using a model of a SMPS having the candidate configuration of the output filter simulating deviation of output voltage of the SMPS in response to change in load current of the SMPS and determining whether the defined load transient response requirement is allowed. | 11-19-2015 |
20150370944 | SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF - Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads. | 12-24-2015 |
20160034626 | EXPERT SYSTEM-BASED INTEGRATED INDUCTOR SYNTHESIS AND OPTIMIZATION - A system and method for designing an electrical component comprises a model extraction engine configured to generate a model based on a set of parameters, a simulator configured to simulate the generated model and measure performance, a rule-set usable to determine changes to the set of parameters, and an inference engine configured to change salience values of expert rules included in the rule set. The salience value determines when and if an expert rule is used to change the set of parameters. One or more microprocessors are configured to determine design characteristics of the electrical component by iteratively performing, until measured performance is within tolerance, the steps of generating a model based on an updated version of the set of parameters, simulating the generated model, measuring performance of the generated model, and updating the set of parameters using the rule-set if the measured performance is not within the predefined tolerance. | 02-04-2016 |
20160048627 | DESIGN TECHNIQUES FOR OPTICAL PROCESSING ELEMENTS - One disclosed method for designing an integrated computational element (ICE) core includes generating with a computer a plurality of predetermined ICE core designs having a plurality of thin film layers, wherein generating the plurality of predetermined ICE core designs includes iteratively varying a thickness of each thin film layer by applying coarse thickness increments to each thin film layer, calculating a transmission spectrum for each predetermined ICE core design, calculating a performance of each predetermined ICE core design based on one or more performance criteria, identifying one or more predictive ICE core designs based on the performance of each predetermined ICE core design, and optimizing the one or more predictive ICE core designs by iteratively varying the thickness of each thin film layer with fine thickness increments, wherein the one or more predictive ICE core designs are configured to detect a particular characteristic of interest. | 02-18-2016 |
20160048628 | METHOD FOR DYNAMIC EXPERIMENTAL DESIGN - The present invention discloses a method for dynamic experimental design that is applied in a semiconductor manufacturing process. During an experimental design process, it will be checked whether an experimental target range is changed so as to rebuild an experimental design table and retain completed experimental factors in order achieve the purpose of dynamically adjusting the experimental factors. The method for dynamic experimental design according to the present invention can be effectively applied in the high-tech industry. | 02-18-2016 |
20160063164 | METHOD FOR DETERMINING BY OPTIMIZATION A MULTI-CORE ARCHITECTURE - The invention relates to a method for determining by optimization a multi-core architecture and a way of implementing an application on the architecture for a given application, the method comprising:
| 03-03-2016 |
20160070839 | METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC. | 03-10-2016 |
20160103944 | SYSTEM AND METHOD FOR SIGNAL INTEGRITY WAVEFORM DECOMPOSITION ANALYSIS - A system and method of analyzing signal performance of a hardware system includes dividing a simulation of the hardware system into a chain of blocks, identifying resonant loops between pairs of blocks in the chain of blocks, determining a loop response for each of the identified resonant loops, and determining an impact of each loop response on a performance of the system. | 04-14-2016 |
20160147932 | ENHANCED PARAMETER TUNING FOR VERY-LARGE-SCALE INTEGRATION SYNTHESIS - A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied. | 05-26-2016 |
20160180007 | Optimization Of Parasitic Capacitance Extraction Using Statistical Variance Reduction Technique | 06-23-2016 |