Class / Patent application number | Description | Number of patent applications / Date published |
716107000 | Equivalence checking | 81 |
20110016441 | METHOD AND SYSTEM FOR DYNAMIC AUTOMATED HINT GENERATION FOR ENHANCED REACHABILITY ANALYSIS - Methods and systems are provided for dynamically generating a hint set for enhanced reachability analysis in a sequential circuitry design that is represented by a Binary Decision Diagram (BDD). After determining a ranking of the BDD variables, they are sorted in the order of the ranking. The ranking is used to select some of the variables for use in creating hints for more efficiently performing the reachability analysis in a creating an equivalent sequential circuitry design. | 01-20-2011 |
20110107283 | METHOD FOR OPTIMIZING LOCATION AND NUMBER OF POWER/GROUND PADS ON POWER/GROUND DISTRIBUTION NETWORK WITH MULTIPLE VOLTAGE DOMAINS - The present invention relates to a method for optimizing power/ground pads in a power/ground distribution network. A power/ground distribution network is created for each of multiple voltage domains and a load current source of each node of the power/ground distribution network is modeled in consideration of the actual shapes and areas of functional blocks. A local optimization method is developed to solve problems generated when a conventional optimization method is applied to optimization of power/ground pads in a bump shape used for a flip chip, and a combination of global optimization and local optimization is applied to layouts using bump bonding, which is discriminated from the conventional optimization method restrictively applicable to layouts using wire bonding. | 05-05-2011 |
20110197171 | COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL - A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test). | 08-11-2011 |
20110214096 | Method For Piecewise Hierarchical Sequential Verification - This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled | 09-01-2011 |
20110214097 | Method for Preparing Re-Architected Designs for Sequential Equivalence Checking - This disclosure describes a method illustrated in FIG. | 09-01-2011 |
20110219345 | Generating Test Benches for Pre-Silicon Validation of Retimed Complex IC Designs Against a Reference Design - This invention ( | 09-08-2011 |
20110283247 | METHOD OF RECORDING AND REPLAYING CALL FRAMES FOR THE TESTBENCH - A computer-implemented method to debug testbench and the associated circuit design by recording a trace of call frames along with the activities of the circuit design. By correlating and displaying the recorded call frames, the method enables users to easily trace the execution history of the subroutines and debug the testbench code. In addition, users can trace the source code of the testbench by using the trace of call frames. Furthermore, users can debug with a virtual simulation, which is done by post-processing the simulation records stored in a database. | 11-17-2011 |
20110307849 | LOGICAL DESCRIPTION DIFFERENCE EXTRACTING METHOD, LOGICAL DESIGN AIDING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM THEREOF - A logical description aiding apparatus identifies a positional relation between a position of an uncorrected description part of an after-correction logical description and a position of a corresponding description part of a before-correction logical description. After that, the logical description aiding apparatus identifies, using the identified positional relation, a position where before-correction check results are accordant with after-correction check results and conducts message replacement so that the format of a message of a before-correction check result located on the identified position is changed to the same format as the format of messages of the after-correction check results. The logical description aiding apparatus then extracts differences between the format-changed before-correction check results and the after-correction check results. | 12-15-2011 |
20120151423 | LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING - An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property. | 06-14-2012 |
20120151424 | CONVERSION OF CIRCUIT DESCRIPTION TO AN ABSTRACT MODEL OF THE CIRCUIT - A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the abstraction level. By changing the abstraction level, the conversion is not simply a code conversion from one language to another, but a process of learning the circuit using neural networks and representing the circuit using a system of equations that approximate the circuit behavior, particularly with respect to timing aspects. A higher level of abstraction eliminates much of the particular implementation details, and allows easier and faster design exploration, analysis, and test, before implementation. In one aspect, a model description of the circuit, protocol information relating to the circuit, and simulation data associated with the lower level description of the circuit are used to generate an abstract model of the circuit that approximates the circuit behavior. | 06-14-2012 |
20120167025 | METHOD FOR ANALYZING SENSITIVITY AND FAILURE PROBABILITY OF A CIRCUIT - A method is disclosed of determining a likelihood of failure of a circuit made in accordance with a circuit design based on at least one variable derived from measurements of a fabricated component or component combination included in the circuit design. Also disclosed is a processor configured to perform the method and a computer-readable medium storing method instructions. | 06-28-2012 |
20120227022 | Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation - An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation. | 09-06-2012 |
20120246604 | COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL - A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test). | 09-27-2012 |
20120272197 | Enhancing Redundancy Removal with Early Merging - A mechanism is provided for simplifying a netlist before computational resources are exceeded. For each of a set of suspected equivalences in a proof graph of a netlist, a determination is made as to whether equivalence holds for at least one of an equivalence or an equivalence class by identifying whether the equivalence or equivalence class is either affecting or non-affecting. Responsive to the equivalence or equivalence class being affecting, a proof dependency is recorded as an edge in a proof graph. For each node in the proof graph, a determination is made as to whether the node has a falsified dependency. Responsive to the node failing to have a falsified dependency, identification is made that all dependencies are satisfied and that the equivalences represented by the node in the proof graph are sequential equivalences. The netlist is then simplified by consuming the sequential equivalences. | 10-25-2012 |
20120272198 | Enhancing Redundancy Removal with Early Merging - A mechanism is provided for simplifying a netlist before computational resources are exceeded. For each of a set of suspected equivalences in a proof graph of a netlist, a determination is made as to whether equivalence holds for at least one of an equivalence or an equivalence class by identifying whether the equivalence or equivalence class is either affecting or non-affecting. Responsive to the equivalence or equivalence class being affecting, a proof dependency is recorded as an edge in a proof graph. For each node in the proof graph, a determination is made as to whether the node has a falsified dependency. Responsive to the node failing to have a falsified dependency, identification is made that all dependencies are satisfied and that the equivalences represented by the node in the proof graph are sequential equivalences. The netlist is then simplified by consuming the sequential equivalences. | 10-25-2012 |
20120278773 | VERIFYING DATA INTENSIVE STATE TRANSITION MACHINES RELATED APPLICATION - A method, system, and computer program product for verification of a state transition machine (STM) are provided in the illustrative embodiments. The STM representing the operation of a circuit configured to perform a computation is received. A segment of the STM is selected from a set of segments of the STM. A set of properties of the segment is determined. The set of properties is translated into a hardware description to form a translation. The segment is verified by verifying whether all relationships between a pre-condition and a post condition in the translation hold true for any set of inputs and any initial state of a hardware design under test. A verification result for the segment is generated. Verification results for each segment in the set of segments are combined to generate a verification result for the STM. | 11-01-2012 |
20120278774 | MODEL CHECKING IN STATE TRANSITION MACHINE VERIFICATION - A method, system, and computer program product for improved model checking for verification of a state transition machine (STM) are provided. A hardware design under test and a property to be verified are received. A level (k) of induction proof needed for the verification is determined. A circuit representation of the property using the hardware design under test for k base cases is configured for checking that the circuit representation holds true for the property for each of the k base cases, and for testing an induction without hypothesis by testing whether the property holds true after k clock cycles starting from a randomized state, where induction without hypothesis is performed by omitting a test whether the property holds true for the next cycle after the property holds for k successive cycles. The induction proof of the property using the hardware design under test by induction without hypothesis is produced. | 11-01-2012 |
20120297351 | METHODS OF MODELING A TRANSISTOR AND APPARATUS USED THEREIN - Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided. | 11-22-2012 |
20120317526 | VERIFICATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND DESIGN VERIFICATION APPARATUS - A design verification method is disclosed. A computer searches for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks. Then, the computer changes an abstraction level of an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist. | 12-13-2012 |
20130007680 | Coverage Based Pairwise Test Set Generation for Verification of Electronic Designs - With various implementations of the invention, test sequences are generated using a pairwise methodology. The generated test sequences are checked using a constraint solver to determine if the test sequences satisfy a set of constraints. In some implementations, the uncovered pairs for a particular input are checked using the constraint solver to determine if any pairs violate the constraints. Any pairs found to violate the constraints can be excluded from the test set. With some implementations, the uncovered pairs are sorted such that the sum of every three consecutive elements is odd. | 01-03-2013 |
20130036392 | GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN - This invention ( | 02-07-2013 |
20130080983 | FUNCTIONAL SIMULATION REDUNDANCY REDUCTION BY STATE COMPARISON AND PRUNING - Methods and systems initiate a simulation of an integrated circuit design. The simulation produces data that will exist in latches of the integrated circuit design when a device manufactured according to the integrated circuit design is operating. The methods and systems evaluate same-state latches associated with different portions of the simulation. If two of the same-state latches have the same state, given the same inputs and environmental conditions, the method and systems terminate a first portion of the simulation associated with a first of the same-state latches, but allow a second portion of the simulation associated with a second of the same-state latches to proceed. | 03-28-2013 |
20130117722 | ACCELERATING COVERAGE CONVERGENCE AND DEBUG USING SYMBOLIC PROPERTIES AND LOCAL MULTI-PATH ANALYSIS - In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions, avoidance of short circuiting logic, and/or symbolic triggering of events. Symbolic elements are propagated through the design and the test bench during multiple simulation runs to collect symbolic properties. Coverage information from the multiple simulation runs is analyzed to identify coverage points to be targeted. For each identified coverage point, the constraints resulting from the collected symbolic properties are solved to generate directed stimuli for the design. These directed stimuli increase the coverage convergence. | 05-09-2013 |
20130125072 | SYSTEM AND METHOD OF DETECTING DESIGN RULE NONCOMPLIANT SUBGRAPHS IN CIRCUIT NETLISTS - An automated system and method of performing electronic design rule checking on the netlist of an integrated circuit composed of a plurality of subgraphs. The electronic design rule is embodied as a two part template with a target subgraph specification and a design rule compliance check specification. The target subgraph specification often is at least partially defined by an interactive visual programming section that allows the user to construct a graphic specification of the target netlist. The method first searches the netlist for target subgraphs that match the target subgraph specification, and the user can verify proper target selection. The method then performs rule checks on these search targets, and non compliant subnets identified. Flexibility is enhanced by use of search wildcards, attribute ranges, and various short user scripts which may contain various Boolean logical operations. | 05-16-2013 |
20130145330 | COMPUTER DESIGNED RESONANT PHOTODETECTORS AND METHOD OF MAKING - A method for designing a photodetector comprising an array of pixels: selecting at a material composition for the photodetector; determining a configuration of at least one pixel in the array of pixels using a computer simulation, each pixel comprising an active region and a diffractive region, and a photodetector/air interface through which light enters, the computer simulation operating to process different configurations of the pixel to determine an optimal configuration for a predetermined wavelength or wavelength range occurring when waves reflected by the diffractive element form a constructive interference pattern inside the active region to thereby increase the quantum efficiency of the photodetector. An infrared photodetector produced by the method. | 06-06-2013 |
20130159946 | GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES - A system, and computer program product for guiding design actions for complex failure modes in an integrated circuit (IC) design are provided in the illustrative embodiments. A probability of failure estimate of a circuit according to the IC design is received, the probability being determined using a simulation. A sensitivity of the probability of failure to a variable associated with a component in the circuit is calculated, wherein the sensitivity is determined by an estimation without the simulation. The sensitivity is depicted relative to the component in the IC design such that the sensitivity is associated with the component and a visual relationship between the component and the sensitivity is usable for adjusting a characteristic of the component to reduce the probability of failure of the circuit. | 06-20-2013 |
20130159947 | GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES - A method for guiding design actions for complex failure modes in an integrated circuit (IC) design is provided in the illustrative embodiments. A probability of failure estimate of a circuit according to the IC design is received, the probability being determined using a simulation. A sensitivity of the probability of failure to a variable associated with a component in the circuit is calculated, wherein the sensitivity is determined by an estimation without the simulation. The sensitivity is depicted relative to the component in the IC design such that the sensitivity is associated with the component and a visual relationship between the component and the sensitivity is usable for adjusting a characteristic of the component to reduce the probability of failure of the circuit. | 06-20-2013 |
20130167095 | STACKED DIE INTERCONNECT VALIDATION - A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns. | 06-27-2013 |
20130198703 | Virtual Flat Traversal Of A Hierarchical Circuit Design - Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria. | 08-01-2013 |
20130212545 | METHOD AND SYSTEM THEREOF FOR OPTIMIZATION OF POWER CONSUMPTION OF SCAN CHAINS OF AN INTEGRATED CIRCUIT FOR TEST - Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing is keeping the power dissipation during testing under the allowed power capabilities of the tester power supplies, as the power used during scan test is much higher than that used during functional testing. A method for estimating the power dissipation of scan blocks in a circuit during the design stage is disclosed. Using the results generated, the circuit designer divides the design into an optimum number of scan blocks for test. Thus at-speed scan of the individual or groups of scan blocks can be estimated, during design, for optimizing test time while keeping the test power within acceptable limits. | 08-15-2013 |
20130227505 | Equivalence Checking Method, Equivalence Checking Program, and Equivalence Checking Device - Specific characteristics of a branch structure between a behavioral description and a hardware description, a structural dependence relation therebetween, and the like are extracted and used to shorten the time of processing for equivalence checking, thereby contributing to the shortening of a processing time required for equivalence checking for a high-level description and a behavioral synthesis result. Upon checking of the equivalence of a high-level description and a synthesis result obtained by performing a behavior synthesis on the high-level description according to a behavioral synthesis restriction, correspondence information between flip-flops with a feedback loop in the synthesis result and variables associated therewith with a backward data dependence relation in a high-level description is generated and used. | 08-29-2013 |
20130246988 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR HIERARCHICAL FORMAL HARDWARE VERIFICATION OF FLOATING-POINT DIVISION AND/OR SQUARE ROOT ALGORITHMIC DESIGNS USING AUTOMATIC SEQUENTIAL EQUIVALENCE CHECKING - A system, method, and computer program product are provided for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking. In use, for at least one of a floating-point division algorithm and a square root algorithm, an architectural specification for hardware, a hardware implementation on the hardware, and at least one intermediate model having a level of specificity between the architectural specification and the hardware implementation are identified. Additionally, an equivalence is automatically determined, hierarchically, between the architectural specification, and the at least one intermediate model, and between the at least one intermediate model and the hardware implementation. Furthermore, for the hardware, the at least one of the floating-point division algorithm and the square root algorithm are formally verified, based on the automatic sequential equivalence determination. | 09-19-2013 |
20130263072 | DESIGNING ANALOG CIRCUITS - According to an aspect of an embodiment, a method of designing an analog circuit may include selecting multiple analog components for a circuit. The method may also include ordering the analog components. The method may also include determining at least one pareto-optimal design point for a parameter of each analog component. The pareto-optimal design point for each analog component may be based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components. | 10-03-2013 |
20130268906 | AUTOMATIC PARITY CHECKING IDENTIFICATION - A method, apparatus and computer program product for automatic parity check identification. The method comprising: automatically identifying a parity signal in a circuit design, wherein the parity signal is defined as a parity function of a set of support signals, wherein the automatic identification comprises: obtaining a candidate parity signal and a corresponding set of candidate support signals; and verifying that a bit flip in exactly one of any of the corresponding candidate set of support signals induces a bit flip on a value of the candidate parity signal; wherein said method further comprises reporting the automatically identified parity signal. | 10-10-2013 |
20130305200 | COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL - A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test). | 11-14-2013 |
20130326442 | RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS - A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology. | 12-05-2013 |
20140019925 | METHOD FOR TESTING A COMPUTER PROGRAM - A method for testing a circuit specification after changing a first version of the circuit specification into a second version of the circuit specification due to a revision of the circuit specification includes receiving a first set of mutations that can be or have been inserted into the first version of the circuit specification and a second set of mutations that can be inserted into the second version of the circuit specification computer program. Changed and unchanged mutations are identified in the first set of mutations and in the second set of mutations based on a comparison between the second version of the circuit specification and against the first version of the circuit specification. Information configured to test the second version of the circuit specification is generated using at least a portion of the identified mutations classified as the changed mutations. | 01-16-2014 |
20140019926 | DESIGN SUPPORT METHOD AND DESIGN SUPPORT APPARATUS - A determining unit determines parameters indicating a relation among voltages and currents at input and output of each of a non-linear device model provided in a high frequency circuit model having a non-linear device and a circuit model of a passive element connected to the non-linear device model. A calculating unit calculates amplitude and phase of a voltage source providing a fundamental wave of an equivalent circuit model, based on an input power and an impedance matching condition preliminarily determined by a designer and parameters determined by the determining unit. In addition, the calculating unit calculates amplitude and phase of a voltage source providing a harmonic wave of the equivalent circuit model, based on a harmonic termination condition preliminarily determined by the designer and the parameters determined by the determining unit. | 01-16-2014 |
20140089873 | Automatically Identifying Resettable Flops For Digital Designs - An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics. | 03-27-2014 |
20140096097 | CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE - An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core. | 04-03-2014 |
20140101628 | FUNCTIONAL TESTING OF A PROCESSOR DESIGN - According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence. | 04-10-2014 |
20140115549 | METHOD FOR VERIFYING DIGITAL TO ANALOG CONVERTER DESIGN - A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance. | 04-24-2014 |
20140123088 | DESIGN SUPPORT PROGRAM, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT APPARATUS - The embodiment is a non-transitory computer readable storage medium storing a design support program which causes a computer to generate design data for a circuit board in which elements are placed. The program causes the computer to perform: storing, in response to an operation input, operation information in an operation storage section; storing a function of a program executed based on the operation input in a function history storage section; upon detection of an operation of a command causing the computer to execute a predetermined function for generating the design data, acquiring a selected element and storing the selected element in an element information storage section; and detecting an abnormal end of the predetermined function to output the function of the program in the function history storage section, the operation information in the operation information storage section, and the element in the element information storage section to a log file. | 05-01-2014 |
20140137057 | Test Validation Planning - A computer-implemented method, computerized apparatus, and computer program product for test validation planning. The computer-implemented method, performed by a processor, comprising: having a test validation activity to be performed to validate results of two or more tests of a test suite; and automatically determining, by a processor, a subset of the two or more tests for which to perform the test validation activity; whereby avoiding performing duplicate validation activities. Optionally, for each test of the test suite a valuation of a set of functional attributes is available, and a subset of the functional attributes is deemed as relevant functional attributes with respect to the test validation activity. In such an embodiment, said determining is based on the valuation of the relevant functional attributes. | 05-15-2014 |
20140137058 | VALIDATION OF CIRCUIT DEFINITIONS - Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion. | 05-15-2014 |
20140143745 | TECHNIQUES FOR SEGMENTING OF HARDWARE TRACE AND VERIFICATION OF INDIVIDUAL TRACE SEGMENTS - A logic verification program, method and system that segments simulation results and then processes the resulting segments separately, and optionally in parallel, reduces memory and other system requirements and improves efficiency of verification of digital logic designs. The verification process fixes up event dependency check for past-directed checkers by including additional information with each segment after an initial segment that describes at least a portion of a state of the logic design, so that resultant events in the current segment that are caused by events in the previous segment(s) can be traced back to those events. Future directed checks are fixed-up by either repeating a failed check with a concatenation of the current segment and a next segment, or by providing an overlap between segments to ensure that the expected time duration between a causative event and the resulting event are included within the same segment file. | 05-22-2014 |
20140173541 | Method and Apparatus for Verifying Debugging of Integrated Circuit Designs - Method and apparatus for verifying debugging aspects of integrated circuit (IC) designs. In one aspect, an IP provider(s) can use the same process that isolated IP defect(s) to demonstrate to the customer (whether an IC designer or an IP consumer such as a smartphone manufacturer) that the debugging was successful, and that errors in operation will not recur. In another aspect, the invention provides a facility that enables the IP provider to demonstrate to an IP consumer that a repaired IP component will work under a sufficiently broad set of circumstances, without that demonstration revealing the provider's proprietary IP to the consumer. | 06-19-2014 |
20140181768 | AUTOMATED PERFORMANCE VERIFICATION FOR INTEGRATED CIRCUIT DESIGN - A method and apparatus for automated performance verification for integrated circuit design is described herein. The method includes test preparation and automated verification stages. The test preparation stage generates design feature-specific performance tests to meet expected performance goals under certain workloads using optimization approaches and for different design configurations. The automated verification stage is implemented by integrating functional, automated modules into a verification infrastructure. These modules include register transfer level (RTL) simulation, performance evaluation and performance publish modules. The RTL simulation module schedules performance testing jobs, runs a series of performance tests on simulation logic simultaneously and generates performance counters for each functional unit. The performance evaluation module consists of three sub-functions including a functional comparison between actual results and a reference file containing the expected results, performance measurements for throughput, execution time, and latency values, and performance analysis. The performance publish module publishes performance results and analysis reports. | 06-26-2014 |
20140189623 | PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME - A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included. | 07-03-2014 |
20140250414 | METHOD FOR MEASURING ASSERTION DENSITY IN A SYSTEM OF VERIFYING INTEGRATED CIRCUIT DESIGN - An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. | 09-04-2014 |
20140282316 | SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION - A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable. | 09-18-2014 |
20140317584 | FORMAL FAULT DETECTION - A method for formal fault detection in a design model includes providing a plurality of faults which are individually activatable in the design model, and providing a plurality of properties for the design model wherein each property of the plurality of properties is valid if none of the plurality of faults is activated. The method further includes selecting a property of the plurality of properties, and determining, by a formal property checker, whether activation of one fault of the plurality of faults causes the selected property to fail. If the formal property checker finds a particular fault which, when activated, causes the selected property to fail, determining that the selected property is capable to detect the particular fault, and if the formal property checker does not find any particular fault which, when activated, causes the selected property to fail, determining that the selected property is not capable to detect any fault of the plurality of faults. | 10-23-2014 |
20140359545 | EQUIVALENCE CHECKING USING STRUCTURAL ANALYSIS ON DATA FLOW GRAPHS - A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description. | 12-04-2014 |
20150012899 | METHOD FOR DERIVING EQUIVALENT CIRCUIT MODEL OF CAPACITOR - A method for deriving an equivalent circuit model of a capacitor which makes it possible to derive, with high accuracy and with ease, an equivalent circuit model having characteristics in accordance with a direct current voltage applied to a capacitor. Characteristic values of predetermined resistive elements and capacitive elements forming an equivalent circuit model of a capacitor change in response to a DC bias voltage being applied to the capacitor, and the change is attributable to the material of a dielectric forming the capacitor. However, by multiplying the characteristic values of the resistive elements and the capacitive elements held while the DC bias voltage is not applied by a dimensionless coefficient in accordance with an application rule, the characteristic values of the resistive elements and the capacitive elements are corrected to values in accordance with the voltage of the DC bias voltage applied to the capacitor. | 01-08-2015 |
20150040086 | METHOD AND SYSTEM FOR REPRODUCING PROTOTYPING FAILURES IN EMULATION - A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype. | 02-05-2015 |
20150074624 | Enhanced Case-Splitting Based Property Checking - An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model. | 03-12-2015 |
20150074625 | VERIFICATION APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT, VERIFICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROGRAM THEREFOR - The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof. | 03-12-2015 |
20150074626 | DETERMINING METHOD, COMPUTER PRODUCT, AND DETERMINING APPARATUS - A determining method includes obtaining terminal information indicating a first object terminal that is among terminals included among partial circuits and subject to determination of whether the first object terminal is an open terminal; obtaining for each terminal, connection information and first attribute information indicating an attribute of any one among an input terminal and an output terminal; generating, by a computer, for each terminal, second attribute information indicating an attribute opposite to the attribute indicated by the first attribute information; and determining, by the computer, whether a state of the first object terminal indicated by the terminal information becomes a high-impedance state, by simulating on the basis of the connection information and the second attribute information, a state of each terminal when a value of a terminal among the terminals and indicated as an output terminal by the second attribute information, is set at a first specified value. | 03-12-2015 |
20150074627 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor. | 03-12-2015 |
20150106775 | METHOD AND SYSTEM OF CHANGE EVALUATION OF AN ELECTRONIC DESIGN FOR VERIFICATION CONFIRMATION - A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature. | 04-16-2015 |
20150121325 | SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE AGAINST ONE OR MORE VIOLATION RULES - A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation. The simulation system further comprises a reporting unit for preparing a report of the rule scores associated with the one or more violation rules and for reporting the report to a user. A method of testing a simulation of a device against one or more violation rules is described. | 04-30-2015 |
20150143308 | SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE AGAINST ONE OR MORE VIOLATION RULES - A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determine information representing the respective violation, wherein detecting the one or more violations comprises comparing a simulated parameter against a threshold. The threshold controller is arranged to determine the threshold for the respective violation rule in dependence on a temporal characteristic of the associated violation. A method of testing a simulation of a device against one or more violation rules is described. | 05-21-2015 |
20150143309 | COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR GENERATING A LAYOUT OF A CELL DEFINING A CIRCUIT COMPONENT - A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell. | 05-21-2015 |
20150143310 | P-CELL CACHING - In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present. | 05-21-2015 |
20150149974 | DIAGNOSIS DEVICE, CONTROL METHOD OF DIAGNOSIS DEVICE, AND RECORDING MEDIUM - A diagnosis device including a storage unit configured to store first circuit configuration information, a circuit unit configured to configure a first plurality of circuits based on the first circuit configuration information and a second plurality of circuits based on second circuit configuration information, and a processor configured to update the first circuit configuration information to the second circuit configuration information and configured to diagnose all circuits newly added by the second circuit configuration information of the second plurality of circuits. | 05-28-2015 |
20150302125 | METHOD AND SYSTEM OF CHANGE EVALUATION OF AN ELECTRONIC DESIGN FOR VERIFICATION CONFIRMATION - A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature. | 10-22-2015 |
20150317422 | SEQUENTIAL STRUCTURE EXTRACTION BY FUNCTIONAL SPECIFICATION - A method and apparatus for structure analysis of a circuit design is described. In one exemplary embodiment, a functional specification of a circuit design is received, where the functional specification based on a behavior layer abstraction. In addition, design codes for the circuit design is received, where the each of the design codes is based on a behavior layer abstraction. Furthermore, the design codes are searched for one or more of the design codes that satisfy the functional specification. This search is performed in the behavior layer abstraction. Each of the design codes that satisfy the functional specification is recognized. | 11-05-2015 |
20150324507 | PRINTED CIRCUIT BOARD DESIGN VERIFICATION SYSTEM, PRINTED CIRCUIT BOARD DESIGN VERIFICATION METHOD, AND RECORDING MEDIUM - [Object] A printed circuit board design verification system for reducing the entire process time required for designing of a printed circuit board. | 11-12-2015 |
20150370939 | GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in a register transfer level circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to one or more possible signal states. Determining the input sequence of signal transition representations includes determining that a subsequence of the input sequence of signal transition representations indicates at most one transition within the subsequence of the input sequence. The design tool can determine, based on the indicated component and on the determination that the subsequence indicates at most one transition, an output sequence of signal transition representations derived from the input sequence of signal transition representations. | 12-24-2015 |
20150370956 | METHOD OF IDENTIFYING A VALUE OF AN UNKNOWN CIRCUIT COMPONENT IN AN ANALOG CIRCUIT - A method for identifying a value of an unknown circuit component for an analog signal having a known output profile in which a simulation list of the analog circuit is first created including the component with the unknown value. A transfer function for the known output value is then created using a programmed processor and the transfer function is then solved by the processor for the value of the unknown component. For nonlinear circuit components, a linear model is substituted for the nonlinear components prior to creating the simulation list. | 12-24-2015 |
20150379174 | VARIATION MODELING - A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout. | 12-31-2015 |
20150379177 | COMPUTER PRODUCT FOR SUPPORTING DESIGN AND VERIFICATION OF INTEGRATED CIRCUIT - Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity. | 12-31-2015 |
20150379187 | Ranking Combinations of Mutants, Test Cases and Random Seeds in Mutation Testing - A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants. | 12-31-2015 |
20160012167 | ELIMINATION OF ILLEGAL STATES WITHIN EQUIVALENCE CHECKING | 01-14-2016 |
20160012168 | CIRCUIT SIMULATION WITH RULE CHECK FOR DEVICE | 01-14-2016 |
20160063160 | SYSTEM FOR AND METHOD OF CHECKING JOULE HEATING OF AN INTEGRATED CIRCUIT DESIGN - A method of checking joule heating of an integrated circuit design, the method includes dividing the integrated circuit design into a plurality of windows, determining a power index of each window, adjusting the specification current value associated with each of the corresponding windows, and generating a current violation report, by a processor, of the integrated circuit. Each window includes one or more circuit elements. Each circuit element is associated with a corresponding current value. Each window is associated with a corresponding specification current value. Each power index is associated with a corresponding window. An amount of adjustment of the specification current value is a function of the power index of each corresponding window. The current violation report includes one or more entries. Each entry is associated with at least a corresponding window and one or more corresponding current values which exceed the corresponding adjusted specification current value. | 03-03-2016 |
20160154902 | Selective Annotation Of Circuits For Efficient Formal Verification With Low Power Design Considerations | 06-02-2016 |
20160154921 | Template Matching for Resilience and Security Characteristics of Sub-Component Chip Designs | 06-02-2016 |
20160188776 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data. | 06-30-2016 |
20160196380 | ADJUSTING FABRICATION OF INTEGRATED COMPUTATIONAL ELEMENTS | 07-07-2016 |
20190147122 | VERIFICATION OF HARDWARE DESIGNS TO IMPLEMENT FLOATING POINT POWER FUNCTIONS | 05-16-2019 |