Entries |
Document | Title | Date |
20100281451 | Designing an ASIC Based on Execution of a Software Program on a Processing System - System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program. | 11-04-2010 |
20100287523 | DESIGN RULE MANAGEMENT METHOD, DESIGN RULE MANAGEMENT PROGRAM, RULE MANAGEMENT APPARATUS, AND RULE VERIFICATION APPARATUS - A design rule management method implemented in a rule verification apparatus for checking a violation against a design rule which specifies a part shape when there is any change in parameters in a system, the rule verification apparatus including: a processing unit for processing information; an input unit for inputting information; and a storage unit for storing a first design rule, a second design rule and relationship strength therebetween in association with one another, the method allowing the processing unit to perform steps including: acquiring the changed parameter via the input unit; and in a rule verification to determine whether or not there is any violation in the design rules that use the changed parameter, acquiring from the storage unit all the design rules having the relationship strength of a predetermined value, and performing the rule verification on all the acquired design rules. | 11-11-2010 |
20100306728 | Coexistence of Multiple Verification Component types in a Hardware Verification Framework - Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided. | 12-02-2010 |
20100313175 | VERIFICATION SYSTEMS AND METHODS - Described are verification devices and methods for controlling X propagation in a circuit design which identify a first location in a circuit at which an X value is generated, specify a second location in the circuit at which the X value is unwanted, and prove that the X value is unable to propagate from the first location to the second location over any path through the circuit between the first and second locations. | 12-09-2010 |
20100318948 | SYSTEM AND METHOD FOR ASSISTING CIRCUIT DESIGN - A system and method for assisting printed circuit board design are characterized by a circuit pre-configuration interface capable of synchronously performing circuit design and performing pre-configuration layout of electronic parts in the circuitry to thereby solve a known problem, wherein engineers spend considerable time arranging electronic parts at a late stage due to layout engineers' unfamiliarity with a circuit's characteristics. The circuit pre-configuration interface also directly adjusts and modifies electronic parts in the finalized circuitry, thereby providing a data exchange platform for the circuit design software and circuit layout software to increase the circuit layout efficiency. | 12-16-2010 |
20100318949 | COMPUTER PRODUCT, DESIGN SUPPORT APPARATUS, AND DESIGN SUPPORT METHOD - A non-transitory computer-readable recording medium stores therein a design support program that causes a computer capable of accessing a database, which stores therein respective starting point and ending point coordinates of line segments included in a wiring path of a circuit-under-test, to execute a process that includes dividing a layout area of the circuit-under-test, by a predetermined width, into a grid pattern to divide the layout area into plural mesh areas, using a predetermined coordinate within the layout area as an origin coordinate; determining whether a line segment selected from among the line segments in the database passes through a vertex of a mesh area obtained at the dividing; and outputting a determination result obtained at the determining. | 12-16-2010 |
20100318950 | ANALYZING METHOD OF SEMICONDUCTOR DEVICE, DESIGNING METHOD THEREOF, AND DESIGN SUPPORTING APPARATUS - A design supporting apparatus of a semiconductor device, includes sections to perform: setting an impurity concentration with respect to a channel direction and a depth direction to node points arranged discretely in a channel region of a model transistor based on a predetermined concentration distribution rule; calculating an electric characteristic of the model transistor by using the impurity concentration; and storing the impurity concentration as a model parameter of the model transistor in a storage unit, when the calculated electric characteristic and an electric characteristic prepared previously are coincident with each other within a predetermined range. The device characteristic calculating section calculates a surface potential to each of the node points by reducing a dimension of the impurity concentration in the depth direction, corrects the surface potential based on interaction between the node points adjacent to each other, and calculates the electric characteristic by using the corrected surface potential. | 12-16-2010 |
20100325594 | PRINTED CIRCUIT BOARD DESIGN ASSISTING METHOD, PRINTED CIRCUIT BOARD DESIGN ASSISTING DEVICE, AND STORAGE MEDIUM - A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path. | 12-23-2010 |
20100333051 | Method and System of Linking On-Chip Parasitic Coupling Capacitance Into Distributed Pre-Layout Passive Models - A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device and an on-chip spiral inductor device, interpreting data obtained from the recognizing the passive device, breaking the passive device into a plurality of sections, the plurality of sections including a terminal of a model call, extracting parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction, connecting the terminal to a pre-layout passive network by selectively low and high resistive paths set by the parameters of the passive device depending on whether crossing lines are present or not present in one of the plurality of sections, connecting the terminal to a distributed passive model, and coupling the crossing lines to the terminal via capacitors produced in an extracted netlist with the passive device having distributed coupling to a plurality of crossing lines. | 12-30-2010 |
20100333052 | Method of manufacturing semiconductor device, semiconductor inspection apparatus, and program - A reliability reference storage unit stores reference data for dividing semiconductor devices into equal to or more than three reliability ranks on the basis of the magnitude of an overlay error between a first interconnect layer and a second interconnect layer disposed over the first interconnect layer. An error storage unit stores overlay errors measured at multiple points within the surface of a semiconductor wafer. An error calculation unit calculates the overlay errors for a plurality of semiconductor chips on the basis of the coordinates of the plurality of semiconductor chips within the surface of the semiconductor wafer and the overlay errors stored in the error storage unit. A reliability information providing unit provides reliability information indicating reliability ranks to the plurality of semiconductor chips on the basis of the overlay errors for the plurality of semiconductor chips and reference data. | 12-30-2010 |
20100333053 | VERIFICATION APPARATUS, VERIFICATION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A verification apparatus includes a reference circuit-side point extraction unit that extracts a point where the input value of a signal changes due to a logic change in a reference circuit in a state before and after the logic change, based on information regarding a signal that has changed due to the logic change in the reference circuit; a circuit to be verified-side point extraction unit that extracts a point where the input value of a signal changes due to a logic change in a circuit to be verified in a state before and after the logic change, based on information regarding a signal that has changed due to the logic change in the circuit to be verified; and a verification script generation unit that generates a verification script with use of the points extracted by the reference circuit-side point extraction unit and the circuit to be verified-side point extraction unit. | 12-30-2010 |
20100333054 | CIRCUIT DESIGN ASSISTING APPARATUS - A circuit design assisting apparatus for assisting a circuit design of a semiconductor by using a noise check result corresponding to a plurality of wiring arrangements, the circuit design assisting apparatus includes a database unit that stores the wiring arrangement data, a wire specifying unit that specifies a first wire from the wiring arrangement data, a wire extracting unit that extracts a plurality of second wires respectively including a wire portion influencing noise to the specified first wire from the wiring arrangement data, and a display controlling unit that generates display information to display the specified first wire and the extracted second wire. | 12-30-2010 |
20110016440 | CHECKING AN ESD BEHAVIOR OF INTEGRATED CIRCUITS ON THE CIRCUIT LEVEL - A system and a method for testing the ESD behaviour, wherein a circuit ( | 01-20-2011 |
20110022997 | METHOD FOR CONJECTURING EFFECTIVE WIDTH AND EFFECTIVE LENGTH OF GATE - A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error. | 01-27-2011 |
20110035713 | CIRCUIT BOARD DESIGN SYSTEM AND METHOD - A method and system for designing a circuit board designs wiring of the circuit board, and determines electronic rules and physical rules of the wiring design. The method and system creates a board file by designating a file name, outputs the electronic rules into the board file, and outputs the physical rules into the board file according to a preset output format. The method and system further generates a circuit diagram according to preset initial parameters, and applies the electronic rules and the physical rules to the circuit diagram according to the board file. | 02-10-2011 |
20110041105 | INTEGRATED DMA PROCESSOR AND PCI EXPRESS SWITCH FOR A HARDWARE-BASED FUNCTIONAL VERIFICATION SYSTEM - A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers. | 02-17-2011 |
20110041106 | Integrated Circuit Modeling Method and Framework Tool - An integrated circuit modeling method | 02-17-2011 |
20110041107 | Identifying Semiconductor System Specification Violations - A method for identifying specification window violations for a system is described. The method includes generating a sample set of input parameters. The system is simulated using the sample set to generate an output set. A mathematical model is best-fit to the output set. A set of desirability functions is defined to an out-of-spec condition. The model is then searched using the desirability functions to identify a worst-case data point. The worst-case data point can then be determined as either being within specification or out of specification. | 02-17-2011 |
20110047521 | DEVELOPMENT TOOL FOR COMPARING NETLISTS - System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is generated for one of the netlists and a normalized score is generated for the other netlist. The baseline reference score and the normalized score are used to generate a similarity score that is displayed on a display monitor. Preferably, the similarity score is displayed as a percentage. | 02-24-2011 |
20110055777 | Verification of Soft Error Resilience - An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance. | 03-03-2011 |
20110055778 | Automatic Application-Rule Checker - A method of checking an integrated circuit design database includes providing the integrated circuit design stored in a storage media; providing application rules; and providing an instance abstract of instances of libraries and IP(s). Instance-level information is extracted from the integrated circuit design database. An application-rule check is performed against the instance-level information using the information provided in an abstract file. | 03-03-2011 |
20110055779 | Nonsequential Hardware Design Synthesis Verification - Methods and apparatuses for verifying a concurrent logical design and a corresponding non-sequential algorithmic description are provided. In some implementations, verification of a non-sequential algorithmic description for a device design is facilitated by monitoring a simulation of the non-sequential algorithmic description and synchronizing the timing of selected events with timing from an already completed simulation of a corresponding logical design. With various implementations, the hierarchical blocks in the logical design are monitored during the prior simulation to record selected event information. Subsequently, the recorded event information may be used to synchronize the simulation of the non-sequential algorithmic description. | 03-03-2011 |
20110055780 | METHOD FOR INTEGRATED CIRCUIT DESIGN VERIFICATION IN A VERIFICATION ENVIRONMENT - The invention relates to a method. In the method a reference model and a register transfer level model are obtained to a test bench. To a user is presented at least one wave diagram in a user interface on a display of an apparatus. A time interval associated with an input vector is determined based on a first type of user input. A random number range is associated with the time interval based on a second type of user input. The generation of an input data file is started for at least one test case for the reference model and the register transfer level model. Random numbers within the random number range are generated, the random numbers being stored within the input data file. The test cases are executed using either of the models. | 03-03-2011 |
20110061035 | VERFICATION APPARATUS AND DESIGN VERFICATION PROGRAM - In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order. | 03-10-2011 |
20110066988 | Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating - A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical. | 03-17-2011 |
20110072403 | Concurrent simulation of hardware designs with behavioral characteristics - Simulating hardware includes generating a data flow representation of the hardware, based on a hardware description language (HDL) description. The data flow representation including compatibility information that preserves behavioral and synthesizable characteristics of the HDL description. Simulating hardware further includes generating code from the data flow representation, and executing the code concurrently. | 03-24-2011 |
20110078641 | Characterization of Long Range Variability - Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design. | 03-31-2011 |
20110078642 | Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine - Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors. | 03-31-2011 |
20110078643 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD THEREOF - A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining corresponding outlines of selected component and unselected components in response to a user selecting one component; obtaining the range value; generating a reference outline according to the obtained range value and outline of the selected component; performing an intersection operation according to the reference outline and outlines of the unselected components, and determining whether one component is associated within the reference outline; marking and displaying the outlines of the corresponding unselected components when the unselected components are associated within the reference outline. | 03-31-2011 |
20110083114 | METHOD AND SYSTEM FOR RE-USING DIGITAL ASSERTIONS IN A MIXED SIGNAL DESIGN - A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process. | 04-07-2011 |
20110093824 | TECHNIQUES FOR PERFORMING CONDITIONAL SEQUENTIAL EQUIVALENCE CHECKING OF AN INTEGRATED CIRCUIT LOGIC DESIGN - A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under which equivalences of the first and second netlists are checked. The technique derives a set of candidate conditional equivalence invariants for each correlated gate in a correlated gate pair set and attempts to prove that each candidate conditional equivalence invariant in the set of candidate conditional equivalence invariants is accurate. The candidate conditional equivalence invariants that cannot be proven accurate are removed from the set of candidate conditional equivalence invariants. The candidate conditional equivalence invariants that have been proven accurate are recorded as a set of conditional equivalence invariants. Finally, the conditional sequential equivalence checking of the equivalence-checking netlist is completed using the set of conditional equivalence invariants that are recorded. | 04-21-2011 |
20110099529 | GEOMETRY BASED ELECTRICAL HOTSPOT DETECTION IN INTEGRATED CIRCUIT LAYOUTS - A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations. | 04-28-2011 |
20110107281 | TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application. | 05-05-2011 |
20110107282 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD THEREOF - A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided. | 05-05-2011 |
20110113393 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY SIDEWALL-IMAGE TRANSFER - Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions. | 05-12-2011 |
20110113394 | PWB Voltage and/or Current Calculation and Verification - Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on the voltage drop calculations and the voltage and current requirement of the various system components, the layout tool may determine if a given system component will remain within its required operating range. The layout tool may additionally be operable to verify proper spacing between traces that make up a differential signal and to verify that certain pins of integrated circuit are properly connected. | 05-12-2011 |
20110138345 | System and Method for Circuit Design - A method and system for designing an electric or electronic circuit. A method may include providing a description of a device; including at least one feature of the device in the description; adding an information pertaining to the at least one feature; configuring the description to detect a relationship between the information and the at least one feature; and generating a message conveying the relationship. The method may include generating one or more derived files. The one or more derived files may be generated or processed by a word processor. Systems based on the foregoing method are also described. | 06-09-2011 |
20110154280 | PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY - An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape. | 06-23-2011 |
20110161899 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED-SIGNAL VERIFICATION AND LOW POWER SIMULATION - Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic. | 06-30-2011 |
20110161900 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED SIGNAL VERIFICATION AND LOW POWER SIMULATION - Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic. | 06-30-2011 |
20110173582 | METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTRACTION IN A MULTI-TECHNOLOGY ENVIRONMENT - A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object. | 07-14-2011 |
20110173583 | METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF - A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit. | 07-14-2011 |
20110185325 | Navigating Analytical Tools Using Layout Software - A background process is used to install at least one system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and, responsive to the call message, current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software, based on the representation of the current layout coordinates. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Responsive to the call message, current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout, corresponding to the representation of the current coordinates from the tool control software, is displayed. | 07-28-2011 |
20110197170 | Active Net Based Approach for Circuit Characterization - In a circuit design method, a computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a limited part of the circuit design, where the limited part determined by the active nets. The computer system performs simulation of the circuit design including the netlist of a circuit design and the parasitic netlist of the limited part of the circuit design. In another method the computer system performs simulation of a circuit design including a netlist of the circuit design and a parasitic netlist of a limited part of the circuit design, where the limited part is determined by active nets of a netlist of the circuit design, and the parasitic netlist of the limited part of the circuit design is extracted from a layout of the circuit design. Other aspects are the computer system and a computer readable medium storing the computer instructions to execute the steps. | 08-11-2011 |
20110209109 | HIGH-SPEED SRAM - A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved. | 08-25-2011 |
20110225559 | LOGIC VERIFYING APPARATUS, LOGIC VERIFYING METHOD, AND MEDIUM - According to one embodiment, a logic verifying apparatus includes an input module, an extracting module, a table generator, and a verification information generator. The input module is configured to accept a first assertion and a first test pattern. The extracting module is configured to extract a definite rule assertion and a hold rule assertion by analyzing the first assertion accepted by the input module. The table generator is configured to generate a rule table indicating a relationship between the definite condition and a signal of the verification object circuit based on the definite rule assertion and hold rule assertion extracted by the extracting module. The verification information generator is configured to generate verification information used to verify a non-formulation behavior of the verification object circuit based on the rule table generated by the table generator. | 09-15-2011 |
20110239171 | Staged Scenario Generation - A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage. | 09-29-2011 |
20110239172 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 09-29-2011 |
20110265051 | Method for Substrate Noise Analysis - In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal. | 10-27-2011 |
20110271243 | Enhanced Analysis of Array-Based Netlists Via Phase Abstraction - A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output. | 11-03-2011 |
20110271244 | Enhanced Analysis of Array-Based Netlists via Reparameterization - A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition which enables optimal reductions though input reparameterization given a netlist with constraints. A post-processing mechanism next prevents input reparameterization from creating topologically inconsistent models in the presence of arrays. Additionally, this technique may be used to rectify inconsistent topologies that may arise when reparameterizing even netlists without arrays, namely false sequential dependencies across initialization constructs. Furthermore, a mechanism is provided to undo the effects of memory array based input reparameterization on verification results. | 11-03-2011 |
20110276930 | Minimizing Memory Array Representations for Enhanced Synthesis and Verification - Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses. | 11-10-2011 |
20110276931 | Eliminating, Coalescing, or Bypassing Ports in Memory Array Representations - Mechanisms are provided in a design environment for eliminating, coalescing, or bypassing ports. The design environment comprises one mechanism to eliminate unnecessary ports in arrays using disabled and disconnected pin information. The design environment may comprise another mechanism to combine and reduce the number of array ports using address comparisons. The design environment may comprise another mechanism to combine and reduce the number of array ports using disjoint enable comparisons. The design environment may comprise one mechanism to combine and reduce the number of array ports using “don't care” computations. The design environment may comprise another mechanism to reduce the number of array ports through bypassing write-to-read paths around arrays. | 11-10-2011 |
20110276932 | Array Concatenation in an Integrated Circuit Design - Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays. | 11-10-2011 |
20110283245 | AUTOMATIC LAYOUT CONVERSION FOR FINFET DEVICE - A method for generating a layout for a FinFET device is disclosed. The method includes receiving an initial layout containing an active region that has an edge extending in a first direction. The method includes designating a portion of the layout as a first region. The first region contains the active region. The method includes designating an elongate portion of the first region as a second region that extends in the first direction. The method includes designating a different elongate portion of the first region as a third region that extends in the first direction and that is adjacent to the second region in a second direction perpendicular to the first direction. The method includes enlarging the active region if the edge of the active region falls inside the third region, and shrinking the active region if the edge of the active region falls outside the third region. | 11-17-2011 |
20110283246 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data - An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model. | 11-17-2011 |
20110289463 | ELECTRICAL DESIGN SPACE EXPLORATION - A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach. | 11-24-2011 |
20110296358 | Computing Resistance Sensitivities with Respect to Geometric Parameters of Conductors with Arbitrary Shapes - A computer system selects a shape included in an integrated circuit's layout file, and then selects a first contact and a second contact located on the shape. Next, the computer system computes a nominal resistance between the first contact and the second contact based upon a nominal boundary of the shape, and then computes an adjoint system vector based upon a perturbed boundary of the shape. Using the adjoint system vector, the computer system computes a resistance sensitivity between the first contact and the second contact. In turn, the computer system simulates the integrated circuit using the computed nominal resistance and the computed resistance sensitivity. | 12-01-2011 |
20110296359 | METHOD AND COMPUTER-READABLE MEDIUM OF OPTICAL PROXIMITY CORRECTION - A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification. | 12-01-2011 |
20110296360 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout. | 12-01-2011 |
20110302541 | Methods and Systems for Evaluating Checker Quality of a Verification Environment - Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve. | 12-08-2011 |
20110320992 | BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit. | 12-29-2011 |
20110320993 | Efficient Continuous Grading Flow for Test Coverage Analysis - A system for performing efficient continuous grading flow for test coverage analysis. The system provides for continuous test coverage grading. The continuous grading flow analyzes individual tests upon completion without requiring an entire set of tests to finish. As a result, the grading process at the end of the regression run is no longer necessary, disk space and memory requirements are dramatically reduced, and partial results are produced as the grading of individual tests complete, allowing engineers to track progress and make real-time decisions based on the intermediate results. The resource requirements of our continuous flow scale linearly with the number of tests rather than exponentially as with traditional approaches. | 12-29-2011 |
20120005640 | METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT TWO LEVELS - A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level, respectively. A stimulus transaction is generated at a first testbench at the first level. The stimulus transaction is transmitted from the first testbench to a second testbench at the second level. The stimulus transaction is transformed into a first response transaction, using the first model, at the first level. The stimulus transaction received at the second testbench is transformed into a second response transaction, using the second model, at the second level. The first and second response transactions are stored in first and second response queues, respectively. Functionality of the SoC at the first and second levels is verified based on a comparison at the first testbench between head entries of the first and second response queues. | 01-05-2012 |
20120017187 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
20120042293 | SYNCHRONIZING TAP CONTROLLER AFTER POWER IS RESTORED - A system includes multiple TAP controllers that can be independently powered up and down. When a first TAP controller is powered up from a powered-down state while a second TAP controller is already in a powered-up state, the first TAP controller is reset causing the first TAP controller to enter a reset state in response to the power-up of a module on which the first TAP controller is disposed. The first TAP controller enters an idle state and its control signal is gated to hold the first TAP controller in the idle state until the second TAP controller enters the idle state. Subsequently, the first TAP controller is released such that the control signal supplied to the first and second TAP controllers are equal, thereby synchronizing the first TAP controller and the second TAP controller. | 02-16-2012 |
20120079439 | SUSPECT LOGICAL REGION SYNTHESIS FROM DEVICE DESIGN AND TEST INFORMATION - Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region. | 03-29-2012 |
20120079440 | SUSPECT LOGICAL REGION SYNTHESIS AND SIMULATION USING DEVICE DESIGN AND TEST INFORMATION - Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region. | 03-29-2012 |
20120089957 | CIRCUIT DESIGN ASSISTING DEVICE, METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A circuit design assisting device for assisting design of a circuit, the circuit design assisting device includes a storage unit that stores circuit connection data of the circuit, a selecting unit that chooses a storage element that holds a signal inputted from an input terminal based on a clock signal and outputs the signal from an output terminal from the circuit connection data, a tracing unit that traces a logical connection from the input terminal of the chosen storage element in an opposite direction against propagation of the signal based on the circuit connection data, and a control unit that suspends the tracing unit to trace the logical connection when the tracing unit reaches to an element having two or more input terminals. | 04-12-2012 |
20120096419 | METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE - A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit. | 04-19-2012 |
20120102443 | N/P CONFIGURABLE LDMOS SUBCIRCUIT MACRO MODEL - A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor. | 04-26-2012 |
20120110527 | CONNECTION VERIFICATION METHOD, RECORDING MEDIUM THEREOF, AND CONNECTION VERIFICATION APPARATUS - A connection verification method is disclosed. A computer verifies a connection between a first node and a second node by starting from the first node in a designed integrated circuit, based on connection information stored in a storage part. The computer detects whether a module connected to the second node is a predetermined module predetermined module having a logic condition therein, based on connection relationship logic information stored in the storage part. The computer conducts a connection verification starting the module to verify a connection between the module and a third node when the module is the predetermined module. | 05-03-2012 |
20120110528 | METHOD OF PREDICTING ELECTRONIC CIRCUIT FLOATING GATES - Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level of predecessor circuit node states earlier in the circuit show up more than once with different values, thus indicating by logical conflict that a particular floating suspect gate does not float. It then repeats this back-trace analysis for the next previous level of predecessor circuit portions, further seeking logical conflicts within the expanding logic tree. This is continued until either no predecessor circuit portion that can cause the suspect gate to float is found, or until a portion that does cause the suspect gate to float is found, in which case the suspect gate is identified as a probable floating gate. | 05-03-2012 |
20120124533 | SEMICONDUCTOR STRUCTURE AND METHOD OF DESIGNING SEMICONDUCTOR STRUCTURE TO AVOID HIGH VOLTAGE INITIATED LATCH-UP IN LOW VOLTAGE SECTORS - A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit. | 05-17-2012 |
20120159409 | METHOD AND APPARATUS FOR PERFORMING TEMPLATE-BASED CLASSIFICATION OF A CIRCUIT DESIGN - A method and apparatus for performing template-based classification of a circuit design are disclosed. A template file is read that defines a plurality of channel-connected-region (CCR) templates. A graph is formatted for each of the CCR templates. A plurality of CCRs are identified based on a partitioned netlist file that defines a given circuit design. A graph is generated for each of the identified CCRs. A matching CCR template graph is identified for each generated CCR graph. The template file may further defines super-CCR templates, and a graph may be formatted for each of the super-CCR templates. All possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph may be determined in an interative manner, for each formatted super-CCR template graph. A determination may be made as to which of the candidate combinations actually match the formatted super-CCR template graph. | 06-21-2012 |
20120174047 | Continuously Referencing Signals Over Multiple Layers in Laminate Packages - A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package. | 07-05-2012 |
20120198399 | SYSTEM, METHOD AND COMPUTER PROGRAM FOR DETERMINING FIXED VALUE, FIXED TIME, AND STIMULUS HARDWARE DIAGNOSIS - The present invention provides a system, method and computer program for determining constraint errors in hardware design debugging. The invention may be included as part of a complete verification solution. The method involves applying a diagnostic technique such that under-constrained problems are identified by adding a model-free error suspect or error candidate on the primary input signals (or other signals where constraints or stimuli are usually added). The present invention also provides a system, method and computer program that enables hardware design correction, consisting of the use of generating correction waveforms for identifying one or more corrections at the gate level and/or logic level of the hardware design. A number of different diagnostic techniques can be used in this way for example, include simulation-based techniques, BDD-based techniques, SAT-based techniques and path tracing. The method described can be implemented as part of a debugging computer system or computer program, including an automated debugger. The method described herein can also be implemented into a design correction engine that is operable to generate correction waveforms for each of the under constrained signals to provide to a user or automated system or computer program deeper insight for under-constrained problems. Furthermore, under-constrained signals may be combined with one or more correction waveforms to provide a software fix or external fix to a fabricated chip by providing a value sequence that is operable to avoid an error or bug in the fabricated chip. | 08-02-2012 |
20120198400 | PROOF BASED BOUNDED MODEL CHECKING - An UNSAT core may be reused during iterations of a bounded model checking process. When increasing the bound, signals corresponding to signals within the UNSAT core may be used to represent the functionality of the model during cycles between the original bound and the increased bound. In case, consecutive unsatisfiability is determined in respect to different bounds, the same UNSAT core may be reused instead of computing a new UNSAT core. | 08-02-2012 |
20120227021 | METHOD FOR SELECTING A TEST CASE AND EXPANDING COVERAGE IN A SEMICONDUCTOR DESIGN VERIFICATION ENVIRONMENT - This invention describes a high level Application Programming interface to interface with block level verification environments. By using simple tasks such as memory_write, memory_read, reg_write and reg_read, the interface becomes user-friendly, and designers as well as verification engineers may be able to write complex test cases using the present invention. This invention also processes generic data objects, generation methods, and comparison methods which are not coupled to the design under verification. Higher level API and objects need not be re-designed from one application to another when using the present invention. | 09-06-2012 |
20120233578 | PERFORMANCE COUNTERS FOR INTEGRATED CIRCUITS - Systems, methods, and other embodiments associated with performance counters are described. In one embodiment, a method includes generating a first register transfer level (RTL) description of an integrated circuit that includes a performance counter. The integrated circuit is emulated in hardware and statistical data is collected with the performance counter. The performance counter is then removed from the integrated circuit. | 09-13-2012 |
20120266118 | Accelerating Coverage Convergence Using Symbolic Properties - In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence. | 10-18-2012 |
20120290993 | LOGIC VERIFICATION MODULE APPARATUS TO SERVE AS A HYPER PROTOTYPE FOR DEBUGGING AN ELECTRONIC DESIGN THAT EXCEEDS THE CAPACITY OF A SINGLE FPGA - A apparatus and a system and method to operate the above provide a reconfigurable platform for emulating and debugging a user design which exceeds the capacity of a single field programmable logic device (FPGA). The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with logic value tunneling circuits in an emulation using a platform including a number of field programmable devices. A verification module apparatus provides a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA. A verification module provides access to a plurality of attached FPGAs by means of Logic Value Tunneling Transmitters and Receivers which deliver many signals over few pins. | 11-15-2012 |
20120311513 | METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION OF AN ELECTRONIC DESIGN - Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design. | 12-06-2012 |
20120324409 | ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION - The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration. | 12-20-2012 |
20130007679 | RECONFIGURABLE LOGIC BLOCK - A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors. | 01-03-2013 |
20130014066 | METHOD AND SYSTEM FOR TEST VECTOR GENERATION - The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips. | 01-10-2013 |
20130019216 | INTEGRATION OF DATA MINING AND STATIC ANALYSIS FOR HARDWARE DESIGN VERIFICATION - A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design. | 01-17-2013 |
20130019217 | Digital Circuit Verification Monitor - A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model. | 01-17-2013 |
20130019218 | HIGH-SPEED SRAM - A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved. | 01-17-2013 |
20130031520 | FUNCTIONAL VERIFICATION SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND FUNCTIONAL VERIFICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A functional verification system for a semiconductor integrated circuit according to an embodiment includes: a stimulus generating section; a result determining section configured to compare an expected value expected to be obtained when the stimulus is input to a logic circuit to be verified and a predetermined operation is thereby performed, and an output value actually obtained as a result of a predetermined operation being performed, to determine whether or not the output value and the expected value correspond to each other; a state dumping section; and a state loading section configured to load the logic circuit state information stored in the storing device into the logic circuit to be verified only if the result determining section determines that the output value and the expected value do not correspond to each other. | 01-31-2013 |
20130036391 | Abstraction for Arrays in Integrated Circuit Models - The illustrative embodiments provide a mechanism for abstraction for arrays in integrated circuit designs. The mechanism constructs abstract models directly from an analysis of the system. The abstract models are both sound and complete for safety properties: a safety property holds in the abstract model if and only if the property holds in the original model. The mechanism of the illustrative embodiments eliminates the need for iterative abstraction refinement. The mechanism of the illustrative embodiments can find small models that verify a system in some cases where other approaches are unable to find a small model. The approach constructs an abstract design from the original design. The abstracted design may have smaller arrays than the original design. The mechanism checks the correctness of the abstracted design by model checking. | 02-07-2013 |
20130047129 | Staged Scenario Generation - A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage. | 02-21-2013 |
20130055178 | THERMAL COUPLING DETERMINATION AND REPRESENTATION - Thermal coupling effects are represented as current into a thermal node of an initial design structure. The current is determined using a thermal coupling coefficient, and thermal resistance and thermal capacitance of a self-heating network of the initial design structure. By using another design structure with devices substantially identical to those of the initial design structure at known locations, operating a device as a heater while operating another device as a heat sensor, and measuring thermal response of the heater and the heat sensor, a thermal coupling coefficient may be determined. | 02-28-2013 |
20130055179 | COMPUTING VALIDATION COVERAGE OF INTEGRATED CIRCUIT MODEL - Embodiments of the present invention provide a method of computing validation coverage of an integrated circuit model, comprising: obtaining a logical structure of a integrated circuit model under validation; searching and recording signal paths in the integrated circuit model under validation based on the logical structure; and computing coverage of validation with respect to the signal paths. According to the technical solution as provided in the embodiments of the present invention, a signal path-based validation coverage may be obtained, thereby providing data regarding validation completeness more accurately. | 02-28-2013 |
20130055180 | COMPUTER PRODUCT, CORRECTING APPARATUS, AND CORRECTING METHOD - A computer-readable medium stores therein a correcting program that causes a computer to execute a process. The process includes decomposing a correction subject assertion, based on a logical structure of the correction subject assertion; detecting by simulation of a circuit-under-test and from among properties obtained by decomposing the correction subject assertion, a property that has failed; concatenating to the detected property and by logical OR, a failure source; and outputting the concatenated property. | 02-28-2013 |
20130055181 | LOGIC CIRCUIT EMULATOR AND CONTROL METHOD THEREFOR - A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle. | 02-28-2013 |
20130074019 | METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT TWO LEVELS - A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level, respectively. A stimulus transaction is generated at a first testbench at the first level. The stimulus transaction is transmitted from the first testbench to a second testbench at the second level. The stimulus transaction is transformed into a first response transaction, using the first model, at the first level. The stimulus transaction received at the second testbench is transformed into a second response transaction, using the second model, at the second level. Functionality of the SoC at the first and second levels is verified based on the first and second response transactions. | 03-21-2013 |
20130086538 | Design Verification System and Method Using Constrained Random Test Parameter Selection - A software program for verifying a system design having at least one integrated circuit chip. The software program, when executed by a processor, result in obtaining a random value for a variable; selecting an unused value for the variable based upon the random value, the variable not having been assigned the unused value during one or more prior verification tests; and creating a new verification test for the system using the unused value for the variable. In this way, the new verification test is created in which variables falling within a random class are more efficiently used. | 04-04-2013 |
20130086539 | METHOD FOR CIRCUIT SIMULATION - A circuit simulation method for checking a circuit error is disclosed. The method may include generating a netlist with respect to a designed circuit, simulating an operation of the designed circuit using the generated netlist, and checking an error of the designed circuit using the generated netlist and using a waveform generated when performing the simulation. | 04-04-2013 |
20130117721 | METHOD AND SYSTEM FOR VERIFICATION OF ELECTRICAL CIRCUIT DESIGNS AT PROCESS, VOLTAGE, AND TEMPERATURE CORNERS - A method for finding the process, voltage, temperature, parasitics, and power settings (PVTPP) corner at which an electrical circuit design has the worst-case optimum simulated output performance. The method uses a global optimization process in a series of iterations that aim to uncover the PVTPP corner at which the ECD has the worst-case output value. By using the present method, a designer does not have to simulate the ECD at each and every PVTPP corner, which can same considerable time or compute effort. Examples using Model-Building Optimization are provided. | 05-09-2013 |
20130132917 | Pattern Matching Hints - Aspects of the invention relate to techniques for generating and applying pattern matching hints. Pattern matching hints are determined for and stored with reference patterns. Once layout patterns that match a reference pattern are identified in a layout design through a pattern matching process, the corresponding pattern matching hints may be associated with the identified layout patterns. The association operation may comprise adjusting the identified layout patterns based on the corresponding pattern matching hints. | 05-23-2013 |
20130174108 | AUTOMATED STIMULUS STEERING DURING SIMULATION OF AN INTEGRATED CIRCUIT DESIGN - A method is contemplated in which the stimulus to an IC design simulation may be automatically manipulated or steered so that the test environment is altered during subsequent simulations of the IC design based upon the simulation results and/or configuration settings of previous simulations of the IC design. More particularly, a stimulation steering tool may analyze the simulation results and/or the test environment, and manipulate the test environment, which may include the test generator output, and the test bench model, for subsequent simulations. | 07-04-2013 |
20130179850 | Verification module apparatus to serve as a prototype for functionally debugging an electronic design that exceeds the capacity of a single FPGA - A plurality of FPGAs and off-chip storage devices provide a verification module for functionally debugging electronic circuit designs. Signal value compression circuits embedded in each FPGA conserve the limited number of pins available on each FPGA. Transmitting addresses to signal values previously stored in off-chip storage further reduce the bottlenecks in analyzing logic functionality distributed across multiple FPGAs. | 07-11-2013 |
20130227504 | SYSTEM AND METHOD FOR DESIGN, PROCUREMENT AND MANUFACTURING COLLABORATION - A method for designing an electronic component includes receiving a device criteria (e.g., a parametric value, procurement value, etc.) from a designer, querying a database for devices corresponding to the device criteria, querying the database for procurement data and/or engineering data associated with the corresponding devices, presenting the devices to the designer based on the procurement data, and receiving input from the designer identifying one of the presented devices as a selected device. In a particular method, the returned devices are sorted based on one or more procurement values (e.g., manufacturer, price, availability, manufacturer status, etc.), and presented to the designer in a ranked list. Objects representative of the selected devices are then entered into a design file, and the objects are associated with the device's engineering and/or procurement data. In a particular embodiment, the objects are associated with the engineering data by embedding the engineering data in the file object. Optionally, data can be associated with the objects via links to the database. Types of engineering data that can be associated with design file objects include, but are not limited to, device footprint data, device pinout data, device physical dimension data, parametric data, and packaging data. Additionally, connection data and annotation data can be entered into the design file objects by the designer. | 08-29-2013 |
20130232459 | ATPG AND COMPRESSION BY USING MAJORITY GATES - A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system. | 09-05-2013 |
20130246986 | METHOD OF CIRCUIT DESIGN YIELD ANALYSIS - A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value. | 09-19-2013 |
20130246987 | Coexistence Of Multiple Verification Component Types In A Hardware Verification Framework - Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided. | 09-19-2013 |
20130263071 | APPARATUS AND METHOD TO COLLECT AND CONDENSE DESIGN VIOLATIONS FROM OUTPUT DATA FILES - A method includes searching a plurality of lines of a log file for a violation of a defined condition; creating a database of all discovered violations; converting the database of all discovered to a list of output violations grouped by master; and producing a condensed summary of error messages, the producing including: searching for a selected error message; extracting a single instance or error message and load into a master log file; searching for all other examples at all levels of a hierarchical output of the list; writing a count of instances of the violation messages to the master log file; and presenting a single instance of the violations, and the count of that violation. | 10-03-2013 |
20130275931 | PLANNING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION - Methods, systems, and computer program products may provide planning for hardware-accelerated functional verification in data processing systems. A method may include receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors. The method may additionally include receiving, by the computer system, a description of the circuit design having a plurality of gates, and representing, by the computer system, each gate, each stage of the functional verification, and each logical processor as a separate object based on the received description of the architecture and the circuit design. The method may further include representing, by the computer system, relationships between gates as pairwise edges, and defining, by the computer system, a goal state that requires each gate to be scheduled for execution by a logical processor during a stage of the functional verification. | 10-17-2013 |
20130290919 | SELECTIVE EXECUTION FOR PARTITIONED PARALLEL SIMULATIONS - Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design. | 10-31-2013 |
20130298093 | Method of Predicting Contention Between Electronic Circuit Drivers - Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions that drive the digital driver's state. The previous level of predecessor circuit node states earlier in the circuit are checked to see if they simultaneously create pull up paths to power nets and pull down paths to ground nets, thus logically determining if a contention configuration is possible. This back-trace analysis is then repeated for the next previous level of predecessor circuit portions, further seeking logical contention issues within the expanding logic tree. This is continued until either no predecessor circuit portion that causes contention is found, or until a portion that does cause logical contention is found, in which case the contention digital drivers are reported. | 11-07-2013 |
20130318486 | METHOD AND SYSTEM FOR GENERATING VERIFICATION ENVIRONMENTS - A method and system for a verification of a DUT is provided. The method and system is configured to generate a verification environment using a rules based metalanguage. The rules are converted into components in the verification environment. The method and system is configured to, for example, generating constraints in transactions and coverpoints in the coverage model; coupling coverage to requirements by ruleid instead of coverage; implement automatic generation, implement checking and coverage of errored transactions; and integrate algorithmic stimulus generation along with constrained random stimulus. | 11-28-2013 |
20130318487 | Programmable Circuit Characteristics Analysis - Techniques for analysis of an electrical circuit design are described, which techniques employ two phases: an initialization phase, and a check phase. During the initialization phase, a circuit design is examined to determine the predicted operating characteristics at various nodes within the design. If the design is hierarchically arranged, then the design is analyzed in a way that preserves its hierarchy. During the check phase, various implementations of the invention will check the determined operating characteristic values to see if they indicate that one or more design rules have been violated. A user may specify or “program” aspects of the analysis, both for the initialization phase and the check phase. | 11-28-2013 |
20140007028 | DISCRETE DEVICE MODELING | 01-02-2014 |
20140013290 | Input Space Reduction for Verification Test Set Generation - Various implementations of the invention provide for the determination of a test set that satisfies a coverage model, where portions of the search space need not be searched in order to generate the test set. With various implementations of the invention, a search space defined by a set of inputs for an electronic design and a coverage model is identified. The search space is then fractured into subspaces. Subsequently, the subspaces are solved to determine if they include at least one input sequence that satisfies the coverage constraints defined in the coverage model. The subspaces found to include at least one input sequence that satisfies these coverage constraints, are then searched for unique input sequences in order to generate a test set. Subspaces found not to include at least one input sequence that satisfies the coverage constraints may be excluded from the overall search space. | 01-09-2014 |
20140019924 | BIOMETRIC MARKERS IN A DEBUGGING ENVIRONMENT - This application discloses a debug tool to prompting display of at least a portion of a simulated output for a circuit design in a debug window, identifying a marker corresponding to a value in the simulated output has been specified for the debug environment, and prompting accentuation of one or more occurrences of the value in the debug window relative to other values in the simulated output based, at least in part, on the marker specified for the debug environment. | 01-16-2014 |
20140040840 | CONFLICT DETECTION WITH FUNCTION MODELS - Systems and methods for detecting design conflicts of a product or process are disclosed. A method for detecting design conflicts includes processing a function model of a product or process to identify a plurality of descriptions of functions to be performed by the product or process. The method includes detecting in the plurality of descriptions a first description and a second description in which the first description includes a first design component name that matches a second design component name of the second description, a first descriptive noun that matches a second descriptive noun of the second description, and a first active verb that does not match a second active verb of the second description. The method further includes flagging a relationship between the first description and the second description as a first conflict type and displaying, on a display device, information regarding the first conflict type. | 02-06-2014 |
20140047401 | RECONFIGURABLE LOGIC BLOCK - A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors. | 02-13-2014 |
20140053121 | ACCELERATOR FOR A READ-CHANNEL DESIGN AND SIMULATION TOOL - A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein. | 02-20-2014 |
20140068532 | INTEGRATED CIRCUIT CHARACTERIZATION BASED ON MEASURED AND STATIC APPARENT RESISTANCES - First and second apparent resistance measures are determined for an integrated circuit and utilized to characterize the integrated circuit. The first apparent resistance measure is determined for the integrated circuit based on a first voltage drop and a first current that are measured using test equipment. The second apparent resistance measure is determined for the integrated circuit based on a second voltage drop and a second current that are obtained using static analysis of a corresponding integrated circuit design. The integrated circuit is characterized based on a comparison of the first and second apparent resistance measures. For example, characterizing the integrated circuit may comprise validating the static analysis of the integrated circuit design based on the comparison of the first and second apparent resistance measures, or determining a quality measure of the integrated circuit based on the comparison of the first and second apparent resistance measures. | 03-06-2014 |
20140075401 | BIT SLICE ELEMENTS UTILIZING THROUGH DEVICE ROUTING - A method for the identification and implementation of a logic function includes determining logic gates connected to a control signal that is common among the logic gates of the identified logic function. Standard cells may be created and characterized in order to implement the identified logic function. Creating the standard cell includes aligning respective portions of the logic devices included in the logic gates that are coupled to the control signal. In addition, creating the standard cell may also include routing the control signal using a single layer conductive material uni-directionally to interconnect the logic devices. | 03-13-2014 |
20140096096 | ANALOG CIRCUIT SIMULATOR AND ANALOG CIRCUIT VERIFICATION METHOD - An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node. | 04-03-2014 |
20140101627 | DESIGN ASSIST APPARATUS, METHOD FOR ASSISTING DESIGN, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR ASSISTING DESIGN - Multiple signal lines in a circuit net the vertex of which is a maximum observation point having a maximum diagnosis difficulty index among a plurality of diagnosis difficulty indexes of all the observation points that are used for observing signal lines in the circuit, each of the plurality of diagnosis difficulty indexes of the observation points representing the difficulty in fault diagnosis at the corresponding observation point are selected as first insersion candidates. A second insertion candidate onto which the test point is to be inserted is selected from the first insertion candidates, considering effects of inserting the test point onto the respective first insertion candidates. Thereby, insertion of a test point reduces dispersion of the diagnosis difficulty indexes of all the observation points. | 04-10-2014 |
20140115548 | METHOD AND SYSTEM FOR INVARIANT-GUIDED ABSTRACTION - A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions. | 04-24-2014 |
20140123087 | COEXISTENCE OF MULTIPLE VERIFICATION COMPONENT TYPES IN A HARDWARE VERIFICATION FRAMEWORK - Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided. | 05-01-2014 |
20140137056 | Packet Switch Based Logic Replication - A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronously with the plurality of clock domains with the delay period. | 05-15-2014 |
20140157216 | MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS - A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model. | 06-05-2014 |
20140157217 | SEQUENTIAL NON-DETERMINISTIC DETECTION IN HARDWARE DESIGN - The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker. | 06-05-2014 |
20140173539 | Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs - Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating the provider's efforts to debug the IP. | 06-19-2014 |
20140173540 | CIRCUIT DESIGN SUPPORT METHOD, CIRCUIT DESIGN SUPPORT APPARATUS, AND COMPUTER PRODUCT - A circuit design support method that is executed by a computer, includes calculating a first performance value of a circuit under design before a layout process, by inputting into a first function model that represents a performance value of the circuit under design before the layout process, the values of parameters among parameters of a second parameter group and corresponding to parameters of a first parameter group; acquiring a second performance value that is of the circuit under design after the layout process and obtained by simulating operation of the circuit under design after the layout process, using the values of the parameters of the second parameter group; and generating based on the calculated first performance value, the acquired second performance value, and the second parameter group, a second function model that represents a difference in the performance value of the circuit under design before and after the layout process. | 06-19-2014 |
20140181767 | METHOD, APPARATUS, AND SYSTEM FOR EFFICIENT PRE-SILICON DEBUG - Described are method, apparatus, and system for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit; recognizing method calls associated with the architectural verification environment; and generating a list of recognized method calls, the list for being loaded for a debug program to debug the HDL architecture of the integrated circuit. | 06-26-2014 |
20140208279 | SYSTEM AND METHOD OF TESTING THROUGH-SILICON VIAS OF A SEMICONDUCTOR DIE - A method includes contacting a first group of through-silicon vias (TSVs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The method also includes determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result. | 07-24-2014 |
20140215418 | Digital Circuit Verification Monitor - A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model. | 07-31-2014 |
20140237438 | INTEGRATED CIRCUIT PAD MODELING - A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model. The method further includes connecting a second inductor, a second resistor, and a second set of parallel-resistor-inductor elements in series between the second node and a third node in the model. The first node corresponds to a first signal port of the bond pad. The second node corresponds to a second signal port of the bond pad. | 08-21-2014 |
20140237439 | METHOD, SYSTEM AND COMPUTER PROGRAM FOR HARDWARE DESIGN DEBUGGING - A plurality of diagnosis methods are provided for enabling hardware debugging, A first diagnosis method enables hardware debugging by means of time abstraction. A second-diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide. | 08-21-2014 |
20140282312 | HARDWARE SIMULATION CONTROLLER, SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION - Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel. | 09-18-2014 |
20140282313 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR APPLYING A CALLBACK FUNCTION TO DATA VALUES - A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified. Additionally, the callback function is recursively applied to the plurality of data values in order to determine a result. Further, the result is returned. | 09-18-2014 |
20140282314 | INTELLIGENT METAMODEL INTEGRATED VERILOG-AMS FOR FAST AND ACCURATE ANALOG BLOCK DESIGN EXPLORATION - A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS. | 09-18-2014 |
20140282315 | GRAPHICAL VIEW AND DEBUG FOR COVERAGE-POINT NEGATIVE HINT - The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom. | 09-18-2014 |
20140298279 | CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, AND CIRCUIT DESIGN SUPPORT APPARATUS - A circuit design support method includes obtaining shared circuit information indicating various types of shared circuits each executing at least any one of various types of logical computations and causing plural signal lines to share an observation point at which a signal value is observable; determining for each of the signal lines to be observed in a circuit under-design, a value based on controllability representing ease of control to set a value of the signal line to be a specific value; selecting based on the obtained shared circuit information, any one shared circuit among the various types of shared circuits; and generating correlation information that correlates each input terminal of the selected shared circuit with a signal line among the signal lines to be observed and whose value determined therefor is equal to a non-controlling value of a logical computation executed for an input signal input into the input terminal. | 10-02-2014 |
20140304668 | VIA DESIGN SYSTEM - A via design system includes a processor to execute operations of displaying a via design interface. The via design interface includes a data input area and a result display area. The data input area is for inputting a variety of data for designing a via. An actual impedance Zvia and an ideal impedance Zc are computed according to the input data and preset equations, and an impedance comparison graph according to the actual impedance Zvia and the ideal impedance Zc, is drawn. The impedance comparison graph is output to the result display area. | 10-09-2014 |
20140304669 | VERIFICATION ITEM EXTRACTION APPARATUS AND METHOD - A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a verification subject circuit based on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined based on the connection relationships being derived. Related I/Fs, which are related to inputs to the logics and are interfaces to an outside of the verification subject circuit, are extracted based on the connection information. Second priority for verifying the related I/Fs is determined based on the first priority. | 10-09-2014 |
20140310667 | CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, AND CIRCUIT DESIGN SUPPORT APPARATUS - A circuit-design support method of a computer includes obtaining circuit information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining control circuit information concerning a control circuit that has a first flip-flop for scanning and controls the value of a given signal line by a value set by the first flip-flop; selecting based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating based on the control circuit information, connection information indicating serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop. | 10-16-2014 |
20140372959 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 12-18-2014 |
20150026652 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CORRELATING TRANSACTIONS WITHIN A SIMULATION OF A HARDWARE PLATFORM FOR POST-SIMULATION DEBUGGING - A system, method, and computer program product for correlating transaction within a simulation of a hardware platform for post-simulation debugging is disclosed. The method includes the steps of initializing state information associated with a hardware simulation for a register-transfer level model representing a digital circuit design, executing the hardware simulation to generate a simulation output, generating one or more transaction objects based on the signals in the simulation output, and correlating a first transaction object of the one or more transaction objects with a second transaction object of the one or more transaction objects based on a set of rules and a state model. | 01-22-2015 |
20150067621 | Logic-Driven Layout Pattern Analysis - A user or other source may specify one or more components in logical design data, such as schematic netlist design data. Based upon the provided logical component, portions of the physical design data that correspond to the logical component are selected. The selected physical design data corresponding to the specified logical component is then compared with a defined geometric element pattern, to determine if the corresponding physical design data matches the defined pattern. The results of the match analysis can be reported to a user as visual images, new design data, or both. Alternately or additionally, the selected physical design data may be modified based upon the results of the match analysis. | 03-05-2015 |
20150067622 | DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION - A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage. | 03-05-2015 |
20150082262 | DYNAMICALLY GENERATING JOG PATCHES FOR JOG VIOLATIONS - Systems, methods, and other embodiments associated with dynamically generating jog patches are described. In one embodiment, a method includes determining a virtual edge within metal of a design at a jog rule violation. The design is a design of an integrated circuit and the virtual edge is an edge of a rectangle associated with one or more edges of the jog rule violation. The example method may also include dynamically generating a jog patch by expanding the metal from the virtual edge. | 03-19-2015 |
20150082263 | MERIT-BASED CHARACTERIZATION OF ASSERTIONS IN HARDWARE DESIGN VERIFICATION - A system is configured to generate assertions for verification of an integrated circuit hardware design expressed at a register transfer level (RTL) for variables of interest, each including an antecedent and a consequent. A relative importance score for the variables is determined by characterizing respective variables by a level of importance with respect to a target variable of the consequent. The relative importance scores may be combined to form a relative importance score of the assertion. A relative complexity score for the variable is determined by characterizing the variable by a level of understandability of the variable with respect to the target variable. The relative complexity scores are combined to form a relative complexity score of the assertion. The relative importance and complexity scores are combined to generate a rank score, which is used in ranking the assertion with respect to the RTL design for which the assertion was generated. | 03-19-2015 |
20150089463 | METHOD OF FAILURE ANALYSIS - In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores. | 03-26-2015 |
20150095862 | VISUALIZATION CONSTRAINTS FOR CIRCUIT DESIGNS - A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform. | 04-02-2015 |
20150100932 | MANIPULATION OF TRACES FOR DEBUGGING A CIRCUIT DESIGN - A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging. | 04-09-2015 |
20150100933 | MANIPULATION OF TRACES FOR DEBUGGING BEHAVIORS OF A CIRCUIT DESIGN - A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging. | 04-09-2015 |
20150135149 | MONITORING COVERAGE FOR STATIC MODELLING OF AN ELECTRONIC DEVICE - A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a solver, that identifies whether the mathematical relationships of the static model can be reconciled, given a set of user-defined constraints that indicate a desired configuration, or range of configurations, of the electronic device. After a solution for a particular set of user-defined constraints has been identified, a constraints adjustment module can identify, based on coverage information generated by the solver, if other sets of user-defined constraints were implicitly solved by the solver. If such other sets were implicitly solved, the adjustments module can mark the sets as solved, such that they will omitted from constraints used for subsequent solutions of the solver. | 05-14-2015 |
20150135150 | FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES - A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design. | 05-14-2015 |
20150149973 | THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN - The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected. | 05-28-2015 |
20150294054 | Incremental Functional Verification of a Circuit Design - A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module. | 10-15-2015 |
20150310154 | METHOD AND APPARATUS FOR TESTING - A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result. | 10-29-2015 |
20150317421 | USING TRACES OF ORIGINAL MODEL TO VERIFY A MODIFIED MODEL - Method, apparatus and product for using traces of an original model to verify a modified model. The method comprising obtaining a trace exemplifying a checker failing in a model; obtaining a modified model, wherein the modified model is a modified version of the model which was modified in an attempt to resolve the checker failing in the model; re-simulating the trace in the modified model to generate a second trace, wherein said re-simulating is performed by a processor; comparing the trace and the second trace to identify a common prefix, wherein the common prefix ends immediately before a cycle in which a state according to the trace is different than a state according to the second trace; and guiding verification of the modified model using values derived from the common prefix. | 11-05-2015 |
20150339432 | VIRTUAL CELL MODEL GEOMETRY COMPRESSION - Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions. | 11-26-2015 |
20150339433 | VIRTUAL CELL MODEL USAGE - Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created. | 11-26-2015 |
20150347639 | SEQUENTIAL NON-DETERMINISTIC DETECTION IN HARDWARE DESIGN - The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker. | 12-03-2015 |
20150379186 | SYSTEM AND METHOD FOR GRADING AND SELECTING SIMULATION TESTS USING PROPERTY COVERAGE - A method implemented as a test grading system (TGS) in a programmable computing system grades simulation tests according to their verification property coverage. The TGS identifies verification properties from one or more of the circuit design (e.g. RTL description), verification properties files and test simulation results, and determines verification property coverage for each test. That is, it finds out which verification properties are covered by each simulation test. According to a specified criterion, the TGS recommends a subset of the available tests based on their verification property coverage. | 12-31-2015 |
20160048624 | CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS - In various embodiments, an integrated circuit derived from an integrated circuit layout is disclosed. In some embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold, the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area. | 02-18-2016 |
20160055272 | METHOD AND COMPILING SYSTEM FOR GENERATING TESTBENCH FOR IC - A method for generating a testbench for an IC is provided. Design information of the IC is obtained according to a bus configuration. The design information is displayed in a graphical user interface (GUI). The design information is modified according to a first user input. It is determined whether the modified design information is correct according to a register transfer level (RTL) code of the IC. The testbench for the IC is generated according to the modified design information when the modified design information is correct. | 02-25-2016 |
20160063161 | RESET VERIFICATION - This application discloses an electronic design automation tool configured to perform one or more static reset checks on reset functionality in a circuit design. The electronic design automation tool can detect the reset functionality in the circuit design, identify a portion of the circuit design having a set of resettable components, and determine whether the portion of the circuit design includes a reset design error based, at least in part, on the reset functionality in the circuit design. The static reset checks can include a domain congruency check, a reset skew check, and a glitch detection check, each of which can identify different design errors that may cause reset functionality in the circuit design to operate improperly. | 03-03-2016 |
20160063162 | SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW - A system and method are provided that use pass/fail test results to prioritize electronic design verification review issues. It may prioritize either generated properties or code coverage items or both. Thus issues, whether generated properties or code coverage items, that have never been violated in any passing or failing test may be given highest priority for review, while those that have been violated in a failing test but are always valid in passing tests may be given lower priority. Still further, where end-users have marked one or more properties or code coverage items as already-reviewed, the method will give these already-reviewed issues the lowest priority. As a result, both properties and code coverage items may be generated together in a progressive manner starting earlier in development and significant duplication of effort is avoided. | 03-03-2016 |
20160070836 | CIRCUIT SIMULATING METHOD, CIRCUIT SIMULATING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The circuit simulating method according to an embodiment includes obtaining a first electrical characteristic value of a circuit element that operates under a predetermined operational condition. The circuit simulating method includes correcting the first electrical characteristic value based on a period in which application of an electrical stress equal to or higher than a reference value is stopped during operation of the circuit element. | 03-10-2016 |
20160070846 | SYSTEM FOR TESTING IC DESIGN - A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design. | 03-10-2016 |
20160103941 | BUFFER CHAIN MANAGEMENT FOR ALLEVIATING ROUTING CONGESTION - Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains. | 04-14-2016 |
20160125111 | MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS - A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user. | 05-05-2016 |
20160125112 | EFFICIENT DEPLOYMENT OF TABLE LOOKUP (TLU) IN AN ENTERPRISE-LEVEL SCALABLE CIRCUIT SIMULATION ARCHITECTURE - A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, if a component of the plurality of components is defined in a table and the table includes the condition to be analyzed, acquiring a result for the condition to be analyzed based on table information, and conducting the analysis of the system using the result based on the table information for the component. | 05-05-2016 |
20160125113 | EFFICIENT DEPLOYMENT OF TABLE LOOKUP (TLU) IN AN ENTERPRISE-LEVEL SCALABLE CIRCUIT SIMULATION ARCHITECTURE - A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be analyzed, a module that is configured to perform a table look-up for components of the plurality of components, a module that is configured to acquire a result for the condition to be analyzed based on table information when a component of the plurality of components is defined in a table and when the table includes the condition to be analyzed, and a module that is configured to conduct the analysis of the circuit using the result based on the table information for the component. | 05-05-2016 |
20160125114 | METHOD AND APPARATUS FOR BITCELL MODELING - A methodology for the simulation of semiconductor memory devices that exhibits improved accuracy and speed, and the apparatus performing the methodology are disclosed. Embodiments may include determining a state of a bitcell of an integrated circuit (IC) design, determining a first threshold voltage for the bitcell based on the state of the bitcell, and simulating electrical characteristics of the bitcell according to the first threshold voltage to verify the IC design. | 05-05-2016 |
20160140284 | TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING A DISPATCHER - A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT. | 05-19-2016 |
20160140285 | TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING A GENERIC MONITOR AND TRANSPORTER - A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT. | 05-19-2016 |
20160140286 | TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD WITH PHASE SYNCHRONIZATION - A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT. | 05-19-2016 |
20160171136 | METHOD FOR AUTOMATED ASSISTANCE TO DESIGN NONLINEAR ANALOG CIRCUIT WITH TRANSIENT SOLVER | 06-16-2016 |
20160171137 | METHOD FOR SEMICONDUCTOR PROCESS CORNER SWEEP SIMULATION BASED ON VALUE SELECTION FUNCTION | 06-16-2016 |
20160171140 | METHOD AND SYSTEM FOR DETERMINING MINIMUM OPERATIONAL VOLTAGE FOR TRANSISTOR MEMORY-BASED DEVICES | 06-16-2016 |
20160171141 | VERIFICATION ENVIRONMENTS UTILZING HARDWARE DESCRIPTION LANGUAGES | 06-16-2016 |
20160180004 | IMPLEMENTING ENHANCED PERFORMANCE DYNAMIC EVALUATION CIRCUIT BY COMBINING PRECHARGE AND DELAYED KEEPER | 06-23-2016 |
20160188773 | ELECTRONIC DESIGN AUTOMATION METHOD AND APPARATUS THEREOF - Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations. | 06-30-2016 |
20180025105 | SIMULATING REFERENCE VOLTAGE RESPONSE IN DIGITAL SIMULATION ENVIRONMENTS | 01-25-2018 |
20220138389 | DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION - A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address. | 05-05-2022 |