Class / Patent application number | Description | Number of patent applications / Date published |
716021000 | Pattern exposure | 78 |
20080235651 | Method and apparatus for determining an optical model that models the effects of optical proximity correction - One embodiment provides a system that can enable a designer to determine the effects of subsequent processes at design time. During operation, the system may receive a test layout and an optical model that models an optical system, but which does not model the effects of subsequent processes, such as optical proximity correction (OPC). The system may generate a first dataset using the test layout and the optical model. Next, the system may apply OPC to the test layout, and generate a second dataset using the corrected test layout and the optical model. The system may then use the first dataset and the second dataset to adjust the optical model to obtain a second optical model that models the effects of subsequent processes. | 09-25-2008 |
20080235652 | Lithography method for forming a circuit pattern - A lithography method for suppressing resist scum includes the steps of designing an original layout with line patterns and pad patterns, extracting a pad patternlayout from the original, layout, obtaining a first reduction layout which is reduced by a first reduction width relative to the pad pattern layout, obtaining a second reduction layout which is reduced by a second reduction width larger than the first reduction width relative to the pad pattern layout, obtaining an assist pattern layout which is self-aligned to the pad pattern layout by deducting the second reduction layout from the first reduction layout, generating assist patterns in the original layout by deducting the assist pattern layout from the original layout, and projecting the layout including the assist patterns on a semiconductor substrate by an exposure process. | 09-25-2008 |
20080250383 | Method for designing mask pattern and method for manufacturing semiconductor device - A mask pattern designing method capable of achieving the reduction in the increasing OPC processing time, shortening the manufacture TAT of a semiconductor device, and achieving the cost reduction is provided. An OPC (optical proximity correction) process at the time when a cell is singularly arranged is performed to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance, and a semiconductor chip is produced using the cell library pattern to which the OPC process has been performed. At this time, since the cell library pattern which has been OPC-processed in advance is influenced by the cell library patterns around it, the correction process thereof is performed to the end portions of the patterns near the cell boundary. As particularly effective OPC correction means, the genetic algorithm is used. | 10-09-2008 |
20080250384 | SYSTEMS AND METHODS FOR CREATING INSPECTION RECIPES - Systems and methods for creating inspection recipes are provided. One computer-implemented method for creating an inspection recipe includes acquiring a first design and one or more characteristics of output of an inspection system for a wafer on which the first design is printed using a manufacturing process. The method also includes creating an inspection recipe for a second design using the first design and the one or more characteristics of the output acquired for the wafer on which the first design is printed. The first and second designs are different. The inspection recipe will be used for inspecting wafers after the second design is printed on the wafers using the manufacturing process. | 10-09-2008 |
20080263502 | MASK PATTERN DATA GENERATING METHOD, INFORMATION PROCESSING APPARATUS, PHOTOMASK FABRICATION SYSTEM, AND IMAGE SENSING APPARATUS - A method for generating mask pattern data of a photomask used to form microlenses divides a pattern formation surface of a mask pattern to be used for the photomask into a plurality of grid cells, acquires data which represents transmitted light distribution of the mask pattern to be used for the photomask, determines whether to place a shield on each of the plurality of grid cells by binarizing the plurality of grid cells in order of increasing or decreasing distance from a center of the pattern formation surface using an error diffusion method to acquire the transmitted light distribution, and generates mask pattern data which represents an arrangement of the shields based on results from the determining step. | 10-23-2008 |
20080276216 | Pattern forming method and system, and method of manufacturing a semiconductor device - A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin. | 11-06-2008 |
20080295061 | Generalization of the Photo Process Window and Its Application to Opc Test Pattern Design - A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns. | 11-27-2008 |
20080295062 | Method of verifying a layout pattern - A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns. | 11-27-2008 |
20080295063 | Method and apparatus for determining factors for design consideration in yield analysis - Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor. | 11-27-2008 |
20080301623 | Lithography Suspect Spot Location and Scoring System - A fast method to detect hot spots using foundry independent models that do not require RET/OPC synthesis is presented. In some embodiments of the present invention, sensitive spots are located. Lithography models are used to simulate the geometry near the sensitive spots to produce a model of the area around the sensitive spots. The sensitive spots are scored using a measure such as intensity (of light) or scoring based on contrast. | 12-04-2008 |
20080301624 | SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION - A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization. | 12-04-2008 |
20080313593 | Occupancy Based on Pattern Generation Method For Maskless Lithography - An occupancy based pattern generation method for a maskless lithography system using micromirrors is disclosed. The present invention includes the steps of recognizing a pattern upon the substrate through the extraction of the pattern boundary and the construction of the pattern region and recognizing the pattern upon the micromirror through the confirmation of the micromirror dependent lithographic pattern region, the extraction of the micromirror dependent pattern based on the occupancy, and the construction of the stream of binary patterns containing binary reflection information for the micromirrors in accordance with the substrate scrolling. | 12-18-2008 |
20080320435 | OPTICAL PROXIMITY CORRECTION IMPROVEMENT BY FRACTURING AFTER PRE-OPTICAL PROXIMITY CORRECTION - A method for fabricating a mask used to make integrated circuits is provided using an improved OPC process whereby a pre-fracturing OPC process is performed on the target design of the integrated circuit. The pre-fractured OPC design is then fractured and a post-fracturing OPC process performed to make the final mask. Either rule-based OPC or model-based OPC processes can be used for both of the OPC steps or each step can be either side-based or model-based OPC. | 12-25-2008 |
20090007052 | Method for Verifying Pattern of Semiconductor Device - Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask. | 01-01-2009 |
20090007053 | Method of Manufacturing Mask for Semiconductor Device - A method of manufacturing a mask for a semiconductor device includes checking layout data for a mask in the semiconductor device and correcting any errors in the layout data that violate the design rule, filling small jogs in the layout data, performing optical proximity correction on the jog-filled layout data, and generating a mask pattern using the jog-filled layout data subjected to the optical proximity correction. By this process, it is possible to simplify the layout database to be subjected to optical proximity correction and minimize any errors that may cause unnecessary optical proximity correction (OPC) issues. | 01-01-2009 |
20090019419 | Method for forming LSI pattern - First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed. | 01-15-2009 |
20090055794 | Apparatus and method for dummy pattern arrangement - The EB data is separated into an area A and other area. The area A is covered by a recognition layer to which an algorism is linked to form a recognition layer A. For arranging a same dummy pattern for respective areas A, a dummy pattern creation starting point is designated in a common position for each recognition layer A. When there are areas A which have different rotation angles, the recognition layer is created to satisfy a condition that, even if any corner of the area A is designated as the dummy pattern creation starting point, the created dummy pattern becomes an identical arrangement. The sizes DP and gaps GAP of the dummy pattern elements composing the dummy pattern are respectively same in X-direction and Y-direction. The size of the recognition layer A is determined by: a multiple of (DP+GAP)+DP, in X and Y-direction respectively. | 02-26-2009 |
20090064084 | PREDICTION MODEL AND PREDICTION METHOD FOR EXPOSURE DOSE - A prediction model for exposure dose is indicated by the following formula, E=E | 03-05-2009 |
20090064085 | METHOD OF CREATING PHOTO MASK LAYOUT, COMPUTER READABLE RECORDING MEDIUM STORING PROGRAMMED INSTRUCTIONS FOR EXECUTING THE METHOD, AND MASK IMAGING SYSTEM - A method of generating a photo mask layout includes providing a first photo mask layout including main patterns and sub-resolution assist features (SRAF) patterns, defining a plurality of mesh cells by dividing the first photo mask layout into regions, generating a rule based table including correction information for correcting defects in the SRAF patterns for at least one of the plurality of mesh cells, and correcting the SRAF patterns by applying values of the correction information to the SRAF patterns corresponding to each mesh cell. | 03-05-2009 |
20090077525 | System and Method for Semiconductor Device Fabrication Using Modeling - System and method for using adjustment patterns as well as physical parameters as targets to control mask structure dimensions using optical proximity correction. A method for correcting layer patterns comprises selecting optimum sacrificial patterns, defining virtual targets from the optimum sacrificial patterns, and executing an optical proximity correction process with the virtual targets to correct layer patterns. The selecting of the optimum sacrificial patterns may be performed in a separate processing stage, thereby reducing the number of targets to be investigated during a process window optical proximity correction, thereby reducing the runtime, processing, and memory requirements. | 03-19-2009 |
20090077526 | Write-Pattern Determination for Maskless Lithography - A method for generating a write pattern to be used in a maskless-lithography process is described. During the method, a computer system determines a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in a spatial-light modulator used in the maskless-lithography process. Furthermore, the computer system generates the write pattern. Note that the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, and the generating is in accordance with a characteristic dimension of an element in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process. | 03-19-2009 |
20090077527 | System for Determining Repetitive Work Units - During a method for generating a mask pattern for a photo-mask, a target pattern is partitioned into subsets of the target pattern. The subsets of the target pattern may be selected so that at least some of the subsets are approximately identical, thereby dividing the subsets into a degenerate group and a non-degenerate group. A group of the subsets may include multiple shapes, and a given target pattern may be significantly larger than a pre-determined length scale and a given shape in the multiple shapes is smaller than the pre-determined length scale. The non-degenerate group of subsets of the target pattern may be distributed to multiple processors. These processors may be used to determine subsets of the mask pattern based on the non-degenerate group of subsets of the target pattern. The subsets of the mask pattern may be combined to generate the mask pattern. | 03-19-2009 |
20090077528 | PATTERN CORRECTION METHOD, PATTERN CORRECTION SYSTEM, MASK MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, RECORDING MEDIUM, AND DESIGNED PATTERN - A semiconductor device having a physical pattern based on a designed pattern is provided. The designed pattern includes a target pattern and a correction pattern. The target pattern includes a first portion of an edge with a first distance between the first portion and a pattern opposed thereto, a second portion of the edge with a second distance between the second portion and a pattern opposed thereto, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance between the first region and the pattern opposed thereto. | 03-19-2009 |
20090077529 | DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM - A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other. | 03-19-2009 |
20090077530 | DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM - A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other. | 03-19-2009 |
20090083692 | FLASH-BASED ANTI-ALIASING TECHNIQUES FOR HIGH-ACCURACY HIGH EFFICIENCY MASK SYNTHESIS - One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout. | 03-26-2009 |
20090083693 | FLASH-BASED UPDATING TECHNIQUES FOR HIGH-ACCURACY HIGH EFFICIENCY MASK SYNTHESIS - Another embodiment of the present invention provides a system that computes the effect of perturbations to an input pattern layout during an OPC (Optical Proximity Correction) process. During operation, the system receives a pattern layout. The system further receives a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. Next, the system computes a model flash lookup table for each of the lithography model kernels, wherein the model flash lookup table contains precomputed values for a set of convolution functions obtained by convolving a set of basis functions with the lithography model kernel. The system additionally receives a perturbation pattern to be added onto the pattern layout. Next, for a query location in a plurality of query locations on the pattern layout, the system obtains a set of convolution values at the query location by using the model flash lookup tables to convolve the perturbation pattern with the set of lithography model kernels. The system then updates the set of convolved patterns at the query location to account for the effect of the perturbation pattern by combining the set of convolution values with the set of convolved patterns. Next, the system computes an intensity value at the query location. | 03-26-2009 |
20090125870 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database, the drawn pattern data describing device circuit features and dummy features. The dummy features have first target patterns. Mask pattern data is generated for the dummy features, wherein one or more of the dummy features have second target patterns that are different from the first target patterns. The mask pattern data is corrected for proximity effects. | 05-14-2009 |
20090125871 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for, preparing a photomask pattern. The method comprises receiving drawn pattern data from a design database. The drawn pattern data describes two or more adjacent feature ends that are positioned at different locations along a y-axis. A photomask pattern is formed for patterning the feature ends, wherein the photomask pattern will result in the feature ends being positioned at the same location along the y-axis. | 05-14-2009 |
20090132992 | STATISTICAL OPTICAL PROXIMITY CORRECTION - An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern. | 05-21-2009 |
20090144693 | Exposure data generator and method thereof - An exposure data generator for generating exposure data representing graphical information of a pattern to be exposed and a computer-readable recording medium are provided. The generator includes a storage device for storing pre-correction exposure data which include information on positions and sizes of patterns placed within an target region and a search device for classifying the patterns according to placement positions within the target region, searching for a pattern which is another pattern by using the classified patterns, and storing information on the patterns. The generator also includes a back-scattering intensity calculation device for calculating a back-scattering intensity from at an evaluation point on the pattern. The generator also includes a movement quantity calculation device for calculating a movement quantity of a side of a pattern. | 06-04-2009 |
20090158236 | Semiconductor device fabrication method and fabrication apparatus using a stencil mask - A semiconductor device fabrication method includes preparing a substrate having a first circuit pattern of a semiconductor device; providing a mask with at least part of second circuit pattern of the semiconductor device; collimating incident direction of particles; changing at least one of the a substrate angle between a vertical axis of the substrate and the incident direction of the particles and a mask angle between a vertical axis of the mask and the incident direction so that the second circuit pattern on the mask can be aligned to the first circuit pattern on the substrate with a design margin; and selectively irradiating the particles to the substrate using the mask. | 06-18-2009 |
20090187878 | DATA GENERATION METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRON BEAM EXPOSURE SYSTEM - A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference in shape between an electron beam exposure pattern formed on a substrate through electron beam exposure on the basis of the electron beam exposure data and a photoexposure pattern formed on the substrate through photoexposure on the basis of the design data of the semiconductor device; determining whether the size of the difference in shape between the electron beam exposure pattern and the photoexposure pattern falls within a predetermined reference value; acquiring shape changed exposure data by changing the shape of the pattern of the electron beam exposure data in accordance with the differential information and updating the electron beam exposure data; and repeating the differential extraction, the determination and the updating when the size of the difference falls outside the predetermined reference value. | 07-23-2009 |
20090193387 | METHODOLOGY AND SYSTEM FOR DETERMINING NUMERICAL ERRORS IN PIXEL-BASED IMAGING SIMULATION IN DESIGNING LITHOGRAPHIC MASKS - A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size. | 07-30-2009 |
20090199152 | Methods and apparatuses for reducing mura effects in generated patterns - A method for generating a pattern on a workpiece is provided. In one method for generating a pattern on a workpiece, at least two sweeps or exposure fields are calibrated based on at least two different calibration maps. The pattern is generated on the workpiece by exposing the workpiece using the at least two sweeps or exposure fields. | 08-06-2009 |
20090199153 | EXPOSURE CONDITION SETTING METHOD AND PROGRAM FOR SETTING EXPOSURE CONDITIONS - There is provided an exposure condition setting method concerning an example of the present invention, the method includes inputting design layout data, extracting a plurality of design patterns having a predetermined dimension from the input design layout data, obtaining a transfer pattern transferred to a transfer target film by exposure of a mask pattern from the mask pattern associated with the extracted patterns, and calculating a dimensional fluctuation amount of the transfer pattern and a design value of the design pattern, obtaining a distribution of the number of the extracted design patterns associated with the dimensional fluctuation amount of the extracted design pattern, and setting exposure conditions in such a manner that the dimensional fluctuation amount of the extracted design pattern associated with a reference value in the distribution of the number of design patterns satisfies allowance conditions. | 08-06-2009 |
20090210851 | LITHOGRAPHY SIMULATION METHOD AND COMPUTER PROGRAM PRODUCT - A lithography simulation method for simulating a lithography process configured to form a pattern on a wafer in which the pattern corresponds to a pattern of a photomask, the lithography process including disposing the photomask above the wafer, disposing an exposure light source above the photomask, and irradiating the wafer with light which is emitted from the exposure light source and has passed through the photomask, the lithography simulation method including assuming a light source corresponding to the exposure light source and used for simulating the lithography process, the light source failing to reflect amplitude transmittance of light emitted from the exposure light source wherein the light is obliquely incident on the photomask, and acquiring a light intensity distribution of the pattern to be formed on the wafer corresponding to the pattern of the photomask by calculation using the light source. | 08-20-2009 |
20090217233 | SIMULATION METHOD AND SIMULATION PROGRAM - A method of simulating an optical intensity distribution on a substrate when a mask pattern formed on the mask is transferred to the substrate through a projection optical system by irradiating an illumination light obliquely on a mask surface of the mask, which comprises setting a phase difference between a zero-order diffraction light and a first-order diffraction light determined according to at least one of a distance between the zero-order diffraction light and the first-order diffraction light on a pupil of the projection optical system, thickness of a light-shielding portion formed on the mask, angle defined by an optical axis direction of the illumination light and an incident direction on the mask, and a difference between a size of the mask pattern and a half cycle of the mask pattern, and carrying out a simulation of the optical intensity distribution on the substrate according to the set phase difference. | 08-27-2009 |
20090235224 | Method for Processing Optical Proximity Correction - A method for processing optical proximity correction includes preparing a chemical mechanical polishing (CMP) map; extracting calibration data depending on a focus degree with the CMP map; and correcting optical proximity with the calibration data. | 09-17-2009 |
20090241087 | System for simplifying layout processing - A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation. | 09-24-2009 |
20090265680 | Method and system for correcting a mask pattern design - A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics. | 10-22-2009 |
20090276751 | METHOD OF PERFORMING MASK-WRITER TUNING AND OPTIMIZATION - A model-based tuning method for tuning a first mask writer unit utilizing a reference mask writer unit, each of which has tunable parameters for controlling mask writing performance. The method includes the steps of defining a test pattern and a mask writing model; generating the test pattern utilizing the reference mask writer unit and measuring the mask writing results; generating the test pattern utilizing the first mask writer unit and measuring the mask writing results; calibrating the mask writing model utilizing the mask writing results corresponding to the reference mask writer unit, where the calibrated mask writing model has a first set of parameter values; tuning the calibrated mask writing model utilizing the mask writing results corresponding to the first mask writer unit, where the tuned calibrated model has a second set of parameter values; and adjusting the parameters of the first mask writer unit based on a difference between the first set of parameter values and the second set of parameter values. | 11-05-2009 |
20090288060 | CHARGED PARTICLE BEAM EXPOSURE METHOD AND CHARGED PARTICLE BEAM EXPOSURE DEVICE - When a space, sandwiched by large patterns having a predetermined size or more, is exposed using a charged particle beam, the space sandwiched by the large patterns is exposed using a common block mask having the space and edge portions of the large patterns on both sides of the space, and portions other than the edge portions of the large patterns on both sides are exposed by a variable rectangular beam or by using another block mask. | 11-19-2009 |
20090300576 | METHOD FOR AMENDING LAYOUT PATTERNS - A method for amending layout patterns is disclosed. First, a layout pattern after an optical proximity correction is provided, which is called an amended pattern. Later, a positive sizing procedure and a negative sizing procedure are respectively performed on the amended pattern to respectively obtain a positive sizing pattern and a negative sizing pattern. Then, the positive sizing pattern and the negative sizing pattern are respectively verified to know whether they are useable. Afterwards, the useable positive sizing pattern and the negative sizing pattern are output for the manufacture of a reticle when they are verified to be useable. | 12-03-2009 |
20090319978 | Mask Patterns for Use in Multiple-Exposure Lithography - A method for determining mask patterns to be used on photo-masks in a multiple-exposure photolithographic process is described. During the method, an initial mask pattern, which is intended for use in a single-exposure photolithographic process, and a target pattern that is to be printed are used to determine a first mask pattern and a second mask pattern, which are intended for use in the multiple-exposure photolithographic process. In particular, the first mask pattern includes a first feature and the second mask pattern includes a second feature, and the first feature and the second feature overlap an intersection between features in the initial mask pattern. Moreover, the first mask pattern and the second mask pattern have at least one decreased spatial frequency relative to the initial mask pattern along at least one direction in the initial mask pattern. | 12-24-2009 |
20100005442 | Apparatus and Methods for Determining Overlay and Uses of Same - Disclosed are techniques and apparatus are provided for determining overlay error or pattern placement error (PPE) across the field of a scanner which is used to pattern a sample, such as a semiconductor wafer or device. This determination is performed in-line on the product wafer or device. That is, the targets on which overlay or PPE measurements are performed are provided on the product wafer or device itself. The targets are either distributed across the field by placing the targets within the active area or by distributing the targets along the streets (the strips or scribe areas) which are between the dies of a field. The resulting overlay or PPE that is obtained from targets distributed across the field may then be used in a number of ways to improve the fabrication process for producing the sample. For instance, the resulting overlay or PPE may be used to more accurately predict device performance and yield, more accurately correct a deviating photolithography scanning tool, or determine wafer lot disposition. | 01-07-2010 |
20100017779 | Method for Decomposing Designed Pattern Layout and Method for Fabricating Exposure Mask Using the Same - A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time. | 01-21-2010 |
20100017780 | DIFFERENTIAL ALTERNATING PHASE SHIFT MASK OPTIMIZATION - A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, such that the first mask design meets predetermined manufacturability design rules, and creating a second mask design by aligning mask features with the critical width segments of the integrated circuit design, such that the second mask design meets predetermined lithographic design rules in regions local to the critical width segments. The method then includes identifying design features of the second mask design that violate the predetermined manufacturability design rules, and then creating a third mask design derived from the second mask design wherein the mask features of the second mask design that violate the predetermined manufacturability rules are selectively replaced by mask features from the first mask design so that the third mask design meets the predetermined manufacturability design rules. By way of example, the mask features used to assist in projecting critical width segments may comprise alternating phase shifting regions or sub-resolution assist features. | 01-21-2010 |
20100031224 | Pattern verification method, program thereof, and manufacturing method of semiconductor device - A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern. | 02-04-2010 |
20100031225 | Methods and systems for pattern generation based on multiple forms of design data - In a pattern generation method, properties of designs are extracted in a mask data preparation system, and the properties are propagated to a lithography write system. A pattern is generated based on fractured design data and the extracted properties. By preserving the design intent to the lithography write system, the fidelity of the pattern replication may improve. | 02-04-2010 |
20100037200 | SYSTEM AND METHOD FOR MODEL BASED MULTI-PATTERNING OPTIMIZATION - Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition. | 02-11-2010 |
20100050149 | Design and Layout of Phase Shifting Photolithographic Masks - A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts. | 02-25-2010 |
20100058280 | BULK IMAGE MODELING FOR OPTICAL PROXIMITY CORRECTION - A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist. | 03-04-2010 |
20100058281 | METHOD FOR OPTICAL PROXIMITY CORRECTION OF A RETICLE TO BE MANUFACTURED USING CHARACTER PROJECTION LITHOGRAPHY - A method for optical proximity correction of a design of a pattern on a surface is disclosed with the method comprising the steps of inputting desired patterns for the substrate and inputting a set of characters some of which are complex characters that may be used for forming the patterns on the surface. A method of creating glyphs is also disclosed. | 03-04-2010 |
20100058282 | METHOD AND SYSTEM FOR DESIGN OF A RETICLE TO BE MANUFACTURED USING CHARACTER PROJECTION LITHOGRAPHY - A method for fracturing or mask data preparation or proximity effect correction is disclosed which comprises the steps of inputting patterns to be formed on a surface, a subset of the patterns being slightly different variations of each other and selecting a set of characters some of which are complex characters to be used to form the number of patterns, and reducing shot count or total write time by use of a character varying technique. A system for fracturing or mask data preparation or proximity effect correction is also disclosed. | 03-04-2010 |
20100064274 | PROXIMITY CORRECTION METHOD AND SYSTEM - A proximity correction method includes creating a first proximity correction model having a focus value and creating a second proximity correction model having a first defocus value. One of the first or second proximity correction models are associated with corresponding first and second layout areas of a semiconductor wafer. | 03-11-2010 |
20100070944 | METHOD FOR CONSTRUCTING OPC MODEL - A method for constructing an optical proximity correction (OPC) model is described. A test pattern is provided, and the test pattern is then written on a mask. The pattern on the mask is measured to obtain a modified pattern. An OPC model is constructed according to the modified pattern. | 03-18-2010 |
20100125823 | SYSTEMS AND METHODS FOR ADJUSTING A LITHOGRAPHIC SCANNER - A system and methods are provide for modeling the behavior of a lithographic scanner and, more particularly, a system and methods are provide using thresholds of an image profile to characterize through-pitch printing behavior of a lithographic scanner. The method includes running a lithographic model for a target tool and running a lithographic model on the matching tool for a plurality of different settings using lens numerical aperture, numerical aperture of the illuminator and annular ratio of a pattern which is produced by an illuminator. The method then selects the setting that most closely matches the output of the target tool. | 05-20-2010 |
20100131915 | Method, device, and program for predicting a manufacturing defect part of a semiconductor device - Provided is a method of predicting a manufacturing defect part of a semiconductor device, which results from optical pattern displacement in an exposure process. The prediction method includes: performing repetitive processing a plurality of times, the repetitive processing including: a site generating step of setting a site at a predetermined position of a layout pattern; an edge shifting step of shifting an edge of the layout pattern according to a predetermined rule; an image forming position calculating step of calculating an image forming position corresponding to the shifted edge on the site; and an error check step of storing error information between the image forming position on the site and the edge of the layout pattern; and extracting, based on the error information, from the first layout data, apart in which the image forming position is unstable, and predicting the extracted part as a hot spot. | 05-27-2010 |
20100146477 | MICROLENS ALIGNMENT PROCEDURES IN CMOS IMAGE SENSOR DESIGN - A method for aligning a microlens array in a sensor die to resolve non-symmetric brightness distribution and color balance of the image captured by the sensor die. The method includes performing a pre-simulation to simulate a microlens array alignment in a silicon die and to determine a shrink-factor and de-centering values, calculating the error in a real product's alignment in process and image offset, performing a post simulation based on offset calculation on the real product and re-design of the microlens alignment, and repeating the steps of calculating the error and performing the post-simulation until a satisfactory brightness distribution is obtained. The sensor die has sensor pixels, each pixel comprising a photodiode and a microlens for directing incoming light rays to the photodiode, wherein optical axis of the microlens is shifted with respect to optical axis of the photodiode by a preset amount determined by at least one iteration of alignment process. | 06-10-2010 |
20100153902 | DETERMINING MANUFACTURABILITY OF LITHOGRAPHIC MASK BY SELECTING TARGET EDGE PAIRS USED IN DETERMINING A MANUFACTURING PENALTY OF THE LITHOGRAPHIC MASK - The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edges are selected from mask layout data of the lithographic mask. The mask layout data includes polygons distributed over cells, where each polygon has edges. The cells include a center cell, two vertical cells above and below the center cell, and two horizontal cells to the left and right of the center cell. Target edge pairs are selected for determining a manufacturing penalty in making the lithographic mask, in a manner that decreases the computational volume in determining the manufacturing penalty. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs selected. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask. | 06-17-2010 |
20100153903 | DETERMINING MANUFACTURABILITY OF LITHOGRAPHIC MASK USING CONTINUOUS DERIVATIVES CHARACTERIZING THE MANUFACTURABILITY ON A CONTINUOUS SCALE - The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has a number of edges. Each target edge pair is defined by two of the edges of one or more of the polygons. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined. Determining the manufacturing penalty is based on the target edge pairs as selected. Determining the manufacturability of the lithographic mask uses continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask. | 06-17-2010 |
20100153904 | Model-based pattern characterization to generate rules for rule-model-based hybrid optical proximity correction - A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by simulation using a lithography model to obtain a partition of the pattern spaces into one portion that requires only rule-based OPC and another portion that requires model-based OPC. A corresponding hybrid OPC system and method are also introduced that utilize the generated rules to correct an integrated circuit (IC) design layout which reduces the OPC output complexity and improves turnaround time. | 06-17-2010 |
20100153905 | PATTERN LAYOUT DESIGNING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COMPUTER PROGRAM PRODUCT - A graph is created in which mask patterns adjacent to one another at a distance in which desired printing resolution cannot be obtained in a lithography process among mask patterns generated based on a pattern layout design drawing are set as nodes connected to one another by edges. An odd number loop formed by an odd number of nodes is selected from closed loops. When the selected odd number loop is not isolated, based on whether a closed loop group in which a plurality of closed loops including the odd number loop are connected includes an even number loop formed by an even number of nodes, rearrangement target nodes are selected from the odd number loop included in the closed loop group according to different selection references. The layout of patterns described in the pattern layout design drawing is rearranged corresponding to the selected rearrangement target nodes. | 06-17-2010 |
20100162197 | METHOD AND SYSTEM FOR LITHOGRAPHY PROCESS-WINDOW-MAXIMIXING OPTICAL PROXIMITY CORRECTION - The present invention relates to an efficient OPC method of increasing imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes the steps of determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and optimizing target gray level for each evaluation point in each OPC iteration based on this function. In one given embodiment, the function is approximated as a polynomial function of focus and exposure, R(ε, f)=P | 06-24-2010 |
20100162198 | Exposure data generation method and device, exposure data verification method and device and storage medium - Exposure verification is applied to exposure data indicating a pattern to be exposed by a charged particle beam. If an error point is extracted from the exposure data by the exposure verification, the values of coefficients are modified and exposure data is regenerated taking into consideration the coefficients whose values have been modified. Thus, exposure data is re-generated by changing each of the coefficient values within its appropriate range. | 06-24-2010 |
20100162199 | THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION - A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image. | 06-24-2010 |
20100175042 | EFFICIENT ISOTROPIC MODELING APPROACH TO INCORPORATE ELECTROMAGNETIC EFFECTS INTO LITHOGRAPHIC PROCESS SIMULATIONS - The present invention relates to the modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography. According to the invention, an isofield perturbation to a thin mask representation of the mask is provided by determining, for the components of the illumination, differences between the electric field on a feature edge having finite thickness and on the corresponding feature edge of a thin mask representation. An isofield perturbation is obtained from a weighted coherent combination of the differences for each illumination polarization. The electric field of a mask having topographic edges is represented by combining a thin mask representation with the isofield perturbation applied to each edge of the mask. | 07-08-2010 |
20100175043 | FAST AND ACCURATE METHOD TO SIMULATE INTERMEDIATE RANGE FLARE EFFECTS - A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy. | 07-08-2010 |
20100180252 | COMPUTER READABLE STORAGE MEDIUM STORING PROGRAM FOR GENERATING RETICLE DATA, AND METHOD OF GENERATING RETICLE DATA - A computer readable storage medium stores a program for generating reticle data for producing a reticle used in an exposure apparatus, the program including the steps of classifying target patterns to be formed on a substrate into a plurality of direction groups, extracting, for each of the plurality of direction groups, a region suited to resolution of a target pattern belonging to the direction group from an effective light source distribution formed on a pupil of a projection optical system by an illumination optical system, thereby determining the extracted region as a partial light source, executing, for each of a plurality of partial light sources determined in the step of extracting a region, processing of determining a pattern to be placed on a reticle when each partial light source is used as an illumination condition, and merging patterns determined in the step of executing processing. | 07-15-2010 |
20100180253 | DEFECT PATTERN MATCHING AND VERIFICATION IN INTEGRATED CIRCUIT DESIGN AND MANUFACTURING - A method is disclosed for correcting design defects in a circuit layout. The method includes storing first-level defect patterns in a first-level defect pattern library and identifying in a first circuit layout a first target that matches the shape of a first-level defect pattern in the first-level defect pattern library, and modifying the first target in the first circuit layout to produce a modified circuit layout. The method also includes storing second-level defect patterns in a second-level defect pattern library. The second-level defect patterns stored in the second-level defect pattern library are related to defects in circuit manufacturing. The first-level defect patterns are not stored in the second-level defect pattern library. A second target in the modified circuit layout is identified to increase manufacturing yield of the circuit layout. The second target substantially matches a second-level defect pattern in the second-level defect pattern library. | 07-15-2010 |
20100205577 | Design Methods for E-Beam Direct Write Lithography - A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system. | 08-12-2010 |
20100218161 | Joint Calibration for Mask Process Models - Methods for jointly calibrating etch and exposure mask process models from etch only data are described. Initially, an etch model and an exposure model may be identified. Subsequently, a combined etch/exposure model may be generated based upon the etch model and the exposure model. Following which, a global optimization process may be performed to calibrate the combined etch/exposure model based upon measured data representing the etch and the exposure effects. With some implementations, the global optimization process is based in part upon a cost function representing the norm of the difference between the simulated mask contours and the measured mask contours. Furthermore, in some implementations, the optimization variable set is the union of the parameter sets corresponding to the etch model and the exposure model individually. Further still, with various implementations, the optimization of based upon the etch parameter set is “nested” inside an optimization of the exposure parameter set, or, vice versa. | 08-26-2010 |
20100229148 | METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING - Various embodiments of the present invention relate to particle beam writing to fabricate an integrated circuit on a wafer. In various embodiments, cell projection (CP) cell library information is stored in the form of a data structure. Subsequently, the CP cell library information is referenced by a writing system. The patterns are written on the wafer depending on the referenced CP cell library. | 09-09-2010 |
20100251203 | Method for Time-Evolving Rectilinear Contours Representing Photo Masks - Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to rectilinear patterns), robustness against process variations, as well as restrictions imposed relating to practical and economic manufacturability of photomasks. | 09-30-2010 |
20100269085 | Automated Generation of Oxide Pillar Slot Shapes in Silicon-On-Insulator Formation Technology - A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of the RX shapes, filtering the PX placement markers, generating a PX slot shape corresponding to each filtered PX placement marker on the RX shapes, correcting location errors associated with the generated PX slot shapes, generating PX slot shapes on RX shapes of a predetermined size for which PX slot shapes were not generated, performing a verification operation of the PX slot shapes, and outputting the PX layer including the verified PX slot shapes. | 10-21-2010 |
20100269086 | Electron Beam Simulation Corner Correction For Optical Lithpography - Methods for approximating simulated contours are provided herein. With some implementations, a function that incorporates a Gaussian proximity kernel to approximate the electron beam exposure effects is used to simulate a printed image. Subsequently, one or more corners of the simulated printed image may be approximated by two or more straight edges. In various implementations, the number of straight edges used to approximate the corner as well as the orientation of the one or more straight edges is determined based upon the characteristics of the corner, such as, the corner having an obtuse angle larger than 135 degrees for example. With various implementations, two straight edges are used to approximate the corner, the orientation of the two straight edges being determined by a first point, a second point, and a shared corner point. | 10-21-2010 |
20100275174 | Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method - A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance. | 10-28-2010 |