Class / Patent application number | Description | Number of patent applications / Date published |
714723000 | Error mapping or logging | 74 |
20080263416 | METHOD AND APPARATUS TO ADJUST VOLTAGE FOR STORAGE LOCATION RELIABILITY - According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable. | 10-23-2008 |
20080263417 | Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy - Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief. | 10-23-2008 |
20080320347 | Testing of Integrated Circuits Using Test Module - A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case into a memory using the DMLED test module, loading initialization signatures of fixed pattern into the memory using the DMLED test module, and executing the test case at an operating clock rate of a processor. The method further includes writing result signatures into the memory, and dumping the results signatures from the memory to a tester using the DMLED test module. | 12-25-2008 |
20090049351 | Method for Creating a Memory Defect Map and Optimizing Performance Using the Memory Defect Map - A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation. | 02-19-2009 |
20090132876 | Maintaining Error Statistics Concurrently Across Multiple Memory Ranks - A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank. | 05-21-2009 |
20090172482 | METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE - Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks. | 07-02-2009 |
20090172483 | ON-CHIP FAILURE ANALYSIS CIRCUIT AND ON-CHIP FAILURE ANALYSIS METHOD - An on-chip failure analysis circuit for analyzing a memory comprises a memory in which data is stored, a built-in self test unit which tests the memory, an failure detection unit which detects an failure of output of the memory, an fail data storage unit in which fail data is stored, the fail data including a location of the failure, an failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit. | 07-02-2009 |
20090199059 | Semiconductor memory test device and method thereof - A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit. | 08-06-2009 |
20090217112 | AC ABIST Diagnostic Method, Apparatus and Program Product - A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester. | 08-27-2009 |
20090222703 | Information Processing Apparatus and Nonvolatile Semiconductor Memory Drive - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive. The semiconductor memory drive includes a control module configured to control execution of data read and write on a nonvolatile semiconductor memory in units of a predetermined number of sectors. In a case where a data size of write data from the information processing apparatus main body is less than a data size of the predetermined number of sectors, the control module reads, from the nonvolatile semiconductor memory, data in a predetermined number of sectors including a sector in which the write data is to be written, and in a case where an error is detected in the read data, the control module stores, in a management table, defective sector information which is indicative of a sector storing the data in which the error is detected. | 09-03-2009 |
20090235131 | METHOD AND APPARATUS FOR PROCESSING FAILURES DURING SEMICONDUCTOR DEVICE TESTING - Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory. | 09-17-2009 |
20090249140 | METHOD FOR MANAGING DEFECT BLOCKS IN NON-VOLATILE MEMORY - A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only. | 10-01-2009 |
20090259896 | BAD BLOCK IDENTIFYING METHOD FOR FLASH MEMORY, STORAGE SYSTEM, AND CONTROLLER THEREOF - A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged. | 10-15-2009 |
20100017665 | DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE - During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location. | 01-21-2010 |
20100088559 | COMPUTER SYSTEM AND MEMORY USE SETTING PROGRAM - A computer system including: a memory configured to store various kinds of data; a use setting data memory means for storing use setting data indicating a use of each of a plurality of memory blocks into which the memory is divided by a certain length; a memory diagnosis means for diagnosing the memory so as to detect a bad area in each of the memory blocks; and a memory use setting means for setting the use setting data of each of the memory blocks stored in the use setting data memory means in accordance with a result of detecting the bad area in each of the memory blocks by means of the memory diagnosis means. | 04-08-2010 |
20100107022 | BAD PAGE MARKING STRATEGY FOR FAST READOUT IN MEMORY - A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit. | 04-29-2010 |
20100125767 | METHOD FOR TESTING RELIABILITY OF SOLID-STATE STORAGE MEDIUM - A method for testing a reliability of a solid-state storage medium is provided, wherein the solid-state storage medium has a plurality of blocks. First, a lifetime of each of the blocks of the solid-state storage medium is obtained. Then, an erase count of each of the blocks is obtained, and whether the erase count is greater than a predetermined erase count is determined. After that, those blocks having their erase counts greater than the predetermined erase count are accumulated to generate a problematic block number, and a test report is output. | 05-20-2010 |
20100131812 | Resizable Cache Memory - A resizable cache memory is disclosed. In a particular embodiment, a system is disclosed and includes a Built-In Self Test (BIST) circuit configured to test a cache memory. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit. | 05-27-2010 |
20100192029 | Systems and Methods for Logging Correctable Memory Errors - In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM. | 07-29-2010 |
20100211837 | Semiconductor test system with self-inspection of memory repair analysis - A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein. | 08-19-2010 |
20100251044 | SYSTEM AND METHOD FOR USING A MEMORY MAPPING FUNCTION TO MAP MEMORY DEFECTS - A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective. | 09-30-2010 |
20100306605 | Apparatus and Method for Manufacturing a Multiple-Chip Memory Device - A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors. | 12-02-2010 |
20100325497 | USING FRACTIONAL SECTORS FOR MAPPING DEFECTS IN DISK DRIVES - Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms. | 12-23-2010 |
20100332926 | APPARATUS FOR FORMATTING INFORMATION STORAGE MEDIUM - An apparatus according to the present invention is designed to perform formatting processing on an information storage medium. The storage medium has a data storage area including a user data area and a spare area. The user data area is provided to write user data on, while the spare area includes a replacement block to be used as a replacement for a block that has been detected as a defective block. The replacement block stores instruction information that instructs to read data from the defective block when data is read from the replacement block. The apparatus includes a control section for controlling the formatting processing. In performing the formatting processing, the control section updates information stored in the replacement block such that when data is read from the replacement block, the data is not read from the defective block. | 12-30-2010 |
20110066903 | DYNAMIC RANDOM ACCESS MEMORY HAVING INTERNAL BUILT-IN SELF-TEST WITH INITIALIZATION - A method for self-contained testing within a DRAM comprises the DRAM receiving an instruction from an external processor to test a memory core on the DRAM, and the DRAM self-testing the memory core with one or more BIST pattern stored in a multipurpose register on the DRAM. Optionally, the step of self-testing may include writing the BIST pattern into all locations of the memory core, reading each location of the memory core, and comparing the content read from each location of the memory core with the BIST pattern, wherein a negative comparison indicates a failure has occurred. In a further option, the method may further comprise, after testing the DRAM, initializing the DRAM with an INIT pattern stored in the multipurpose register on the DRAM. | 03-17-2011 |
20110154138 | FAILURE ANALYSIS METHOD, FAILURE ANALYSIS APPARATUS, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, electrical test results of a semiconductor memory arrayed in a logical address order are stored in a first memory secured in a main memory, a plurality of second memory areas in each of which loading and storing of each data in a unit size is performed is secured in the main memory, FBMs in which pass/fail information is arrayed in a physical address order are generated based on different parts of the electrical test results stored in the first memory area, respectively, the FBMs generated from the different parts of the electrical test results are stored in the second memory areas, respectively, and the FBMs stored in the second memory areas, respectively, are output. | 06-23-2011 |
20110167308 | MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS - A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. | 07-07-2011 |
20110179324 | TESTING APPARATUS AND METHOD FOR ANALYZING A MEMORY MODULE OPERATING WITHIN AN APPLICATION SYSTEM - A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis. | 07-21-2011 |
20110197101 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor device includes a first management area storing a plurality of inspection results, the plurality of inspection results being obtained by executing inspections for each of a plurality of storage areas which store a plurality of data; and a second management area storing the plurality of inspection results. The first and second management areas are independent from each other. | 08-11-2011 |
20110239064 | MANAGEMENT OF A NON-VOLATILE MEMORY BASED ON TEST QUALITY - Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. The NVM may be managed based on results of a test performed on the NVM. The test may indicate, for example, physical memory locations that may be susceptible to errors, such as certain pages in the blocks of the NVM. Tests on multiple NVMs of the same type may be compiled to create a profile of error tendencies for that type of NVM. In some embodiments, data may be stored in the NVM based on individual test results for the NVM or based on a profile of the NVM type. For example, memory locations susceptible to error may be retired or data stored in those memory locations may be protected by a stronger error correcting code. | 09-29-2011 |
20110239065 | RUN-TIME TESTING OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for performing run-time tests on a non-volatile memory (“NVM”), such as flash memory. The run-time tests may be tests that are performed on the NVM while the NVM can be operated by an end user (as opposed to during a manufacturing phase). In some embodiments, a controller for the NVM may detect an error event that may be indicative of a systemic failure of a die of the NVM. The controller may then select one or more blocks in the die to test, which may be dies that are currently not being used to store user data. The controller may post process the results of the test to determine whether there is a systemic failure, such as a column failure, and may treat the systemic failure if there is one. | 09-29-2011 |
20110296261 | APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT - Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address. | 12-01-2011 |
20110320892 | MEMORY ERROR ISOLATION AND RECOVERY IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error. | 12-29-2011 |
20120036405 | FAILURE ANALYZING DEVICE AND FAILURE ANALYZING METHOD - According to one embodiment, a failure analyzing device includes a classifying unit that classifies a failure type in a fail bit map corresponding to each layer, a storage unit that stores a rule to combine failed cells of different layers, and a determining unit that groups a classification result matched with the rule among classification results based on the classifying unit. The rule includes a base point failure, an association failure becoming a combination object of the base point failure, a combination condition defining a relationship between the base point failure and the association failure, and a combination failure name. The determining unit extracts the base point failure from the classification result of one layer, extracts the association failure matched with the combination condition from the classification results of the other layers, groups the extracted base point failure and association failure, and provides the combination failure name. | 02-09-2012 |
20120072796 | MEMORY CONTROLLER WITH AUTOMATIC ERROR DETECTION AND CORRECTION - A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines. | 03-22-2012 |
20120084611 | Apparatus, System, and Method for Bad Block Remapping - An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm. | 04-05-2012 |
20120131399 | APPARATUS AND METHODS FOR TESTING MEMORY CELLS - Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array. | 05-24-2012 |
20120204071 | WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES - Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses. | 08-09-2012 |
20120221904 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes a first storage unit configured to store a plurality of first fault address information provided in a first test operation, a second storage unit configured to store a plurality of second fault address information provided in a second test operation which is performed later than the first test operation; a redundancy operation unit configured to, in performing a redundancy operation, determine the number of operation circuits corresponding to the first fault address information and the number of operation circuits corresponding to the second fault address information among a plurality of redundancy operation circuits based on address number information; and an address providing unit configured to read the plurality of first fault address information and the plurality of second fault address information, and sequentially provide the read information to the redundancy operation unit, wherein the address providing unit is further configured to detect the number of the first fault address information and generate the address number information. | 08-30-2012 |
20120221905 | Managing Memory Faults - Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received. | 08-30-2012 |
20120254680 | NONVOLATILE MEMORY DEVICE AND BAD AREA MANAGING METHOD THEREOF - Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area. | 10-04-2012 |
20120260138 | ERROR LOGGING IN A STORAGE DEVICE - The present disclosure provides a method for operating a storage drive. The method includes receiving a storage command from an initiator and generating an error in response to the storage command. The method also includes adding a check condition data parameter to a check condition log stored to a storage media of the storage drive. The check condition data parameter comprises a physical memory address corresponding to a physical location of a storage element corresponding to the error. | 10-11-2012 |
20120260139 | Firmware Monitoring of Memory Scrub Coverage - Mechanisms are provided in which firmware verifies he entire system's memory scrub coverage through some additional memory controller (MC) registers/attentions and builds up a processor runtime diagnostic (PRD) scrub coverage table during every scrub cycle. Firmware may go through the scrub coverage table rank-by-rank on a periodic basis to determine whether any ranks had not been covered by hardware scrubbing. Firmware may initiate a targeted scrub and diagnostic for all of the ranks that did not have adequate scrub coverage. If for some reason the system still has some memory ranks that have not been covered by the initial hardware scrub and the targeted scrub, then the firmware may perform some course of action for fault isolation. | 10-11-2012 |
20130007544 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 01-03-2013 |
20130007545 | MANAGING LOGICALLY BAD BLOCKS IN STORAGE DEVICES - At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block. | 01-03-2013 |
20130139012 | APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT - Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address. | 05-30-2013 |
20130151914 | FLASH ARRAY BUILT IN SELF TEST ENGINE WITH TRACE ARRAY AND FLASH METRIC REPORTING - A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array. | 06-13-2013 |
20130173975 | METHOD OF TESTING FLASH MEMORY - A method of testing a flash memory is applied to retrieve the flash memory available by picking up a defective flash memory. The flash memory includes at least a block, a page, and a cell. The method comprises inputting a test command into the flash memory to execute at least one of write, read, or compare of the flash memory. After the test command is executed, the states of the block, page, and cell in the flash memory may be obtained. The states are marked in a flash memory distribution list to allow a controller to access at least one of the normal block, page, and cell from the list. Thus, in the method, the normal block, page, and cell may be obtained. | 07-04-2013 |
20130179740 | MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS - Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed. | 07-11-2013 |
20130283110 | CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE - A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element. | 10-24-2013 |
20140047291 | AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES - A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells. | 02-13-2014 |
20140115411 | APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT - Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address. | 04-24-2014 |
20140237307 | GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE - A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler. | 08-21-2014 |
20140289575 | SYSTEMS AND METHODS FOR TESTING PAGES OF DATA STORED IN A MEMORY MODULE - A memory module including a first memory, a second memory, a test module, and a control module. The first memory is configured to store pages of data to be tested for errors. The second memory is configured to store addresses for the pages of data and store copies of the pages of data. The test module is configured to perform testing on the pages of data stored in the first memory. The control module is configured to, prior to the testing being performed by the test module on the pages of data stored in the first memory, cause the second memory to store the addresses and the copies of the pages of data stored in the first memory and, subsequent to the testing being performed by the test module, store the copies of the pages of data to the first memory based on the addresses stored in the second memory. | 09-25-2014 |
20140304561 | SHARED FUSE WRAPPER ARCHITECTURE FOR MEMORY REPAIR - A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture. | 10-09-2014 |
20140372816 | ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE - A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device. | 12-18-2014 |
20150019926 | MANUFACTURING TESTING FOR LDPC CODES - An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding. | 01-15-2015 |
20150067421 | DISPERSED STORAGE WITH VARIABLE SLICE LENGTH AND METHODS FOR USE THEREWITH - A dispersed storage processing unit selects a slice length for a data segment to be stored in a dispersed storage network (DSN). The data segment is encoded using a dispersed storage error coding function to produce a set of data slices in accordance with the slice length. A storage file is selected based on the slice length. A storage file identifier (ID) is generated that indicates the storage file. A set of DSN addresses are generated corresponding to the set of data slices, wherein the set of DSN addresses each include the storage file ID and a corresponding one of a plurality of offset identifiers (IDs). The set of data slices are written in accordance with the set of DSN addresses. A directory is updated to associate the set of DSN addresses with an identifier of the data segment. | 03-05-2015 |
20150074476 | DATA STORING SYSTEM AND OPERATING METHOD THEREOF - A data storing system performs a test operation on a memory block on which a read operation is determined to be failed, and determines whether the memory block is or is not a bad block based on a result of the test operation. The data storing system may improve reliability and yield of a device. | 03-12-2015 |
20150082106 | MEMORY DEVICES, TESTING SYSTEMS AND METHODS - Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested. | 03-19-2015 |
20150121157 | Selection of Data for Redundancy Calculation By Likely Error Rate - Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. | 04-30-2015 |
20150128000 | METHOD OF OPERATING MEMORY SYSTEM - In a method of operating a memory system including a memory device and a memory controller, the memory controller reads fail information from a fail info region included in the memory device. The memory controller maps a logical address related to a program to a physical address of a safe region based on the fail information to store the program in the safe region except the fail info region and a fail region included in the memory device. The memory controller loads the program into the safe region of the memory device according to the address mapping. The method of operating the memory system according to example embodiments increases the performance of the memory system. | 05-07-2015 |
20150135028 | LEVERAGING CHIP VARIABILITY - Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc. | 05-14-2015 |
20150143187 | IMPLEMENTING ENHANCED PERFORMANCE WITH READ BEFORE WRITE TO PHASE CHANGE MEMORY - A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified. | 05-21-2015 |
20150143188 | METHODS FOR ACCESSING A STORAGE UNIT OF A FLASH MEMORY AND APPARATUSES USING THE SAME - An embodiment of a method for accessing a storage unit of a flash memory, performed by a control unit, is disclosed to include at least the following steps. A transaction is appended to a bad-column table each time a bad column of a block within the storage unit is inspected. It is determined whether a total number of the transactions within the bad-column table is odd when the control unit determines that the last column of the block is a regular column. A transaction is appended to the bad-column table to indicate that the last column of the block is a bad column when the control unit determines that the total number of the transactions within the bad-column table is odd. | 05-21-2015 |
20150293854 | DYNAMIC REMAPPING OF CACHE LINES - A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index. | 10-15-2015 |
20150348649 | BIT ERROR RATE MAPPING IN A MEMORY SYSTEM - A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program. | 12-03-2015 |
20150364217 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - A semiconductor device includes a latch circuit suitable for storing a test result; a non-volatile memory circuit suitable for staring information used for an operation of the semiconductor device; a decoding unit suitable for generating one or more internal program commands by using one or more control signals; and a control unit suitable for programming information in the non-volatile memory circuit in response to the test result stored in the latch circuit when the internal program commands are activated. | 12-17-2015 |
20160035436 | APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE - Subject matter described pertains to apparatuses and methods for operating a memory device. | 02-04-2016 |
20160042762 | DETECTION OF LOGICAL CORRUPTION IN PERSISTENT STORAGE AND AUTOMATIC RECOVERY THEREFROM - A method, system, and computer program product for restoring blocks of data stored at a corrupted data site using two or more mirror sites. The method commences by receiving a trigger event from a component within an application server environment where the trigger event indicates detection of a corrupted data site. The trigger is classified into at least one of a plurality of trigger event types, which trigger event type signals further processing for retrieving from at least two mirror sites, a first stored data block and a second stored data block corresponding to the same logical block identifier from the first mirror site. The retrieved blocks are compared to determine a match value, and when the match value is greater than a confidence threshold, then writing good data to the corrupted data site before performing consistency checks on blocks in physical or logical proximity to the corrupted data site. | 02-11-2016 |
20160042810 | METHOD OF REPAIRING NON-VOLATILE MEMORY BASED STORAGE DEVICE AND METHOD OF OPERATING ELECTRONIC SYSTEM INCLUDING THE STORAGE DEVICE - A method of repairing a storage device including a non-volatile memory includes powering on the storage device, performing a booting sequence, determining whether an error has occurred during the booting sequence or during a normal mode, writing a failure signature to a predetermined signature address in the non-volatile memory upon determining that the error has occurred, reporting a failure to a host upon writing the failure signature, entering into a repair mode upon reporting the failure, and operating in the normal mode upon determining that the error has not occurred. | 02-11-2016 |
20160078966 | METHOD OF PERFORMING WEAR MANAGEMENT IN NON-VOLATILE MEMORY DEVICES - A method is provided for performing wear management in a non-volatile memory device which includes a plurality of storage units. A first error count associated with the amount of error bits generated in a specific storage unit during a first access is acquired. A second error count associated with an amount of error bits generated in the specific storage unit during a second access is retrieved, wherein the second access occurs earlier than the first access. An early retirement threshold is set to a first value when the difference between the first error count and the second error count does not exceed the predetermined value, or set to a second value smaller than the first value when the difference between the first error count and the second error count exceeds the predetermined value. The specific storage unit is marked as a bad storage unit when the first error count exceeds the early retirement threshold. | 03-17-2016 |
20160139976 | MEMORY DEVICE WITH SECURE TEST MODE - A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device. | 05-19-2016 |
20160155514 | SYSTEM AND METHOD OF TESTING AND IDENTIFYING MEMORY DEVICES | 06-02-2016 |