Class / Patent application number | Description | Number of patent applications / Date published |
714710000 | Replacement of memory spare location, portion, or segment | 54 |
20080215936 | Non-chronological AV-stream recording - The invention relates to a method for storing of a sequence of data elements in sequence of sectors on a storage medium and a corresponding method for reproducing a sequence of data elements read from a sequence of sectors on a storage medium. | 09-04-2008 |
20080229161 | MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF - Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure. | 09-18-2008 |
20090077434 | STATUS OF OVERALL HEALTH OF NONVOLATILE MEMORY - A nonvolatile memory system includes nonvolatile memory organized into blocks, one or more of which are designated as spare blocks and one or more of which may be defective at the time of manufacturing of the nonvolatile memory. A controller device is coupled to the nonvolatile memory for measuring the health status of the nonvolatile memory by determining the number of growing defects on an on-going basis. | 03-19-2009 |
20090187798 | NONVOLATILE MEMORY HAVING NON-POWER OF TWO MEMORY CAPACITY - A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device. | 07-23-2009 |
20090265588 | SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL - A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer. | 10-22-2009 |
20090282301 | APPARATUS, SYSTEM, AND METHOD FOR BAD BLOCK REMAPPING - An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm. | 11-12-2009 |
20100205489 | JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 08-12-2010 |
20100281315 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 11-04-2010 |
20100293420 | CACHE COHERENT SUPPORT FOR FLASH IN A MEMORY HIERARCHY - System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region. | 11-18-2010 |
20110035635 | JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 02-10-2011 |
20110161749 | READING METHOD AND APPARATUS FOR AN INFORMATION RECORDING MEDIUM AND SPARE AREA ALLOCATION THEREOF - A reading apparatus for reading an information recording medium is provided. The information recording medium has a user data area for recording data and a spare area for recording replacements corresponding to registered defects of the user data area. The reading apparatus comprising a first storage device for storing the data read from the user data area, a second storage device for storing replacements, and a replacement controller for searching a corresponding replacement in the second storage device when a registered defect is found in the user data area, while reading the corresponding replacement and neighboring replacements thereof from the spare area of the information recording medium and storing the read replacements into the second storage device when the corresponding replacement is failed to be found in the second storage device. | 06-30-2011 |
20110161750 | Pre-Code Device, and Pre-Code System and Pre-Coding Method Thereof - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 06-30-2011 |
20110161751 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH MEMORY REPAIR CIRCUIT - A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit | 06-30-2011 |
20110179319 | FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES - An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors. | 07-21-2011 |
20110209011 | METHOD FOR ERROR TEST, RECORDATION AND REPAIR - In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell. | 08-25-2011 |
20120066560 | ACCESS METHOD OF VOLATILE MEMORY AND ACCESS APPARATUS OF VOLATILE MEMORY - An access method of a volatile memory accesses the volatile memory via a block access fashion. The volatile memory includes a plurality of blocks. The method includes: performing a reading operation for a block having at least one known bad cell among the blocks, which includes reading a block data and an error correction code data corresponding to the block and applying the ECC data to correct data read from the at least one known bad cell to generate a corrected block data. | 03-15-2012 |
20120096321 | BLOCK MANAGEMENT METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A block management method for managing physical blocks of a rewritable non-volatile memory, and a memory controller and a memory storage apparatus using the same are provided. The method includes grouping the physical blocks into at least a data area, a free area, and a replacement area, and grouping the physical blocks of the data area and the free area into a plurality of physical units. The method also includes when one of the physical blocks belonging to of the physical units of the data area becomes a bad physical block, getting a physical block from the replacement area and replacing the bad physical block with the gotten physical block. The method further includes associating a physical unit that contains no valid data in the free area with the replacement area. Thereby, the physical blocks can be effectively managed and the access efficiency can be improved. | 04-19-2012 |
20120221902 | BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION - The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells. | 08-30-2012 |
20120297257 | MEMORY DEVICES AND METHOD FOR ERROR TEST, RECORDATION AND REPAIR - In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell. | 11-22-2012 |
20120297258 | Apparatus, System, and Method for Bad Block Remapping - An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm. | 11-22-2012 |
20120324298 | MEMORY DEVICE REPAIR APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed. | 12-20-2012 |
20120324299 | FLASH STORAGE WEAR LEVELING DEVICE AND METHOD - A flash storage device performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data. | 12-20-2012 |
20130007541 | PREEMPTIVE MEMORY REPAIR BASED ON MULTI-SYMBOL, MULTI-SCRUB CYCLE ANALYSIS - An apparatus includes a processor, a memory, and an error module operable on the processor. The error module is configured to perform a memory scrub of the memory across a scrub cycle of multiple scrub cycles. The error module is configured to identify correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The error module is configured to perform an analysis across the multiple scrub cycles, wherein the analysis comprises a determination whether at least two symbols across the multiple scrub cycles have at least one correctable error. The error module is configured to responsive to a determination that at least two symbols across the multiple scrub cycles have at least one correctable error, execute at least one repair of the memory that includes the section of memory. | 01-03-2013 |
20130007542 | PREEMPTIVE MEMORY REPAIR BASED ON MULTI-SYMBOL, MULTI-SCRUB CYCLE ANALYSIS - In some example embodiments, a method includes performing a memory scrub of a memory across a scrub cycle of multiple scrub cycles. The method includes identifying correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The method also includes performing an analysis across the multiple scrub cycles, wherein the performing of the analysis comprises determining whether at least two symbols across the multiple scrub cycles have at least one correctable error. The method includes responsive to determining that at least two symbols across the multiple scrub cycles have at least one correctable error, executing at least one repair of the memory that includes the section of memory. | 01-03-2013 |
20130061100 | Field-Repair System and Method - With increasing capacity, testing of three-dimensional mask-programmed read-only memory (3D-MPROM) becomes too time-consuming and expensive. Accordingly, the present invention discloses a field-repair system. Most of the 3D-MPROM data are not checked in the factory, but checked and repaired in the field. The field-repair system comprises a playback device with a communicating means. The playback device checks the 3D-MPROM data as they are read out. When bad data are detected, the good data to replace the bad data are fetched from a remote server with the communicating means. The remote server stores at least a copy of the content being read. | 03-07-2013 |
20130117615 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS - In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells. | 05-09-2013 |
20130173970 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR - A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. | 07-04-2013 |
20130227361 | HARDWIRED REMAPPED MEMORY - Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device. | 08-29-2013 |
20130227362 | SYSTEMS AND METHODS OF USING DYNAMIC DATA FOR WEAR LEVELING IN SOLID-STATE DEVICES - Methods and systems for wear-leveling in flash storage devices are provided. A flash storage system performs wear-leveling by tracking data errors that occur when dynamic data is read from a first storage block in a first flash storage device and moving the dynamic data to a second storage block in a second flash storage device. Additionally, wear-leveling is achieved by identifying a third storage block containing static data and moves the static data to the storage block previously containing the dynamic data. | 08-29-2013 |
20130232384 | METHOD AND SYSTEM FOR ITERATIVELY TESTING AND REPAIRING AN ARRAY OF MEMORY CELLS - A memory system includes an array of memory cells and a repair module. Multiple memory cells in the array are redundant to other memory cells in the array. The repair module iteratively tests the array. During the iterative testing of the array, the repair module, during each test of the array, (i) identifies one or more defective memory cells in the array, if any, and (ii) in response to one or more defective memory cells being identified during the test, respectively replaces the one or more defective memory cells with one or more memory cells that are redundant to other memory cells in the array. The repair module performs the iterative testing of the array until (i) the repair module does not detect a defective memory cell or (ii) no memory cells of the memory cells that are redundant remain available for replacement of a defective memory cell. | 09-05-2013 |
20130332783 | INTEGRITY OF AN ADDRESS BUS - A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus. | 12-12-2013 |
20140082438 | ONE-TIME PROGRAM CELL ARRAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability. | 03-20-2014 |
20140298119 | METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias. | 10-02-2014 |
20140317460 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND BUILT-IN SELF-TESTING - A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively. | 10-23-2014 |
20140359382 | MEMORY CONTROLLER AND OPERATING METHOD PROVIDING REPLACEMENT BLOCK FOR BAD BLOCK - An operating method for a memory controller that controls operation of a nonvolatile memory device that stores data according to a plurality of multiple blocks includes; determining that a block among the plurality of blocks is a bad block, and then determining a type of the bad block, determining a number of free blocks, and providing a replacement block to the nonvolatile memory device for the bad block using a replacement block provision policy that is responsive to the type of the bad block and the number of free blocks. | 12-04-2014 |
20150039948 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes: a nonvolatile memory device comprising a plurality of memory blocks, each including a plurality of pages; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller determines whether or not a memory block including damaged pages in which stored data are damaged occurs in the memory blocks, sets a memory block including the damaged pages to an invalid memory block based on the determination result, and regenerates free pages of the memory block set as the invalid memory block into a valid memory block. | 02-05-2015 |
20150046761 | SYSTEM AND METHOD FOR GENERATING FIELD REPLACEABLE UNIT INFORMATION FILES - Technologies are described herein for generating field replaceable unit (FRU) information files in a format that is readable by a management controller in accordance with IPMI such that the FRU and the management controller are interoperable. In particular, a FRU installation station is in operative communication with a general purpose computer comprising a FRU information conversion module. A script utilized by the FRU information conversion module is configured to receive FRU information relating to a specified FRU and convert the information FRU binary files or a FRU image binary. The FRU binary files or FRU image binary are then received by the FRU installation station where they are subsequently transmitted to the inventory device of the specified FRU storage space according to the specified IPMI standard. | 02-12-2015 |
20150074474 | SYSTEM AND METHOD FOR ON-THE-FLY INCREMENTAL MEMORY REPAIR - A device for repairing a memory device may include spare memory blocks that may replace corresponding memory blocks that include at least one non-operational memory cell. One or more registers may be coupled in a chain to store memory repair information. A memory repair module may identify, upon a power-up test of the memory device, non-operational memory cells, which are incremental to previously identified defective memory cells in previous power-up tests, and may provide corresponding memory repair information of the identified non-operational memory cells. A logic circuit may block access to one or more registers and may facilitate storing, in one or more unblocked registers, the corresponding memory repair information of the identified one or more non-operational memory cells. The memory repair module may swap a memory block including the identified non-operational memory cells with a spare memory block based on content of the one or more unblocked registers. | 03-12-2015 |
20150100837 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a memory cell array including a normal region for storing a plurality of data, an error information region for storing a plurality of error information data corresponding to the plurality of normal data, respectively, and a redundancy region for replacing the normal region, an error detection unit suitable for detecting an error on the plurality of data in response to the plurality of error information data, and storing an error location information, which indicates a storage region of a data having an error in the normal and redundancy regions, based on an error detection result, and a repair operation unit suitable for replacing the storage region, which is indicated by the error location information, by the redundancy region during a repair operation period. | 04-09-2015 |
20150331623 | METHOD AND APPARATUS FOR USING A DEFECTIVE DYNAMIC READ-ONLY MEMORY REGION - Methods and apparatus for using a defective dynamic read-only memory region are provided. In an example, a defective Dynamic Random Access Memory (DRAM) page is used, instead of being disabled. A compress-and-store technique uses a non-defective region of a defective DRAM page to store page-swapping data. This allows the defective DRAM page to be used as a fast swapping resource, which results in increasing system performance, saving materials, saving time, and saving energy. In an example, a method for using a defective DRAM page in a DRAM includes using an error history table to determine that the defective DRAM page has a defective block, and updating a defect table with an address of the defective block. The defect table is used to determine an address of a good block in the defective DRAM page. Page swap data is compressed and stored in the good block in the defective DRAM page. | 11-19-2015 |
714711000 | Spare row or column | 14 |
20080244340 | TEST APPARATUS AND SELECTION APPARATUS - There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns. The test apparatus includes a testing section, a flag memory that stores thereon a flag indicating whether each column is defective, a counter memory that stores thereon the number of defective blocks in association with each column, a failure writing section that writes a flag indicating that a column is defective into the flag memory under a condition that one of the following conditions is satisfied: when a test result indicates that the column is defective; and when a flag stored on the flag memory in association with the column indicates that the column is defective, a counting section that increments the number of defective blocks stored on the counter memory in association with the column under a condition that the test result indicates that the column is defective and the flag indicating that the column is defective is not stored on the flag memory in association with the column, and a selecting section that selects columns to be replaced with the repairing columns based on the number of defective blocks stored in association with each column. | 10-02-2008 |
20090006911 | DATA REPLACEMENT PROCESSING METHOD - A data replacement processing method is disclosed. In the present invention, buffering and decoding are not interrupted when a data block to be replaced is found. The data block to be replaced can be a defect or a remapped block. The data block to be replaced is not processed until it is requested to be transferred. When the data block to be replaced is to be transferred, transferring is stopped and the data block to be replaced is processed. Therefore, efficiency of the optical disc drive can be promoted since interruption number of the buffering and decoding is decreased. In addition, the optical disc will not execute redundant processing for data blocks to be replaced which are not requested to be transferred. | 01-01-2009 |
20090106607 | Method and Apparatus for SRAM Macro Sparing in Computer Chips - SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros. | 04-23-2009 |
20090132873 | Method and System for Determining Element Voltage Selection Control Values for a Storage Device - A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization. | 05-21-2009 |
20090319839 | Repairing memory arrays - A memory array comprising a plurality of rows and a plurality of columns, each row comprising at least one addressable word, said memory array comprising at least one redundant row and at least one redundant column; error detection circuitry for analysing said memory array, by addressing words within said memory array and detecting errors within said addressed words; error repair circuitry for selecting for a detected error either a redundant row or a redundant column to replace one of said row or column containing said error; wherein said error repair circuitry is configured to determine for said detected error whether said error is a single error bit in said addressed word or whether it is one of a plurality of error bits within said word, and if said error is said one of said plurality of errors, said error repair circuitry is configured to preferentially select a redundant row rather than a redundant column to repair said error. | 12-24-2009 |
20100017663 | DATA PROCESSING CIRCUIT AND METHOD - A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the target page data are saved as a first codeword and a second codeword. An errata locator polynomial is obtained according to the syndrome polynomials, and a first error count and a second error count are obtained according to the errata locator polynomial, the first codeword and the second codeword. A set of reference codes is obtained according to the errata locator polynomial. Read page data are outputted according to the addresses of the programmed-error bits, the first error count and the second error count. The read page data are corrected according to the set of reference codes to obtain corrected read page data. | 01-21-2010 |
20100064186 | METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY - Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair. | 03-11-2010 |
20100070809 | REPAIR BITS FOR A LOW VOLTAGE CACHE - A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit. | 03-18-2010 |
20110041016 | MEMORY ERRORS AND REDUNDANCY - Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list. When another error occurs, it is determined whether its failed address is on the stored list. If it is not, then the error is again assumed to be a soft error, the data at this location is corrected, and the failed address is added to the stored address list, etc. If, however, the failed address is already in the stored failed address list, the error is considered either a latent error or VTR, and is repaired on the fly using on-chip redundancy. | 02-17-2011 |
20110219275 | MEMORY REPAIR SYSTEM AND METHOD - A memory system includes an array of memory cells. The array of memory cells includes redundant memory cells. The redundant memory cells include at least two of a redundant row and a redundant column of memory cells. The repair module is configured to (i) identify at least two of a row and a column of the array of memory cells having non-operational memory cells and (ii) substitute the at least two of the row and the column of the array of memory cells with selected rows or columns of the redundant memory cells based on X predetermined sequences of substitutions. The repair module is configured to detect a failure in the array of memory cells that cannot be repaired using the X predetermined sequences of substitutions, and use an alternative repair sequence to repair the non-operational memory cells based on the detection of the failure. | 09-08-2011 |
20110289368 | MEMORY SYSTEM THAT SUPPORTS PROBALISTIC COMPONENT-FAILURE CORRECTION WITH PARTIAL-COMPONENT SPARING - The disclosed embodiments relate to a memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. During operation, the memory system accesses blocks of data, wherein each block of data includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R−S inner checkbits and S spare bits, and ( | 11-24-2011 |
20130139010 | CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR - A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed. | 05-30-2013 |
20150012784 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 01-08-2015 |
20160062860 | METHOD OF IMPROVING ERROR CHECKING AND CORRECTION PERFORMANCE OF MEMORY - A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used. | 03-03-2016 |