Class / Patent application number | Description | Number of patent applications / Date published |
714056000 | Bus or I/O channel device fault | 25 |
20080276133 | Software-Controlled Dynamic DDR Calibration - A system, device and method are described that provide dynamic calibration of high-speed systems, such as high-speed DDR memory systems. In accordance with certain embodiments of the invention, a DDR controller includes functionality that both initializes settings associated with a data window and dynamically maintains the data window within a defined threshold of operation. In various embodiments, an initial calibration module is provided on the DDR controller for performing a full calibration wherein a data window is initially generated and a center point of the data window is established within a specified threshold. Interrupts may be generated to evaluate the data window and center point and/or recalibrate the data window and center point in response to the evaluation or an interrupt generated from another source, such as a system error or user generated interrupt. If a timer expiration interrupt occurs, the data window and its center point are re-evaluated. | 11-06-2008 |
20090144589 | DEVICE AND METHOD FOR CONTROLLING AN EXECUTION OF A DMA TASK - A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval. | 06-04-2009 |
20090292958 | ELECTRONIC APPARATUS AND STATE NOTIFICATION METHOD - According to one embodiment, an electronic apparatus includes a timing detection module which detects a timing of notification to a user in association with execution of an application, a photographing module which captures an image at the timing of notification, which is detected by the timing detection module, a face image detection module which detects a face image of a person from the image which is captured by the photographing module, a direction detection module which detects a direction of the face on the basis of the face image, a setting module which sets a notification method in accordance with the direction of the face, which is detected by the direction detection module, and a notification module which gives a notice according to the notification method which is set by the setting module. | 11-26-2009 |
20100162054 | DETECTION OF AND RECOVERY FROM AN ELECTRICAL FAST TRANSIENT/BURST (EFT/B) ON A UNIVERSAL SERIAL BUS (USB) DEVICE - An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst controller. The USB core provides serial communications with a host device through a USB data channel. The burst controller is coupled to the USB core. The burst controller detects an EFT/B event and automatically reconnects the USB core to the host device in response to recognition of a suspend state of the USB core by the host device. | 06-24-2010 |
20100268998 | MASTER/SLAVE COMMUNICATION SYSTEM - A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data. | 10-21-2010 |
20100275071 | VALIDATION OF COMPUTER INTERCONNECTS - A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results. | 10-28-2010 |
20100306602 | SEMICONDUCTOR DEVICE AND ABNORMALITY DETECTING METHOD - A semiconductor device comprises: a task state storage configured to store an executing state of a processing task of software executed by a CPU and to output an executing state signal to show the executing state of the processing task; a task validity judging section configured to acquire an interruption signal corresponding to the processing task based on a control of the CPU and the execution state signal, and to output a valid signal when the processing task is executed validly; a clear signal output section configured to output a clear signal in response to the valid signal; and a watchdog timer configured to clear a timer count value when the clear signal is acquired within a prescribed time and to output a reset signal when the clear signal is not acquired within the prescribed time. | 12-02-2010 |
20110209009 | Distributed Memory Usage for a System Having Multiple Integrated Circuits Each Including Processors - A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol. | 08-25-2011 |
20120036401 | SELECTION OF A DOMAIN OF A CONFIGURATION ACCESS - A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs. | 02-09-2012 |
20120102372 | UNIVERSAL SERIAL BUS HUB WITH WIRELESS COMMUNICATION TO REMOTE PERIPHERAL DEVICES - A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer. | 04-26-2012 |
20120278666 | MOBILE DEVICE AND METHOD FOR CORRECTING ERRORS OCCURRING IN ATTENTION COMMANDS OF THE MOBILE DEVICE - In a method for correcting errors occurring in attention (AT) commands of a mobile device, the mobile device includes a first user identity module (UIM) chipset, a second UIM chipset, a buffer and a timer. The method sets a response time for a communication between the first UIM chipset and the second chipset according to an AT command, backups the AT command into the buffer, and counts a communication time using the timer. When the communication time exceeds the response time, the method restarts the first UIM chipset using a watchdog timer and restarts the second UIM chipset by resetting voltage levels of I/O pins of the second UIM chipset. The method further clears the communication data stored in the buffer, reads the AT command from the buffer and resends the AT command to control the first UIM chipset to communicate with the UIM second chipset normally. | 11-01-2012 |
20120290885 | OVERSAMPLED CLOCK AND DATA RECOVERY WITH EXTENDED RATE ACQUISITION - In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value. | 11-15-2012 |
20140250338 | VIRTUAL FUNCTION TIMEOUT FOR SINGLE ROOT INPUT/OUTPUT VIRTUALIZATION CONTROLLERS - Systems and methods presented herein provide for resetting a controller in a Single Root Input/Output Virtualization (SR-IOV) architecture. The architecture includes a physical function that periodically issues a heartbeat command to a physical function of an SR-IOV controller, starts a first timer, determines a firmware failure of the controller upon expiration of the first timer, and issues a command to reset the firmware of the controller. The architecture also includes a plurality of a virtual function drivers coupled to a plurality of virtual functions of the controller. Each virtual function driver periodically issues a heartbeat command to its corresponding virtual function, starts a second timer having a duration that is less than a duration of the first timer, determines a firmware failure of the controller upon expiration of the second timer, and pauses input/output operations to its corresponding virtual function until the firmware of the controller is reset. | 09-04-2014 |
20140281752 | REDUNDANT BUS FAULT DETECTION - A system and method for an approach of detecting faults in a redundant bus system based upon four timers. | 09-18-2014 |
20140281753 | Systems, Apparatuses, and Methods for Handling Timeouts - Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state. | 09-18-2014 |
20140317458 | EMBEDDED RESILIENT BUFFER - Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit. | 10-23-2014 |
20150019919 | STORAGE CONTROL DEVICE AND CONTROL DEVICE FOR DETECTING ABNORMALITY OF SIGNAL LINE - A controller module (CM) includes buffers that feed back signals output using respective signal lines used for mutual communication with other CM, and a first detecting unit and a second detecting unit that detect abnormality such that the levels of the signals output using the signal lines do not change from respective specific levels when each level of the fed-back signals does not coincide with an expected level being a level previously determined according to a predetermined timing. | 01-15-2015 |
20150331773 | SIDEBAND LOGIC FOR MONITORING PCIe HEADERS - Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets. | 11-19-2015 |
20150355989 | SAFETY NODE IN INTERCONNECT DATA BUSES - In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall. | 12-10-2015 |
20160041862 | METHOD AND SYSTEM FOR TIMEOUT MONITORING - Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively. | 02-11-2016 |
20160077799 | CONTROL DEVICE AND CONTROL METHOD - A control device includes a first processor, a relay device, a second processor, and a third processor. The first processor is configured to perform data communications with an electronic device. The relay device is configured to relay the data communications. The relay device includes a buffer for storing data to be transmitted or received in the data communications. The second processor is configured to check a state of the buffer to detect a buffer full state in which the buffer is full. The third processor is configured to check a state of the first processor to detect a halt state in which the first processor has halted. The third processor is configured to reset the relay device upon detecting the halt state and upon the second processor detecting the buffer full state. | 03-17-2016 |
20160117215 | SYSTEM AND METHOD FOR DYNAMIC BANDWIDTH THROTTLING BASED ON DANGER SIGNALS MONITORED FROM ONE MORE ELEMENTS UTILIZING SHARED RESOURCES - A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger level of an unacceptable deadline miss (“UDM”) element of the portable computing device may be determined with a danger level sensor within the UDM element. Next, a quality of service (“QoS”) controller may adjust a magnitude for one or more danger levels received based on the UDM element type that generated the danger level and based on a potential fault condition type associated with the particular danger level. The danger levels received from one UDM element may be mapped to at least one of another UDM element and a non-UDM element. A quality of service policy for each UDM element and non-UDM element may be mapped in accordance with the danger levels. | 04-28-2016 |
20160170823 | CLOUD ALERT TO REPLICA | 06-16-2016 |
20160179610 | ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY | 06-23-2016 |
20160179738 | METHOD, APPARATUS AND SYSTEM FOR INTEGRATING DEVICES IN A ROOT COMPLEX | 06-23-2016 |