Class / Patent application number | Description | Number of patent applications / Date published |
714017000 | Reexecuting single instruction or bus cycle | 19 |
20090063899 | Register Error Correction of Speculative Data in an Out-of-Order Processor - In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit. | 03-05-2009 |
20090113240 | Detecting Soft Errors Via Selective Re-Execution - In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed. | 04-30-2009 |
20090172471 | METHOD AND SYSTEM FOR RECOVERY FROM AN ERROR IN A COMPUTING DEVICE - A method and system for supporting recovery of a computing device includes determining and storing a sub-set of firmware instructions used to establish a pre-boot environment and executing the sub-set of firmware instructions in response to an error. | 07-02-2009 |
20100088544 | ARITHMETIC DEVICE FOR CONCURRENTLY PROCESSING A PLURALITY OF THREADS - A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device | 04-08-2010 |
20100162043 | Method, Apparatus, and System for Restarting an Emulated Mainframe IOP - A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs. | 06-24-2010 |
20100293412 | DATA MIGRATION MANAGEMENT APPARATUS AND INFORMATION PROCESSING SYSTEM - The present invention provides a data migration management apparatus that can easily create a re-execution task for re-executing an error-terminated data migration task, and also can increase the possibility of the re-execution task being successful. In a case where a data migration from a migration-source volume to a migration-destination volume fails, the management apparatus uses the information of the failed task to create a re-execution task. The management apparatus changes the configuration of a volume pair as necessary. The management apparatus manages the failed task in association with the re-execution task. | 11-18-2010 |
20110004788 | HANDLING AND PROCESSING OF MASSIVE NUMBERS OF PROCESSING INSTRUCTIONS IN REAL TIME - A system is designed for processing instructions in real time during a session. This system comprises: a preloader for obtaining reference data relating to the instructions, the reference data indicating the current values of each specified resource account data file, and the preloader being arranged to read the reference data for a plurality of received instructions in parallel from a master database; an enriched instruction queue for queuing the instructions together with their respective preloaded reference data; an execution engine for determining sequentially whether each received instruction can be executed under the present values of the relevant resource account files and for each executable instruction to generate an updating command; and an updater, responsive to the updating command from the execution engine (for updating the master database with the results of each executable instruction, the operation of the plurality of updaters being decoupled from the operation of the execution engine. | 01-06-2011 |
20110060943 | APPARATUS AND METHOD FOR DETECTION AND CORRECTION OF DENORMAL SPECULATIVE FLOATING POINT OPERAND - A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed. | 03-10-2011 |
20110302450 | FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES - A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions. | 12-08-2011 |
20120017116 | MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller. | 01-19-2012 |
20120047398 | Detecting Soft Errors Via Selective Re-Execution - In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed. | 02-23-2012 |
20120304005 | ELECTRONIC APPARATUS - A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point. | 11-29-2012 |
20130151894 | Fault-Tolerant Computer System - A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component. | 06-13-2013 |
20130262926 | RECOVERABLE PARITY AND RESIDUE ERROR - An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced. | 10-03-2013 |
20140136894 | EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK - An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error. | 05-15-2014 |
20140136895 | EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK - An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error. | 05-15-2014 |
20150095700 | ISOLATING A PCI HOST BRIDGE IN RESPONSE TO AN ERROR EVENT - Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices. | 04-02-2015 |
20150113323 | METHOD AND APPARATUS FOR RECOVERING ABNORMAL DATA IN INTERNAL MEMORY - The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit. | 04-23-2015 |
20160041883 | COMPUTER SYSTEM - A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred. | 02-11-2016 |