Entries |
Document | Title | Date |
20080201590 | Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation - A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations. | 08-21-2008 |
20080209244 | Centralized service for awakening a computing device - Various technologies and techniques are disclosed for providing and interacting with a centralized wake service. A server-side wake service is provided that is operable to allow applications to subscribe to the wake service. The wake service receives a wake request directed to a particular computing device from a particular one of the applications. The wake request is forwarded from the wake service to a client-side communication service on the particular computing device if forwarding is determined to be appropriate. When the client-side communication service on the particular computing device receives the wake request while in a reduced power mode, the computing device wakes up and an appropriate response is determined. | 08-28-2008 |
20080209245 | Accounting for Microprocessor Resource Consumption - Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function. | 08-28-2008 |
20080215903 | POWER MANAGEMENT OF NON-VOLATILE MEMORY SYSTEMS - Methods and apparatus for placing a non-volatile memory systems in one of a number of power-down modes in response to events being monitored are useful in reducing power consumption of the non-volatile memory system. The power-down modes provide for successively less functionality, thus providing for successively less power consumption. A non-volatile memory system thus can respond to the events to place the system in a mode that permits the desired operation or a desired response time for subsequent operations while seeking to minimize power consumption. | 09-04-2008 |
20080229129 | Remote Control Save and Sleep Override - An approach is provided that handles a power down signal received by a device. Other types of signals, such as suspend or save and sleep, may also be handled. A device, such as a parent device, sends a power down signal to another device, such as a child device. The power down signal is received by the child device and acted upon, based on the activities currently being executed by the child device. Each activity currently being executed by the child device is handled according to its corresponding setting in an activity list. For example, if the child device is currently executing a preferred activity, the power down signal is ignored. A user of the child device may also send an explanation (or explanations) to the parent device. | 09-18-2008 |
20080250258 | NETWORK PROCESSOR AND ENERGY SAVING METHOD THEREOF - A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed. | 10-09-2008 |
20080263377 | METHOD AND APPARATUS FOR ON-DEMAND POWER MANAGEMENT - An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system. | 10-23-2008 |
20080282100 | INTEGRATED CIRCUIT WITH POWER CONTROL AND POWER CONTROL METHOD THEREOF - Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal. | 11-13-2008 |
20080282101 | Optimum power management of system on chip based on tiered states of operation - Optimum power management of system on chip based on tiered states of operation is disclosed. In one embodiment, a system on chip includes a hardware module including one or more of a microcontroller, a microprocessor, a DSP core, a memory, a timing source, a peripheral, and an external interface to have a real time counter module of the peripheral isolated from a rest of the hardware module using a plurality of voltage level shifting cells and/or a plurality of voltage island cells. Also, the system on chip includes a software module associated with the real time counter module to generate one or more control signals to one or more devices external to the system on chip during a sleep mode of the system on chip. | 11-13-2008 |
20080288797 | Method and apparatus for power reduction on a processor bus - Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals. | 11-20-2008 |
20080288798 | Power management of low power link states - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 11-20-2008 |
20080301479 | METHOD AND SYSTEM FOR MANAGING DATA CENTER POWER USAGE BASED ON SERVICE COMMITMENTS - A method of managing data center power usage based on service commitments. A power and capacity management utility measures performance characteristics of applications hosted by a data center that include power consumption and transaction processing time. When the performance characteristics are above (or below) a first pre-defined target range, the utility decreases (or increases, respectively) a clock rate and processor voltage of one or more active servers. When the performance characteristics are within the first target range and the clock speed is above (or below) a second pre-defined target range, the utility activates (or deactivates, respectively) one or more inactive (or active, respectively) servers. When the size of an inactive server pool is above a third pre-defined target range, the utility moves inactive servers to an unallocated server pool. When the size of the inactive server pool is below the third target range, the utility allocates additional servers. | 12-04-2008 |
20080313478 | MECHANISM TO GATE CLOCK TRUNK AND SHUT DOWN CLOCK SOURCE - An apparatus, method, and system are disclosed. In one embodiment, the apparatus includes a clock source unit that generates a clock signal, multiple clock trunk lines that supply the clock signal to multiple devices, and a clock control unit that instructs the clock source unit that can gate or supply the clock signal on the clock trunk lines. | 12-18-2008 |
20080313479 | Device and Method for Media Access Control - A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method is characterized by monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. | 12-18-2008 |
20090013201 | Method for Reducing Power Consumption of Processor - A method for reducing power consumption of a processor is disclosed comprising steps of applying time-frequency transformation to a plurality of load values of the processor to obtain the feature sampling cycle of the processor, and adjusting the voltage/frequency of the processor based on said feature sampling cycle. With the method of the present invention, the processor load value in next time interval can be accurately predicted, and thus the voltage/frequency of the processor in the next time interval can be adjusted on the basis of the load value. | 01-08-2009 |
20090037754 | BATTERY MODULE, COMPUTER SYSTEM HAVING THE SAME, AND CONTROL METHOD OF THE COMPUTER SYSTEM - A computer system includes a device which operates depending on a clock frequency; a battery unit which comprises a plurality of battery cells and supplies power to the device; a temperature sensor which senses temperature of the battery cells; and a controller which decreases the clock frequency if the sensed temperature is beyond a first preset critical point. | 02-05-2009 |
20090037755 | Microcontroller and control method therefor - Provided is a microcontroller including: a first low-voltage detection circuit to detect that a power supply voltage is equal to or lower than a first voltage value; a second low-voltage detection circuit to detect that the power supply voltage is equal to or lower than a second voltage value, the second voltage value being lower than the first voltage value; a CPU to stop operating when the first low-voltage detection circuit detects that the power supply voltage is equal to or lower than the first voltage value; and a real-time clock to continue operating unless the second low-voltage detection circuit detects that the power supply voltage is equal to or lower than the second voltage value, in which the first low-voltage detection circuit, the second low-voltage detection circuit, the CPU, and the real-time clock are formed on a single chip. | 02-05-2009 |
20090044033 | METHOD FOR COMPUTING POWER SAVINGS AND DETERMINING THE PREFERRED CLOCK GATING CIRCUIT OF AN INTEGRATED CIRCUIT DESIGN - A method for computing the power savings in an integrated circuit (IC) design is disclosed. The method computes the difference in power savings between techniques used for clock gating. Based on the computation results, the method outputs a script to control the implementation tool so as to provide for the best implementation clock gating technique in terms of power and area savings. | 02-12-2009 |
20090049319 | Electronic Power Conversion Circuit - An electronic power conversion circuit is presented for converting an input power to an output power. The circuit comprises at least one conversion block and a clock generator. Each conversion block comprises an input, an output and a plurality of charge storage elements and switches between the input and output. Each block is alternately switchable between a first state in which electric charge is loaded from the input and a second state in which electric charge is supplied as converted power to the output. The clock generator generates clock signals for controlling the switches and thereby switches between the first and second states. The circuit is characterized in that the clock generator comprises at least one input node for receiving at least one input parameter and in that the clock generator is provided for varying the frequency of the clock signals in relation to the at least one input parameter. | 02-19-2009 |
20090055667 | MEMORY CARD WITH POWER SAVING - A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate. | 02-26-2009 |
20090055668 | Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design - A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies. | 02-26-2009 |
20090055669 | METHOD, COMPUTER SYSTEM AND CONTROL DEVICE FOR REDUCING POWER CONSUMPTION - A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result. | 02-26-2009 |
20090070610 | DATA PROCESSOR - The present invention provides a data processor which can reduce the power consumption with the continuous compressed data, such as AV reproduction data, broadcast data or the like, to be reproduced, viewed and listened. | 03-12-2009 |
20090070611 | Managing Computer Power Consumption In A Data Center - Methods, systems, and computer program products are provided for managing computer power consumption in a data center. Embodiments include monitoring aggregate power consumption of a plurality of computers in the data center, each of the computers being supplied power individually from a shared circuit in the data center; determining whether the aggregate power consumption exceeds a predetermined maximum threshold; if the aggregate power consumption exceeds the predetermined maximum threshold, selecting a number of computers for throttling in dependence upon priority; and throttling-down the selected computers, reducing the aggregate power consumption to a level below the predetermined maximum threshold. Some embodiments may also include determining whether the aggregate power consumption is below a predetermined minimum threshold; if the aggregate power consumption is below the predetermined minimum threshold, selecting a number of computers for throttling in dependence upon priority; and throttling-up the selected computers, increasing the aggregate power consumption to a level above the predetermined minimum threshold. | 03-12-2009 |
20090070612 | MEMORY POWER MANAGEMENT - A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation. | 03-12-2009 |
20090089598 | SYSTEM AND METHOD FOR SELECTING OPTIMAL PROCESSOR PERFORMANCE LEVELS BY USING PROCESSOR HARDWARE FEEDBACK MECHANISMS - An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize processor frequency and power/watt usage based on the hardware feedback and processor stall behavior. | 04-02-2009 |
20090106572 | Microcomputer system - A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer. | 04-23-2009 |
20090113222 | TERMINAL HAVING REAL TIME CLOCK (RTC) OPERATOR AND METHOD OF RTC OPERATION USING THE SAME - A method of operating a Real Time Clock (RTC) in a terminal is provided. The method includes detecting a clock signal transmitted to an RTC block when the main power supply is switched off, and supplying a power to the RTC block for its operation by charging and discharging the power periodically supplied from the backup battery according to the detected clock signal. A DC/DC converter connected to a backup battery is periodically switched on and off, and a capacitor is charged and discharged using the power of the backup battery, thereby avoiding supplying power from a backup battery continuously to an RTC block. Therefore, power consumption is reduced and a duration of time for maintaining RTC data is extended. | 04-30-2009 |
20090113223 | APPARATUS AND METHOD FOR POWER SAVING - An apparatus and method for power savings are provided. The apparatus includes a register analysis unit and a register change unit. The register analysis unit determines if registers among bit-switching targeted registers are one of changeable and unchangeable. The register change unit searches for a register pair having a minimum bit switching frequency among registers determined to be changeable, and changes at least one register. | 04-30-2009 |
20090119523 | Managing Power Consumption Based on Historical Average - In one embodiment, an upper power limit and an average power limit are specified for each server of a computer system. Power to each server is controlled so that the instantaneous power consumption does not exceed the upper power limit and the average power consumption does not exceed the average power limit. Servers whose average power consumption is currently less than the average power limit are identified. The instantaneous power consumption of each identified server is temporarily allowed to exceed its average power limit, to maximize server throughput. In cases where the average power limit of a device is reduced, such as may occur during peak energy pricing hours, the instantaneous power consumption of the device may be throttled down below the average power limit until the average power consumption no longer exceeds the average power limit. | 05-07-2009 |
20090119524 | Energy Efficient Ethernet Using Active/Idle Toggling - Generally, this disclosure describes an energy-efficient Ethernet communications approach. In at least one embodiment described herein, an Ethernet controller may be configured to operate in an active power state to transmit or receive data packets at a maximum available link speed. The maximum available link speed may be determined by a negotiation between the Ethernet controller and a link partner coupled to the Ethernet controller. Once the data packets are transmitted or received, the Ethernet controller may be configured to operate in an idle power state to reduce energy consumption. | 05-07-2009 |
20090125737 | Power Management of an Electronic System - A variable group power limit is enforced to limit the net power consumption of a group of devices in a computer system, and a variable device power limit enforced on each device is independently adjustable to satisfy the current group power limit. The device power limits are dynamically selected according to a power management method that selectively reduces the device power limits of lower-utilization devices and increases the device power limits of higher-utilization devices. | 05-14-2009 |
20090125738 | DATA PROCESSING APPARATUS - An access stop control apparatus is provided in a resource control apparatus so that reception of access from a master apparatus is temporarily stopped during changing of a clock frequency and the clock frequency is changed at safe timing. Thereby, the operation of the master apparatus does not need to be stopped during changing of the clock frequency and a period for which access to a resource is stopped can be suppressed. Therefore, execution of an application requiring real-timeness is not affected. | 05-14-2009 |
20090125739 | APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING INFORMATION - A receiving unit receives data from an external network device through a network. A determining unit determines whether a data processing is needed for the data received by the receiving unit. When the determining unit determines that the data processing is needed for the data, a data processing unit performs the data processing on the data. A power control unit switches, according to the data, a power mode of the information processing apparatus between a normal mode in which power is supplied to all components of the information processing apparatus and a power-saving mode in which power supplying is limited to selected components. | 05-14-2009 |
20090132842 | Managing Computer Power Consumption In A Computer Equipment Rack - Methods, systems, and computer program products are provided for managing power consumption of computing devices in a computer equipment rack. Embodiments include monitoring aggregate power consumption of a plurality of computing devices in the computer equipment rack; determining whether the aggregate power consumption exceeds a predetermined maximum threshold; if the aggregate power consumption exceeds the predetermined maximum threshold, selecting a number of computing devices for throttling in dependence upon priority; and throttling-down the selected computing devices computing devices, reducing the aggregate power consumption to a level below the predetermined maximum threshold. Some embodiments may also include determining whether the aggregate power consumption is below a predetermined minimum threshold; if the aggregate power consumption is below the predetermined minimum threshold, selecting a number of computing devices computing devices computing devices for throttling in dependence upon priority; and throttling-up the selected computing devices, increasing the aggregate power consumption to a level above the predetermined minimum threshold. | 05-21-2009 |
20090138737 | APPARATUS, METHOD AND PROGRAM PRODUCT FOR ADAPTIVE REAL-TIME POWER AND PERFOMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS - An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized. | 05-28-2009 |
20090144572 | APPARATUS AND METHOD FOR CONTROLLING VOLTAGE AND FREQUENCY - A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination. The method includes: (i) receiving, at a hardware module, indication of a load of a system; (ii) determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system; and (iii) configuring, by a software module, a voltage source and a clock signal source in response to the determination. | 06-04-2009 |
20090158066 | Power management using automatic load/unload detection of DAC - An automatic load detection system. A first reference signal that may be known apriori can be used for load detection. For example, the first reference signal may be used for invisible portion of a frame. The DAC receives the first reference signal and outputs a signal that is based on the first reference signal. The output of the DAC may have two known values depending on whether the load is coupled to the DAC, e.g., by having a different impedance. Thus, the output signal may be used for detecting whether the load is uncoupled from the DAC. If it is determined that the load is uncoupled from the DAC, the clocking signal to the DAC may be turned off. Thus, DAC no longer consumes power when the load is uncoupled, thereby saving power. | 06-18-2009 |
20090164817 | Interrupt controller - An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request monitoring circuitry in a second domain. The interrupt control circuitry comprises interrupt inputs for receiving interrupt requests and is configured to selectively output a received interrupt request to data processing logic. The interrupt control circuitry is responsive to a low power request signal received by the interrupt controller to communicate interrupt select information to the interrupt request monitoring circuitry prior to the first domain being switched to a low power mode, the interrupt select information identifying interrupt requests which indicate exit from the low power mode. The interrupt request monitoring circuitry comprises a select information store configured to store the select information communicated to the interrupt request monitoring circuitry by the interrupt control circuitry. The interrupt request monitoring circuitry comprises interrupt inputs for receiving the interrupt requests, and is responsive to a received interrupt request identified by the stored interrupt select information as indicating exit from the low power mode to trigger switching of the first domain out of the low power mode. | 06-25-2009 |
20090172437 | Power Switch and Power Supply Using the Same - A power switch includes a power status providing module, a trigger, and a logic circuit. The power status providing module is configured for providing a first signal when being turned on, and for providing a second signal when being turned off. The trigger is configured for providing a first logic voltage when being pushed down, and for providing a second logic voltage when being released. The logic circuit has a data input terminal, a clock input terminal and an output terminal. The data input terminal is configured for receiving the first signal and the second signal to form a data signal. The clock input terminal is configured for receiving the first logic voltage and the second logic voltage to form an operation clock. The output terminal is configured for outputting a power control signal inverse to the data signal according to the operation clock. | 07-02-2009 |
20090177903 | METHOD AND DEVICE FOR POWER MANAGEMENT - A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter. | 07-09-2009 |
20090177904 | Method, system, and apparatus for dynamic clock adjustment - A method, apparatus, article of manufacture, and system, the method including, in some embodiments, determining an impedance of a power distribution network of a load for a range of frequencies, and adjusting a functionality of the load based on a relationship between the impedance of the power distribution network for the range of frequencies and the functionality of the load. | 07-09-2009 |
20090187778 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION DURING PERIODS OF LOW LINK UTILIZATION - A system and method for reducing power consumption during periods of low link utilization. A single enhanced core can be defined that enables operation of subset of parent physical layer devices (PHYs). The subset and parent PHYs can have a fundamental relationship that enables synchronous switching between them depending on the link utilization state. | 07-23-2009 |
20090204830 | POWER MANAGEMENT WITH DYNAMIC FREQUENCY DAJUSTMENTS - A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode. | 08-13-2009 |
20090204831 | GLOBAL HARDWARE SUPERVISED POWER TRANSITION MANAGEMENT CIRCUITS, PROCESSES AND SYSTEMS - An electronic circuit including a bus ( | 08-13-2009 |
20090204832 | METHOD AND APPARATUS FOR ADAPTIVE POWER MANAGMENT OF MEMORY SUBSYSTEM - A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time. | 08-13-2009 |
20090217068 | Structure For Detecting Clock Gating Opportunities In A Pipelined Electronic Circuit Design - A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies. | 08-27-2009 |
20090217069 | Power Management Method for a Multi-Microprocessor System - A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor. | 08-27-2009 |
20090217070 | Dynamic Bus Parking - Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to the power saving message. In one embodiment, the power saving message is issued by de-asserting a bus arbitration signal and the power saving activity can include disabling one or more input buffers of the controller. | 08-27-2009 |
20090222681 | METHODS OF CLOCK THROTTLING IN AN INTEGRATED CIRCUIT - Thermal throttling control to safely throttle clocks OFF and ON in an integrated circuit. Digital thermal throttling control is provided to gradually throttle a clock's frequency from ON to OFF and from OFF to ON. The gradual throttling can minimize an instantaneous current rise that would otherwise occur with a rapid shut OFF and a rapid turn ON of a clock. Included are methods and apparatus for digital thermal throttle control in an integrated circuit. | 09-03-2009 |
20090249097 | OPTIMIZING PERFORMANCE AND POWER CONSUMPTION DURING MEMORY POWER DOWN STATE - Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described. | 10-01-2009 |
20090249098 | Power management for a system on a chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 10-01-2009 |
20090259862 | CLOCK-GATED SERIES-COUPLED DATA PROCESSING MODULES - A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data. | 10-15-2009 |
20090271646 | Power Management Using Clustering In A Multicore System - A multi-core system including cores and voltage sources supplying power to the cores. The cores are divided into clusters based on the particular voltage source supplying power to each core. Power management is performed in the multi-core system based on one or more of core utilization and a management policy. | 10-29-2009 |
20090287944 | System and method of controlling an operating frequency in an electronic system - A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms. Alternatively, the invention enables adaptive adjustment of the operating frequency of an integrated circuit. The invention enables system designers to adaptively optimize either system performance or power consumption on a part-by-part basis in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms. | 11-19-2009 |
20090300388 | Distributed Clock Gating with Centralized State Machine Control - A method, computer program product, and system are provided for controlling a clock distribution network. For example, an embodiment of the method can include programming a predetermined delay time into a plurality of processing elements and controlling an activation and de-activation of these processing elements in a sequence based on the predetermined delay time. The processing elements are located in a system incorporating the clock distribution network, where the predetermined delay time can be programmed in a control register of a clock gate control circuit residing in the processing element. Further, when controlling the activation and de-activation of the processing elements, this activity can be controlled with a state machine based on the system's mode of operation. In controlling the activation and de-activation of the processing elements, the method described above can not only control the effects of di/dt in the system but also shut off clock signals in the clock distribution network when idle, thus reducing dynamic power consumption. | 12-03-2009 |
20090307509 | DYNAMIC CPU VOLTAGE REGULATOR PHASE SHEDDING - A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performance state, adjust active voltage regulator phase, and adjust performance state. The voltage regulator phase shedding system can also include one or more subsystems to read a power measurement, calculate throttling requirements, determine whether to adjust a throttling, lookup voltage regulator information for new performance state capacity, adjust active voltage regulator phase, and adjust throttling. | 12-10-2009 |
20090307510 | PROCESSOR AND POWER CONTROLLING METHOD THEREOF - A processor including a plurality of computation circuit blocks each having a function to perform a computation for each of a plurality of pieces of divided data to be computed, and a function to power on/off each power supply includes a signal value fixing circuit, which is provided for each of the computation circuit blocks, for fixing one or both of signal values of an input and an output of each of the computation circuit blocks, and a power supply control sequencer circuit for instructing each signal value fixing circuit to fix the signal value or to release the signal value from being fixed, and for respectively instructing the computation circuit blocks to power on/off each power supply in a step-by-step manner on the basis of a power supply control signal provided from an instruction controlling circuit for controlling an input of a computation instruction to the processor. | 12-10-2009 |
20090313491 | NOISE REDUCTION APPARATUS AND METHOD OF DYNAMIC POWER MANAGEMENT PROCESSOR - A noise reduction apparatus and method of a processor to which a dynamic power management technique is applied. The noise reduction apparatus includes a mode setting unit for detecting a use state of a processor and setting an operation mode; and a power supply unit for supplying voltage corresponding to the operation mode set by the mode setting unit. The operation mode includes a general mode in which the processor normally operates; a sleep mode in which activity of the processor is suspended; and a low frequency mode in which the processor operates at voltage and clock frequency lower than those of the general mode and higher than those of the sleep mode. The mode setting unit changes between the general mode and the sleep mode, wherein the processor is set to the low frequency mode as an intermediate step. | 12-17-2009 |
20090319812 | CONFIGURING PROCESSORS AND LOADS FOR POWER MANAGEMENT - Controlling processors and processor hardware components in a computing device based on execution load and a power saving preference. The power saving preference relates to responsiveness of the processors versus power consumption of the processors to manage battery life of the device. The processors and processor hardware components may be powered on and off based on a determined execution load for the processors and based on the power saving preference. For example, arithmetic logic units, caches, vectorization units, and units for graphics or multimedia support may be individually enabled or disabled based on the execution load and the power saving preference. | 12-24-2009 |
20100005328 | Integrated Circuit with Modular Dynamic Power Optimization Architecture - A system and method for regulating power consumption within an integrated circuit (IC) with a modular design. The IC is designed so that any one distinct functional module within the IC utilizes only transistors with a substantially same or similar critical voltage level, which may for example be the threshold voltage of the transistors. Consequently, the supply voltage delivered to each functional modules can be lowered to the minimum voltage necessary to enable the transistors within the module to operate. Similarly, modules within the IC may be designed with transistors which share a common value for a substrate bias voltage or a clock speed, or with a combination of common values for several electrical factors. In this way, it is possible to reduce power consumption by fine-tuning the voltages supplied to (or clock speeds driving) specific modules, in a way which is custom-tuned to each module. | 01-07-2010 |
20100011233 | ADAPTIVE POWER CONTROL - A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted. | 01-14-2010 |
20100017634 | DUAL-MODE COMMUNICATION APPARATUS AND POWER MANAGEMENT METHOD THEREOF - A dual-mode communication apparatus and a method thereof are provided. The dual-mode communication apparatus comprises a microprocessor, a first tick generator, a second tick generator, and an operation system tick module that comprises a tick converter and an OS tick generator. The microprocessor receives an OS clock tick to execute a real-time program task. The first tick generator receives a first predetermined number of first clocks to generate a first clock tick when the first clock is active. The second tick generator receives a second predetermined number of second clocks to generate a second clock tick when the second clock is active. The tick converter, coupled to the first and second tick generators, converts the second clock tick such that the converted second clock tick has a converted clock tick rate substantially identical to the clock tick rate of the first clock tick. The OS tick generator, coupled to the tick converter, receives the first clock tick and the converted second clock tick to generate the OS clock tick for use in the microprocessor. | 01-21-2010 |
20100017635 | ZERO INDICATION FORWARDING FOR FLOATING POINT UNIT POWER REDUCTION - A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations. | 01-21-2010 |
20100017636 | POWER SUPPLY SYSTEM - In a power supply system having: a processor | 01-21-2010 |
20100023790 | CPU POWER MANAGEMENT BASED ON UTILIZATION WITH LOWEST PERFORMANCE MODE AT THE MID-UTILIZATION RANGE - A demand-based method and system of a processor power management is described. A processor is caused to enter a particular performance mode based on a first and a second utilization threshold. The particular performance mode includes at least a first performance mode, a second performance mode, and a third performance mode. The processor is caused to operate with a clock frequency in the third performance mode that is lower than the clock frequency of the processor in the first and second performance modes. | 01-28-2010 |
20100058086 | ENERGY-EFFICIENT MULTI-CORE PROCESSOR - Energy-efficient multi-core processor systems are provided. A multi-core processor may include a plurality of processor cores configured to process a task in parallel and at least one of a lowest voltage level and a lowest clock frequency among available voltage levels and clock frequencies is chosen to enable the selected processor cores to complete a task within a task deadline. | 03-04-2010 |
20100058087 | METHOD AND SYSTEM FOR POWER MANAGEMENT FOR A HANDHELD MOBILE ELECTRONIC DEVICE | 03-04-2010 |
20100064156 | VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 03-11-2010 |
20100064157 | ELECTRONIC DEVICE, METHOD FOR CONTROLLING ELECTRONIC DEVICE, AND RECORDING MEDIUM - When a user presses down an extension directing button, a control unit of an image forming apparatus detects the press-down of the extension directing button and executes a setting process of new mode set time. In this case, the control unit calculates the new mode set time by adding extension time extracted from an extension time data storage unit to basic set time acquired from a basic set time data storage unit and records the new mode set time in a mode set time data storage unit. Then, when start of a sleep mode is detected, the control unit of the image forming apparatus records the basic set time, which is extracted from the basic set time data storage unit, in the mode set time data storage unit as new mode set time when the mode set time is extended. | 03-11-2010 |
20100070787 | POWER CAP LOWER BOUND EXPLORATION IN A SERVER ENVIRONMENT - Disclosed is a computer implemented method, computer program product, and apparatus for determining a safe lower bound for a commonly powered data processing system. A power management module operates the data processing system using at least one nominal operating parameter during an exploration periodicity, with the at least one nominal operating parameter being clock speed. The power management module determines whether a calibration period is occurring. The power management module calibrates the data processing system up to a measurement interval duration expiration. The power management module may repeat operating the data processing system using the at least one nominal operating parameter. | 03-18-2010 |
20100077242 | DATA PROCESSOR - In order to reduce an electric power necessary to reproduce data in real time, a data processor includes: a data input unit ( | 03-25-2010 |
20100083020 | INFORMATION PROCESSING SYSTEM AND CONTROL METHOD THEREOF - An information processing system comprising a main system which executes an application, and a subsystem which controls communication with an external apparatus, the information processing system having a power saving mode in which power consumption of the information processing system is reduced, the main system including a power control unit configured to control power consumption of the subsystem, the subsystem including a first communication processing unit configured to communicate with the external apparatus, a second communication processing unit configured to communicate with the external apparatus, and a control unit for the subsystem, wherein when the information processing system shifts to the power saving mode, the power control unit controls power consumption of the subsystem in the power saving mode in accordance with a type of instruction sent from the external apparatus to accept cancellation of the power saving mode. | 04-01-2010 |
20100095142 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING OPERATING FREQUENCY OF AN INFORMATION PROCESSING APPARATUS - An information processing apparatus has a CPU, a clock supply unit configured to supply a clock signal, a CPU idle ratio obtaining unit configured to obtain the idle ratio of the CPU at each predetermined time, a clock control unit configured to determine an operating frequency of the clock signal, and a DMA transfer unit configured to execute a DMA transfer in synchronization with the clock signal supplied from the clock supply unit. The clock control unit controls the operating frequency of the clock signal to the operating frequency determined based on the idle ratio of the CPU if the DMA transfer is not being executed, whereas the clock control unit controls the operating frequency of the clock signal to a predetermined frequency if the DMA transfer is being executed. | 04-15-2010 |
20100106989 | EMBEDDED SYSTEM WITH POWER-SAVING FUNCTIONS AND POWER-SAVING METHOD THEREOF - An embedded system with power-saving functions includes a central processing unit, a detecting and controlling unit, and a clock generating unit. The central processing unit is used for controlling operations of the embedded system. The detecting and controlling unit is used for detecting a designated operating status of the central processing unit to generate a control signal. The clock generating unit is coupled to the detecting and controlling unit and the central processing unit for setting a clock signal to the central processing unit according to the control signal. The designated operating status includes a usage or a loading status of the central processing unit. | 04-29-2010 |
20100131786 | Single Chip 3D and 2D Graphics Processor with Embedded Memory and Multiple Levels of Power Controls - An apparatus and method is provided for data processing where power is automatically controlled with a feed back loop with the host processor based on the internal work load characterized by performance counters. The host automatically adjusts internal frequencies or voltage level to match the work load. The feedback loop allows tuning of frequency or voltage controlling power dissipation. | 05-27-2010 |
20100131787 | Adaptive Power Consumption Techniques - A method for adapting power consumption of a processor based upon an application demand is provided. The method initiates with determining an application demand based upon a current processing operation. Then, a time interval associated with the application demand is determined. Next, unnecessary power consuming functions for the application demand are determined. Then, a clock frequency for the unnecessary power consuming functions is reduced for the time interval. In one embodiment, the power is terminated to the unnecessary power consuming functions. In another embodiment, the clock frequency of the processor is adjusted for at least a portion of the time interval. A program interface for adapting power consumption of a computer system, processor instructions for adapting power consumption of a computer system and a processor are included. | 05-27-2010 |
20100146316 | Optimizing Power Consumption by Tracking How Program Runtime Performance Metrics Respond to Changes in Operating Frequency - A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted. | 06-10-2010 |
20100153759 | POWER GATING TECHNIQUE TO REDUCE POWER IN FUNCTIONAL AND TEST MODES - A method and apparatus of a power gating technique to reduce power in functional and test modes are disclosed. In one embodiment, a method includes separating a power domain of a module to two distinctive sets of sub-power domains, powering a combinational logic with one of the two distinctive sets of power domains, and powering a sequential logic with the other of the two distinctive sets of power domains. The method may reduce an active and leakage power in a functional mode by gating power of the combinational logic and not gating power of the sequential logic. A system state may be retained in the sequential logic because the sequential logic remains powered during the functional mode without requiring a retention flop, an on-chip memory and/or an off-chip memory. A wake up time of the module may be reduced through the retention of the system state in the sequential logic. | 06-17-2010 |
20100162018 | SYSTEM AND METHOD FOR OPTIMIZING ELECTRICAL POWER CONSUMPTION - A system and a method for optimizing power in an electronic device are described. The system may be used to implement low power techniques to achieve maximum performance with low battery utilization. A processing load level monitor monitors load(s) on processors. Processor frequencies are updated through the driver until the load is close to 100%, which means that the core frequency is changed to the load processor around 100% at the minimum possible frequency. | 06-24-2010 |
20100174932 | CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS - The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed. | 07-08-2010 |
20100180134 | APPARATUS AND METHOD FOR POWER SAVING OF BUS INTERFACE IN PORTABLE TERMINAL - An apparatus and a method for power saving in a portable terminal are provided. The method for power saving in the portable terminal includes determining a throughput when processed by a bus, determining a throughput required for a program and selectively controlling a bus clock connected with a modem according to the determined throughput. | 07-15-2010 |
20100185885 | Method and Apparatus for Adjusting a Performance State of a Processor Resource - A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer. | 07-22-2010 |
20100191993 | LOGICAL POWER THROTTLING - A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages. | 07-29-2010 |
20100205468 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION IN SYSTEM ON CHIP - An apparatus and method for reducing power consumption in a System on Chip (SoC) are provided. The SoC includes a clock unit for providing clocks to all elements included in the SoC, a Central Processing Unit (CPU) for controlling the SoC to perform designated functions, a main regulator for supplying power provided from an external battery to remaining elements included in the SoC other than a PMU, and a restoration processor for storing, in the PMU, registration information on the CPU and all peripherals included in the SoC when a transition from an active state to a sleep state is made. The PMU stops provision of a clock from the CPU by controlling the clock unit for stopping provision of all clocks by controlling the clock unit and for controlling the main regulator to be powered off when the restoration processor, wherein the PMU requests the restoration processor to store the registration information, completes the register information storing, when the transition from the sleep state to the active state is made. | 08-12-2010 |
20100218018 | APPLYING POWER MANAGEMENT ON A PARTITION BASIS IN A MULTIPARTITIONED COMPUTER SYSTEM - A partition power policy wizard receives power policy adherence information for at least one of a plurality of logical partitions (LPAR) and calculates a processing units allotment (PUA) for each LPAR based on the power policy adherence information. In one embodiment, a power management policy reduces an operating frequency of one or more processor(s) allocated to a plurality of LPARs. The power policy adherence information, which is input via a graphical user interface (GUI), specifies whether each LPAR is to be impacted by the power management policy, and if so, by how much. The PUA calculated for each LPAR by the partition policy wizard rebalances the processing units allocated to the individual LPARs to accommodate the power policy adherence information input by the user. Preferably, the partition power policy wizard includes a validation mechanism to validate the executability and/or advisability of each PUA so calculated. | 08-26-2010 |
20100218019 | NON-RECURSIVE ADAPTIVE FILTER FOR PREDICTING THE MEAN PROCESSING PERFORMANCE OF A COMPLEX SYSTEM'S PROCESSING CORE - A power management unit and a corresponding method for controlling performance and power consumption of a complex low-power integrated system's processing core by automatically reducing them to a level where outstanding computational operations and software tasks can be performed just in time for further processing. A linear non-recursive adaptive filter performs a processor load prediction of the system's processing core is applied, whose filter coefficients may e.g., be calculated based on the least mean square (LMS) optimization criterion or based on any other similarity measure. In this connection, the adaptive filter may e.g., be used to predict the regularity of the clock frequency in the processing core. By using this information, the linear non-recursive adaptive filter predicts the duration of how long the processing core may lower its operating voltage to still be able to complete all its tasks in time. | 08-26-2010 |
20100218020 | Systems and Methods for Operational Power Management - Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit. | 08-26-2010 |
20100223483 | Information processing apparatus, operation control method and operation control program storage medium - An information processing apparatus having a processing circuit to execute a program by operating at a set operating frequency, including: a measuring section that measures an elapsed time from the user's last operation; a notification section that notifies operation allowing frequencies in the processing circuit and instructs, in response to an elapsed time longer than a predetermined threshold time measured by the measuring section, fixing to a specific low-operating frequency among the operation allowing frequencies and in response to the user's operation in an input section, instructs to release the fixing; and a setting section that selects an operating frequency from among the operation allowing frequencies according to a processing situation and sets the selected operating frequency to the processing circuit and upon release of the fixing, restarts setting of an operating frequency selected from among the operation allowing frequencies, according to a processing situation in the processing circuit. | 09-02-2010 |
20100229011 | Power Reduction in Microcontrollers - The disclosed implementations provide for power reduction in microcontrollers by reactivating a clock in the microcontroller for one or more peripheral modules in response to an internal or external trigger event, thus allowing the one or more peripheral modules to respond to events while operating in a low-power sleep mode. In some implementations, one or more peripheral modules in a microcontroller provide a clock request signal to a clock generator in the microcontroller. In response to the clock request signal, the clock generator reactivates one or more oscillator sources. The clock generator resumes clock generation only for the one or more requesting peripheral modules, keeping power consumption in the microcontroller to a minimum and not disturbing other modules in the microcontroller. | 09-09-2010 |
20100229012 | MICROPROCESSOR THAT PERFORMS ADAPTIVE POWER THROTTLING - A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software. To maintain a running average power value, a counter is incremented, both in sleeping and running states, by different increments depending upon the current performance point. | 09-09-2010 |
20100235662 | SERVER POWER MANAGER AND METHOD FOR DYNAMICALLY MANAGING SERVER POWER CONSUMPTION - A server power manager and method for dynamic server power management are generally described herein. The server power manager is configured to implement one or more server management policies that identify target server power consumption and/or target functionality for the server system. The server power manager determines an amount of excess processing capability and/or an amount of excess physical memory based on the target server power consumption and the target functionality. The server power manager may transition a processor core to a lower-operational state when at least a predetermined amount of excess processing capability is determined while maintaining server system functionality. The server power manager may transition a memory module to a lower-operational state when at least a predetermined amount of excess physical memory is determined while maintaining the server system functionality. | 09-16-2010 |
20100241884 | Power Adjustment Based on Completion Times in a Parallel Computing System - A method, apparatus, and program product optimize power consumption in a parallel computing system that includes a plurality of computing nodes by selectively throttling performance of selected nodes to effectively slow down the completion of quicker executing parts of a workload of the computing system when those parts are dependent upon or otherwise associated with the completion of other, slower executing parts of the same workload. Parts of the workload are executed on the computing nodes, including concurrently executing a first part on a first computing node and a second part on a second computing node. The first node is selectively throttled during execution of the first part to decrease power consumption of the first node and conform a completion time of for the first node in completing the first part of the workload with a completion time for the second node in completing the second part. | 09-23-2010 |
20100241885 | Method, system and apparatus for controlling power consumption of embedded system - Embodiments of the present disclosure disclose a method for controlling power consumption of an embedded system. The method obtains a data transmission index that is between a bus module and a bus, compares the obtained data transmission index with a preset numeric value range, and adjusts an operation frequency or an operation voltage of the bus module when the data transmission index exceeds the preset numeric value range. Embodiments of the present disclosure further provide a system and a relevant apparatus for controlling power consumption of the embedded system. In comparison with the conventional art, embodiments of the present disclosure effectively monitor the load of the bus module, and adjust the operation parameters of the module according to the monitoring result to enable the module to operate under proper operation parameters and to thereby reduce unnecessary power consumption. | 09-23-2010 |
20100268972 | METHOD AND APPARATUS FOR CONTROLLING CLOCK FREQUENCY - A clock frequency adjusting method capable of reducing power consumption without reducing a response speed for a command output from a host in an idle mode is provided. In the clock frequency adjusting method, a central processing unit (CPU) generates a detection signal according to whether an interrupt signal is activated, and a frequency adjusting circuit provides a clock signal having a first frequency or a second frequency higher than the first frequency to the CPU in response to the detection signal. | 10-21-2010 |
20100275045 | POWER MANAGEMENT METHOD AND RELATED CHIPSET AND COMPUTER SYSTEM - A power management method for use in a computer system having a processor, a power management module and a phase lock loop circuit (PLL) is provided. The power management module is coupled to a plurality of peripheral modules and the computer system and the processor are capable of being operated in a working state and power saving states. The method includes the following. When the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, states of the peripheral modules are detected to determine whether a specific condition has been matched. If the specific condition is matched, the processor is directed to a control state to control the PLL according to a control state configuration. | 10-28-2010 |
20100287393 | ELECTRONIC DEVICE AND METHOD OF PERFORMING A POWER MANAGEMENT IN AN ELECTRONIC DEVICE - An electronic device is provided which comprises at least one functional unit (HB) for performing a processing. The functional unit (HB) receives a supply current (Isupply). The electronic device furthermore comprises a supply current monitor (SCM) for monitoring the supply current (Isupply) in order to determine an average supply current (Iavg). The electronic device furthermore comprises a characterization unit (CU) for determining a relation between the average supply current (Iavg) and an operating frequency of the functional unit. Furthermore, a slope calculation unit (SCU) is provided to determine the slope of the relation. Moreover, a power management unit (PMU) is provided to control the operation of the functional unit (HB) according to the results of the slope calculation unit (SCU) in order to control the power dissipation of the functional unit (HB). | 11-11-2010 |
20100299545 | Methods of power management and apparatus thereof - A method of power management detects a workload rate of a processor, increases a power level of the processor based on a first value that is an average of the detected workload rate over an up reference time, and decreases the power level of the processor based on a second value that is an average of the detected workload rate over a down reference time. The down reference time may be longer than the up reference time. A power management apparatus includes a processor, a workload detector configured to detect a workload rate of the processor, a power management unit configured to receive the workload rate of the processor and generate a level control signal indicating a power level of the processor, a voltage control unit configured to provide the processor with a supply voltage corresponding to the level control signal, and a clock control unit configured to provide the processor with a clock signal having a frequency corresponding to the level control signal. | 11-25-2010 |
20100318822 | ENERGY SAVING IN SYSTEMS-ON-CHIP - A System-on-Chip may include initiators, targets exchanging information with the initiators, and a control module. The control module may be configured to selectively set to one of different reduced power consumption modes each of the initiators and each of the targets based upon external reduced power consumption instructions, and selectively wake-up from the reduced power consumption mode each initiator and each target. | 12-16-2010 |
20100318823 | COMPUTER AND CONTROL METHOD THEREOF - A computer includes a CPU and a system unit, and further includes a power source, a system driving power generator which converts source power input from the power source to be outputted to the system unit, a CPU driving power generator which outputs driving power to drive the CPU, and a controller which selectively supplies either the source power from the power source or the system power converted from the system driving power generator to an input terminal of the CPU driving power generator according to an operation mode of the CPU. Thus, a computer adjusts a level of power supplied to a CPU driving power generator according to a CPU mode and improves power efficiency, and includes a control method thereof. | 12-16-2010 |
20100332874 | MICROCOMPUTER AND MICROCOMPUTER SYSTEM - A microcomputer includes a CPU, a standby controller that controls setting of and recovering from a sleep mode of the CPU, an output terminal, a first timer, an output terminal controller, and a second timer. When the first timer performs predetermined time measurement when the CPU is in the sleep mode, the output terminal controller changes the level of the output terminal while maintaining the sleep mode. The second timer starts time measurement when the output terminal controller changes the level of the output terminal in the sleep mode. The standby controller performs recovering from the sleep mode of the CPU when the second timer performs a prescribed time measurement. | 12-30-2010 |
20100332875 | Fan Speed Control from Thermal Diode Measurement - Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly. | 12-30-2010 |
20110022863 | ELECTRONIC APPARATUS HAVING REDUCIBLE POWER CONSUMPTION IN THE READINESS STATE - Method for an electronic device (IT) that is controllable in at least one operating state (OP) and one standby state (SBY), with which a main processing unit (MPU) controls the operating state (OP) and a preprocessing unit (PPU) controls the standby state (SBY), such that, by means of the preprocessing unit (PPU), the main processing unit (MPU) and, to some extent, the functional units of the electronic device (IT) that are implemented by circuitry are switched by the control into at least one state having reduced energy consumption. An advantage can be seen in the fact that, by using a preprocessing unit (PPU), in the operating state of “standby” (SBY) the total energy consumption of the electronic device (IT) is reduced, both due to the significantly reduced energy consumption of a preprocessor (PPE) in the preprocessing unit (PPU) and to the units (MPU) that have been switched by the control into a state having reduced energy consumption, and the electronic device can therefore be operated more economically. An additional advantage is that the reduction of the energy consumption is achieved exclusively by circuitry measures and that no implementations must be included in the programs of the electronic device (IT). | 01-27-2011 |
20110022864 | REAL-TIME CLOCK - A real-time clock circuit, comprising: an oscillator; and a counter, coupled to an output of the oscillator, for generating a real-time clock value. In a first mode the oscillator is configured to generate oscillations and the counter is configured to increment the real-time clock value based on the oscillations. In a second mode the oscillator is stopped, and the counter is configured to retain the real-time clock value at a frozen value. | 01-27-2011 |
20110022865 | INDEPENDENT POWER CONTROL OF PROCESSING CORES - Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores. | 01-27-2011 |
20110022866 | METHOD AND APPARATUS FOR THERMAL SENSITIVITY BASED DYNAMIC POWER CONTROL - A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance. | 01-27-2011 |
20110029795 | DEVICE FOR POWERING AN ELECTRONIC CIRCUIT, IN PARTICULAR A DIGITAL CIRCUIT, AND ASSOCIATED METHOD - A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration. | 02-03-2011 |
20110047396 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM - An information processing apparatus including (a) a storage section storing AC adapter capacity identification, (b) a first section for outputting the AC adapter capacity information, (c) a setting section for setting threshold values used to control power consumption of the apparatus, (d) a detection section for detecting the power consumption of the apparatus, and (e) a control section for controlling power consumption based on whether the power consumption exceeds one of the thresholds. | 02-24-2011 |
20110078477 | POWER MANAGEMENT METHOD FOR ELECTRONIC DEVICE - An electronic device performs power management by switching between an active mode and an idle mode. The active mode is launched by applying a main clock signal to a processor within the electronic device. The idle mode is launched in parallel with a scaling down of a power level of processor. | 03-31-2011 |
20110087908 | Advanced Energy Profiler - An energy profiling apparatus for profiling power consumption characteristics of code being executed at an integrated circuit being powered by a power source and having a measurement module, a data processing module and a display module is disclosed. The energy profiling apparatus comprises first, second and third interfaces as well as a profile module. The first interface is configured to receive a first data set from the measurement module. The second interface is configured to receive a second data set from the data processing module. The third interface is configured to transmit a third data set to the display module. The profile module is configured to generate an energy profile of the code executed at the data processing module based on a correlation between the first data set and the second data set. Furthermore, the profile module is configured to transmit the energy profile as part of the third data set to the display module. | 04-14-2011 |
20110087909 | Power Consumption Reduction In A Multiprocessor System - Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g., because the other processor has released the lock on the data), the loop count is reset to zero and the frequency of operation of waiting processor is increased to an increased frequency, such as the normal, initial level. | 04-14-2011 |
20110099399 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes: a host interface that receives a standard specification command and an internal specification command; a register unit; a logic circuit unit; and a first oscillation circuit, wherein the first oscillation circuit is controlled on the basis of a first command as the internal specification command and shifts to a state in which power supply voltage is supplied but oscillation is stopped, and the first oscillation circuit is controlled through the register unit on the basis of a second command as the internal specification command and returns to an oscillation state from the state in which the oscillation is stopped. | 04-28-2011 |
20110099400 | METHOD AND SYSTEM THEREOF FOR OPTIMIZATION OF POWER CONSUMPTION OF SCAN CHAINS OF AN INTEGRATED CIRCUIT FOR TEST - Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing is keeping the power dissipation during testing under the allowed power capabilities of the tester power supplies, as the power used during scan test is much higher than that used during functional testing. A method for estimating the power dissipation of scan blocks in a circuit during the design stage is disclosed. Using the results generated, the circuit designer divides the design into an optimum number of scan blocks for test. Thus at-speed scan of the individual or groups of scan blocks can be estimated, during design, for optimizing test time while keeping the test power within acceptable limits. | 04-28-2011 |
20110107129 | METHODS AND APPARATUS FOR LOAD-BASED POWER MANAGEMENT IN A STORAGE SYSTEM - Apparatus and method for managing power consumption of circuits within a Serial Attached SCSI (SAS) device. A SAS device having a plurality of PHY logic circuits includes a queue manager and a power manager. The queue manager is operable to determine a current workload based on queued entries for the plurality of PHY logic circuits. Based on the current workload, the power manager is operable to set identified ones of the plurality of PHY logic circuits into a low power mode. In some embodiments, PHY logic circuits may be restored to full power operation responsive to changes in the current workload and/or responsive to receipt of a signal from another SAS device coupled to the SAS device. In other embodiments the power manager is further operable to manage power consumption of link and/or DMA logic circuits of the SAS device. | 05-05-2011 |
20110113274 | ELECTRONIC DEVICE, A METHOD OF CONTROLLING AN ELECTRONIC DEVICE, AND SYSTEM ON-CHIP - An electronic device is provided, which comprises at least one processing unit (CPU) for processing at least one application, an operating system (OS) for controlling the at least one application performed by the at least one processing unit (CPU), at least one workload build-up detector (WBD) for detecting a build-up of the workload of the at least one processing unit (CPU), at least one workload decrease detector (WDD) for detecting a decrease of the workload of the at least one processing unit (CPU), and at least one power management unit (SPM) for controlling an operating frequency and/or an operating voltage of the at least one processing unit in dependence on the detected workload build-up or the detected workload decrease. | 05-12-2011 |
20110131435 | INFORMATION PROCESSING APPARATUS AND METHOD OF OPERATION OF DATA TRANSFER CIRCUIT - An information processing apparatus transferring data between at least a plurality of processors through first and second routes running through first and second data transfer circuits, which retires the first and second routes so as to reduce the power consumption under the control of a system control device. The system provides a unit for measuring the amounts of data transfer on the first and second routes and measures the usage rates of the first and second routes. It monitors the measured usage rates by the system control device and, when the usage rates are below a predetermined value, controls the first or second data transfer circuit to make it retire the first or second route. | 06-02-2011 |
20110138206 | Power Management Method and Apparatus - Embodiments of the invention provide a power management subsystem which provides an interface which allows baseport subsystems such as device drivers and the like to register operational constraints on system resources such as power supplies, clocks, and the like, as well as to specify a maximum allowable wake-up time to ensure correct operation. Once registered, such operational constraints are then typically sorted to determine the strictest constraints, and the strictest constraints are then mapped to the characteristics of the various low-power modes offered by a particular device platform, to determine the most appropriate low power mode which can be entered whilst still allowing the registered constraints to be met. In this way, when required a device having the power management subsystem can still make use of low power modes when appropriate, without compromising the operation of base port sub systems such as device drivers, controllers, or the like. Additionally, the power management subsystem insulated the base port subsystems from the low power modes provided by the device, such that existing base port subsystem components can be used with the device, without requiring any bespoke tailoring thereto. | 06-09-2011 |
20110154075 | DATA NEGOTIATION USING SERIAL VOLTAGE IDENTIFICATION COMMUNICATION - According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the processor, transmit address information to the plurality of voltage regulators that are electrically coupled to the processor at a first speed associated with the slowest one of the plurality of voltage regulators, determine a second speed associated with a voltage regulator to which the address information is associated, and transmit a second portion of the packet at the second speed associated with the voltage regulator to which the address information is associated. | 06-23-2011 |
20110154076 | TIME NEGOTIATION USING SERIAL VOLTAGE IDENTIFICATION COMMUNICATION - According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the integrated circuit, and communicate with the plurality of voltage regulators that are electrically coupled to the integrated circuit at a speed associated with the slowest one of the plurality of voltage regulators. | 06-23-2011 |
20110154077 | ELECTRONIC APPARATUS AND METHOD OF CONTROLLING ELECTRONIC APPARATUS - An electronic apparatus is provided. A management hoard includes: a control section; a real-time clock that outputs data indicating current date and time to the control section; a memory that stores fiscal data including the data indicating the current date and time and fiscal information under the control of the control section; and a power source that supplies power to the real-time clock through a power supply path. A housing box includes a box main body and a cover. The housing box that houses the management board. When the cover is in a closed state, the power supply path is formed and the power is supplied to the real-time clock. When the cover is placed in an open state, the power supply path is shut off and the power supplied to the real-time clock is shut off. | 06-23-2011 |
20110191615 | MEMORY CLOCK SLOWDOWN - Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other. | 08-04-2011 |
20110239018 | Microcomputer and control method thereof - A microcomputer according to the present invention includes: a CPU (Central Processing Unit) that has a plurality of modes including a usual operational mode and a STANDBY mode, a clock supply being stopped in the STANDBY mode; a clock generation circuit that generates a clock supplied to the CPU; and a control circuit that monitors a mode of the CPU, determines a mode to which the CPU should transit according to the mode of the CPU and a type of an interruption request to the CPU, and controls the clock generation circuit according to the determined mode. | 09-29-2011 |
20110246800 | OPTIMIZING POWER MANAGEMENT IN MULTICORE VIRTUAL MACHINE PLATFORMS BY DYNAMICALLY VARIABLE DELAY BEFORE SWITCHING PROCESSOR CORES INTO A LOW POWER STATE - Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases. | 10-06-2011 |
20110271128 | STATE TRANSITIONING CLOCK GATING - In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption. | 11-03-2011 |
20110307722 | REDUCING POWER CONSUMPTION IN CLOCK AND DATA RECOVERY SYSTEMS - Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system. | 12-15-2011 |
20110307723 | PERSONAL ELECTRONIC DEVICE WITH A DUAL CORE PROCESSOR - A novel personal electronic device includes a processor having first (embedded) and second (non-embedded) cores including associated operating systems and functions. In one aspect, the first core performs relatively limited functions, while the second core performs relatively broader functions under control of the first core. Often the second core requires more power than the first core and is selectively operated by the first core to minimize overall power consumption. Protocols for functions to be performed by the second core may be provided directly to the second core and processed by the second core. In another aspect, a display controller is designed to interface with both cores. In another aspect, the operating systems work with one another. In another aspect, the first core employs a thermal control program. Advantages of the invention include a broad array of functions performed by relatively small personal electronics device. | 12-15-2011 |
20110320839 | MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES - Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory. | 12-29-2011 |
20120023351 | DYNAMIC ALLOCATION OF POWER BUDGET FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for dynamically allocating power for a system having non-volatile memory. A power budgeting manager of a system can determine if the total amount of power available for the system is below a pre-determined power level (e.g., a low power state). While the system is operating in the low power state, the power budgeting manager can dynamically allocate power among various components of the system (e.g., a processor and non-volatile memory). | 01-26-2012 |
20120023352 | ACTIVE POWER MANAGEMENT - A method of controlling the clock frequency of a processor executing software in a plurality of active periods, the method comprising, for each period: supplying to a power management application at least one parameter defining an execution profile for the period having high frequency and low frequency operating intervals; the power management application determining, based on said profile, granted clock frequencies for the high and low frequency operating intervals; the processor supplying to the power management application at the commencement of a period an operating cycle requirement for the period; the power management application determining, for each period, based on the operating cycle requirement, the length of the low frequency interval; and controlling the clock frequency in each interval based on the granted clock frequencies determined by the power management application. | 01-26-2012 |
20120030488 | METHOD AND APPARATUS FOR INDICATING MULTI-POWER RAIL STATUS OF INTEGRATED CIRCUITS - Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal. | 02-02-2012 |
20120036380 | Clock Ratio Controller For Dynamic Voltage and Frequency Scaled Digital Systems, and Applications Thereof - The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit. | 02-09-2012 |
20120066530 | Configurable Power Switch Cells and Methodology - In one embodiment, a configurable power switch cell methodology may include designing multiple power switch cells which may be assembled to form a set of power switches such as a power switch segment. The power switch cells may all be designed to occupy the same amount of integrated circuit area, in an embodiment. Accordingly, one cell may be readily replaced by another, even late in the design process, without disturbing the placement of surrounding circuitry. In an embodiment, the power switch cells may include the interconnect layers that connect between cells, and abutting the power switch cells may automatically connect the interconnect between cells. Accordingly, swapping one power switch cell for another may be accomplished by placing the cell. No routing work may be required. | 03-15-2012 |
20120072749 | MULTI-CORE POWER MANAGEMENT - The disclosed embodiments provide a system that operates a processor in a multi-core processor system. During operation, the system detects the creation of an asynchronous wakeup event for the processor. In response to detecting the creation of the asynchronous wakeup event, when the processor is subsequently placed into an idle state, the system configures the processor to resume operation at a reduced frequency that is a fraction of an operating frequency for the multi-core processor system, wherein the reduced frequency allows more power to be allocated to other processors in the multi-core processor system. | 03-22-2012 |
20120072750 | METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE - Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. | 03-22-2012 |
20120084588 | VOLTAGE REGULATOR WITH DRIVE OVERRIDE - Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock signal is powered by at least one switching-type voltage regulator. When the functional block is about to require an increased level of power, the associated clock is provided to drive the at least one regulator switches overriding their normal drive signal, which has a lower frequency. Thus, the switches are driven at a higher frequency sufficiently prior to (e.g., just ahead of) the load change to reduce the amount of droop that would otherwise occur. | 04-05-2012 |
20120089852 | ENERGY OPTIMIZATION TECHNIQUES IN A COMPUTING SYSTEM - A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions. | 04-12-2012 |
20120089853 | HIGH SPEED NETWORK INTERFACE WITH AUTOMATIC POWER MANAGEMENT WITH AUTO-NEGOTIATION - A power management circuit for managing power of a network interface is provided. The network interface includes a medium interface unit coupled to a network media supporting at least a high speed protocol and a lower speed protocol. The power management logic includes logic to determine that an event signalling entry of the medium interface unit into the lower speed protocol has occurred; and logic to force the medium interface unit into the lower speed protocol in response to a determination that the event has occurred. | 04-12-2012 |
20120096292 | METHOD, SYSTEM AND APPARATUS FOR MULTI-LEVEL PROCESSING - A Multi-Level Processor | 04-19-2012 |
20120102344 | FUNCTION BASED DYNAMIC POWER CONTROL - A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same. | 04-26-2012 |
20120102345 | APPARATUS AND METHOD FOR ADAPTIVE FREQUENCY SCALING IN DIGITAL SYSTEM - An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller. | 04-26-2012 |
20120102346 | CONNECTED STANDBY SLEEP STATE - Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state. | 04-26-2012 |
20120117402 | Memory Read Timing Margin Adjustment - An apparatus and method for changing the extra margin adjustment (EMA) for a memory is disclosed. A control unit may access a table responsive to an indication of a change of operating point. The table includes a number of different delay times, each of which corresponds to a particular operating point. The control unit may select the delay time that corresponds to the new operating point to which the memory operation is being changed. The control unit may further convey an indication of the selected delay time to the memory, thereby causing the memory to operate according thereto. | 05-10-2012 |
20120117403 | POWER MANAGEMENT FOR PROCESSING CAPACITY UPGRADE ON DEMAND - A method, computer program product, and apparatus for managing power in a data processing system are presented. A core is activated in the data processing system and configured to operate at a frequency in response to receiving a request to increase a processing capacity of a set of resources in the data processing system. A determination whether a use of power resulting from activating the core configured to operate at the frequency meets a policy for the use of the power in the data processing system is made. A set of parameters associated with devices in the set of resources are adjusted to meet the policy for the use of power in the data processing system in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed per unit of time by a set of cores associated with the set of resources increased after activating the core is made. An indication that the request to increase the processing capacity of the set of resources is unavailable is made in response to a determination that the number of operations performed per unit of time by the set of cores associated with the set of resources has not increased. | 05-10-2012 |
20120137152 | REDUCTION OF POWER CONSUMPTION FOR DATA ERROR ANALYSIS - A controller (e.g., a memory controller) includes initial error analysis logic (e.g., a section of a Reed Solomon or BCH codeword decoder) that determines an error count for a data element. The data element may be data stored in the memory of a memory device (e.g., a flash memory device) that incorporates the controller. Comparison logic in the controller determines when the error count exceeds a power control threshold. When the error count exceeds the power control threshold, control logic in the controller reduces the operational speed of subsequent error analysis logic (e.g., a different section of the Reed Solomon or BCH codeword decoder) for the data element. For example, the subsequent error analysis logic may be error locator logic, such as Chien search logic, that determines where the errors exist in the data element. | 05-31-2012 |
20120144218 | Transferring Power and Speed from a Lock Requester to a Lock Holder on a System with Multiple Processors - Power is allocated between processors in a multiprocessor system. A request to acquire a lock is received from a first thread executing on a first processor. Responsive to receiving the request to acquire a lock, determination is made as to whether a second thread has acquired the lock. Responsive to determining that the second thread has acquired the lock, an original frequency of the first thread executing on the first processor and an operating frequency of the second thread executing on the second processor is identified. The operating frequency of the second thread executing on the second processor is then altered based on the original frequency of the first thread executing on the first processor. When the second thread releases the lock, the spinning thread with the highest original frequency acquires the lock. | 06-07-2012 |
20120144219 | Method of Making Power Saving Recommendations in a Server Pool - A method, system and computer-usable medium are disclosed for optimizing the power consumption of a plurality of information processing systems. Historical usage data representing power usage of a plurality of information processing systems is retrieved in response to a request to generate power savings recommendations. Statistical analysis is performed on the historical usage data are to determine usage patterns, which are then further analyzed to determine repetitions of the usage patterns. In turn, the repetitions of the usage patterns are analyzed to generate power consumption management recommendations to initiate power consumption management actions at particular times. One or more business constraints are determined, which are used to generate constraints to the power consumption management recommendations. | 06-07-2012 |
20120151232 | CPU in Memory Cache Architecture - One exemplary CPU in memory cache architecture embodiment comprises a demultiplexer, and multiple partitioned caches for each processor, said caches comprising an I-cache dedicated to an instruction addressing register and an X-cache dedicated to a source addressing register; wherein each processor accesses an on-chip bus containing one RAM row for an associated cache; wherein all caches are operable to be filled or flushed in one RAS cycle, and all sense amps of the RAM row can be deselected by the demultiplexer to a duplicate corresponding bit of its associated cache. Several methods are also disclosed which evolved out of, and help enhance, the various embodiments. It is emphasized that this abstract is provided to enable a searcher to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 06-14-2012 |
20120151233 | NETWORK DEVICE FOR CONTROLLING POWER CONSUMPTION AND METHOD EMPLOYING THE SAME - A network device for controlling power consumption includes a power supply unit, a central processing unit (CPU) and a power consumption control unit. The power supply unit provides electrical energy to the network device. The power consumption control unit includes a baseband management controller (BMC) and a north bridge. The BMC presets a predetermined power, the north bridge detects output power of the power supply unit, the BMC compares the output power with the predetermined power of the network device, and controls the north bridge to adjust operating frequency of the CPU according to the comparison until the output power of the power supply unit equals the predetermined power of the network device. | 06-14-2012 |
20120159216 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENHANCED TEMPERATURE BASED VOLTAGE CONTROL - Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enhanced temperature based voltage control are described. In one embodiment, an apparatus includes a processor and a controller coupled with the processor. In one embodiment, the controller receives a temperature measurement corresponding to a current temperature of the processor. In one embodiment, the controller further determines an adjustment to a voltage being applied to the processor based at least in part on the temperature measurement and a plurality of internal limits of the processor, wherein the determined adjustment to the voltage is based on an inverse temperature dependence relationship between at least one of an operating frequency and a voltage of the processor, and temperature. In one embodiment, the controller provides the determined adjustment to the voltage to a voltage regulator interface. | 06-21-2012 |
20120166838 | METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ON-OFF KEYING FOR POWER CONTROL - Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying. | 06-28-2012 |
20120166839 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE - Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state. | 06-28-2012 |
20120185712 | METHODS AND SYSTEMS FOR POWER MANAGEMENT IN A DATA PROCESSING SYSTEM - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 07-19-2012 |
20120198255 | ESTABLISHING AN OPERATING RANGE FOR DYNAMIC FREQUENCY AND VOLTAGE SCALING - During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor. | 08-02-2012 |
20120198256 | Method for Setting the Clock Frequency of a Microprocessor of an Industrial Automation Component, and Automation Component Having a Microprocessor with a Variable Clock Frequency - Method and an automation component for setting the clock frequency of a microprocessor in an industrial automation arrangement, the clock frequency of the microprocessor being selected depending on a required computation power, wherein in a first step, the required duration for execution of the main program cycle of a control program running on the automation component is detected, in a second step, this duration is compared with a maximum value, and in a third step, a new clock frequency is determined depending on the result of the comparison and used for the microprocessor. The method and automation component make it possible to match the clock frequency of the microprocessor dynamically, wherein firstly, the required computation power is always provided, and secondly an unnecessarily high clock frequency is avoided. As a result, a corresponding saving on energy and reduction in the power losses can be achieved. | 08-02-2012 |
20120198257 | MULTIPROCESSOR | 08-02-2012 |
20120204045 | System and Method for Reducing Power Consumption During Periods of Low Link Utilization - A system and method for reducing power consumption during periods of low link utilization. A single enhanced core can be defined that enables operation of subset of parent physical layer devices (PHYs). The subset and parent PHYs can have a fundamental relationship that enables synchronous switching between them depending on the link utilization state. | 08-09-2012 |
20120216058 | System, Method and Apparatus for Energy Efficiency and Energy Conservation by Configuring Power Management Parameters During Run Time - According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed | 08-23-2012 |
20120216059 | METHOD OF OPERATION OF A MEMORY DEVICE AND SYSTEM INCLUDING INITIALIZATION AT A FIRST FREQUENCY AND OPERATION AT A SECOND FREQUENCEY AND A POWER DOWN EXIT MODE - Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device. | 08-23-2012 |
20120221873 | Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices - According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device. | 08-30-2012 |
20120221874 | Methods And Apparatuses For Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 08-30-2012 |
20120226926 | INDEPENDENT POWER CONTROL OF PROCESSING CORES - Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores. | 09-06-2012 |
20120239954 | APPARATUS AND METHOD FOR REDUCING CURRENT CONSUMPTION IN A PORTABLE TERMINAL - An apparatus and method for reducing current consumption in a portable terminal are provided, in which upon generation of a task, a controller transitions to a Virtual Maximum Clock (VMC) level and changes a clock level from the VMC level according to a load state of the controller, to process the task. Moreover, the controller changes the clock level by at least one of transition from the VMC level to an RMC level, a stepwise increase from the VMC level, a stepwise decrease from the VMC level, and a hold at the VMC level, according to the load state of the controller. | 09-20-2012 |
20120272080 | Multi-Core Electronic System and Associated Rate Adjustment Device - A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements. | 10-25-2012 |
20120278639 | DATA PROCESSOR - Provided is a data processor comprising: a signal processing unit operable to read out data stored in an input data storing unit, and perform signal processing of the data; a signal processing control unit operable to control the signal processing unit to take an active period to perform the signal processing at a processing speed faster than an input speed of the data inputted into the data input unit, and an inactive period not to perform the signal processing; a power control unit operable to restrict in the inactive period at least one of an electric power and a clock signal both supplied with the signal processing unit; and an input monitor unit operable to request the power control unit to remove the restriction on the basis of the volume of the data in the input data storing unit. | 11-01-2012 |
20120284546 | USING HISTORIC LOAD PROFILES TO DYNAMICALLY ADJUST OPERATING FREQUENCY AND AVAILABLE POWER TO A HANDHELD MULTIMEDIA DEVICE PROCESSOR CORE - A technique is provided for use in a handheld multimedia device that uses the historical load profile statistics of a particular multimedia stream to dynamically scale the computational power of a computing engine, depending upon the complexity of the multimedia content and thereby reduce the power consumption for computationally less intensive content and consequently reduce the power consumption by a significant amount over a duration of time. | 11-08-2012 |
20120284547 | METHODS AND APPARATUSES FOR OPERATING A DATA PROCESSING SYSTEM - Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption). | 11-08-2012 |
20120284548 | Zero Indication Forwarding for Floating Point Unit Power Reduction - A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations. | 11-08-2012 |
20120297224 | Power Management Method and Device Thereof - A power management method for a mobile device including a basic input output system (BIOS) and an embedded controller (EC) includes determining whether the mobile device is operated in a direct current (DC) mode, determining whether a loading of an operating system of the mobile device exceeds a predetermined value, adding a flag associated with the embedded controller in a physical memory of the mobile device when the mobile device is operated in the DC mode and the loading of the operating system exceeds the predetermined value, and reading the flag in the physical memory via the basic input output system, to notify the embedded controller to perform a power management process corresponding to the flag. | 11-22-2012 |
20120324266 | Microarchitecture Controller For Thin-Film Thermoelectric Cooling - A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control. | 12-20-2012 |
20130007492 | TIMER INTERRUPT LATENCY - An indication that a subsystem is about to enter an idle state is received, and an original fire time for a next timer interrupt is determined. An idle state for a subsystem is selected based on the original fire time; and a new fire time for the next timer interrupt is determined based on the selected idle state to reduce timer interrupt latency. A current latency in exiting an idle state is measured. The measured latency is added to a running average of latencies for the idle state. A latency value is determined based on the running average and a worst case latency to adjust an original fire time for a next timer interrupt. | 01-03-2013 |
20130007493 | COMPUTER SYSTEM, METHOD FOR CONTROLLING POWER OF COMPUTER SYSTEM, AND RECORDING MEDIUM FOR POWER CONTROL PROGRAM - A computer system for managing a plurality of virtual machines, the computer system including: a processor; and a memory coupled to the processor, wherein the processor executes a process includes: recording, on the memory, an operation history of a virtual machine that is related to a user operation in the plurality of virtual machines; determining whether the user operation is performed or not at switching of the virtual machines by referring to the operation history and comparing an operation time of the virtual machine that has operated most recently with the operation time of a control table, the control table being stored in the memory; and increasing an operation frequency of a CPU when performance of the user operation is detected. | 01-03-2013 |
20130024707 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD - An information processing apparatus | 01-24-2013 |
20130036318 | SYSTEMS AND METHODS FOR CONTROLLING POWER CONSUMPTION IN ELECTRONIC DEVICES - A method of controlling power consumption in an electronic device may include selecting between an on mode of the electronic device in which first circuitry of the electronic device is configured to perform a first operation, an off/standby mode in which second circuitry of the electronic device is configured to perform a second operation, and a sleep/vacation mode in which the second circuitry is controlled to at least one of reduce a frequency of and suspend performance of the second operation. An electronic device may include: first circuitry configured to perform a first operation when the electronic device is in an on mode; second circuitry configured to perform a second operation when in an off/standby mode; and a circuitry controller configured to control the second circuitry to at least one of reduce a frequency of and suspend performance of the second operation when in a sleep/vacation mode. | 02-07-2013 |
20130042126 | MEMORY LINK POWER MANAGEMENT - Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions. | 02-14-2013 |
20130054992 | DYNAMIC CONTROL OF REDUCED VOLTAGE STATE OF GRAPHICS CONTROLLER COMPONENT OF MEMORY CONTROLLER - A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component. | 02-28-2013 |
20130061077 | Power Management For A System On A Chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 03-07-2013 |
20130067258 | DATA PROCESSOR AND ELECTRONIC CONTROL UNIT - A data processor ( | 03-14-2013 |
20130080808 | BIOMEDICAL DEVICE FOR COMPREHENSIVE AND ADAPTIVE DATA-DRIVEN PATIENT MONITORING - A biomedical device for comprehensive and a data-driven patient monitoring is disclosed. The biomedical device includes a receiver to receive sensor data associated with physiological signals and perform feature computations on the sensor data. A control system is included to classify the sensor data using the feature computations to generate medically-relevant decisions and identify relevant data instances, and to automatically select a set of relevant data instances. A base station or programming interface can provide a patient-generic seed model to the biomedical device. The patient-specific seed model is usable by the control system to automatically select a coarse set of relevant data instances that are transmitted to the base station, which in turn analyzes the coarse set of relevant data instances to generate a patient-specific model. The biomedical device receives the patient-specific model, which is usable by the control system to automatically select a refined set of relevant data instances. | 03-28-2013 |
20130080809 | SERVER SYSTEM AND POWER MANAGING METHOD THEREOF - A server system and a power management method thereof are provided. The method includes following steps: detecting an utilization corresponding to at least one CPU in a specific node so as to calculate an average utilization of the specific node; judging a state of the specific node according to the average utilization; adjusting an operation parameter of the CPU to reduce the processing speed of the CPU when the state is lower than a normal-load state; adjusting the operation parameter of the CPU to advance the processing speed of the CPU so as to make the above-mentioned state back to the normal-load state when the state is higher than the normal-load state. The power management method dynamically adjusts the operation performance and duty-cycle of the CPU according to the utilization of the CPUs of the node so as to save power without affecting the working efficiency of the virtual machines. | 03-28-2013 |
20130080810 | OPTIMIZATION OF THE PROCESSING SPEED OF AN ELECTROMAGNETIC TRANSPONDER - A method for setting the clock frequency of a processing unit of an electromagnetic transponder, wherein a ratio between data, representative of a voltage across an oscillating circuit of the transponder and obtained for two values of the resistive load, is compared with one to decide whether to increase or decrease the clock frequency of the processing unit. | 03-28-2013 |
20130086401 | CONFIGURABLE THERMAL AND POWER MANAGEMENT FOR PORTABLE COMPUTERS - Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device. | 04-04-2013 |
20130086402 | DFVS-Enabled Multiprocessor - One or more tasks to be executed on one or more processors are formulated into a graph, with dependencies between the tasks defined as edges in the graph. In the case of a Radio Access Technology (RAT) application, the graph is iterative, whereby each task may be activated a number of times that may be unknown at compile time. A discrete number of allowable frequencies for processors while executing tasks are defined, and the power dissipation of the processors at those frequencies determined. A linear programming problem is then formulated and solved, which minimizes the overall power dissipation across all processors executing all tasks, subject to several constraints that guarantee complete and proper functionality. The switching of processors executing the tasks between operating points (frequency, voltage) may be controlled by embedding instructions into the tasks at design or compile time, or by a local supervisor monitoring execution of the tasks. | 04-04-2013 |
20130097442 | MOBILE DEVICE CHIP AND MOBILE DEVICE CONTROLLING METHOD THEREFOR - A mobile device chip is provided. The mobile device chip includes a main processor, a multimedia processor, and a direct memory access (DMA) circuit. The multimedia processor is electrically coupled to the main processor. The DMA circuit accesses storage, and the DMA circuit is electrically coupled to the multimedia processor. When the mobile device chip operates in a normal mode, the main processor provides file accessing information of at least part of an audio file stored in the storage to the multimedia processor. When the mobile device chip operates in a power-saving mode, the multimedia processor obtains the data of the at least part of the audio file stored in the storage through the DMA circuit according to the file accessing information provided by the main processor. | 04-18-2013 |
20130097443 | DYNAMIC VOLTAGE AND CLOCK SCALING CONTROL BASED ON RUNNING AVERAGE, VARIANT AND TREND - The aspects enable a computing device or microprocessor to scale the frequency and/or voltage of a processor to an optimal value balancing performance and power savings in view of a current processor workload. Busy and/or idle duration statistics are calculated from the processor during execution. The statistics may include a running average busy and/or idle duration or idle/busy ratio, a variance of the running average and a trend of the running average. Current busy or idle durations or an idle-to-busy ratio may be computed based on collected statistics. The current idle-to-busy ratio may be compared to a target idle-to-busy ratio and the frequency/voltage of the processor may be adjusted based on the results of the comparison to drive the current running average toward the target value. The target value of idle-to-busy ratio may be adjusted based on the calculated variance and/or trend values. | 04-18-2013 |
20130111241 | POWER SAVING APPARATUS AND METHOD FOR MOBILE TERMINAL | 05-02-2013 |
20130117593 | Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects - A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle. | 05-09-2013 |
20130117594 | CONFIGURABLE THERMAL AND POWER MANAGEMENT FOR PORTABLE COMPUTERS - Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device. | 05-09-2013 |
20130124891 | EFFICIENT CONTROL OF POWER CONSUMPTION IN PORTABLE SENSING DEVICES - The various embodiments of the invention relate generally to portable devices and systems, including wearable devices, that include sensors that are used for sensing the physiological, emotional and/or environmental condition of a person carrying, wearing or otherwise using the device or system and more specifically, to an architecture and method reducing the power consumption of such devices and systems that include one or more sensors. In an embodiment, a wearable device includes one or more sensors, sensor data power optimization controller, a power-clock controller, a memory optimizer and a sensor optimizer. | 05-16-2013 |
20130124892 | ELECTRONIC DEVICE AND POWER MANAGEMENT METHOD THEREOF - A power management method is suitable for an electronic device including a controller, a processor and a battery, and includes following steps. A first power is provided to the electronic device by a power adapter, and a maximum value of the first power is smaller than a maximum value of a rated consumed power of the electronic device. A power state of a second power of the battery is obtained by the controller. A control signal is generated according to the power state, and the processor adjusts an operation performance of the processor based on the control signal. The operation performance of the processor is continuously adjusted according to the power state. | 05-16-2013 |
20130132749 | ADAPTIVE POWER CONTROL - A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted. | 05-23-2013 |
20130145188 | Advanced Pstate Structure with Frequency Computation - A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity. | 06-06-2013 |
20130145189 | SERVER SYSTEM CAPABLE OF DECREASING POWER CONSUMPTION AND METHOD THEREOF - A server system and a control method applied therein are illustrated. The server system includes a server cabinet, servers accommodated in the server cabinet, a cooling fan module for cooling the servers, a thermal sensor detecting an ambient temperature in the server cabinet, and a controller. The controller includes a speed control module controlling a rotation speed of the fan module according to the ambient temperature and any overloading of servers, an obtaining module receives power consumed values of the servers, a determining module determining if a ratio of the highest power consumed value to the lowest power consumed value is greater than a predetermined value, and an executing module reducing the clocking speed of the server having the highest power consumed value if the determining module determines that the ratio of the highest power consumed value to the lowest power consumed value is greater than the predetermined value. | 06-06-2013 |
20130145190 | DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode. | 06-06-2013 |
20130151879 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES - Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors. | 06-13-2013 |
20130159747 | DATA PROCESSING APPARATUS AND METHOD FOR MAINTAINING A TIME COUNT VALUE - A counting circuit for a data processing apparatus has a normal mode in which a main counter increments the time count value in response to edges of a main clock signal, and a power saving mode in which the main clock signal is disabled and a further clock counter counts elapsed edges of a further clock signal having a lower frequency than the main clock signal. On switching to power saving mode, a reference time count value of the main counter is captured at a timing triggered by an edge of the further clock signal. On switching back to normal mode, an expected time count value from the main counter is calculated based on the captured reference value and the counted number of elapsed edges during the power saving mode, and the main counter is restarted at a timing triggered by another edge of the further clock signal. | 06-20-2013 |
20130159748 | Energy-Efficient Polling Loop - Logic is provided for increasing energy-efficiency of a data processing system. First logic continuously checks a plurality of I/O ports for incoming workload. Responsive to the incoming workload being lower than a low workload threshold for a current operating frequency, second logic reduces an operating frequency of the processor. Responsive to the incoming workload being higher than a high workload threshold, the second logic increases the operating frequency of the processor. | 06-20-2013 |
20130166930 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system adapted to enable power-gating in one or more memories. Each memory has a corresponding timing characteristic. A monitor in the memory system determines a timing threshold and determines whether the timing characteristic of a memory is at least equal to the timing threshold. If the corresponding timing characteristic is at least equal to the timing threshold, power-gating is applied to the memory. | 06-27-2013 |
20130166931 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock. | 06-27-2013 |
20130179710 | MULTI-CORE PROCESSOR SYSTEM, DYNAMIC POWER MANAGEMENT METHOD THEREOF AND CONTROL APPARATUS THEREOF - A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off. | 07-11-2013 |
20130179711 | GRAPHICS PROCESSOR CLOCK SCALING BASED ON IDLE TIME - A method for graphics processor clock scaling comprises the following steps. A percentage of idle-time is calculated, based upon an elapsed idle-time and an elapsed active time. A graphics processor clock rate is reduced if the percentage of idle time is higher than a high limit threshold. The graphics processor clock rate is increased if the percentage of idle time is lower than a low limit threshold. | 07-11-2013 |
20130179712 | All-in-one Computer and Power Management Method thereof - An all-in-one computer includes a display module and a host provided in a housing of the display module. The host includes a power module, a cell module and a circuit board electrically connected with the power module, the cell module and a panel of the display module respectively. A processing unit and a control unit are provided on the circuit board. The processing unit is configured to optionally receive the power from the power module and operating at a first frequency or receive the power from the cell module and operate at a second frequency lower than the first frequency. The control unit is configured to disable the power module and enable the cell module according to a voltage level of the power module and cause the processing unit to operate at a reduced frequency for decreasing power consumption thereof are provided. | 07-11-2013 |
20130179713 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 07-11-2013 |
20130185577 | METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 07-18-2013 |
20130191665 | Method and Apparatus for Decreasing Leakage Power Consumption in Power Gated Memories - A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed. | 07-25-2013 |
20130191666 | Methods and Apparatuses for Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 07-25-2013 |
20130191667 | CONNECTED STANDBY SLEEP STATE - Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state. | 07-25-2013 |
20130198542 | SYSTEMS AND METHODS OF TASK ALLOCATION IN A MULTIPROCESSING ENVIRONMENT HAVING POWER MANAGEMENT - Systems and Methods for task allocation in a multiprocessor environment employing power management techniques are described wherein tasks are allocated relative to the density given by the ratio of worst-case-execution time and deadline of a task and also the harmonicity of a task's period with respect to a task-set. Tasks are allocated to a given processor based on either minimum density or maximum harmonicity depending on which allocation results in a lower clock frequency. Assigning a task to the processor with lowest density results in balancing the density across processors while assigning task to the processor with maximum harmonicity attempts to maximize the utilization of the processor. | 08-01-2013 |
20130198543 | Apparatus and Method for TPM and LAN Power Management - In Gigibit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes. | 08-01-2013 |
20130205146 | Systems and Methods for Power Governance in a Data Processing Circuit - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-08-2013 |
20130205147 | BATTERY DISCHARGING METHOD - A battery discharging method for a computer system is disclosed. The battery discharging method is to detect a first detection value relative to a first status of a battery of the computer system and a second detection value relative to a second status of the battery, then to determine a clock adjustment parameter according to the first detection value and the second detection value, and at last to adjust an operation clock rate of a processor of the computer system according to the clock adjustment parameter. Therein, the statuses of the battery can be discharging temperature, discharging current, discharging voltage, residual capacity, or other statuses of the battery. Therefore, the invention can adjust the operation clock rate of the processor under the consideration to the statuses of the battery, so as to extend the discharging period of the battery and utilize the stored energy in the battery efficiently. | 08-08-2013 |
20130205148 | USB 3.0 HOST WITH LOW POWER CONSUMPTION AND METHOD FOR REDUCING POWER CONSUMPTION OF A USB 3.0 HOST - A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is coupled to the super speed circuit and the non-super speed circuit for controlling the super speed circuit or the non-super speed circuit to transmit data with a USB peripheral device, and turning-on or turning-off of the super speed circuit and the non-super speed circuit. | 08-08-2013 |
20130205149 | APPARATUS AND METHOD FOR DYNAMICALLY ADJUSTING FREQUENCY OF CENTRAL PROCESSING UNIT - The embodiment of the application provides an apparatus and a method for dynamically adjusting a frequency of central processing unit CPU. The apparatus is used for a computer system which executes a CPU bound application and a memory bound application, and comprises: a ratio acquiring unit for acquiring the ratio of memory access instruction as executing an application task set; a frequency calculating unit connected with the ratio acquiring unit for calculating an adjusted new frequency of CPU in inverse proportional to the ratio of memory access instruction acquired by the ratio acquiring unit; and a frequency adjusting unit connected with the frequency calculating unit for adjusting the frequency of CPU to the new frequency of CPU. With the apparatus and method for adjusting the frequency of CPU according to the embodiment of the invention, the frequency of CPU can be decreased in consideration of the ratio of memory access instruction so as to reduce the power consumption of the computer system. | 08-08-2013 |
20130205150 | AUTONOMOUS MICROPROCESSOR RE-CONFIGURABILITY VIA POWER GATING PIPELINED EXECUTION UNITS USING DYNAMIC PROFILING - In an embodiment, a functional unit control method includes, using a performance monitoring unit connected to a processor, collecting performance data of a first type of functional unit in an execution stage of the processor for each process running on a time multiplexed computing system running a multitasking operating system. The method further includes determining a utilization level of the first type of functional unit based on the performance data, and comparing the utilization level of the first type of functional unit with a first threshold. The method also includes, when a first condition has been satisfied, power gating at least one of the first type of functional unit in the processor. The method may include dynamically loading a specific needs register for each time quantum that a process runs on the processor. | 08-08-2013 |
20130212415 | Partition Level Power Management Using Fully Asynchronous Cores with Software that has Limited Asynchronous Support - A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range. | 08-15-2013 |
20130219199 | CLOCKING A PROCESSOR - A technique includes clocking a processor; and in response to the processor providing a signal indicating that the processor is transitioning between a first power state that is associated with a first power consumption and a second power state that is associated with a second power consumption different than the first power consumption, changing a frequency of the clocking. | 08-22-2013 |
20130227321 | METHOD AND APPARATUS FOR CACHE CONTROL - A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed. | 08-29-2013 |
20130227322 | BATTERY MODULE, COMPUTER SYSTEM HAVING THE SAME, AND CONTROL METHOD OF THE COMPUTER SYSTEM - A computer system is provided. The computer system includes a device which operates according to a clock frequency, a battery unit, which comprises a plurality of battery cells, for supplying power to the device, a temperature sensor provided at a location outside of the battery unit for detecting a temperature of the battery cells, a current sensor coupled to the battery unit for detecting a value of a current supplied from the battery unit to the device, and a controller, which is coupled to the temperature sensor and the current sensor, configured to control the clock frequency of the device according to the detected temperature and the detected current value, wherein the controller is configured to decrease the clock frequency if the detected temperature is greater than a first reference value or if the detected current value is greater than a second reference value. | 08-29-2013 |
20130232357 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION OF A PROCESSOR - A method for controlling the clock frequency of a processor while suppressing performance degradation is disclosed. The processor receives power from a battery to operate at a high clock frequency HFM(f) or a low clock frequency LFM(f). An allowable current Im is set for the discharge current of the battery. The time during which the processor operates at the HFM(f) and the time during which the processor operates at the LFM(f) are controlled by PWM. As the feedback current Ifb increases, the time during which the processor operates at the LFM(f) become longer than the time during which the processor operates at the HFM(f). | 09-05-2013 |
20130232358 | METHOD AND APPARATUS FOR INCREASING THE POWER CAPABILITY OF A POWER SUPPLY - One controller for a power supply includes an oscillator, a first circuit, a counter, and a pause circuit. The first circuit generates a drive signal to control switching of a switch to regulate an output of the power supply. The first circuit initiates an on time period of the switch in response to both a clock signal of the oscillator and an enable signal that is generated in response to a feedback signal of the power supply. The counter receives the enable signal and generates an output signal when the counter reaches a count value indicating that the enable signal has been idle for an amount of time. The pause circuit generates a pause signal in response to the output signal of the counter. The oscillator is paused in response to the pause signal and a maximum on time period of the switch is extended while the oscillator is paused. | 09-05-2013 |
20130238918 | Connected Standby Sleep State - Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state. | 09-12-2013 |
20130246821 | Serial Interface Transmitting method and Peripheral Device Chip - The present invention discloses a serial interface transmitting method utilized in a serial interface for connecting between a master controller and a peripheral device. The serial interface transmitting method comprises receiving a saving power signal from the master controller, a peripheral clock source and a serial interface clock source for generating a clock source selection result, switching an operational mode of the peripheral device according to the clock source selection result, and transmitting a datum to a peripheral-device register or a serial interface register according to the saving power signal and the operational mode. | 09-19-2013 |
20130254570 | OPERATING CLOCK SYNCHRONIZATION ADJUSTING METHOD FOR INDUCTION TYPE POWER SUPPLY SYSTEM - An operating clock synchronization adjusting method, for an induction type power supply system, includes receiving a plurality of data pulses, by a supplying-end module, according to a clock of a microprocessor of the supplying-end module, for generating a plurality of data frames. A period between first data pulses corresponding to starting bits of a first detecting data frame and a second detecting frame among the plurality of data frame is calculated, for acquiring a data frame period. A period between the first data pulse of the second data frame and a second data pulse of the second data frame is calculated, for acquiring a bit period. The bit period and a bit time threshold are compared for determining whether to adjust the clock of the microprocessor according to the data frame period and a frame time threshold. | 09-26-2013 |
20130262894 | SYSTEM-ON-CHIP, ELECTRONIC SYSTEM INCLUDING SAME, AND METHOD CONTROLLING SAME - A system-on-chip (SoC) operates with a memory device and includes a performance monitoring unit (PMU) that measures memory usage for the memory device, and a central processing unit (CPU) configured to implement a dynamic voltage frequency scaling (DVFS) controller that compares the memory usage during a performance monitoring period with a reference value and selects a control scheme accordingly. | 10-03-2013 |
20130262895 | SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD - In a system large-scale integration (LSI) including a plurality of subsystems having a power shutdown mechanism, sometimes instantaneous power consumption of the LSI intensively increases at timing of supplying a clock for initialization due to a shift of a power mode of a subsystem. After power supply starts to return to a first subsystem and a second subsystem, an increase in power consumption during initialization is distributed by desynchronizing timing of clock supply to start initialization for the first subsystem and the second subsystem. | 10-03-2013 |
20130262896 | PROCESSOR AND ELECTRONIC DEVICE - Power consumption is reduced. A processor includes an instruction register unit in which data of a plurality of instructions is fetched; an instruction decoder unit in which each of the plurality of instructions is translated; a logic unit including a functional circuit which is supplied with a clock signal and a power source voltage, supplied with a data signal including the translated data of the instructions, and operates in accordance with the supplied data of the instructions; a data analysis unit in which the translated data is analyzed so as to calculate a non-operating period of the functional circuit, and a control signal is generated; and a control unit which controls the supply of the clock signal or both the clock signal and the power source voltage to the functional circuit in accordance with the control signal. | 10-03-2013 |
20130262897 | Power Management of Components Having Clock Processing Circuits - A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a cock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. | 10-03-2013 |
20130268787 | METHOD AND APPARATUS FOR REALIZING CPU POWER CONSERVATION - A method and apparatus are disclosed for conserving CPU power. The method includes: obtaining CPU occupation rates of all threads triggering frequency adjustment in each domain and domains those threads belong to; in a domain a thread triggering frequency adjustment belongs to, calculating a target CPU frequency to be adjusted to according to the CPU occupation rate of the thread triggering frequency adjustment; calculating a timer parameter according to the target CPU frequency and setting a CPU frequency value for the thread triggering frequency adjustment. CPU frequency values of threads in each domain are synchronized according to the CPU occupation rate of each thread trigging frequency adjustment in this disclosure, so as to synchronize the CPU frequency values in a multi-core system to conserve CPU power. | 10-10-2013 |
20130275790 | MULTICORE PROCESSOR SYSTEM AND POWER CONTROL METHOD - A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes. | 10-17-2013 |
20130283075 | SYSTEMS AND METHODS FOR IMPLEMENTING REDUCED POWER STATES - In some embodiments, provided is a way for devices to request S0ix (or the like) entry and exit. | 10-24-2013 |
20130283076 | METHODS AND SYSTEMS FOR POWER MANAGEMENT IN A DATA PROCESSING SYSTEM - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 10-24-2013 |
20130305068 | Leakage Variation Aware Power Management For Multicore Processors - A system and method are provided to improve power efficiency of processor cores, such as processor cores in a multicore processor. A break-even time of a processor core may be determined that affects which power saving mode a processor core should enter when an expected idle of the processor core is identified. The break-even time of the processor core may be determined during run-time to help determine an applicable power saving mode that improves power efficiency of the processor core. | 11-14-2013 |
20130311805 | SYSTEM-WIDE TIME SYNCHRONIZATION ACROSS POWER MANAGEMENT INTERFACES AND SENSOR DATA - A power management control system for an information handling system is disclosed. The power management control system includes a power management interface bus interfacing a plurality of devices, where one or more of the devices is each associated with a time clock. The power management control system further includes a management agent interfacing the power management interface bus. The management agent is configured to: receive a system time; synchronize the one or more time clocks based, at least in part, on the system time; and maintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives. | 11-21-2013 |
20130311806 | PARALLEL PROCESSING COMPUTER SYSTEMS WITH REDUCED POWER CONSUMPTION AND METHODS FOR PROVIDING THE SAME - A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function. | 11-21-2013 |
20130332758 | SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION PROCESSING APPARATUS - In a semiconductor integrated circuit having a power domain and a mechanism for a power supply shutoff, when a power supply to the power domain is started, if a clock for an initialization operation is supplied in a state where a voltage to the power domain is unstable, power consumption during the initialization operation increases. Thus, the clock for the initialization operation of the power domain is supplied after detecting that the voltage supplied to the power domain is stabilized. | 12-12-2013 |
20130332759 | Inter-Processor Communication Channel Including Power-Down Functionality - Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel. | 12-12-2013 |
20140006822 | Oversubscribing to a Packet Processing Device to Adjust Power Consumption | 01-02-2014 |
20140025972 | ADAPTIVE REAL-TIME POWER AND PERFORMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS - An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized. | 01-23-2014 |
20140032949 | SYSTEM ON CHIP AND TEMPERATURE CONTROL METHOD THEREOF - A temperature control method of a semiconductor device is provided. The temperature control method includes detecting a temperature of the semiconductor device; activating a reverse body biasing operation in which a body bias voltage applied to a function block of the semiconductor device is regulated, when the detected temperature is greater than a first temperature level; and activating a thermal throttling operation in which at least one of a frequency of a driving clock provided to a function block of the semiconductor device and a driving voltage applied to the function block of the semiconductor device is regulated, when the detected temperature is greater than a second temperature level that is different than the first temperature level. | 01-30-2014 |
20140032950 | METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 01-30-2014 |
20140040647 | SYNTHESIZING INTERMEDIATE PERFORMANCE LEVELS IN INTEGRATED CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA - Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval. | 02-06-2014 |
20140053008 | METHOD AND SYSTEM FOR AUTOMATIC CLOCK-GATING OF A CLOCK GRID AT A CLOCK SOURCE - A system and method for power management by performing clock-gating at a clock source. In the method a critical stall condition is detected within a clocked component of a core of a processing unit. The core includes one or more clocked components synchronized in operation by a clock signal distributed by a clock grid. The clock grid is clock-gated to suspend distribution of the clock signal to the core during the critical stall condition. | 02-20-2014 |
20140053009 | INSTRUCTION THAT SPECIFIES AN APPLICATION THREAD PERFORMANCE STATE - An apparatus is described that includes a processor. The processor has a processing core to execute an instruction that specifies a performance state of an application thread. The instruction belongs to the application thread. The processor includes a register to store the performance state. The processor includes power management control logic coupled to the register to set a performance state of the processing core as a function of the performance state. | 02-20-2014 |
20140068298 | SYSTEM AND PROCESS FOR ACCOUNTING FOR AGING EFFECTS IN A COMPUTING DEVICE - Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated circuits and products which include integrated circuits over time, and the dynamic adjustment of operating conditions to increase or decrease wear in response to the accumulated wear relative to the expected wear during the lifetime of the circuit and/or product. | 03-06-2014 |
20140068299 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND POWER CONSUMPTION MANAGEMENT METHOD - When a result of detection by a current sensor | 03-06-2014 |
20140068300 | MICROCONTROLLER - To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register of the peripheral circuit is formed at an interface with a bus line. A power gate is provided for control of power supply, and the microcontroller can operate in the low power consumption mode where some circuits alone are active, in addition to in a normal operation mode where all circuits are active. A register with no power supply in the low power consumption mode, such as a register of the CPU, includes a volatile memory and a nonvolatile memory. | 03-06-2014 |
20140068301 | Semiconductor Device and Electronic Device - To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled. | 03-06-2014 |
20140075223 | ELECTRONIC DEVICE WITH POWER MANAGEMENT MECHANISM AND POWER MANAGEMENT METHOD THEREOF - An electronic device with a power management mechanism and a power management method thereof are disclosed. The electronic device includes a multi-core processor and a temperature sensor. The multi-core processor has a plurality of processor cores. The temperature sensor is coupled to the multi-core processor. The temperature sensor detects the temperature of the multi-core processor and determines whether the electronic device enters an underclocking mode from a performance priority mode according to the detected temperature. When the temperature of the multi-core processor is greater than a first temperature threshold, the multi-core processor controls the electronic device to enter a first underclocking mode and dynamically adjusts an enabled core number. When the temperature of the multi-core processor is greater than a second temperature threshold, the multi-core processor controls the electronic device to enter a second underclocking mode. The first temperature threshold is smaller than the second temperature threshold. | 03-13-2014 |
20140075224 | METHOD OF PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING OPERATION, APPLICATION PROCESSOR PERFORMING METHOD, AND MOBILE DEVICE COMPRISING APPLICATION PROCESSOR - A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit. | 03-13-2014 |
20140082387 | Method and Apparatus for Controlling Central Processing Unit - A method for controlling a central processing unit (CPU), where the method includes: acquiring a usage rate and an operating frequency of one CPU of operating CPUs; if the operating frequency of the one CPU is smaller than a core off-line frequency, multiplying the usage rate of the one CPU by a first weight to obtain a CPU power consumption sensitive factor corresponding to the one CPU; if the operating frequency of the one CPU is greater than or equal to the core off-line frequency, multiplying the usage rate of the one CPU by a second weight to obtain a CPU power consumption sensitive factor corresponding to the one CPU; and turning off at least one operating CPU if the mean is smaller than a CPU turn-off power consumption sensitive factor threshold. | 03-20-2014 |
20140089698 | SENSING CURRENT TO PROTECT A FUSE - The speed of a processor is adjusted based on the current sensed by a current sensor in order to protect a fuse from being damaged. | 03-27-2014 |
20140089699 | POWER MANAGEMENT SYSTEM AND METHOD FOR A PROCESSOR - The present disclosure relates to a method and apparatus for dynamically controlling power consumption by at least one processor. A power management method includes monitoring, by power control logic of the at least one processor, performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor. The method includes adjusting, by the power control logic following an execution of the repetitive workload, an operating frequency of at least one of a compute unit and a memory controller upon a determination that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload. | 03-27-2014 |
20140089700 | PERFORMANCE MANAGEMENT METHODS FOR ELECTRONIC DEVICES WITH MUTIPLE CENTRAL PROCESSING UNITS - Performance management methods for an electronic device with multiple central processing units (CPUs) are provided. First, thread loading rearrangement and CPU frequency evaluation are performed to obtain a plurality of evaluated performance values for different amounts of CPUs, wherein the plurality of evaluated performance values are relevant to power consumption values of the multiple CPUs. It is then determined whether to adjust an amount of used CPUs based on the plurality of evaluated performance values corresponding to the different amounts of CPUs. | 03-27-2014 |
20140095909 | MULTIPLE CLOCK DOMAIN CYCLE SKIPPING UTILIZING OPTIMAL MASKS TO MINIMIZE VOLTAGE NOISE - Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The skipped cycle clock signals may be changed by the computing system during operation of the system by altering masks applied to a global clock signal. However, the flexibility to alter various skipped cycle clock signals may introduce noise or signal disruptions within the system. Thus, the present disclosure may also involve an apparatus and/or method for managing the altering of the clock cycle skipping masks to manage the voltage noise introduced into the system by the adjustment of the operating frequency of the portions of the system. In one embodiment, the method includes prioritizing or otherwise ordering the bits of the masks applied to the global clock signal to attempt to prevent similar bits from being altered simultaneously. | 04-03-2014 |
20140101471 | POWER MANAGEMENT FOR PROCESSING CAPACITY UPGRADE ON DEMAND - A method, computer program product, and apparatus for managing power management in a data processing system are presented. A core is activated and configured to operate at a frequency in response to a request to increase a processing capacity. A determination whether a use of power resulting from activating the core meets a policy for the use of the power is made. A set of parameters is adjusted to meet the policy for the use of power in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed by a set of cores is made. An indication that the request to increase the processing capacity is unavailable is made in response to the number of operations having not increased. | 04-10-2014 |
20140108838 | Method and Apparatus for Controlling Central Processing Unit - The present invention discloses a method for controlling a central processing unit CPU. A usage and a working frequency of a working CPU is obtained. When the usage is greater than a usage threshold, it is determined whether the working frequency is smaller than a first frequency. The working frequency as the first frequency is determined when the working frequency is smaller than the first frequency. The first frequency is smaller than a maximum frequency of the CPU. | 04-17-2014 |
20140115361 | LOAD STEP MANAGEMENT - Various embodiments of the present disclosure are directed to managing load steps caused by processing circuitry. The processing circuitry may generate a series of clock pulses at an average clock period. The processing circuitry may estimate a current consumption of the processing circuitry at each clock pulse. Accordingly, a clock pulse from the series of clock pulses may be omitted when a change in the current consumption exceeds a predetermined threshold amount, thereby increasing the average clock period. | 04-24-2014 |
20140115362 | OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES - For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed. | 04-24-2014 |
20140129858 | METHOD AND APPARATUS FOR SETTING AN I/O BANDWIDTH-BASED PROCESSOR FREQUENCY FLOOR - An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The | 05-08-2014 |
20140136868 | POWER SAVING METHOD AND HANDHELD ELECTRONIC DEVICE USING THE SAME - A power saving method and a handheld electronic device using the same are provided. The method includes the following steps. A trigger signal is received. An user interface is displayed in a touch display panel unit of the handheld electronic device, wherein the user interface includes at least one control item and the at least one control item respectively corresponds to at least one working mode of the handheld electronic device. An operating signal corresponding to one of the at least one control item is received from the touch display panel unit. The working mode of the handheld electronic device is switched according to the operating signal and a working frequency of the handheld electronic device is adjusted according to the working mode. | 05-15-2014 |
20140149769 | COMPUTING SYSTEM FREQUENCY TARGET MONITOR - An apparatus includes memory, a processor coupled to the memory, and a set of one or more frequency target monitors. The processor includes a set of one or more processor cores, and the set of one or more frequency target monitors are coupled to the set of one or more processor cores. Each frequency target monitor is configured to determine a difference between an actual performance and an expected performance of a processor core from the set of one or more processor cores. Each frequency target monitor is also configured to, responsive to determining the difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores, record an indication of a difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores. | 05-29-2014 |
20140157022 | ELECTRONIC DEVICE AND METHOD FOR REDUCING CPU POWER CONSUMPTION - An electronic device includes a processing system, a storage unit for storing a table, an input unit for generating instruction in response to the operations of the user, and an actuating unit for generating an interrupt in response to the instructions to request the processing system to execute the instructions to perform desired functions. The table recording a relationship between an occupancy and a desired operating speed of the processing system. When the processing system is requested to execute instructions, the processing system calculates the occupancy and adjusts operating speed according to the calculated occupancy and the table. A method for reducing CPU power consumption is also provided. | 06-05-2014 |
20140157023 | NETWORK TERMINAL, METHOD FOR CONTROLLING THE SAME, AND NETWORK SYSTEM - A network terminal includes: an oscillator circuit; a communication processing unit which transmits and receives communication data through a transmission path, using the clock; a controller unit which controls a function of the network terminal, using the clock; a clock control unit which causes the oscillator circuit to start or stop oscillating, and supply the clock; and a signal detecting unit which monitors a wave detection signal communicated through the transmission path in the case where the communication processing unit is not operating, and generates an activation signal according to which the clock control unit causes the oscillator circuit to start oscillating at a time when the wave detection signal exceeds a threshold value. The signal detecting unit is operable without using the clock, and the controller unit switches a detectable wave detection signal by changing a circuit constant of the signal detecting unit. | 06-05-2014 |
20140164800 | ELECTRONIC DEVICE WITH OPERATING FREQUENCY ADJUTING FUNCTION AND METHOD FOR ADJUSTING OPERATING FREQUENCY - The present invention provides an electronic device with operating frequency adjusting function. The electronic device detects the inner temperature value T0 of the electronic device and the power consumption W0 of an electronic component of the electronic device. The electronic device determines whether a trigger condition is met according to the detected inner temperature value T0 and the detected power consumption W0 of the electronic component, determines the adjusting schedule corresponding to the trigger condition determined to be met, and adjusts the operating frequency of the electronic component according to the determined adjusting schedule. | 06-12-2014 |
20140164801 | SWITCHED-MODE POWER SUPPLY UNIT, METHOD OF OPERATION AND USE OF A SWITCHED-MODE POWER SUPPLY UNIT IN A COMPUTER - A switched-mode power supply unit for a computer includes at least one switching element that switches a charging current to charge a storage element, at least one secondary output circuit that provides an output voltage (Vout+), at least one controllable oscillator circuit that provides a switching clock, and at least one control circuit that determines a switch-off time for the at least one switching element, wherein, in operation of the switched-mode power supply unit, a mean oscillator clock of the oscillator circuit is controlled in dependence on a controlled variable (Vcontrol) specifying the output voltage or power of the secondary output circuit such that the mean oscillator clock rises monotonously with the output power and a switch-on time for the at least one switching element is determined in dependence on the mean oscillator clock and a random deviation. | 06-12-2014 |
20140164802 | Frequency And Voltage Scaling Architecture - A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. | 06-12-2014 |
20140181551 | MIXED CELL TYPE BATTERY MODULE AND USES THEREOF - Various embodiments are generally directed to operation of a computing device powered with first and second sets of energy storage cells, the cells of the first set structurally optimized for higher density storage of electric power, and the cells of the second set structurally optimized for providing electric power at a high electric current level. A battery module includes a casing, a first cell disposed within the casing to store electric energy with a high density, and a second cell disposed within the casing to provide electric energy stored therein with a high current level. Other embodiments are described and claimed herein. | 06-26-2014 |
20140201550 | APPARATUS, METHOD, AND SYSTEM FOR ADAPTIVE COMPENSATION OF REVERSE TEMPERATURE DEPENDENCE - Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD). | 07-17-2014 |
20140208141 | DYNAMICALLY CONTROLLING INTERCONNECT FREQUENCY IN A PROCESSOR - In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed. | 07-24-2014 |
20140208142 | SEMICONDUCTOR DEVICE - Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface. The address monitoring circuit acquires and monitors an address signal between a signal processing circuit and the cache memory or the input/output interface periodically. When one of the cache memory and the input/output interface is in a standby state and the other is in the access state, power gating is performed on the circuit that is in the standby state. | 07-24-2014 |
20140208143 | Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply - A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies. | 07-24-2014 |
20140215241 | COMPUTER POWER MANAGEMENT - A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes. | 07-31-2014 |
20140215242 | Wearable Device-Aware Supervised Power Management for Mobile Platforms - Methods, systems, and computer program products are provided for supervised power management between a primary platform and a secondary platform. Communication between a primary platform and a secondary platform is established. An application running on the secondary platform is captured. Input features and output measures are collected to build a training set for the application, wherein the input features are collected through direct measurement and the output measures reflect characteristics of the application. Based on the training set, power consumption of the secondary platform with an expected performance level is predicted for a new application running on the secondary platform. Accordingly, an optimal power management policy is derived that minimizes the total power consumption of the primary and secondary platforms. | 07-31-2014 |
20140215243 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE - A semiconductor device includes a CPU core, a frequency regulating circuit, and a frequency control circuit. The frequency regulating circuit includes a table. The frequency control circuit provides a clock to the CPU core. The CPU core outputs an operating state signal indicating an operating state of the CPU core. The frequency regulating circuit controls a frequency of the clock based on the table and the operating state signal. Thus it is possible to provide a seiconductor device that allows performance to follow a dynamically changing load. | 07-31-2014 |
20140223210 | Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode. | 08-07-2014 |
20140223211 | Regulating the Activity of a Core - It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S | 08-07-2014 |
20140237275 | Multiple Critical Paths Having Different Threshold Voltages in a Single Processor Core - A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode. | 08-21-2014 |
20140245039 | INFORMATION PROCESSING APPARATUS, DEVICE CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit. | 08-28-2014 |
20140281610 | EXPLOITING PROCESS VARIATION IN A MULTICORE PROCESSOR - A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core. | 09-18-2014 |
20140281611 | POWER MANAGEMENT FOR A MEMORY DEVICE - An improved method and apparatus for performing power management in a memory device is disclosed. | 09-18-2014 |
20140281612 | MEASUREMENT OF PERFORMANCE SCALABILITY IN A MICROPROCESSOR - A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability. | 09-18-2014 |
20140281613 | FREQUENCY CONTROL DEVICE AND FREQUENCY CONTROL METHOD - For every application, a storage unit stores performance information which indicates processing performance required for processing of the application. A derivation unit derives processing performance required for processing of an application executed in a processor on the basis of the performance information. A frequency control unit controls an operation frequency of a CPU in accordance with the processing performance derived by the derivation unit. | 09-18-2014 |
20140281614 | SYSTEM AND METHOD OF RACK MANAGEMENT - A rack management method and system is disclosed. The method includes detecting the presence of a computing device releasably mounted in a frame, the detecting based on an electrical connection established between a configuration bar disposed in a rear portion of the frame and the computing device, and determining a physical location of the computing device within the frame based on the electrical connection. The method also includes retrieving management information about the computing device from a profile storage disposed within the computing device via the electrical connection and storing the management information in a management table, the management table associating the computing device with the physical location within the frame. | 09-18-2014 |
20140289544 | Methods and Apparatuses for Switch Power Down - The discussion makes reference to methods and apparatuses for message-driven switch power, power control, and central processing unit (CPU)-assisted full switch power-down. The link layer in computer networking can be used to save power in switching elements. | 09-25-2014 |
20140289545 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a memory, and a processor coupled to the memory and configured to set an operating frequency of the processor at a first value in response to an occurrence of a first event, when a second event occurs after the occurrence of the first event, to determine whether the second event occurs within a predetermined period after the occurrence of the first event, and when the second event occurs after the predetermined period, set the operating frequency at a second value, and when the second event occurs within the predetermined period, set the operating frequency at a third value higher than the second value. | 09-25-2014 |
20140298058 | ADVANCED FINE-GRAINED CACHE POWER MANAGEMENT - Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section. | 10-02-2014 |
20140310549 | FIFO Clock and Power Management - An apparatus and method for saving power when transmitting data across a clock boundary is disclosed. In one embodiment, an apparatus includes a FIFO coupled to receive data from circuitry in a first clock domain and output data to circuitry in a second clock domain. A first control circuit is responsible for writing data into the FIFO. A second control circuit is responsible for reading data from the FIFO. If the amount of data in the FIFO exceeds a first threshold, a power management circuit may place the first control circuit in a low power state. The second control circuit may monitor the amount of data in the FIFO. If the amount of data in the FIFO falls below a second threshold, it may assert an indication to the power management circuit. Thereafter, the power management circuit may cause the first control circuit to exit the low power state. | 10-16-2014 |
20140317427 | DYNAMIC CLOCK VOLTAGE SCALING (DCVS) BASED ON APPLICATION PERFORMANCE IN A SYSTEM-ON-A-CHIP (SOC), AND RELATED METHODS AND PROCESSOR-BASED SYSTEMS - Dynamic clock voltage scaling (DCVS) based on application performance in a system-on-a-chip (SOC), and related methods and processor-based systems are disclosed. In this regard, in one embodiment, a method of providing an application-specific DCVS in a SOC is provided. The method comprises receiving performance data corresponding to at least one performance characteristic of a SOC indicative of an execution performance of an application executing on the SOC. The method also comprises storing the performance data for the application executing on the SOC. The method further comprises, responsive to executing the application on the SOC, determining an application-specific DCVS setting for the application based on the performance data, and setting a DCVS parameter of the SOC based on the determined application-specific DCVS setting for the application. In this manner, an optimal DCVS setting is provided for the SOC to optimize computing resources, thus improving perceived performance of the application. | 10-23-2014 |
20140331067 | PORTABLE ELECTRONIC DEVICE - A portable electronic device is provided. The portable electronic device includes a host, a power adapter and a signal transmission interface. The host generates state information according to present operating state, and the power adapter is used to provide a voltage to the host. The power adapter receives the state information of the host via the signal transmission interface, and adjusts the output voltage according to the state information. By transmitting information between the host and the power adapter, the power adapter can be adjusted according to the operating state of the host. Moreover, the host can adjust the operating state according to the specification information of the power adapter. Consequently, the power consuming of the portable electronic device has best efficiency thus to reduce carbon emission. | 11-06-2014 |
20140337646 | Adaptively Limiting A Maximum Operating Frequency In A Multicore Processor - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed. | 11-13-2014 |
20140337647 | SYSTEMS AND METHODS FOR MANAGING CURRENT CONSUMPTION BY AN ELECTRONIC DEVICE - Systems and methods for managing current consumption by an electronic device are provided. The electronic device includes first and second clock units. The first clock unit generates a first reference clock signal based on a first current input. The second clock unit generates a second reference clock signal based on a second current input greater than the first current input. The system includes a control module configured to identify an application to be executed. The control module is configured to determine whether the application is associated with a first current consumption level or a second current consumption level greater than the first current consumption level. The control module is configured to select the first or second reference clock signal based on whether the application is determined to be associated with the first or second current consumption level. The system includes circuitry configured to execute the application based on the selection. | 11-13-2014 |
20140337648 | INFORMATION PROCESSING APPARATUS AND POWER SAVING CONTROL METHOD - An information processing apparatus includes a detection unit and a frequency control unit and is designed to activate power saving control and perform information processing. The detection unit detects an idle time of a processor caused by job scheduling. The frequency control unit reduces the operating frequency of the processor for executing a job scheduled to be executed immediately before the idle time, below the maximum frequency. At this time, the frequency control unit reduces the operating frequency such that the execution time of the job is extended to the execution start time of a waiting job, which is included in the idle time. | 11-13-2014 |
20140344596 | Controlling Power Consumption Of A Processor Using Interrupt-Mediated On-Off Keying - In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed. | 11-20-2014 |
20140344597 | DYNAMIC LOAD AND PRIORITY BASED CLOCK SCALING FOR NON-VOLATILE STORAGE DEVICES - This disclosure discusses systems, methods, and apparatus for dynamically scaling a clock frequency of an I/O interface to a non-volatile storage device. The scaling can be based on monitoring an idle time on the I/O interface, a priority of one or more applications having read/write requests queued for dispatch to the I/O interface, a load of the queued read/write requests on the I/O interface or a combination of priority and load. Such variables can be compared to thresholds in a frequency governor. | 11-20-2014 |
20140344598 | Enabling A Non-Core Domain To Control Memory Bandwidth - In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed. | 11-20-2014 |
20140351615 | INTEGRATED CIRCUIT WAKE-UP CONTROL SYSTEM - An integrated circuit (IC) that operates in high and low power modes includes high and low power regulators, first and second sets of circuits, a switch connecting the high power regulator and the second set of circuits, and a wake-up control system. The wake-up control system includes a state machine that enables the high power regulator when the IC is in the high power mode, and enables the low power regulator when the IC is in the low power mode. The switch is closed when the high power regulator reaches a first threshold voltage. The state machine operates on a low frequency clock signal when the IC is in the low power mode and during wake-up, and on a high frequency clock signal in the high power mode after the switch is closed. | 11-27-2014 |
20140351616 | VOLTAGE-CONTROLLABLE POWER-MODE-AWARE CLOCK TREE, AND SYNTHESIS METHOD AND OPERATION METHOD THEREOF - A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers. | 11-27-2014 |
20140359328 | METHOD AND SYSTEM FOR RUN-TIME REALLOCATION OF LEAKAGE CURRENT AND DYNAMIC POWER SUPPLY CURRENT - A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICC | 12-04-2014 |
20140359329 | ADAPTIVE POWER SWITCH CIRCUIT - An adaptive power-switch circuit suitable for an electronic device includes a multi-gate power switch module, a monitoring module and a driving controller circuit. The multi-gate power switch module includes to plurality of power switch units connected in parallel. The power switch units include a gate control terminal respectively. The monitoring module is used to monitor an operating load of the electronic device. The driving control circuit is coupled to the monitoring module to selectively disable the gate controlling terminals to form a plurality of configurations. The driving control circuit selects one of the configurations to operate the multi-gate power switch module according to the operating load. | 12-04-2014 |
20140372778 | SERVER BACKPLANE - A server backplane includes a circuit board, a first connector, a second connector, a power connector, a plurality of hard disk drive interfaces to be coupled to HDDs, a HDD controller interface, and a controller coupled to the plurality of HDD interfaces and the HDD controller interface. The controller can detect the respective statuses of all the HDD according to report signals from the HDD controller interface and status signals from the HDD interfaces. | 12-18-2014 |
20140380072 | Digital Power Estimator to Control Processor Power Consumption - In an embodiment, a digital power estimator (DPE) may be provided that may monitor the processors to estimate the amount of power being consumed. If the estimate exceeds a power threshold, the DPE may throttle one or more of the processors. Additionally, throttling events may be monitored to determine if a change in the operating point is desired. In one embodiment, the DPE throttling events may be counted, and if the counts exceed a count threshold, a change in the operating point to a reduced operation point may be requested. Additionally, if the DPE estimate is below the power threshold (or a second power threshold), a second count of events may be maintained. If the second count exceeds a threshold and the operating point is the reduced operating point, a return to the original operating point may be requested. | 12-25-2014 |
20140380073 | COMPUTER SYSTEM AND POWER MANAGEMENT METHOD THEREOF - A power management method for a computer system is provided. The power management method includes: obtaining a system power consumption; determining whether the system power consumption is greater than a first safe operating point; when the system power consumption is greater than the first safe operating point, controlling a CPU and a graphics processing unit (GPU) to activate a frequency reduction mechanism according to a first adjustment sequence; when the system power consumption is not greater than the first safe operating point, determining whether the system power consumption is smaller than a second safe operating point; and when the system power consumption is smaller than the second safe operating point, controlling the CPU and the GPU to deactivate the frequency reduction mechanism according to a second adjustment sequence. The second adjustment sequence is reverse to the first adjustment sequence. | 12-25-2014 |
20140380074 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM - When a printing apparatus operates in a normal power mode, a control unit specifies a time of receipt of a packet and a reception interval between packets by using an RTC. On the other hand, when the printing apparatus operates in a power-saving mode, a communication unit specifies a time of receipt of a packet and a reception interval between packets on the basis of time-of-day information acquired from an SNTP server. | 12-25-2014 |
20150012767 | Sensor Interface Systems and Methods - A sensor interface system includes a system bus, a bus master and a sensor. The bus master is coupled to the system bus. The bus master is configured to provide voltage regulation at a first band and perform data transmission within or at a second band. The sensor is also coupled to the system bus. The sensor is configured to receive or utilize the voltage regulation and to perform data transmission within or at the second band. | 01-08-2015 |
20150012768 | DYNAMIC CONTROL OF REDUCED VOLTAGE STATE OF GRAPHICS CONTROLLER COMPONENT OF MEMORY CONTROLLER - A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component. | 01-08-2015 |
20150019891 | CONTROLLING POWER CONSUMPTION IN MULTI-CORE ENVIRONMENTS - Systems and methods of enabling modulation of a frequency of a first core in a multi-core environment include logic to determine a power limit assigned to the first core, logic to determine a stall count of the first core, and logic to modulate the frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core. The first core is included in a first tile of a socket in the multi-core computer environment. | 01-15-2015 |
20150026494 | INTELLIGENT MESOCHRONOUS SYNCHRONIZER - A method and apparatus for transmitting data over a clock-gated mesochronous clock domain boundary in an interconnect network of an integrated circuit. New data is received into storage buffers within a sender domain. The data is synchronized by sending time-controlled signals from storage elements in a sender control within the sender domain to corresponding inputs in a receiver control signal path in a receiver domain. Multiplexers are signaled to sequentially transmit the data from the storage buffers across the domain boundary to the receiver domain according to the time-controlled signals received from the sender control by the receiver control signal path, where the multiplexers receive signals from a data path pointer counter in communication with the receiver control signal path. | 01-22-2015 |
20150033050 | SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTING DEVICE INCLUDING THE SAME - A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node. The clock output node of the integrated clock gating cell and the clock input nodes of the clock-based cells are aligned on a straight line and commonly connected to a clock gating path. | 01-29-2015 |
20150033051 | Restricting Clock Signal Delivery Based On Activity In A Processor - In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed. | 01-29-2015 |
20150039920 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 02-05-2015 |
20150039921 | MEMORY SYSTEM AND MEMORY CHIP - A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted. | 02-05-2015 |
20150046731 | SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION OF A COMMUNICATION DEVICE - Generally, this disclosure describes an energy-efficient Ethernet communications approach including use of clock gating of transmit circuitry. | 02-12-2015 |
20150067367 | METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS - An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency. | 03-05-2015 |
20150067368 | CORE SYNCHRONIZATION MECHANISM IN A MULTI-DIE MULTI-CORE MICROPROCESSOR - A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores. | 03-05-2015 |
20150074435 | Processor Power and Performance Manager - Techniques are provided for managing the power consumption and performance of a processing device. Power consumption and utilization ratios for a processing device may be continuously measured. The measured power consumption and utilization ratios may be compared to target power consumption and utilization ratios to adjust an operating frequency of the processing device. In one implementation a power controller may take the target and measured power consumption as inputs to generate a power output and a utilization controller may take the target and measured utilization ratios as inputs to generate a utilization output. The lower of the power output and the utilization output may be selected and used to adjust the operating frequency of the processing device. The power and utilization controllers may implement a proportional-integral control scheme. | 03-12-2015 |
20150074436 | In-Kernel CPU Clock Boosting on Input Event - One embodiment provides a method to wake an electronic device having a central processing unit (CPU) from an idle condition. The method includes creating a worker queue in an interrupt-request (IRQ) driver module of the operating-system kernel of the device, receiving in the kernel an indication of user input in a form of an IRQ, and in response to receiving the indication of user input, posting a request in the worker queue to boost clock speed in the CPU. The request is then processed, causing an increase in the clock speed. | 03-12-2015 |
20150074437 | MEMORY CONTROLLER WITH TRANSACTION-QUEUE-MONITORING POWER MODE CIRCUITRY - An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device. | 03-12-2015 |
20150082060 | POWER CONSUMPTION MANAGEMENT SYSTEM AND METHOD - A power consumption management system for a central processing unit may include a power consumption estimation block and an activity control block. The power consumption estimation block may be configured to estimate power consumption of the central processing unit based on information related to a status of the central processing unit. The activity control block may be configured to use the estimated power consumption to determine a control to be applied to the central processing unit for regulating a rate of change in power consumption of the central processing unit. | 03-19-2015 |
20150089259 | SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS - Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values. | 03-26-2015 |
20150089260 | Electronic Apparatus, Method, and Storage Medium - According to one embodiment, an electronic apparatus includes a measurement module configured to measure power of a secondary battery, a comparator configured to compare the measured power with a first threshold and with a second threshold smaller than the first threshold, and a controller configured to, when the electronic apparatus is driven by the secondary battery, operate the electronic apparatus in any one of a first power range, second power range, and third power range based on the comparison. The first power range requires greater power than power required in the second power range, and the second power range requires greater power than power required in the third power range. | 03-26-2015 |
20150089261 | INFORMATION PROCESSING DEVICE AND SEMICONDUCTOR DEVICE - According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited. When the processor enters the second state and if an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state in which power consumption is lower as compared to the first state. If the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state in which power consumption is lower as compared to the third state. | 03-26-2015 |
20150095674 | Utilization of Processor Capacity at Low Operating Frequencies - In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed. | 04-02-2015 |
20150095675 | Methods And Apparatuses For Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 04-02-2015 |
20150100807 | CONTROLLING METHOD, POWER CONTROLLER, AND POWER CONTROLLING METHOD - A power supply has an inductor and determines loading state of the power supply according to a compensation signal. When the loading state is determined to be a light loading state or a no-loading state, a switch is operated at a low operating frequency. When the loading state is determined to be a heavy loading state, the switch is operated at a high operating frequency. If the compensation signal exceeds a critical value, it is determined that the loading state is an overloaded state. When the overloaded state continues past a tolerable duration, the switch is turned off. The tolerable duration is determined by an external capacitor and is independent of the operating frequency. | 04-09-2015 |
20150113304 | ENERGY-EFFICIENT MULTICORE PROCESSOR ARCHITECTURE FOR PARALLEL PROCESSING - A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption. | 04-23-2015 |
20150113305 | DATA STORAGE DEVICE - A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device based on a request from a host device, wherein the controller includes a first core activated in a normal mode and a second core activated in a standby mode. | 04-23-2015 |
20150121103 | INFORMATION PROCESSING APPARATUS AND LOAD CONTROL METHOD - An information processing apparatus includes a processor that is capable of switching a performance level to one of a plurality of performance levels with different power consumption, and a storage unit that stores a program for controlling the performance level of the processor. The processor executing the program detects the periodicity of load variation of the information processing apparatus, and changes, according to the periodicity of the load variation, a determination interval for determining whether to switch the performance level of the processor. | 04-30-2015 |
20150121104 | INFORMATION PROCESSING METHOD, INFORMATION PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - An information processing method using a first information processing apparatus, the first information processing apparatus including a power supply circuit, a first processor configured to receive power supply from the power supply circuit, and a second processor configured to receive power supply from the power supply circuit, the information processing method includes decreasing an operating frequency of the first processor, based on a decrease in an amount of power supply from the power supply circuit; and stopping data processing of the first processor in a state in which the second processor is being operated, after decreasing the operating frequency of the first processor. | 04-30-2015 |
20150121105 | ELECTRONIC SYSTEMS INCLUDING HETEROGENEOUS MULTI-CORE PROCESSORS AND METHODS OF OPERATING SAME - A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core. | 04-30-2015 |
20150127963 | DYNAMICALLY OPTIMIZING BUS FREQUENCY OF AN INTER-INTEGRATED CIRCUIT ('I2C') BUS - Optimizing an I | 05-07-2015 |
20150127964 | METHOD AND APPARATUS FOR THERMAL SENSITIVITY BASED DYNAMIC POWER CONTROL OF A PROCESSOR - A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance. | 05-07-2015 |
20150134988 | New Power Thermal Policy Using Micro-Throttle - Method and apparatus are provided for thermal management of mobile devices. In one novel aspect, a micro-throttle method is used to control the fast rising temperature for the device. In one embodiment, the thermal management method determines a temperature of the mobile device and compares the temperature with a plurality of predefined temperature thresholds. The thermal management applies a first micro-throttle solution upon detecting the temperature reaches a first predefined temperature threshold and applies a second micro-throttle solution upon detecting the temperature reaches a second predefined temperature threshold. In one embodiment, the first and the second micro-throttle solution control the slope of the rising temperature to be below a first predefined slope and a second predefined slope, respectively. In one embodiment, the temperature is controlled by adjusting the operating frequency or voltage of at least one heat-generating components of the mobile device. | 05-14-2015 |
20150149800 | PERFORMING AN OPERATING FREQUENCY CHANGE USING A DYNAMIC CLOCK CONTROL TECHNIQUE - In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed. | 05-28-2015 |
20150293574 | TECHNIQUES FOR POWER OPTIMIZATION BASED ON NETWORK PARAMETERS - A method for power optimization by an apparatus is disclosed. The method includes identifying one or more network parameters that affect one or more of a processing rate and a power usage of the processor in a connected state. The method also includes identifying a trigger event for the one or more network parameters. The method further includes adjusting a performance of the processor in the connected state when the trigger event occurs. | 10-15-2015 |
20150295426 | BATTERY AND ELECTRONIC DEVICE - According to one embodiment, a battery stack includes a plurality of battery cells connected in series. A first battery terminal is electrically connected to a positive electrode of a topmost battery cell in the battery stack. Through the first battery terminal, first power is supplied from the battery stack to a host. A first switch selects a highest-voltage battery cell from the plurality of battery cells. A feed circuit supplies second power to a controller in a battery or a first device in the host by using a charge of the selected battery cell. | 10-15-2015 |
20150301575 | SYSTEM INTERCONNECT DYNAMIC SCALING BY LANE WIDTH AND OPERATING FREQUENCY BALANCING - Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency. | 10-22-2015 |
20150301576 | SYSTEM INTERCONNECT DYNAMIC SCALING BY LANE WIDTH AND OPERATING FREQUENCY BALANCING - Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency. | 10-22-2015 |
20150301914 | Dynamically Limiting Bios Post For Effective Power Management - Presented herein are methods for budgeting power during a power-on self-test (POST) sequence. A determination is made for one or more stages of a power-on-self-test sequence of a system, whether a power profile of a particular stage is greater than a power budget for that stage. The power profile specifies a maximum power consumption as determined by the characteristics of the system and the power budget specifies a power consumption currently allocated to the system. When the power profile is greater than the power budget for that stage, power consumption of the system during the power-on-self-test sequence is limited such that the system does not consume more power than specified by the power budget. | 10-22-2015 |
20150309552 | ENHANCEMENT IN LINUX ONDEMAND GOVERNOR FOR PERIODIC LOADS - An enhanced OnDemand Governor is disclosed that computes a steady-state frequency based on prior recommended CPU frequencies and applies a steady-state frequency when available. When not available, a turbo frequency or a computed lower frequency is applied. For increased loads, the steady-state frequency can be applied for one or more cycles until it becomes apparent that gradual frequency increases are not sufficient to meet a large CPU load, at which point the turbo frequency is applied and the history of CPU frequencies can be flushed. The enhanced OnDemand Governor can be turned on where periodic loads are detected while the traditional OnDemand Governor can be used in all other use cases. | 10-29-2015 |
20150309553 | SERVER AND METHOD FOR ADJUSTMENT OF FREQUENCY OF MONITORING COMPONENTS OF SERVER - A monitoring frequency adjustment method monitors a power state of each of the plurality of components at preset intervals, determines a monitoring frequency of each of the plurality of components associated with the determined power state of a corresponding one of the plurality of components, and adjusts the preset intervals for monitoring each of the plurality of components to the determined monitoring frequency of the corresponding one of the plurality of components. A related server and a related non-transitory storage medium are provided. | 10-29-2015 |
20150323973 | METHOD FOR CONTROLLING OUTPUT OF A POWER SUPPLY UNIT TO SUPPLY POWER TO MULTIPLE PROCESSORS - A method for controlling an output of a power supply unit (PSU) in order to prevent a shutdown of the PSU to supply power to a group of processors (CPUs) is disclosed. A PSU supplies power to a multicore CPU. An input current flowing into multiple CPU cores includes a pulse current. When the pulse current of each of CPU cores is superposed on an output current of the PSU, a protection device is operated to perform a shutdown. A clock control determination unit compares the output current and a reference signal and thereby outputs a control signal. A group of peak detection units detects a peak value of the pulse current. A control unit selects a processor targeted for clock control, based on the peak value and outputs a control signal for reducing a clock frequency to the selected processor while receiving the control signal. | 11-12-2015 |
20150346796 | ELECTRONIC DEVICE WITH POWER MANAGEMENT MECHANISM AND POWER MANAGEMENT METHOD THEREOF - An electronic device with a power management mechanism and a power management method thereof are disclosed. The electronic device includes a multi-core processor and a temperature sensor. The multi-core processor has a plurality of processor cores. The temperature sensor is coupled to the multi-core processor. The temperature sensor detects the temperature of the multi-core processor and determines whether the electronic device enters an underclocking mode from a performance priority mode according to the detected temperature. When the temperature of the multi-core processor is greater than a first temperature threshold, the multi-core processor controls the electronic device to enter a first underclocking mode and dynamically adjusts an enabled core number. When the temperature of the multi-core processor is greater than a second temperature threshold, the multi-core processor controls the electronic device to enter a second underclocking mode. The first temperature threshold is smaller than the second temperature threshold. | 12-03-2015 |
20150355692 | POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS - A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit. | 12-10-2015 |
20150355699 | DATA CENTER MANAGEMENT - Techniques for providing power to components of a computer system are described. An example of a computer system includes a plurality of server nodes and a power distribution system that provides power to the plurality of server nodes. The computer system also includes a hardware-based alert signal line that couples the power distribution system to the plurality of server nodes. If a power failure occurs, the power distribution system is to send an alert signal to all of the server nodes through the alert signal line. The alert signal triggers each server node to activate a low power state. | 12-10-2015 |
20150355705 | Forcing A Processor Into A Low Power State - In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed. | 12-10-2015 |
20150362973 | ELECTRONIC DEVICE AND METHOD FOR RECOGNIZING OUTPUT POWER OF POWER SUPPLY THEREOF - An electronic device and a method for recognizing output power of a power supply thereof are provided. The electronic device includes a host and a power supply. The power supply is coupled to the host, receives an input power and converts the input power to a supplied power. The power supply transmits the supplied power to the host, and loads a notification signal to the supplied power in at least a time period. The acknowledge signal is a periodic clock signal, and corresponds to the output power of the power supply. The power supply loads the acknowledge signal to the supplied power in one or more time periods, and transmits the acknowledge signal to the corresponding host. The host can get the output power of the power supply via the acknowledge signal, which can improve efficiency and security of the supplied power. | 12-17-2015 |
20150362974 | Input-Output Device Management Using Dynamic Clock Frequency - In an example, a method includes determining, at a host device, a power state of a digital input/output device, and transmitting a clock signal having a first frequency from the host device to the input/output device responsive to a determination that the input/output device is in a lower power state. The method also includes determining, at the host device, that the input/output device has transitioned into a higher power state, and transmitting a clock signal having a second frequency from the host device to the input/output device responsive to a determination that the input/output device has transitioned into the higher power state. The first frequency is lower than the second frequency. | 12-17-2015 |
20150362978 | HIERARCHICAL CLOCK CONTROL USING HYSTERISIS AND THRESHOLD MANAGEMENT - In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved. | 12-17-2015 |
20150362987 | POWER MODE MANAGEMENT OF PROCESSOR CONTEXT - A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal. | 12-17-2015 |
20150370294 | ADAPTIVE OPTIMIZATION OF DATA CENTER COOLING - An electronic system comprises: at least one electronic component; a cooling system condition receiver, wherein the cooling system condition receiver is capable of receiving a condition signal, and wherein the condition signal describes a current condition of a cooling system that provides conditioned air to an ambient environment of the electronic system; and a throttle, wherein the throttle, in response to the cooling system condition receiver receiving the condition signal that describes the current condition of the cooling system, adjusts an amount of heat generated by said at least one electronic component by throttling back operations of said at least one electronic component. | 12-24-2015 |
20150370301 | PREVENTING OVERSUBSCRIPTION TO POWER RESOURCES IN A COMPUTING SYSTEM - Preventing oversubscription to power resources in a computing system that includes a plurality of power supplies configured to deliver power to a plurality of integrated technology elements (‘ITEs’), including: detecting, by a power management module, that power delivery capabilities of the power supplies have changed; determining, by the power management module in dependence upon a power redundancy policy and the power delivery capabilities of the power supplies, power settings for the plurality of ITEs; and updating, by the power management module, power settings for the plurality of ITEs. | 12-24-2015 |
20150370303 | SYSTEM AND METHOD FOR MANAGING POWER IN A CHIP MULTIPROCESSOR USING A PROPORTIONAL FEEDBACK MECHANISM - A system includes a power management unit that may monitor the power consumed by a processor including a plurality of processor core. The power management unit may throttle or reduce the operating frequency of the processor cores by applying a number of throttle events in response to determining that the plurality of cores is operating above a predetermined power threshold during a given monitoring cycle. The number of throttle events may be based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold. The number of throttle events may correspond to a portion of a total number of throttle events, and which may be dynamically determined during operation based upon a proportionality constant and the difference between the total power consumed by the processor and a predetermined power threshold. | 12-24-2015 |
20150370304 | ENHANCING POWER-PERFORMANCE EFFICIENCY IN A COMPUTER SYSTEM - Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value. | 12-24-2015 |
20150370308 | BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL - A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions. | 12-24-2015 |
20150378407 | Loading-Based Dynamic Voltage And Frequency Scaling - Techniques related to loading-based dynamic voltage and frequency scaling are described. A method may involve measuring a loading of a first power domain. The first power domain may include one or more circuit sections each of which operating in one of a plurality of loading states. The measuring of the loading of the first power domain may involve determining a respective loading state of each of the one or more circuit sections of the first power domain. The measured loading of the first power domain may be representative of a combination of the one or more loading states of the one or more circuit sections. The method may also involve determining at least one operating parameter of the first power domain according to the measured loading of the first power domain. | 12-31-2015 |
20150378418 | SYSTEMS AND METHODS FOR CONSERVING POWER IN A UNIVERSAL SERIAL BUS (USB) - Systems and methods for conserving power in a universal serial bus (USB) are disclosed. In one aspect, when a USB device enters a low power mode (e.g., U1 or U2), a clock associated with the USB device is modified to also enter a low power mode. Since the PIPE interface associated with the USB device still requires a clock signal, the low power clock mode must still be able to provide the PIPE interface with a clock signal. However, the clock signal to the PIPE interface does not need to be the same frequency or accuracy as the clock signal used by the USB interface. The modification to the clock changes the clock frequency to a low frequency compared to the normal clock frequency. By using a low frequency clock for the PIPE interface, power is conserved while preserving the functionality of the PIPE interface. | 12-31-2015 |
20160004289 | TERMINAL DEVICE FOR REDUCING POWER CONSUMPTION AND METHOD FOR CONTROLLING THE SAME - Disclosed are a terminal device and a method for controlling the terminal device that can reduce power consumption. The disclosed terminal device includes: a response time establisher unit which establishes a response time of an interactive application executed on the terminal device, with a frequency of a processor within the terminal device and a priority value of the interactive application as variables; a frequency determiner unit which determines the frequency of the processor based on a default priority value such that the response time does not exceed a preset response time threshold; a priority value determiner unit which determines the priority value based on the determined frequency such that the response time does not exceed the response time threshold; and an executor unit which runs the interactive application based on the determined frequency and the determined priority value. | 01-07-2016 |
20160011642 | POWER AND THROUGHPUT OPTIMIZATION OF AN UNBALANCED INSTRUCTION PIPELINE | 01-14-2016 |
20160011645 | SYSTEM-ON-CHIP INCLUDING MULTI-CORE PROCESSOR AND DYNAMIC POWER MANAGEMENT METHOD THEREOF | 01-14-2016 |
20160018868 | POWER MANAGEMENT CIRCUIT AND ELECTRONIC DEVICE EMPLOYING THE SAME - A power management circuit that controls a plurality of power circuits for generating supply voltages at least for a processor is disclosed. The circuit includes: a real time clock that generates clock signals with a predetermined frequency; a power-on terminal to which a power-on key is connected, wherein the power-on terminal receives a voltage whose level depends on whether the power-on key is pressed or not; a power-on detecting unit that monitors a voltage at the power-on terminal and asserts a start signal if it is determined using the clock signals that the power-on key is pressed and held for a predetermined time period; and a power management controller that receives a system voltage based on a battery voltage or a DC voltage from a DC power source and, upon the start signal is asserted, starts up the plurality of power circuits in a predetermined sequence using the clock signals. | 01-21-2016 |
20160026227 | DYNAMIC ROUTER POWER CONTROL IN MULTI-CORE PROCESSORS - Technologies are generally described for systems, devices and methods effective to dynamically select at least one power supply rail for a router. In some examples, a power control unit may be configured to determine a buffer occupancy level of one or more buffers of the router. In some further examples, the buffer occupancy level may be compared to a threshold value. In various other examples, the at least one power supply rail of the router may be switched from a first power rail to a second power rail based on the results of the comparison. | 01-28-2016 |
20160026229 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed. | 01-28-2016 |
20160041577 | Semiconductor Apparatus and System - A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal. | 02-11-2016 |
20160048181 | BALANCED CONTROL OF PROCESSOR TEMPERATURE - In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed. | 02-18-2016 |
20160048191 | Subsystem Idle Aggregation - A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units. | 02-18-2016 |
20160054776 | METHOD FOR PERFORMING SYSTEM POWER CONTROL WITHIN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing system power control within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and triggering a power limiter protection operation for the electronic device according to the power consumption index. For example, the power consumption index corresponding to the specific subsystem may represent a power consumption value of the specific subsystem, and the method may further include: comparing the power consumption value of the specific subsystem with a peak power threshold to determine whether the power consumed by the specific subsystem reaches the peak power threshold to generate a determining result, for triggering the power limiter protection operation. | 02-25-2016 |
20160062437 | APPLICATION PROCESSOR FOR ADJUSTING CLOCK SIGNAL USING HARDWARE POWER MANAGEMENT UNIT AND DEVICES INCLUDING THE SAME - An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals. | 03-03-2016 |
20160062438 | SYSTEM AND METHOD FOR PROVIDING DYNAMIC QUALITY OF SERVICE LEVELS BASED ON COPROCESSOR OPERATION - Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor. | 03-03-2016 |
20160077568 | METHOD AND APPARATUS FOR SAVING POWER OF A PROCESSOR SOCKET IN A MULTI-SOCKET COMPUTER SYSTEM - Described is an apparatus comprising: a plurality of system agents, at least one system agent including one or more queues; and logic to monitor the one or more queues in at least one system agent and to cause the plurality of system agents to block traffic after satisfaction of a criterion. | 03-17-2016 |
20160077570 | DISTRIBUTED INFORMATION TECHNOLOGY INFRASTRUCTURE DYNAMIC POLICY DRIVEN PEAK POWER MANAGEMENT SYSTEM - A peak power management system for networked smart IT devices. These smart devices have computing capability with at least one CPU and memory and can be networked. An uninterruptible power supply provides power to the smart devices. A central intelligent power management server controls the power consumed by all the smart devices networked with the server. The system uses priority based peak power management policies for smart IT devices assisted by fine grain control of external power drawn by each device. By applying different power management policies at different scheduled intervals and controlling the power consumption on the smart devices, the aggregated peak power demand is controlled. The policies can be adapted in-time to suit the actual, real-time power requirement of devices, their priorities, and applicable peak power limit at that time. Also, dynamic policy based peak power management can be extended to an intelligent hierarchical power distribution network. | 03-17-2016 |
20160091954 | LOW ENERGY PROCESSOR FOR CONTROLLING OPERATING STATES OF A COMPUTER SYSTEM - Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system. | 03-31-2016 |
20160098077 | ELECTRONIC CONTROL UNIT - An electronic control unit includes a microcomputer, a monitoring unit, a clock-generating oscillator circuit, a first power circuit supplying power to the microcomputer, and a second power circuit supplying power to the monitor microcomputer. The first power circuit includes a first switching power source including a first transistor and a first series power source including a second transistor. The second power circuit includes a second switching power source including a third transistor and a second series power source including a fourth transistor. Further, the ECU includes a power control circuit controlling each of the transistors and an oscillation stop detection circuit. When a stop of oscillation is detected, the power control circuit switches ON the second transistor, and switches OFF the fourth transistor, thereby diminishing a no-monitoring period of the microcontroller during a stop of the clock output. | 04-07-2016 |
20160098078 | Providing Per Core Voltage And Frequency Control - In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed. | 04-07-2016 |
20160098079 | Providing Per Core Voltage And Frequency Control - In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed. | 04-07-2016 |
20160109921 | HARDWARE APPARATUS AND METHOD FOR MULTIPLE PROCESSORS DYNAMIC ASYMMETRIC AND SYMMETRIC MODE SWITCHING - A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory. | 04-21-2016 |
20160109922 | NOVEL LOW COST, LOW POWER HIGH PERFORMANCE SMP/ASMP MULTIPLE-PROCESSOR SYSTEM - A processing system includes multiple processors in which first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). A third processor may be included that also operates at the first clock frequency and the first supply voltage at all times. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. A controller enables control and fast-switching between the two modes for the switchable processor. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory. | 04-21-2016 |
20160109923 | FAST SMP/ASMP MODE-SWITCHING HARDWARE APPARATUS FOR A LOW-COST LOW-POWER HIGH PERFORMANCE MULTIPLE PROCESSOR SYSTEM - A processing system includes multiple processors in which a first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). An integrated controller (e.g., finite state-machine (FSM)) controls not only voltage change, but also clock-switching. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory. | 04-21-2016 |
20160147274 | Controlling Turbo Mode Frequency Operation In A Processor - In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed. | 05-26-2016 |
20160147275 | CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR - In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed. | 05-26-2016 |
20160147277 | PROCESSOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A processor and a semiconductor device including the same are provided. The processor includes an operation unit, an operation counter which measures a first operation pattern by counting first operations of the operation unit and measures a second operation pattern by counting second operations of the operation unit which are different from the first operations, a power measurement unit which calculates power consumption of the operation unit using a first weight for the first operation pattern and a second weight for the second operation pattern, and a frequency controller which adjusts an operating frequency used for the first or second operations by using the calculated power consumption. | 05-26-2016 |
20160154449 | SYSTEM ON CHIPS FOR CONTROLLING POWER USING WORKLOADS, METHODS OF OPERATING THE SAME, AND COMPUTING DEVICES INCLUDING THE SAME | 06-02-2016 |
20160162001 | METHOD OF OPERATING SEMICONDUCTOR DEVICE - Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption. | 06-09-2016 |
20160170467 | Electronic Device Comprising a Wake Up Module Distinct From a Core Domain | 06-16-2016 |
20160170468 | Configuring Power Management Functionality In A Processor | 06-16-2016 |
20160179164 | SYSTEM AND METHOD FOR PEAK DYNAMIC POWER MANAGEMENT IN A PORTABLE COMPUTING DEVICE | 06-23-2016 |
20160179176 | SEMICONDUCTOR INTEGRATED CIRCUIT | 06-23-2016 |
20160179186 | REPLICA PATH TIMING ADJUSTMENT AND NORMALIZATION FOR ADAPTIVE VOLTAGE AND FREQUENCY SCALING | 06-23-2016 |
20160195913 | OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU | 07-07-2016 |
20160195914 | MEDIA PLAYBACK POWER MANAGEMENT DEVICES AND METHODS | 07-07-2016 |
20160252942 | SUPERCAPACITOR-BASED POWER SUPPLY PROTECTION FOR MULTI-NODE SYSTEMS | 09-01-2016 |
20190146566 | Event-Based Power Manager | 05-16-2019 |
20190146567 | PROCESSOR THROTTLING BASED ON ACCUMULATED COMBINED CURRENT MEASUREMENTS | 05-16-2019 |