Class / Patent application number | Description | Number of patent applications / Date published |
712038000 | Offchip interface | 8 |
20080209169 | Output Stage Circuit Apparatus for a Processor Device and Method Therefor - A drive circuit arrangement for a processor device comprises a non-volatile register for recording the identities of outputs of the processor device at which a same output signal is required. Configuration circuitry employs dual pairs of switching devices to couple register locations associated with a predetermined output of the processor to buffers of outputs identified in the non-volatile register, thereby resulting in a same output signal being provided at the identified outputs as at the predetermined output. | 08-28-2008 |
20110035571 | ON-CHIP PACKET INTERFACE PROCESSOR ENCAPSULATING MEMORY ACCESS FROM MAIN PROCESSOR TO EXTERNAL SYSTEM MEMORY IN SERIAL PACKET SWITCHED PROTOCOL - A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture. | 02-10-2011 |
20130007414 | MULTI-CORE PROCESSOR APPARATUS WITH FLEXIBLE COMMUNICATION INTERCONNECTION - A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture. | 01-03-2013 |
712039000 | Externally controlled internal mode switching via pin | 2 |
20080244228 | Electronic Device With an Array of Processing Units - The invention concerns electronics devices like X-ray detectors with an array of pixels ( | 10-02-2008 |
20090282219 | METHOD FOR REDUCING PIN COUNTS AND MICROPROCESSOR USING THE SAME - The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the present invention, a new higher bit address latching signal is added in order to latch the higher bit address so that an original lower bit address latching signal and the higher bit address latching signal can respectively latch the lower bit address and the higher bit address. | 11-12-2009 |
712040000 | External sync or interrupt signal | 3 |
20080229064 | Package designs for fully functional and partially functional chips - A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip. | 09-18-2008 |
20090292902 | APPARATUS AND METHOD FOR MANAGING A MICROPROCESSOR PROVIDING FOR A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus. The secure application program executes in a secure execution mode. The microprocessor has secure execution mode logic that monitors conditions corresponding to the microprocessor associated with tampering, and causes the microprocessor to transition to a degraded operating mode from the secure execution mode following detection of a first one or more of the conditions. The degraded operating mode exclusively provides for execution of BIOS instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, stores the secure application program. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor. | 11-26-2009 |
20120166763 | DYNAMIC MULTI-CORE MICROPROCESSOR CONFIGURATION DISCOVERY - A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes. | 06-28-2012 |